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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Filename:    spec.tex
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%%
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%% Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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%%
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%% Purpose:     This LaTeX file contains all of the documentation/description
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%%              currently provided with this Zip CPU soft core.  It supersedes
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%%              any information about the instruction set or CPUs found
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%%              elsewhere.  It's not nearly as interesting, though, as the PDF
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%%              file it creates, so I'd recommend reading that before diving
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%%              into this file.  You should be able to find the PDF file in
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%%              the SVN distribution together with this PDF file and a copy of
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%%              the GPL-3.0 license this file is distributed under.  If not,
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%%              just type 'make' in the doc directory and it (should) build
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%%              without a problem.
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%%
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%%
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%% Creator:     Dan Gisselquist
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%%              Gisselquist Technology, LLC
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%% Copyright (C) 2015, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of  the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program.  (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.)  If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License:     GPL, v3, as defined and found on www.gnu.org,
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%%              http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\documentclass{gqtekspec}
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\project{Zip CPU}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.5}
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\definecolor{webred}{rgb}{0.2,0,0}
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\definecolor{webgreen}{rgb}{0,0.2,0}
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\usepackage[dvips,ps2pdf,colorlinks=true,
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        anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames,
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        pdfauthor={Dan Gisselquist},
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        pdfsubject={Zip CPU}]{hyperref}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\titlepage
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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64
This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of  the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
72
for more details.
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74
You should have received a copy of the GNU General Public License along
75
with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a
76
copy.
77
\end{license}
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\begin{revisionhistory}
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0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
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0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
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0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline
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0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline
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\end{revisionhistory}
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% Revision History
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% Table of Contents, named Contents
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\tableofcontents
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\listoffigures
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\listoftables
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\begin{preface}
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Many people have asked me why I am building the Zip CPU. ARM processors are
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good and effective. Xilinx makes and markets Microblaze, Altera Nios, and both
93
have better toolsets than the Zip CPU will ever have. OpenRISC is also
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available, RISC--V may be replacing it. Why build a new processor?
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96
The easiest, most obvious answer is the simple one: Because I can.
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98
There's more to it, though. There's a lot that I would like to do with a
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processor, and I want to be able to do it in a vendor independent fashion.
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First, I would like to be able to place this processor inside an FPGA.  Without
101
paying royalties, ARM is out of the question.  I would then like to be able to
102
generate Verilog code, both for the processor and the system it sits within,
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that can run equivalently on both Xilinx and Altera chips, and that can be
104
easily ported from one manufacturer's chipsets to another. Even more, before
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purchasing a chip or a board, I would like to know that my soft core works. I
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would like to build a test bench to test components with, and Verilator is my
107
chosen test bench. This forces me to use all Verilog, and it prevents me from
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using any proprietary cores. For this reason, Microblaze and Nios are out of
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the question.
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111
Why not OpenRISC? That's a hard question. The OpenRISC team has done some
112
wonderful work on an amazing processor, and I'll have to admit that I am
113
envious of what they've accomplished. I would like to port binutils to the
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Zip CPU, as I would like to port GCC and GDB. They are way ahead of me. The
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OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has
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a lot of features of modern CPUs within it that ... well, let's just say it's
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not the little guy on the block. The Zip CPU is lighter weight, costing only
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about 2,300 LUTs with no peripherals, and 3,200 LUTs with some very basic
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peripherals.
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121
My final reason is that I'm building the Zip CPU as a learning experience. The
122
Zip CPU has allowed me to learn a lot about how CPUs work on a very micro
123
level. For the first time, I am beginning to understand many of the Computer
124
Architecture lessons from years ago.
125
 
126
To summarize: Because I can, because it is open source, because it is light
127
weight, and as an exercise in learning.
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129
\end{preface}
130
 
131
\chapter{Introduction}
132
\pagenumbering{arabic}
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\setcounter{page}{1}
134
 
135
 
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The original goal of the Zip CPU was to be a very simple CPU.   You might
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think of it as a poor man's alternative to the OpenRISC architecture.
138
For this reason, all instructions have been designed to be as simple as
139
possible, and are all designed to be executed in one instruction cycle per
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instruction, barring pipeline stalls.  Indeed, even the bus has been simplified
141
to a constant 32-bit width, with no option for more or less.  This has
142
resulted in the choice to drop push and pop instructions, pre-increment and
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post-decrement addressing modes, and more.
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145
For those who like buzz words, the Zip CPU is:
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\begin{itemize}
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\item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits,
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                instructions are 32-bits wide, etc.
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\item A RISC CPU.  There is no microcode for executing instructions.  All
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        instructions are designed to be completed in one clock cycle.
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\item A Load/Store architecture.  (Only load and store instructions
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                can access memory.)
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\item Wishbone compliant.  All peripherals are accessed just like
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                memory across this bus.
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\item A Von-Neumann architecture.  (The instructions and data share a
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                common bus.)
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\item A pipelined architecture, having stages for {\bf Prefetch},
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                {\bf Decode}, {\bf Read-Operand}, the {\bf ALU/Memory}
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                unit, and {\bf Write-back}.  See Fig.~\ref{fig:cpu}
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\begin{figure}\begin{center}
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\includegraphics[width=3.5in]{../gfx/cpu.eps}
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\caption{Zip CPU internal pipeline architecture}\label{fig:cpu}
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\end{center}\end{figure}
164
                for a diagram of this structure.
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\item Completely open source, licensed under the GPL.\footnote{Should you
166
        need a copy of the Zip CPU licensed under other terms, please
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        contact me.}
168
\end{itemize}
169
 
170
Now, however, that I've worked on the Zip CPU for a while, it is not nearly
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as simple as I originally hoped.  Worse, I've had to adjust to create
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capabilities that I was never expecting to need.  These include:
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\begin{itemize}
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\item {\bf External Debug:} Once placed upon an FPGA, some external means is
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        still necessary to debug this CPU.  That means that there needs to be
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        an external register that can control the CPU: reset it, halt it, step
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        it, and tell whether it is running or not.  My chosen interface
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        includes a second register similar to this control register.  This
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        second register allows the external controller or debugger to examine
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        registers internal to the CPU.
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182
\item {\bf Internal Debug:} Being able to run a debugger from within
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        a user process requires an ability to step a user process from
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        within a debugger.  It also requires a break instruction that can
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        be substituted for any other instruction, and substituted back.
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        The break is actually difficult: the break instruction cannot be
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        allowed to execute.  That way, upon a break, the debugger should
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        be able to jump back into the user process to step the instruction
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        that would've been at the break point initially, and then to
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        replace the break after passing it.
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        Incidentally, this break messes with the prefetch cache and the
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        pipeline: if you change an instruction partially through the pipeline,
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        the whole pipeline needs to be cleansed.  Likewise if you change
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        an instruction in memory, you need to make sure the cache is reloaded
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        with the new instruction.
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\item {\bf Prefetch Cache:} My original implementation had a very
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        simple prefetch stage.  Any time the PC changed the prefetch would go
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        and fetch the new instruction.  While this was perhaps this simplest
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        approach, it cost roughly five clocks for every instruction.  This
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        was deemed unacceptable, as I wanted a CPU that could execute
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        instructions in one cycle.  I therefore have a prefetch cache that
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        issues pipelined wishbone accesses to memory and then pushes
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        instructions at the CPU.  Sadly, this accounts for about 20\% of the
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        logic in the entire CPU, or 15\% of the logic in the entire system.
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208
 
209
\item {\bf Operating System:} In order to support an operating system,
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        interrupts and so forth, the CPU needs to support supervisor and
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        user modes, as well as a means of switching between them.  For example,
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        the user needs a means of executing a system call.  This is the
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        purpose of the {\bf `trap'} instruction.  This instruction needs to
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        place the CPU into supervisor mode (here equivalent to disabling
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        interrupts), as well as handing it a parameter such as identifying
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        which O/S function was called.
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My initial approach to building a trap instruction was to create an external
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peripheral which, when written to, would generate an interrupt and could
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return the last value written to it.  In practice, this approach didn't work
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at all: the CPU executed two instructions while waiting for the
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trap interrupt to take place.  Since then, I've decided to keep the rest of
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the CC register for that purpose so that a write to the CC register, with the
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GIE bit cleared, could be used to execute a trap.  This has other problems,
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though, primarily in the limitation of the uses of the CC register.  In
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particular, the CC register is the best place to put CPU state information and
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to ``announce'' special CPU features (floating point, etc).  So the trap
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instruction still switches to interrupt mode, but the CC register is not
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nearly as useful for telling the supervisor mode processor what trap is being
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executed.
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232
Modern timesharing systems also depend upon a {\bf Timer} interrupt
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to handle task swapping.  For the Zip CPU, this interrupt is handled
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external to the CPU as part of the CPU System, found in {\tt zipsystem.v}.
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The timer module itself is found in {\tt ziptimer.v}.
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237
\item {\bf Pipeline Stalls:} My original plan was to not support pipeline
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        stalls at all, but rather to require the compiler to properly schedule
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        all instructions so that stalls would never be necessary.  After trying
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        to build such an architecture, I gave up, having learned some things:
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242
        For example, in  order to facilitate interrupt handling and debug
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        stepping, the CPU needs to know what instructions have finished, and
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        which have not.  In other words, it needs to know where it can restart
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        the pipeline from.  Once restarted, it must act as though it had
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        never stopped.  This killed my idea of delayed branching, since what
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        would be the appropriate program counter to restart at?  The one the
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        CPU was going to branch to, or the ones in the delay slots?  This
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        also makes the idea of compressed instruction codes difficult, since,
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        again, where do you restart on interrupt?
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252
        So I switched to a model of discrete execution: Once an instruction
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        enters into either the ALU or memory unit, the instruction is
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        guaranteed to complete.  If the logic recognizes a branch or a
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        condition that would render the instruction entering into this stage
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        possibly inappropriate (i.e. a conditional branch preceding a store
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        instruction for example), then the pipeline stalls for one cycle
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        until the conditional branch completes.  Then, if it generates a new
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        PC address, the stages preceding are all wiped clean.
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261
        The discrete execution model allows such things as sleeping: if the
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        CPU is put to ``sleep,'' the ALU and memory stages stall and back up
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        everything before them.  Likewise, anything that has entered the ALU
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        or memory stage when the CPU is placed to sleep continues to completion.
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        To handle this logic, each pipeline stage has three control signals:
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        a valid signal, a stall signal, and a clock enable signal.  In
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        general, a stage stalls if it's contents are valid and the next step
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        is stalled.  This allows the pipeline to fill any time a later stage
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        stalls.
270
 
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        This approach is also different from other pipeline approaches.  Instead
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        of keeping the entire pipeline filled, each stage is treated
273
        independently.  Therefore, individual stages may move forward as long
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        as the subsequent stage is available, regardless of whether the stage
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        behind it is filled.
276
 
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\item {\bf Verilog Modules:} When examining how other processors worked
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        here on open cores, many of them had one separate module per pipeline
279
        stage.  While this appeared to me to be a fascinating and commendable
280
        idea, my own implementation didn't work out quite so nicely.
281
 
282
        As an example, the decode module produces a {\em lot} of
283
        control wires and registers.  Creating a module out of this, with
284
        only the simplest of logic within it, seemed to be more a lesson
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        in passing wires around, rather than encapsulating logic.
286
 
287
        Another example was the register writeback section.  I would love
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        this section to be a module in its own right, and many have made them
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        such.  However, other modules depend upon writeback results other
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        than just what's placed in the register (i.e., the control wires).
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        For these reasons, I didn't manage to fit this section into it's
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        own module.
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294
        The result is that the majority of the CPU code can be found in
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        the {\tt zipcpu.v} file.
296
\end{itemize}
297
 
298
With that introduction out of the way, let's move on to the instruction
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set.
300
 
301
\chapter{CPU Architecture}\label{chap:arch}
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The Zip CPU supports a set of two operand instructions, where the second operand
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(always a register) is the result.  The only exception is the store instruction,
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where the first operand (always a register) is the source of the data to be
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stored.
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\section{Simplified Bus}
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The bus architecture of the Zip CPU is that of a simplified WISHBONE bus.
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It has been simplified in this fashion: all operations are 32--bit operations.
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The bus is neither little endian nor big endian.  For this reason, all words
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are 32--bits.  All instructions are also 32--bits wide.  Everything has been
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built around the 32--bit word.
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\section{Register Set}
316
The Zip CPU supports two sets of sixteen 32-bit registers, a supervisor
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and a user set as shown in Fig.~\ref{fig:regset}.
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\begin{figure}\begin{center}
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\includegraphics[width=3.5in]{../gfx/regset.eps}
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\caption{Zip CPU Register File}\label{fig:regset}
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\end{center}\end{figure}
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The supervisor set is used in interrupt mode when interrupts are disabled,
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whereas the user set is used otherwise.  Of this register set, the Program
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Counter (PC) is register 15, whereas the status register (SR) or condition
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code register
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(CC) is register 14.  By convention, the stack pointer will be register 13 and
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noted as (SP)--although there is nothing special about this register other
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than this convention.
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The CPU can access both register sets via move instructions from the
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supervisor state, whereas the user state can only access the user registers.
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The status register is special, and bears further mention.  As shown in
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Fig.~\ref{tbl:cc-register},
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\begin{table}\begin{center}
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\begin{bitlist}
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31\ldots 11 & R/W & Reserved for future uses\\\hline
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10 & R & (Reserved for) Bus-Error Flag\\\hline
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9 & R & Trap, or user interrupt, Flag.  Cleared on return to userspace.\\\hline
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8 & R & (Reserved for) Illegal Instruction Flag\\\hline
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7 & R/W & Break--Enable\\\hline
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6 & R/W & Step\\\hline
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5 & R/W & Global Interrupt Enable (GIE)\\\hline
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4 & R/W & Sleep.  When GIE is also set, the CPU waits for an interrupt.\\\hline
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3 & R/W & Overflow\\\hline
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2 & R/W & Negative.  The sign bit was set as a result of the last ALU instruction.\\\hline
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1 & R/W & Carry\\\hline
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348
\end{bitlist}
349
\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
350
\end{center}\end{table}
351
the lower 11~bits of the status register form
352
a set of CPU state and condition codes.  Writes to other bits of this register
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are preserved.
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Of the condition codes, the bottom four bits are the current flags:
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                Zero (Z),
357
                Carry (C),
358
                Negative (N),
359
                and Overflow (V).
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361
The next bit is a clock enable (0 to enable) or sleep bit (1 to put
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        the CPU to sleep).  Setting this bit will cause the CPU to
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        wait for an interrupt (if interrupts are enabled), or to
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        completely halt (if interrupts are disabled).
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The sixth bit is a global interrupt enable bit (GIE).  When this
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        sixth bit is a `1' interrupts will be enabled, else disabled.  When
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        interrupts are disabled, the CPU will be in supervisor mode, otherwise
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        it is in user mode.  Thus, to execute a context switch, one only
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        need enable or disable interrupts.  (When an interrupt line goes
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        high, interrupts will automatically be disabled, as the CPU goes
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        and deals with its context switch.)  Special logic has been added to
373
        keep the user mode from setting the sleep register and clearing the
374
        GIE register at the same time, with clearing the GIE register taking
375
        precedence.
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377
The seventh bit is a step bit.  This bit can be
378
        set from supervisor mode only.  After setting this bit, should
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        the supervisor mode process switch to user mode, it would then
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        accomplish one instruction in user mode before returning to supervisor
381
        mode.  Then, upon return to supervisor mode, this bit will
382
        be automatically cleared.  This bit has no effect on the CPU while in
383
        supervisor mode.
384
 
385
        This functionality was added to enable a userspace debugger
386
        functionality on a user process, working through supervisor mode
387
        of course.
388
 
389
 
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The eighth bit is a break enable bit.  This controls whether a break
391
instruction in user mode will halt the processor for an external debugger
392
(break enabled), or whether the break instruction will simply send send the
393
CPU into interrupt mode.  Encountering a break in supervisor mode will
394
halt the CPU independent of the break enable bit.  This bit can only be set
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within supervisor mode.
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397 32 dgisselq
% Should break enable be a supervisor mode bit, while the break enable bit
398
% in user mode is a break has taken place bit?
399
%
400
 
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This functionality was added to enable an external debugger to
402
        set and manage breakpoints.
403
 
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The ninth bit is reserved for an illegal instruction bit.  When the CPU
405
tries to execute either a non-existant instruction, or an instruction from
406
an address that produces a bus error, the CPU will (once implemented) switch
407
to supervisor mode while setting this bit.  The bit will automatically be
408
cleared upon any return to user mode.
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410
The tenth bit is a trap bit.  It is set whenever the user requests a soft
411
interrupt, and cleared on any return to userspace command.  This allows the
412
supervisor, in supervisor mode, to determine whether it got to supervisor
413
mode from a trap or from an external interrupt or both.
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These status register bits are summarized in Tbl.~\ref{tbl:ccbits}.
416
\begin{table}
417
\begin{center}
418
\begin{tabular}{l|l}
419
Bit & Meaning \\\hline
420
9 & Soft trap, set on a trap from user mode, cleared when returning to user mode\\\hline
421
8 & (Reserved for) Floating point enable \\\hline
422
7 & Halt on break, to support an external debugger \\\hline
423
6 & Step, single step the CPU in user mode\\\hline
424
5 & GIE, or Global Interrupt Enable \\\hline
425
4 & Sleep \\\hline
426
3 & V, or overflow bit.\\\hline
427
2 & N, or negative bit.\\\hline
428
1 & C, or carry bit.\\\hline
429
 
430
\end{tabular}
431
\caption{Condition Code / Status Register Bits}\label{tbl:ccbits}
432
\end{center}\end{table}
433
 
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\section{Conditional Instructions}
435 36 dgisselq
Most, although not quite all, instructions may be conditionally executed.  From
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the four condition code flags, eight conditions are defined.  These are shown
437
in Tbl.~\ref{tbl:conditions}.
438
\begin{table}
439
\begin{center}
440
\begin{tabular}{l|l|l}
441
Code & Mneumonic & Condition \\\hline
442
3'h0 & None & Always execute the instruction \\
443
3'h1 & {\tt .Z} & Only execute when 'Z' is set \\
444
3'h2 & {\tt .NE} & Only execute when 'Z' is not set \\
445
3'h3 & {\tt .GE} & Greater than or equal ('N' not set, 'Z' irrelevant) \\
446
3'h4 & {\tt .GT} & Greater than ('N' not set, 'Z' not set) \\
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3'h5 & {\tt .LT} & Less than ('N' set) \\
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3'h6 & {\tt .C} & Carry set\\
449
3'h7 & {\tt .V} & Overflow set\\
450
\end{tabular}
451
\caption{Conditions for conditional operand execution}\label{tbl:conditions}
452
\end{center}
453
\end{table}
454 24 dgisselq
There is no condition code for less than or equal, not C or not V.  Sorry,
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I ran out of space in 3--bits.  Conditioning on a non--supported condition
456
is still possible, but it will take an extra instruction and a pipeline stall.  (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})
457 21 dgisselq
 
458 36 dgisselq
Conditionally executed ALU instructions will not further adjust the
459
condition codes.
460
 
461 21 dgisselq
\section{Operand B}
462 24 dgisselq
Many instruction forms have a 21-bit source ``Operand B'' associated with them.
463 21 dgisselq
This Operand B is either equal to a register plus a signed immediate offset,
464
or an immediate offset by itself.  This value is encoded as shown in
465
Tbl.~\ref{tbl:opb}.
466
\begin{table}\begin{center}
467
\begin{tabular}{|l|l|l|}\hline
468
Bit 20 & 19 \ldots 16 & 15 \ldots 0 \\\hline
469 24 dgisselq
1'b0 & \multicolumn{2}{l|}{20--bit Signed Immediate value} \\\hline
470
1'b1 & 4-bit Register & 16--bit Signed immediate offset \\\hline
471 21 dgisselq
\end{tabular}
472
\caption{Bit allocation for Operand B}\label{tbl:opb}
473
\end{center}\end{table}
474 24 dgisselq
 
475 33 dgisselq
Sixteen and twenty bit immediate values don't make sense for all instructions.
476
For example, what is the point of a 20--bit immediate when executing a 16--bit
477 24 dgisselq
multiply?  Likewise, why have a 16--bit immediate when adding to a logical
478
or arithmetic shift?  In these cases, the extra bits are reserved for future
479
instruction possibilities.
480
 
481 21 dgisselq
\section{Address Modes}
482 36 dgisselq
The Zip CPU supports two addressing modes: register plus immediate, and
483 21 dgisselq
immediate address.  Addresses are therefore encoded in the same fashion as
484
Operand B's, shown above.
485
 
486
A lot of long hard thought was put into whether to allow pre/post increment
487
and decrement addressing modes.  Finding no way to use these operators without
488 32 dgisselq
taking two or more clocks per instruction,\footnote{The two clocks figure
489
comes from the design of the register set, allowing only one write per clock.
490
That write is either from the memory unit or the ALU, but never both.} these
491
addressing modes have been
492 21 dgisselq
removed from the realm of possibilities.  This means that the Zip CPU has no
493
native way of executing push, pop, return, or jump to subroutine operations.
494 24 dgisselq
Each of these instructions can be emulated with a set of instructions from the
495
existing set.
496 21 dgisselq
 
497
\section{Move Operands}
498
The previous set of operands would be perfect and complete, save only that
499 24 dgisselq
the CPU needs access to non--supervisory registers while in supervisory mode.
500
Therefore, the MOV instruction is special and offers access to these registers
501
\ldots when in supervisory mode.  To keep the compiler simple, the extra bits
502
are ignored in non-supervisory mode (as though they didn't exist), rather than
503
being mapped to new instructions or additional capabilities.  The bits
504
indicating which register set each register lies within are the A-Usr and
505
B-Usr bits.  When set to a one, these refer to a user mode register.  When set
506
to a zero, these refer to a register in the current mode, whether user or
507
supervisor.  Further, because a load immediate instruction exists, there is no
508
move capability between an immediate and a register: all moves come from either
509
a register or a register plus an offset.
510 21 dgisselq
 
511 24 dgisselq
This actually leads to a bit of a problem: since the MOV instruction encodes
512
which register set each register is coming from or moving to, how shall a
513
compiler or assembler know how to compile a MOV instruction without knowing
514
the mode of the CPU at the time?  For this reason, the compiler will assume
515
all MOV registers are supervisor registers, and display them as normal.
516
Anything with the user bit set will be treated as a user register.  The CPU
517
will quietly ignore the supervisor bits while in user mode, and anything
518 36 dgisselq
marked as a user register will always be valid.
519 21 dgisselq
 
520
\section{Multiply Operations}
521 36 dgisselq
The Zip CPU supports two Multiply operations, a 16x16 bit signed multiply
522
({\tt MPYS}) and a 16x16 bit unsigned multiply ({\tt MPYU}).  In both
523 21 dgisselq
cases, the operand is a register plus a 16-bit immediate, subject to the
524
rule that the register cannot be the PC or CC registers.  The PC register
525
field has been stolen to create a multiply by immediate instruction.  The
526
CC register field is reserved.
527
 
528
\section{Floating Point}
529 36 dgisselq
The Zip CPU does not (yet) support floating point operations.  However, the
530 32 dgisselq
instruction set reserves two possibilities for future floating point
531
operations.
532 21 dgisselq
 
533 32 dgisselq
The first floating point operation hole in the instruction set involves
534 36 dgisselq
setting a proposed (but non-existent) floating point bit in the CC register.
535
The next instruction
536
would then simply interpret its operands as floating point instructions.
537 32 dgisselq
Not all instructions, however, have floating point equivalents.  Further, the
538
immediate fields do not apply in floating point mode, and must be set to
539
zero.  Not all instructions make sense as floating point operations.
540
Therefore, only the CMP, SUB, ADD, and MPY instructions may be issued as
541
floating point instructions.  Other instructions allow the examining of the
542
floating point bit in the CC register.  In all cases, the floating point bit
543
is cleared one instruction after it is set.
544 21 dgisselq
 
545 32 dgisselq
The other possibility for floating point operations involves exploiting the
546
hole in the instruction set that the NOOP and BREAK instructions reside within.
547 36 dgisselq
These two instructions use 24--bits of address space, when only a single bit
548
is necessary.  A simple adjustment to this space could create instructions
549
with 4--bit register addresses for each register, a 3--bit field for
550
conditional execution, and a 2--bit field for which operation.
551
In this fashion, such a floating point capability would only fill 13--bits of
552
the 24--bit field, still leaving lots of room for expansion.
553 32 dgisselq
 
554
In both cases, the Zip CPU would support 32--bit single precision floats
555 36 dgisselq
only, since other choices would complicate the pipeline.
556 32 dgisselq
 
557
The current architecture does not support a floating point not-implemented
558
interrupt.  Any soft floating point emulation must be done deliberately.
559
 
560 21 dgisselq
\section{Native Instructions}
561
The instruction set for the Zip CPU is summarized in
562
Tbl.~\ref{tbl:zip-instructions}.
563
\begin{table}\begin{center}
564
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline
565 36 dgisselq
\rowcolor[gray]{0.85}
566 21 dgisselq
Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}
567
        & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}
568 36 dgisselq
        & Sets CC? \\\hline\hline
569 39 dgisselq
{\tt CMP(Sub)} & \multicolumn{4}{l|}{4'h0}
570 21 dgisselq
                & \multicolumn{4}{l|}{D. Reg}
571
                & \multicolumn{3}{l|}{Cond.}
572
                & \multicolumn{21}{l|}{Operand B}
573
                & Yes \\\hline
574 39 dgisselq
{\tt TST(And)} & \multicolumn{4}{l|}{4'h1}
575 21 dgisselq
                & \multicolumn{4}{l|}{D. Reg}
576
                & \multicolumn{3}{l|}{Cond.}
577
                & \multicolumn{21}{l|}{Operand B}
578
        & Yes \\\hline
579 39 dgisselq
{\tt MOV} & \multicolumn{4}{l|}{4'h2}
580 21 dgisselq
                & \multicolumn{4}{l|}{D. Reg}
581
                & \multicolumn{3}{l|}{Cond.}
582
                & A-Usr
583
                & \multicolumn{4}{l|}{B-Reg}
584
                & B-Usr
585
                & \multicolumn{15}{l|}{15'bit signed offset}
586
                & \\\hline
587 39 dgisselq
{\tt LODI} & \multicolumn{4}{l|}{4'h3}
588 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
589
                & \multicolumn{24}{l|}{24'bit Signed Immediate}
590
                & \\\hline
591 39 dgisselq
{\tt NOOP} & \multicolumn{4}{l|}{4'h4}
592 21 dgisselq
                & \multicolumn{4}{l|}{4'he}
593
                & \multicolumn{24}{l|}{24'h00}
594
                & \\\hline
595 39 dgisselq
{\tt BREAK} & \multicolumn{4}{l|}{4'h4}
596 21 dgisselq
                & \multicolumn{4}{l|}{4'he}
597
                & \multicolumn{24}{l|}{24'h01}
598
                & \\\hline
599 36 dgisselq
{\em Reserved} & \multicolumn{4}{l|}{4'h4}
600 21 dgisselq
                & \multicolumn{4}{l|}{4'he}
601
                & \multicolumn{24}{l|}{24'bits, but not 0 or 1.}
602
                & \\\hline
603 39 dgisselq
{\tt LODIHI }& \multicolumn{4}{l|}{4'h4}
604 21 dgisselq
                & \multicolumn{4}{l|}{4'hf}
605
                & \multicolumn{3}{l|}{Cond.}
606
                & 1'b1
607
                & \multicolumn{4}{l|}{R. Reg}
608
                & \multicolumn{16}{l|}{16-bit Immediate}
609
                & \\\hline
610 39 dgisselq
{\tt LODILO} & \multicolumn{4}{l|}{4'h4}
611 21 dgisselq
                & \multicolumn{4}{l|}{4'hf}
612
                & \multicolumn{3}{l|}{Cond.}
613
                & 1'b0
614
                & \multicolumn{4}{l|}{R. Reg}
615
                & \multicolumn{16}{l|}{16-bit Immediate}
616
                & \\\hline
617 39 dgisselq
16-b {\tt MPYU} & \multicolumn{4}{l|}{4'h4}
618 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
619
                & \multicolumn{3}{l|}{Cond.}
620
                & 1'b0 & \multicolumn{4}{l|}{Reg}
621
                & \multicolumn{16}{l|}{16-bit Offset}
622
                & Yes \\\hline
623 39 dgisselq
16-b {\tt MPYU}(I) & \multicolumn{4}{l|}{4'h4}
624 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
625
                & \multicolumn{3}{l|}{Cond.}
626
                & 1'b0 & \multicolumn{4}{l|}{4'hf}
627
                & \multicolumn{16}{l|}{16-bit Offset}
628
                & Yes \\\hline
629 39 dgisselq
16-b {\tt MPYS} & \multicolumn{4}{l|}{4'h4}
630 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
631
                & \multicolumn{3}{l|}{Cond.}
632
                & 1'b1 & \multicolumn{4}{l|}{Reg}
633
                & \multicolumn{16}{l|}{16-bit Offset}
634
                & Yes \\\hline
635 39 dgisselq
16-b {\tt MPYS}(I) & \multicolumn{4}{l|}{4'h4}
636 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
637
                & \multicolumn{3}{l|}{Cond.}
638
                & 1'b1 & \multicolumn{4}{l|}{4'hf}
639
                & \multicolumn{16}{l|}{16-bit Offset}
640
                & Yes \\\hline
641 39 dgisselq
{\tt ROL} & \multicolumn{4}{l|}{4'h5}
642 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
643
                & \multicolumn{3}{l|}{Cond.}
644
                & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}
645
                & \\\hline
646 39 dgisselq
{\tt LOD} & \multicolumn{4}{l|}{4'h6}
647 21 dgisselq
                & \multicolumn{4}{l|}{R. Reg}
648
                & \multicolumn{3}{l|}{Cond.}
649
                & \multicolumn{21}{l|}{Operand B address}
650
                & \\\hline
651 39 dgisselq
{\tt STO} & \multicolumn{4}{l|}{4'h7}
652 21 dgisselq
                & \multicolumn{4}{l|}{D. Reg}
653
                & \multicolumn{3}{l|}{Cond.}
654
                & \multicolumn{21}{l|}{Operand B address}
655
                & \\\hline
656 39 dgisselq
{\tt SUB} & \multicolumn{4}{l|}{4'h8}
657 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
658
        &       \multicolumn{3}{l|}{Cond.}
659 32 dgisselq
        &       \multicolumn{21}{l|}{Operand B}
660 21 dgisselq
        & Yes \\\hline
661 39 dgisselq
{\tt AND} & \multicolumn{4}{l|}{4'h9}
662 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
663
        &       \multicolumn{3}{l|}{Cond.}
664
        &       \multicolumn{21}{l|}{Operand B}
665
        & Yes \\\hline
666 39 dgisselq
{\tt ADD} & \multicolumn{4}{l|}{4'ha}
667 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
668
        &       \multicolumn{3}{l|}{Cond.}
669
        &       \multicolumn{21}{l|}{Operand B}
670
        & Yes \\\hline
671 39 dgisselq
{\tt OR} & \multicolumn{4}{l|}{4'hb}
672 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
673
        &       \multicolumn{3}{l|}{Cond.}
674
        &       \multicolumn{21}{l|}{Operand B}
675
        & Yes \\\hline
676 39 dgisselq
{\tt XOR} & \multicolumn{4}{l|}{4'hc}
677 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
678
        &       \multicolumn{3}{l|}{Cond.}
679
        &       \multicolumn{21}{l|}{Operand B}
680
        & Yes \\\hline
681 39 dgisselq
{\tt LSL/ASL} & \multicolumn{4}{l|}{4'hd}
682 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
683
        &       \multicolumn{3}{l|}{Cond.}
684 33 dgisselq
        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
685 21 dgisselq
        & Yes \\\hline
686 39 dgisselq
{\tt ASR} & \multicolumn{4}{l|}{4'he}
687 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
688
        &       \multicolumn{3}{l|}{Cond.}
689 33 dgisselq
        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
690 21 dgisselq
        & Yes \\\hline
691 39 dgisselq
{\tt LSR} & \multicolumn{4}{l|}{4'hf}
692 21 dgisselq
        &       \multicolumn{4}{l|}{R. Reg}
693
        &       \multicolumn{3}{l|}{Cond.}
694 33 dgisselq
        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}
695 21 dgisselq
        & Yes \\\hline
696
\end{tabular}
697
\caption{Zip CPU Instruction Set}\label{tbl:zip-instructions}
698
\end{center}\end{table}
699
 
700
As you can see, there's lots of room for instruction set expansion.  The
701 24 dgisselq
NOOP and BREAK instructions are the only instructions within one particular
702 36 dgisselq
24--bit hole.  The rest of this space is reserved for future enhancements.
703 21 dgisselq
 
704
\section{Derived Instructions}
705 36 dgisselq
The Zip CPU supports many other common instructions, but not all of them
706 24 dgisselq
are single cycle instructions.  The derived instruction tables,
707 36 dgisselq
Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, \ref{tbl:derived-3}
708
and~\ref{tbl:derived-4},
709 21 dgisselq
help to capture some of how these other instructions may be implemented on
710 36 dgisselq
the Zip CPU.  Many of these instructions will have assembly equivalents,
711 21 dgisselq
such as the branch instructions, to facilitate working with the CPU.
712
\begin{table}\begin{center}
713
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
714
Mapped & Actual  & Notes \\\hline
715 39 dgisselq
{\tt ABS Rx}
716
        & \parbox[t]{1.5in}{\tt TST -1,Rx\\NEG.LT Rx}
717 36 dgisselq
        & Absolute value, depends upon derived NEG.\\\hline
718 39 dgisselq
\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
719
        & \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
720 21 dgisselq
        & Add with carry \\\hline
721 39 dgisselq
{\tt BRA.Cond +/-\$Addr}
722
        & \hbox{\tt MOV.cond \$Addr+PC,PC}
723 24 dgisselq
        & Branch or jump on condition.  Works for 15--bit
724
                signed address offsets.\\\hline
725 39 dgisselq
{\tt BRA.Cond +/-\$Addr}
726
        & \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
727 21 dgisselq
        & Branch/jump on condition.  Works for
728
        23 bit address offsets, but costs a register, an extra instruction,
729 33 dgisselq
        and sets the flags. \\\hline
730 39 dgisselq
{\tt BNC PC+\$Addr}
731
        & \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
732 21 dgisselq
        & Example of a branch on an unsupported
733
                condition, in this case a branch on not carry \\\hline
734 39 dgisselq
{\tt BUSY } & {\tt MOV \$-1(PC),PC} & Execute an infinite loop \\\hline
735
{\tt CLRF.NZ Rx }
736
        & {\tt XOR.NZ Rx,Rx}
737 21 dgisselq
        & Clear Rx, and flags, if the Z-bit is not set \\\hline
738 39 dgisselq
{\tt CLR Rx }
739
        & {\tt LDI \$0,Rx}
740 21 dgisselq
        & Clears Rx, leaves flags untouched.  This instruction cannot be
741
                conditional. \\\hline
742 39 dgisselq
{\tt EXCH.W Rx }
743
        & {\tt ROL \$16,Rx}
744 21 dgisselq
        & Exchanges the top and bottom 16'bit words of Rx \\\hline
745 39 dgisselq
{\tt HALT }
746
        & {\tt Or \$SLEEP,CC}
747
        & This only works when issued in interrupt/supervisor mode.  In user
748
        mode this is simply a wait until interrupt instruction. \\\hline
749
{\tt INT } & {\tt LDI \$0,CC} &  \\\hline
750
{\tt IRET}
751
        & {\tt OR \$GIE,CC}
752
        & Also known as an RTU instruction (Return to Userspace) \\\hline
753
{\tt JMP R6+\$Addr}
754
        & {\tt MOV \$Addr(R6),PC}
755 21 dgisselq
        & \\\hline
756 39 dgisselq
{\tt JSR PC+\$Addr}
757
        & \parbox[t]{1.5in}{\tt SUB \$1,SP \\\
758 21 dgisselq
        MOV \$3+PC,R0 \\
759
        STO R0,1(SP) \\
760
        MOV \$Addr+PC,PC \\
761
        ADD \$1,SP}
762 24 dgisselq
        & Jump to Subroutine. Note the required cleanup instruction after
763 36 dgisselq
        returning.  This could easily be turned into a three instruction
764
        operand, removing the preliminary stack instruction before and
765
        the cleanup after, by adjusting how any stack frame was built for
766
        this routine to include space at the top of the stack for the PC.
767 39 dgisselq
        Note also that jumping to a subroutine costs a copy register, {\tt R0}
768
        in this case.
769 36 dgisselq
        \\\hline
770 39 dgisselq
{\tt JSR PC+\$Addr  }
771
        & \parbox[t]{1.5in}{\tt MOV \$3+PC,R12 \\ MOV \$addr+PC,PC}
772 21 dgisselq
        &This is the high speed
773
        version of a subroutine call, necessitating a register to hold the
774
        last PC address.  In its favor, this method doesn't suffer the
775
        mandatory memory access of the other approach. \\\hline
776 39 dgisselq
{\tt LDI.l \$val,Rx }
777
        & \parbox[t]{1.8in}{\tt LDIHI (\$val$>>$16)\&0x0ffff, Rx \\
778
                        LDILO (\$val\&0x0ffff),Rx}
779 21 dgisselq
        & Sadly, there's not enough instruction
780
                space to load a complete immediate value into any register.
781
                Therefore, fully loading any register takes two cycles.
782
                The LDIHI (load immediate high) and LDILO (load immediate low)
783
                instructions have been created to facilitate this. \\\hline
784
\end{tabular}
785
\caption{Derived Instructions}\label{tbl:derived-1}
786
\end{center}\end{table}
787
\begin{table}\begin{center}
788
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
789
Mapped & Actual  & Notes \\\hline
790 39 dgisselq
{\tt LOD.b \$addr,Rx}
791
        & \parbox[t]{1.5in}{\tt %
792 21 dgisselq
        LDI     \$addr,Ra \\
793
        LDI     \$addr,Rb \\
794
        LSR     \$2,Ra \\
795
        AND     \$3,Rb \\
796
        LOD     (Ra),Rx \\
797
        LSL     \$3,Rb \\
798
        SUB     \$32,Rb \\
799
        ROL     Rb,Rx \\
800
        AND \$0ffh,Rx}
801
        & \parbox[t]{3in}{This CPU is designed for 32'bit word
802
        length instructions.  Byte addressing is not supported by the CPU or
803
        the bus, so it therefore takes more work to do.
804
 
805
        Note also that in this example, \$Addr is a byte-wise address, where
806 24 dgisselq
        all other addresses in this document are 32-bit wordlength addresses.
807
        For this reason,
808 21 dgisselq
        we needed to drop the bottom two bits.  This also limits the address
809
        space of character accesses using this method from 16 MB down to 4MB.}
810
                \\\hline
811 39 dgisselq
\parbox[t]{1.5in}{\tt LSL \$1,Rx\\ LSLC \$1,Ry}
812
        & \parbox[t]{1.5in}{\tt LSL \$1,Ry \\
813 21 dgisselq
        LSL \$1,Rx \\
814
        OR.C \$1,Ry}
815
        & Logical shift left with carry.  Note that the
816
        instruction order is now backwards, to keep the conditions valid.
817 33 dgisselq
        That is, LSL sets the carry flag, so if we did this the other way
818 21 dgisselq
        with Rx before Ry, then the condition flag wouldn't have been right
819
        for an OR correction at the end. \\\hline
820 39 dgisselq
\parbox[t]{1.5in}{\tt LSR \$1,Rx \\ LSRC \$1,Ry}
821
        & \parbox[t]{1.5in}{\tt CLR Rz \\
822 21 dgisselq
        LSR \$1,Ry \\
823
        LDIHI.C \$8000h,Rz \\
824
        LSR \$1,Rx \\
825
        OR Rz,Rx}
826
        & Logical shift right with carry \\\hline
827 39 dgisselq
{\tt NEG Rx} & \parbox[t]{1.5in}{\tt XOR \$-1,Rx \\ ADD \$1,Rx} & \\\hline
828
{\tt NEG.C Rx} & \parbox[t]{1.5in}{\tt MOV.C \$-1+Rx,Rx\\XOR.C \$-1,Rx} & \\\hline
829
{\tt NOOP} & {\tt NOOP} & While there are many
830 21 dgisselq
        operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these
831
        operations have consequences in that they might stall the bus if
832
        Rx isn't ready yet.  For this reason, we have a dedicated NOOP
833
        instruction. \\\hline
834 39 dgisselq
{\tt NOT Rx } & {\tt XOR \$-1,Rx } & \\\hline
835
{\tt POP Rx }
836
        & \parbox[t]{1.5in}{\tt LOD \$1(SP),Rx \\ ADD \$1,SP}
837 21 dgisselq
        & Note
838
        that for interrupt purposes, one can never depend upon the value at
839
        (SP).  Hence you read from it, then increment it, lest having
840 33 dgisselq
        incremented it first something then comes along and writes to that
841 21 dgisselq
        value before you can read the result. \\\hline
842 36 dgisselq
\end{tabular}
843
\caption{Derived Instructions, continued}\label{tbl:derived-2}
844
\end{center}\end{table}
845
\begin{table}\begin{center}
846
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
847 39 dgisselq
{\tt PUSH Rx}
848 33 dgisselq
        & \parbox[t]{1.5in}{SUB \$1,SP \\
849 21 dgisselq
        STO Rx,\$1(SP)}
850 39 dgisselq
        & Note that for pipelined operation, it helps to coalesce all the
851
        {\tt SUB}'s into one command, and place the {\tt STO}'s right
852
        after each other.\\\hline
853
{\tt PUSH Rx-Ry}
854
        & \parbox[t]{1.5in}{\tt SUB \$n,SP \\
855 36 dgisselq
        STO Rx,\$n(SP)
856
        \ldots \\
857
        STO Ry,\$1(SP)}
858
        & Multiple pushes at once only need the single subtract from the
859
        stack pointer.  This derived instruction is analogous to a similar one
860
        on the Motoroloa 68k architecture, although the Zip Assembler
861 39 dgisselq
        does not support this instruction (yet).  This instruction
862
        also supports pipelined memory access.\\\hline
863
{\tt RESET}
864
        & \parbox[t]{1in}{\tt STO \$1,\$watchdog(R12)\\NOOP\\NOOP}
865
        & This depends upon the peripheral base address being
866 21 dgisselq
        in R12.
867
 
868
        Another opportunity might be to jump to the reset address from within
869 39 dgisselq
        supervisor mode.\\\hline
870
{\tt RET} & \parbox[t]{1.5in}{\tt LOD \$1(SP),PC}
871 24 dgisselq
        & Note that this depends upon the calling context to clean up the
872
        stack, as outlined for the JSR instruction.  \\\hline
873 39 dgisselq
{\tt RET} & {\tt MOV R12,PC}
874 21 dgisselq
        & This is the high(er) speed version, that doesn't touch the stack.
875
        As such, it doesn't suffer a stall on memory read/write to the stack.
876
        \\\hline
877 39 dgisselq
{\tt STEP Rr,Rt}
878
        & \parbox[t]{1.5in}{\tt LSR \$1,Rr \\ XOR.C Rt,Rr}
879 21 dgisselq
        & Step a Galois implementation of a Linear Feedback Shift Register, Rr,
880
                using taps Rt \\\hline
881 39 dgisselq
{\tt STO.b Rx,\$addr}
882
        & \parbox[t]{1.5in}{\tt %
883 21 dgisselq
        LDI \$addr,Ra \\
884
        LDI \$addr,Rb \\
885
        LSR \$2,Ra \\
886
        AND \$3,Rb \\
887
        SUB \$32,Rb \\
888
        LOD (Ra),Ry \\
889
        AND \$0ffh,Rx \\
890 39 dgisselq
        AND \~\$0ffh,Ry \\
891 21 dgisselq
        ROL Rb,Rx \\
892
        OR Rx,Ry \\
893
        STO Ry,(Ra) }
894
        & \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized
895
        for byte-wise operations.
896
 
897
        Note that in this example, \$addr is a
898
        byte-wise address, whereas in all of our other examples it is a
899
        32-bit word address. This also limits the address space
900
        of character accesses from 16 MB down to 4MB.F
901
        Further, this instruction implies a byte ordering,
902
        such as big or little endian.} \\\hline
903 39 dgisselq
{\tt SWAP Rx,Ry }
904
        & \parbox[t]{1.5in}{\tt
905 21 dgisselq
        XOR Ry,Rx \\
906
        XOR Rx,Ry \\
907
        XOR Ry,Rx}
908
        & While no extra registers are needed, this example
909
        does take 3-clocks. \\\hline
910 39 dgisselq
{\tt TRAP \#X}
911
        & \parbox[t]{1.5in}{\tt LDI \$x,R0 \\ AND \~\$GIE,CC }
912 36 dgisselq
        & This works because whenever a user lowers the \$GIE flag, it sets
913
        a TRAP bit within the CC register.  Therefore, upon entering the
914
        supervisor state, the CPU only need check this bit to know that it
915
        got there via a TRAP.  The trap could be made conditional by making
916
        the LDI and the AND conditional.  In that case, the assembler would
917
        quietly turn the LDI instruction into an LDILO and LDIHI pair,
918 37 dgisselq
        but the effect would be the same. \\\hline
919 36 dgisselq
\end{tabular}
920
\caption{Derived Instructions, continued}\label{tbl:derived-3}
921
\end{center}\end{table}
922
\begin{table}\begin{center}
923
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
924 39 dgisselq
{\tt TST Rx}
925
        & {\tt TST \$-1,Rx}
926 21 dgisselq
        & Set the condition codes based upon Rx.  Could also do a CMP \$0,Rx,
927
        ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc.  The TST and CMP
928
        approaches won't stall future pipeline stages looking for the value
929
        of Rx. \\\hline
930 39 dgisselq
{\tt WAIT}
931
        & {\tt Or \$GIE | \$SLEEP,CC}
932
        & Wait until the next interrupt, then jump to supervisor/interrupt
933
        mode.
934 21 dgisselq
\end{tabular}
935 36 dgisselq
\caption{Derived Instructions, continued}\label{tbl:derived-4}
936 21 dgisselq
\end{center}\end{table}
937
\section{Pipeline Stages}
938 32 dgisselq
As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},
939
the Zip CPU supports a five stage pipeline.
940 21 dgisselq
\begin{enumerate}
941 36 dgisselq
\item {\bf Prefetch}: Reads instruction from memory and into a cache, if so
942
        configured.  This
943 21 dgisselq
        stage is actually pipelined itself, and so it will stall if the PC
944
        ever changes.  Stalls are also created here if the instruction isn't
945
        in the prefetch cache.
946 36 dgisselq
 
947
        The Zip CPU supports one of two prefetch methods, depending upon a flag
948
        set at build time within the {\tt zipcpu.v} file.  The simplest is a
949
        non--cached implementation of a prefetch.  This implementation is
950
        fairly small, and ideal for
951
        users of the Zip CPU who need the extra space on the FPGA fabric.
952
        However, because this non--cached version has no cache, the maximum
953
        number of instructions per clock is limited to about one per five.
954
 
955
        The second prefetch module is a pipelined prefetch with a cache.  This
956
        module tries to keep the instruction address within a window of valid
957
        instruction addresses.  While effective, it is not a traditional
958
        cache implementation.  One unique feature of this cache implementation,
959
        however, is that it can be cleared in a single clock.  A disappointing
960
        feature, though, was that it needs an extra internal pipeline stage
961
        to be implemented.
962
 
963
\item {\bf Decode}: Decodes an instruction into op code, register(s) to read,
964
        and immediate offset.  This stage also determines whether the flags will
965 32 dgisselq
        be set or whether the result will be written back.
966 21 dgisselq
\item {\bf Read Operands}: Read registers and apply any immediate values to
967 24 dgisselq
        them.  There is no means of detecting or flagging arithmetic overflow
968
        or carry when adding the immediate to the operand.  This stage will
969
        stall if any source operand is pending.
970 21 dgisselq
\item Split into two tracks: An {\bf ALU} which will accomplish a simple
971 36 dgisselq
        instruction, and the {\bf MemOps} stage which handles {\tt LOD} (load)
972
        and {\tt STO} (store) instructions.
973 21 dgisselq
        \begin{itemize}
974 36 dgisselq
        \item Loads will stall the entire pipeline until complete.
975
        \item Condition codes are available upon completion of the ALU stage
976
        \item Issuing an instruction to the memory unit while the memory unit
977
                is busy will stall the entire pipeline.  If the bus deadlocks,
978
                only a reset will release the CPU.  (Watchdog timer, anyone?)
979 24 dgisselq
        \item The Zip CPU currently has no means of reading and acting on any
980
        error conditions on the bus.
981 21 dgisselq
        \end{itemize}
982 32 dgisselq
\item {\bf Write-Back}: Conditionally write back the result to the register
983 36 dgisselq
        set, applying the condition.  This routine is bi-entrant: either the
984 21 dgisselq
        memory or the simple instruction may request a register write.
985
\end{enumerate}
986
 
987 24 dgisselq
The Zip CPU does not support out of order execution.  Therefore, if the memory
988
unit stalls, every other instruction stalls.  Memory stores, however, can take
989 36 dgisselq
place concurrently with ALU operations, although memory reads (loads) cannot.
990 24 dgisselq
 
991 32 dgisselq
\section{Pipeline Stalls}
992
The processing pipeline can and will stall for a variety of reasons.  Some of
993
these are obvious, some less so.  These reasons are listed below:
994
\begin{itemize}
995
\item When the prefetch cache is exhausted
996 21 dgisselq
 
997 36 dgisselq
This reason should be obvious.  If the prefetch cache doesn't have the
998
instruction in memory, the entire pipeline must stall until enough of the
999
prefetch cache is loaded to support the next instruction.
1000 21 dgisselq
 
1001 32 dgisselq
\item While waiting for the pipeline to load following any taken branch, jump,
1002 36 dgisselq
        return from interrupt or switch to interrupt context (5 stall cycles)
1003 32 dgisselq
 
1004
If the PC suddenly changes, the pipeline is subsequently cleared and needs to
1005
be reloaded.  Given that there are five stages to the pipeline, that accounts
1006 36 dgisselq
for four of the five stalls.  The stall cycle is lost in the pipelined prefetch
1007 32 dgisselq
stage which needs at least one clock with a valid PC before it can produce
1008 36 dgisselq
a new output.
1009 32 dgisselq
 
1010 36 dgisselq
The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and
1011
{\tt LDI \$X,PC} instructions specially, however.  These instructions, when
1012
not conditioned on the flags, can execute with only 3~stall cycles.
1013
 
1014 32 dgisselq
\item When reading from a prior register while also adding an immediate offset
1015
\begin{enumerate}
1016
\item\ {\tt OPCODE ?,RA}
1017
\item\ {\em (stall)}
1018
\item\ {\tt OPCODE I+RA,RB}
1019
\end{enumerate}
1020
 
1021
Since the addition of the immediate register within OpB decoding gets applied
1022
during the read operand stage so that it can be nicely settled before the ALU,
1023
any instruction that will write back an operand must be separated from the
1024
opcode that will read and apply an immediate offset by one instruction.  The
1025
good news is that this stall can easily be mitigated by proper scheduling.
1026 36 dgisselq
That is, any instruction that does not add an immediate to {\tt RA} may be
1027
scheduled into the stall slot.
1028 32 dgisselq
 
1029 36 dgisselq
\item When any write to either the CC or PC Register is followed by a memory
1030
        operation
1031 32 dgisselq
\begin{enumerate}
1032
\item\ {\tt OPCODE RA,PC} {\em Ex: a branch opcode}
1033
\item\ {\em (stall, even if jump not taken)}
1034 36 dgisselq
\item\ {\tt LOD \$X(RA),RB}
1035 32 dgisselq
\end{enumerate}
1036
Since branches take place in the writeback stage, the Zip CPU will stall the
1037
pipeline for one clock anytime there may be a possible jump.  This prevents
1038
an instruction from executing a memory access after the jump but before the
1039
jump is recognized.
1040
 
1041 36 dgisselq
This stall may be mitigated by shuffling the operations immediately following
1042
a potential branch so that an ALU operation follows the branch instead of a
1043
memory operation.
1044 33 dgisselq
 
1045 32 dgisselq
\item When reading from the CC register after setting the flags
1046
\begin{enumerate}
1047 36 dgisselq
\item\ {\tt ALUOP RA,RB} {\em Ex: a compare opcode}
1048
\item\ {\em (stall)}
1049 32 dgisselq
\item\ {\tt TST sys.ccv,CC}
1050
\item\ {\tt BZ somewhere}
1051
\end{enumerate}
1052
 
1053
The reason for this stall is simply performance.  Many of the flags are
1054
determined via combinatorial logic after the writeback instruction is
1055
determined.  Trying to then place these into the input for one of the operands
1056
created a time delay loop that would no longer execute in a single 100~MHz
1057
clock cycle.  (The time delay of the multiply within the ALU wasn't helping
1058
either \ldots).
1059
 
1060 33 dgisselq
This stall may be eliminated via proper scheduling, by placing an instruction
1061
that does not set flags in between the ALU operation and the instruction
1062
that references the CC register.  For example, {\tt MOV \$addr+PC,uPC}
1063
followed by an {\tt RTU} ({\tt OR \$GIE,CC}) instruction will not incur
1064
this stall, whereas an {\tt OR \$BREAKEN,CC} followed by an {\tt OR \$STEP,CC}
1065 36 dgisselq
will incur the stall, while a {\tt LDI \$BREAKEN|\$STEP,CC} will not.
1066 33 dgisselq
 
1067 32 dgisselq
\item When waiting for a memory read operation to complete
1068
\begin{enumerate}
1069
\item\ {\tt LOD address,RA}
1070 36 dgisselq
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
1071 32 dgisselq
\item\ {\tt OPCODE I+RA,RB}
1072
\end{enumerate}
1073
 
1074 36 dgisselq
Remember, the Zip CPU does not support out of order execution.  Therefore,
1075 32 dgisselq
anytime the memory unit becomes busy both the memory unit and the ALU must
1076
stall until the memory unit is cleared.  This is especially true of a load
1077 33 dgisselq
instruction, which must still write its operand back to the register file.
1078
Store instructions are different, since they can be busy with no impact on
1079
later ALU write back operations.  Hence, only loads stall the pipeline.
1080 32 dgisselq
 
1081
This also assumes that the memory being accessed is a single cycle memory.
1082
Slower memories, such as the Quad SPI flash, will take longer--perhaps even
1083 33 dgisselq
as long as forty clocks.   During this time the CPU and the external bus
1084 32 dgisselq
will be busy, and unable to do anything else.
1085
 
1086
\item Memory operation followed by a memory operation
1087
\begin{enumerate}
1088
\item\ {\tt STO address,RA}
1089 36 dgisselq
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
1090 32 dgisselq
\item\ {\tt LOD address,RB}
1091 36 dgisselq
\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
1092 32 dgisselq
\end{enumerate}
1093
 
1094 36 dgisselq
In this case, the LOD instruction cannot start until the STO is finished.
1095 32 dgisselq
With proper scheduling, it is possible to do something in the ALU while the
1096 36 dgisselq
memory unit is busy with the STO instruction, but otherwise this pipeline will
1097
stall waiting for it to complete.
1098 32 dgisselq
 
1099 39 dgisselq
The Zip CPU does have the capability of supporting pipelined memory access,
1100
but only under the following conditions: all accesses within the pipeline
1101
must all be reads or all be writes, all must use the same register for their
1102
address, and there can be no stalls or other instructions between pipelined
1103
memory access instructions.  Further, the offset to memory must be increasing
1104
by one address each instruction.  These conditions work well for saving or
1105
storing registers to the stack.
1106 36 dgisselq
 
1107
\item When waiting for a conditional memory read operation to complete
1108
\begin{enumerate}
1109
\item\ {\tt LOD.Z address,RA}
1110
\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
1111
\item\ {\tt OPCODE I+RA,RB}
1112
\end{enumerate}
1113
 
1114
In this case, the Zip CPU doesn't warn the prefetch cache to get off the bus
1115
two cycles before using the bus, so there's a potential for an extra three
1116
cycle cost due to bus contention between the prefetch and the CPU.
1117
 
1118
This is true for both the LOD and the STO instructions, with the exception that
1119
the STO instruction will continue in parallel with any ALU instructions that
1120
follow it.
1121
 
1122 32 dgisselq
\end{itemize}
1123
 
1124
 
1125 21 dgisselq
\chapter{Peripherals}\label{chap:periph}
1126 24 dgisselq
 
1127
While the previous chapter describes a CPU in isolation, the Zip System
1128
includes a minimum set of peripherals as well.  These peripherals are shown
1129
in Fig.~\ref{fig:zipsystem}
1130
\begin{figure}\begin{center}
1131
\includegraphics[width=3.5in]{../gfx/system.eps}
1132
\caption{Zip System Peripherals}\label{fig:zipsystem}
1133
\end{center}\end{figure}
1134
and described here.  They are designed to make
1135
the Zip CPU more useful in an Embedded Operating System environment.
1136
 
1137 21 dgisselq
\section{Interrupt Controller}
1138 24 dgisselq
 
1139
Perhaps the most important peripheral within the Zip System is the interrupt
1140
controller.  While the Zip CPU itself can only handle one interrupt, and has
1141
only the one interrupt state: disabled or enabled, the interrupt controller
1142
can make things more interesting.
1143
 
1144
The Zip System interrupt controller module supports up to 15 interrupts, all
1145
controlled from one register.  Bit~31 of the interrupt controller controls
1146
overall whether interrupts are enabled (1'b1) or disabled (1'b0).  Bits~16--30
1147
control whether individual interrupts are enabled (1'b0) or disabled (1'b0).
1148
Bit~15 is an indicator showing whether or not any interrupt is active, and
1149
bits~0--15 indicate whether or not an individual interrupt is active.
1150
 
1151
The interrupt controller has been designed so that bits can be controlled
1152
individually without having any knowledge of the rest of the controller
1153
setting.  To enable an interrupt, write to the register with the high order
1154
global enable bit set and the respective interrupt enable bit set.  No other
1155
bits will be affected.  To disable an interrupt, write to the register with
1156
the high order global enable bit cleared and the respective interrupt enable
1157
bit set.  To clear an interrupt, write a `1' to that interrupts status pin.
1158
Zero's written to the register have no affect, save that a zero written to the
1159
master enable will disable all interrupts.
1160
 
1161
As an example, suppose you wished to enable interrupt \#4.  You would then
1162
write to the register a {\tt 0x80100010} to enable interrupt \#4 and to clear
1163
any past active state.  When you later wish to disable this interrupt, you would
1164
write a {\tt 0x00100010} to the register.  As before, this both disables the
1165
interrupt and clears the active indicator.  This also has the side effect of
1166
disabling all interrupts, so a second write of {\tt 0x80000000} may be necessary
1167
to re-enable any other interrupts.
1168
 
1169
The Zip System currently hosts two interrupt controllers, a primary and a
1170
secondary.  The primary interrupt controller has one interrupt line which may
1171
come from an external interrupt controller, and one interrupt line from the
1172
secondary controller.  Other primary interrupts include the system timers,
1173
the jiffies interrupt, and the manual cache interrupt.  The secondary interrupt
1174
controller maintains an interrupt state for all of the processor accounting
1175
counters.
1176
 
1177 21 dgisselq
\section{Counter}
1178
 
1179
The Zip Counter is a very simple counter: it just counts.  It cannot be
1180
halted.  When it rolls over, it issues an interrupt.  Writing a value to the
1181
counter just sets the current value, and it starts counting again from that
1182
value.
1183
 
1184
Eight counters are implemented in the Zip System for process accounting.
1185
This may change in the future, as nothing as yet uses these counters.
1186
 
1187
\section{Timer}
1188
 
1189
The Zip Timer is also very simple: it simply counts down to zero.  When it
1190
transitions from a one to a zero it creates an interrupt.
1191
 
1192
Writing any non-zero value to the timer starts the timer.  If the high order
1193
bit is set when writing to the timer, the timer becomes an interval timer and
1194
reloads its last start time on any interrupt.  Hence, to mark seconds, one
1195
might set the timer to 100~million (the number of clocks per second), and
1196
set the high bit.  Ever after, the timer will interrupt the CPU once per
1197 24 dgisselq
second (assuming a 100~MHz clock).  This reload capability also limits the
1198
maximum timer value to $2^{31}-1$, rather than $2^{32}-1$.
1199 21 dgisselq
 
1200
\section{Watchdog Timer}
1201
 
1202
The watchdog timer is no different from any of the other timers, save for one
1203
critical difference: the interrupt line from the watchdog
1204
timer is tied to the reset line of the CPU.  Hence writing a `1' to the
1205
watchdog timer will always reset the CPU.
1206 32 dgisselq
To stop the Watchdog timer, write a `0' to it.  To start it,
1207 21 dgisselq
write any other number to it---as with the other timers.
1208
 
1209
While the watchdog timer supports interval mode, it doesn't make as much sense
1210
as it did with the other timers.
1211
 
1212
\section{Jiffies}
1213
 
1214
This peripheral is motivated by the Linux use of `jiffies' whereby a process
1215
can request to be put to sleep until a certain number of `jiffies' have
1216
elapsed.  Using this interface, the CPU can read the number of `jiffies'
1217
from the peripheral (it only has the one location in address space), add the
1218 24 dgisselq
sleep length to it, and write the result back to the peripheral.  The zipjiffies
1219 21 dgisselq
peripheral will record the value written to it only if it is nearer the current
1220
counter value than the last current waiting interrupt time.  If no other
1221
interrupts are waiting, and this time is in the future, it will be enabled.
1222
(There is currently no way to disable a jiffie interrupt once set, other
1223 24 dgisselq
than to disable the interrupt line in the interrupt controller.)  The processor
1224 21 dgisselq
may then place this sleep request into a list among other sleep requests.
1225
Once the timer expires, it would write the next Jiffy request to the peripheral
1226
and wake up the process whose timer had expired.
1227
 
1228
Indeed, the Jiffies register is nothing more than a glorified counter with
1229
an interrupt.  Unlike the other counters, the Jiffies register cannot be set.
1230
Writes to the jiffies register create an interrupt time.  When the Jiffies
1231
register later equals the value written to it, an interrupt will be asserted
1232
and the register then continues counting as though no interrupt had taken
1233
place.
1234
 
1235
The purpose of this register is to support alarm times within a CPU.  To
1236
set an alarm for a particular process $N$ clocks in advance, read the current
1237
Jiffies value, and $N$, and write it back to the Jiffies register.  The
1238
O/S must also keep track of values written to the Jiffies register.  Thus,
1239 32 dgisselq
when an `alarm' trips, it should be removed from the list of alarms, the list
1240 21 dgisselq
should be sorted, and the next alarm in terms of Jiffies should be written
1241
to the register.
1242
 
1243 36 dgisselq
\section{Direct Memory Access Controller}
1244 24 dgisselq
 
1245 36 dgisselq
The Direct Memory Access (DMA) controller can be used to either move memory
1246
from one location to another, to read from a peripheral into memory, or to
1247
write from a peripheral into memory all without CPU intervention.  Further,
1248
since the DMA controller can issue (and does issue) pipeline wishbone accesses,
1249
any DMA memory move will by nature be faster than a corresponding program
1250
accomplishing the same move.  To put this to numbers, it may take a program
1251
18~clocks per word transferred, whereas this DMA controller can move one
1252
word in two clocks--provided it has bus access.  (The CPU gets priority over the
1253
bus.)
1254 24 dgisselq
 
1255 36 dgisselq
When copying memory from one location to another, the DMA controller will
1256
copy in units of a given transfer length--up to 1024 words at a time.  It will
1257
read that transfer length into its internal buffer, and then write to the
1258
destination address from that buffer.  If the CPU interrupts a DMA transfer,
1259
it will release the bus, let the CPU complete whatever it needs to do, and then
1260
restart its transfer by writing the contents of its internal buffer and then
1261
re-entering its read cycle again.
1262 24 dgisselq
 
1263 36 dgisselq
When coupled with a peripheral, the DMA controller can be configured to start
1264
a memory copy on an interrupt line going high.  Further, the controller can be
1265 39 dgisselq
configured to issue reads from (or to) the same address instead of incrementing
1266 36 dgisselq
the address at each clock.  The DMA completes once the total number of items
1267
specified (not the transfer length) have been transferred.
1268
 
1269
In each case, once the transfer is complete and the DMA unit returns to
1270
idle, the DMA will issue an interrupt.
1271
 
1272
 
1273 21 dgisselq
\chapter{Operation}\label{chap:ops}
1274
 
1275 33 dgisselq
The Zip CPU, and even the Zip System, is not a System on a Chip (SoC).  It
1276
needs to be connected to its operational environment in order to be used.
1277
Specifically, some per system adjustments need to be made:
1278
\begin{enumerate}
1279
\item The Zip System depends upon an external 32-bit Wishbone bus.  This
1280
        must exist, and must be connected to the Zip CPU for it to work.
1281
\item The Zip System needs to be told of its {\tt RESET\_ADDRESS}.  This is
1282
        the program counter of the first instruction following a reset.
1283
\item If you want the Zip System to start up on its own, you will need to
1284
        set the {\tt START\_HALTED} parameter to zero.  Otherwise, if you
1285
        wish to manually start the CPU, that is if upon reset you want the
1286
        CPU start start in its halted, reset state, then set this parameter to
1287
        one.
1288
\item The third parameter to set is the number of interrupts you will be
1289
        providing from external to the CPU.  This can be anything from one
1290
        to nine, but it cannot be zero.  (Wire this line to a 1'b0 if you
1291
        do not wish to support any external interrupts.)
1292
\item Finally, you need to place into some wishbone accessible address, whether
1293
        RAM or (more likely) ROM, the initial instructions for the CPU.
1294
\end{enumerate}
1295
If you have enabled your CPU to start automatically, then upon power up the
1296
CPU will immediately start executing your instructions.
1297
 
1298
This is, however, not how I have used the Zip CPU.  I have instead used the
1299 36 dgisselq
Zip CPU in a more controlled environment.  For me, the CPU starts in a
1300 33 dgisselq
halted state, and waits to be told to start.  Further, the RESET address is a
1301
location in RAM.  After bringing up the board I am using, and further the
1302
bus that is on it, the RAM memory is then loaded externally with the program
1303
I wish the Zip System to run.  Once the RAM is loaded, I release the CPU.
1304
The CPU then runs until its halt condition, at which point its task is
1305
complete.
1306
 
1307
Eventually, I intend to place an operating system onto the ZipSystem, I'm
1308
just not there yet.
1309
 
1310 36 dgisselq
The rest of this chapter examines some common programming constructs, and
1311
how they might be applied to the Zip System.
1312 33 dgisselq
 
1313 36 dgisselq
\section{Example: Idle Task}
1314
One task every operating system needs is the idle task, the task that takes
1315
place when nothing else can run.  On the Zip CPU, this task is quite simple,
1316
and it is shown in assemble in Tbl.~\ref{tbl:idle-asm}.
1317
\begin{table}\begin{center}
1318
\begin{tabular}{ll}
1319
{\tt idle\_task:} \\
1320
&        {\em ; Wait for the next interrupt, then switch to supervisor task} \\
1321
&        {\tt WAIT} \\
1322
&        {\em ; When we come back, it's because the supervisor wishes to} \\
1323
&        {\em ; wait for an interrupt again, so go back to the top.} \\
1324
&        {\tt BRA idle\_task} \\
1325
\end{tabular}
1326
\caption{Example Idle Loop}\label{tbl:idle-asm}
1327
\end{center}\end{table}
1328
When this task runs, the CPU will fill up all of the pipeline stages up the
1329
ALU.  The {\tt WAIT} instruction, upon leaving the ALU, places the CPU into
1330
a sleep state where nothing more moves.  Sure, there may be some more settling,
1331
the pipe cache continue to read until full, other instructions may issue until
1332
the pipeline fills, but then everything will stall.  Then, once an interrupt
1333
takes place, control passes to the supervisor task to handle the interrupt.
1334
When control passes back to this task, it will be on the next instruction.
1335
Since that next instruction sends us back to the top of the task, the idle
1336
task thus does nothing but wait for an interrupt.
1337
 
1338
This should be the lowest priority task, the task that runs when nothing else
1339
can.  It will help lower the FPGA power usage overall---at least its dynamic
1340
power usage.
1341
 
1342
\section{Example: Memory Copy}
1343
One common operation is that of a memory move or copy.  Consider the C code
1344
shown in Tbl.~\ref{tbl:memcp-c}.
1345
\begin{table}\begin{center}
1346
\parbox{4in}{\begin{tabbing}
1347
{\tt void} \= {\tt memcp(void *dest, void *src, int len) \{} \\
1348
        \> {\tt for(int i=0; i<len; i++)} \\
1349
        \> \hspace{0.2in} {\tt *dest++ = *src++;} \\
1350
\}
1351
\end{tabbing}}
1352
\caption{Example Memory Copy code in C}\label{tbl:memcp-c}
1353
\end{center}\end{table}
1354
This same code can be translated in Zip Assembly as shown in
1355
Tbl.~\ref{tbl:memcp-asm}.
1356
\begin{table}\begin{center}
1357
\begin{tabular}{ll}
1358
memcp: \\
1359
&        {\em ; R0 = *dest, R1 = *src, R2 = LEN} \\
1360
&        {\em ; The following will operate in 17 clocks per word minus one clock} \\
1361
&        {\tt CMP 0,R2} \\
1362
&        {\tt LOD.Z -1(SP),PC} {\em ; A conditional return }\\
1363
&        {\em ; (One stall on potentially writing to PC)} \\
1364
&        {\tt LOD (R1),R3} \\
1365
&        {\em ; (4 stalls, cannot be scheduled away)} \\
1366
&        {\tt STO R3,(R2)} {\em ; (4 schedulable stalls, has no impact now)} \\
1367
&        {\tt ADD 1,R1} \\
1368
&        {\tt SUB 1,R2} \\
1369
&        {\tt BNZ loop} \\
1370
&        {\em ; (5 stalls, if branch taken, to clear and refill the pipeline)} \\
1371
&        {\tt RET} \\
1372
\end{tabular}
1373
\caption{Example Memory Copy code in Zip Assembly}\label{tbl:memcp-asm}
1374
\end{center}\end{table}
1375
This example points out several things associated with the Zip CPU.  First,
1376
a straightforward implementation of a for loop is not the fastest loop
1377
structure.  For this reason, we have placed the test to continue at the
1378
end.  Second, all pointers are {\tt void} pointers to arbitrary 32--bit
1379
data types.  The Zip CPU does not have explicit support for smaller or larger
1380
data types, and so this memory copy cannot be applied at a byte level.
1381
Third, we've optimized the conditional jump to a return instruction into a
1382
conditional return instruction.
1383
 
1384
\section{Context Switch}
1385
 
1386
Fundamental to any multiprocessing system is the ability to switch from one
1387
task to the next.  In the ZipSystem, this is accomplished in one of a couple
1388
ways.  The first step is that an interrupt happens.  Anytime an interrupt
1389
happens, the CPU needs to execute the following tasks in supervisor mode:
1390
\begin{enumerate}
1391
\item Check for a trap instruction.  That  is, if the user task requested a
1392
        trap, we may not wish to adjust the context, check interrupts, or call
1393
        the scheduler.  Tbl.~\ref{tbl:trap-check}
1394
\begin{table}\begin{center}
1395
\begin{tabular}{ll}
1396
{\tt return\_to\_user:} \\
1397
&       {\em; The instruction before the context switch processing must} \\
1398
&       {\em; be the RTU instruction that enacted user mode in the first} \\
1399
&       {\em; place.  We show it here just for reference.} \\
1400
&       {\tt RTU} \\
1401
{\tt trap\_check:} \\
1402
&       {\tt MOV uCC,R0} \\
1403
&       {\tt TST \$TRAP,R0} \\
1404
&       {\tt BNZ swap\_out} \\
1405
&       {; \em Do something here to execute the trap} \\
1406
&       {; \em Don't need to call the scheduler, so we can just return} \\
1407
&       {\tt BRA return\_to\_user} \\
1408
\end{tabular}
1409
\caption{Checking for whether the user issued a TRAP instruction}\label{tbl:trap-check}
1410
\end{center}\end{table}
1411
        shows the rudiments of this code, while showing nothing of how the
1412
        actual trap would be implemented.
1413
 
1414
You may also wish to note that the instruction before the first instruction
1415
in our context swap {\em must be} a return to userspace instruction.
1416
Remember, the supervisor process is re--entered where it left off.  This is
1417
different from many other processors that enter interrupt mode at some vector
1418
or other.  In this case, we always enter supervisor mode right where we last
1419
left.\footnote{The one exception to this rule is upon reset where supervisor
1420
mode is entered at a pre--programmed wishbone memory address.}
1421
 
1422
\item Capture user counters.  If the operating system is keeping track of
1423
        system usage via the accounting counters, those counters need to be
1424
        copied and accumulated into some master counter at this point.
1425
 
1426
\item Preserve the old context.  This involves pushing all the user registers
1427
        onto the user stack and then copying the resulting stack address
1428
        into the tasks task structure, as shown in Tbl.~\ref{tbl:context-out}.
1429
\begin{table}\begin{center}
1430
\begin{tabular}{ll}
1431
{\tt swap\_out:} \\
1432 39 dgisselq
&        {\tt MOV -15(uSP),R5} \\
1433
&        {\tt STO R5,stack(R12)} \\
1434
&        {\tt MOV uR0,R0} \\
1435
&        {\tt MOV uR1,R1} \\
1436
&        {\tt MOV uR2,R2} \\
1437
&        {\tt MOV uR3,R3} \\
1438
&        {\tt MOV uR4,R4} \\
1439
&        {\tt STO R0,1(R5)} {\em ; Exploit memory pipelining: }\\
1440
&        {\tt STO R1,2(R5)} {\em ; All instructions write to stack }\\
1441
&        {\tt STO R2,3(R5)} {\em ; All offsets increment by one }\\
1442
&        {\tt STO R3,4(R5)} {\em ; Longest pipeline is 5 cycles.}\\
1443
&        {\tt STO R4,5(R5)} \\
1444
        & \ldots {\em ; Need to repeat for all user registers} \\
1445
\iffalse
1446
&        {\tt MOV uR5,R0} \\
1447
&        {\tt MOV uR6,R1} \\
1448
&        {\tt MOV uR7,R2} \\
1449
&        {\tt MOV uR8,R3} \\
1450
&        {\tt MOV uR9,R4} \\
1451
&        {\tt STO R0,6(R5) }\\
1452
&        {\tt STO R1,7(R5) }\\
1453
&        {\tt STO R2,8(R5) }\\
1454
&        {\tt STO R3,9(R5) }\\
1455
&        {\tt STO R4,10(R5)} \\
1456
\fi
1457
&        {\tt MOV uR10,R0} \\
1458
&        {\tt MOV uR11,R1} \\
1459
&        {\tt MOV uR12,R2} \\
1460
&        {\tt MOV uCC,R3} \\
1461
&        {\tt MOV uPC,R4} \\
1462
&        {\tt STO R0,11(R5)}\\
1463
&        {\tt STO R1,12(R5)}\\
1464
&        {\tt STO R2,13(R5)}\\
1465
&        {\tt STO R3,14(R5)}\\
1466
&        {\tt STO R4,15(R5)} \\
1467 36 dgisselq
&       {\em ; We can skip storing the stack, uSP, since it'll be stored}\\
1468
&       {\em ; elsewhere (in the task structure) }\\
1469
\end{tabular}
1470
\caption{Example Storing User Task Context}\label{tbl:context-out}
1471
\end{center}\end{table}
1472
For the sake of discussion, we assume the supervisor maintains a
1473
pointer to the current task's structure in supervisor register
1474
{\tt R12}, and that {\tt stack} is an offset to the beginning of this
1475
structure indicating where the stack pointer is to be kept within it.
1476
 
1477
        For those who are still interested, the full code for this context
1478
        save can be found as an assembler macro within the assembler
1479
        include file, {\tt sys.i}.
1480
 
1481
\item Reset the watchdog timer.  If you are using the watchdog timer, it should
1482
        be reset on a context swap, to know that things are still working.
1483
        Example code for this is shown in Tbl.~\ref{tbl:reset-watchdog}.
1484
\begin{table}\begin{center}
1485
\begin{tabular}{ll}
1486
\multicolumn{2}{l}{{\tt `define WATCHDOG\_ADDRESS 32'hc000\_0002}}\\
1487
\multicolumn{2}{l}{{\tt `define WATCHDOG\_TICKS 32'd1\_000\_000} {; \em = 10 ms}}\\
1488
&       {\tt LDI WATCHDOG\_ADDRESS,R0} \\
1489
&       {\tt LDI WATCHDOG\_TICKS,R1} \\
1490
&       {\tt STO R1,(R0)}
1491
\end{tabular}
1492
\caption{Example Watchdog Reset}\label{tbl:reset-watchdog}
1493
\end{center}\end{table}
1494
 
1495
\item Interrupt handling.  An interrupt handler within the Zip System is nothing
1496
        more than a task.  At context swap time, the supervisor needs to
1497
        disable all of the interrupts that have tripped, and then enable
1498
        all of the tasks that would deal with each of these interrupts.
1499
        These can be user tasks, run at higher priority than any other user
1500
        tasks.  Either way, they will need to re--enable their own interrupt
1501
        themselves, if the interrupt is still relevant.
1502
 
1503
        An example of this master interrut handling is shown in
1504
        Tbl.~\ref{tbl:pre-handler}.
1505
\begin{table}\begin{center}
1506
\begin{tabular}{ll}
1507
{\tt pre\_handler:} \\
1508
&       {\tt LDI PIC\_ADDRESS,R0 } \\
1509
&       {\em ; Start by grabbing the interrupt state from the interrupt}\\
1510
&       {\em ; controller.  We'll store this into the register R7 so that }\\
1511
&       {\em ; we can keep and preserve this information for the scheduler}\\
1512
&       {\em ; to use later. }\\
1513
&       {\tt LOD (R0),R1} \\
1514
&       {\tt MOV R1,R7 } \\
1515
&       {\em ; As a next step, we need to acknowledge and disable all active}\\
1516
&       {\em ; interrupts. We'll start by calculating all of our active}\\
1517
&       {\em ; interrupts.}\\
1518
&       {\tt AND 0x07fff,R1 } \\
1519
&       {\em ; Put the active interrupts into the upper half of R1} \\
1520
&       {\tt ROL 16,R1 } \\
1521
&       {\tt LDILO 0x0ffff,R1   } \\
1522
&       {\tt AND R7,R1}\\
1523
&       {\em ; Acknowledge and disable active interrupts}\\
1524
&       {\em ; This also disables all interrupts from the controller, so}\\
1525
&       {\em ; we'll need to re-enable interrupts in general shortly } \\
1526
&       {\tt STO R1,(R0) } \\
1527
&       {\em ; We leave our active interrupt mask in R7 so the scheduler can}\\
1528
&       {\em ; release any tasks that depended upon them. } \\
1529
\end{tabular}
1530
\caption{Example checking for active interrupts}\label{tbl:pre-handler}
1531
\end{center}\end{table}
1532
 
1533
\item Calling the scheduler.  This needs to be done to pick the next task
1534
        to switch to.  It may be an interrupt handler, or it may  be a normal
1535
        user task.  From a priority standpoint, it would make sense that the
1536
        interrupt handlers all have a higher priority than the user tasks,
1537
        and that once they have been called the user tasks may then be called
1538
        again.  If no task is ready to run, run the idle task to wait for an
1539
        interrupt.
1540
 
1541
        This suggests a minimum of four task priorities:
1542
        \begin{enumerate}
1543
        \item Interrupt handlers, executed with their interrupts disabled
1544
        \item Device drivers, executed with interrupts re-enabled
1545
        \item User tasks
1546
        \item The idle task, executed when nothing else is able to execute
1547
        \end{enumerate}
1548
 
1549
        For our purposes here, we'll just assume that a pointer to the current
1550
        task is maintained in {\tt R12}, that a {\tt JSR scheduler} is
1551
        called, and that the next current task is likewise placed into
1552
        {\tt R12}.
1553
 
1554
\item Restore the new tasks context.  Given that the scheduler has returned a
1555
        task that can be run at this time, the stack pointer needs to be
1556
        pulled out of the tasks task structure, placed into the user
1557
        register, and then the rest of the user registers need to be popped
1558
        back off of the stack to run this task.  An example of this is
1559
        shown in Tbl.~\ref{tbl:context-in},
1560
\begin{table}\begin{center}
1561
\begin{tabular}{ll}
1562
{\tt swap\_in:} \\
1563 39 dgisselq
&       {\tt LOD stack(R12),R5} \\
1564 36 dgisselq
&       {\tt MOV 15(R1),uSP} \\
1565 39 dgisselq
        & {\em ; Be sure to exploit the memory pipelining capability} \\
1566
&       {\tt LOD 1(R5),R0} \\
1567
&       {\tt LOD 2(R5),R1} \\
1568
&       {\tt LOD 3(R5),R2} \\
1569
&       {\tt LOD 4(R5),R3} \\
1570
&       {\tt LOD 5(R5),R4} \\
1571
&       {\tt MOV R0,uR0} \\
1572
&       {\tt MOV R1,uR1} \\
1573
&       {\tt MOV R2,uR2} \\
1574
&       {\tt MOV R3,uR3} \\
1575
&       {\tt MOV R4,uR4} \\
1576 36 dgisselq
        & \ldots {\em ; Need to repeat for all user registers} \\
1577 39 dgisselq
&       {\tt LOD 11(R5),R0} \\
1578
&       {\tt LOD 12(R5),R1} \\
1579
&       {\tt LOD 13(R5),R2} \\
1580
&       {\tt LOD 14(R5),R3} \\
1581
&       {\tt LOD 15(R5),R4} \\
1582
&       {\tt MOV R0,uR10} \\
1583
&       {\tt MOV R1,uR11} \\
1584
&       {\tt MOV R2,uR12} \\
1585
&       {\tt MOV R3,uCC} \\
1586
&       {\tt MOV R4,uPC} \\
1587
 
1588 36 dgisselq
&       {\tt BRA return\_to\_user} \\
1589
\end{tabular}
1590
\caption{Example Restoring User Task Context}\label{tbl:context-in}
1591
\end{center}\end{table}
1592
        assuming as before that the task
1593
        pointer is found in supervisor register {\tt R12}.
1594
        As with storing the user context, the full code associated with
1595
        restoring the user context can be found in the assembler include
1596
        file, {\tt sys.i}.
1597
 
1598
\item Clear the userspace accounting registers.  In order to keep track of
1599
        per process system usage, these registers need to be cleared before
1600
        reactivating the userspace process.  That way, upon the next
1601
        interrupt, we'll know how many clocks the userspace program has
1602
        encountered, and how many instructions it was able to issue in
1603
        those many clocks.
1604
 
1605
\item Jump back to the instruction just before saving the last tasks context,
1606
        because that location in memory contains the return from interrupt
1607
        command that we are going to need to execute, in order to guarantee
1608
        that we return back here again.
1609
\end{enumerate}
1610
 
1611 21 dgisselq
\chapter{Registers}\label{chap:regs}
1612
 
1613 24 dgisselq
The ZipSystem registers fall into two categories, ZipSystem internal registers
1614
accessed via the ZipCPU shown in Tbl.~\ref{tbl:zpregs},
1615
\begin{table}[htbp]
1616
\begin{center}\begin{reglist}
1617 32 dgisselq
PIC   & \scalebox{0.8}{\tt 0xc0000000} & 32 & R/W & Primary Interrupt Controller \\\hline
1618
WDT   & \scalebox{0.8}{\tt 0xc0000001} & 32 & R/W & Watchdog Timer \\\hline
1619 36 dgisselq
  & \scalebox{0.8}{\tt 0xc0000002} & 32 & R/W & {\em (Reserved for future use)} \\\hline
1620 32 dgisselq
CTRIC & \scalebox{0.8}{\tt 0xc0000003} & 32 & R/W & Secondary Interrupt Controller \\\hline
1621
TMRA  & \scalebox{0.8}{\tt 0xc0000004} & 32 & R/W & Timer A\\\hline
1622
TMRB  & \scalebox{0.8}{\tt 0xc0000005} & 32 & R/W & Timer B\\\hline
1623
TMRC  & \scalebox{0.8}{\tt 0xc0000006} & 32 & R/W & Timer C\\\hline
1624
JIFF  & \scalebox{0.8}{\tt 0xc0000007} & 32 & R/W & Jiffies \\\hline
1625
MTASK  & \scalebox{0.8}{\tt 0xc0000008} & 32 & R/W & Master Task Clock Counter \\\hline
1626
MMSTL  & \scalebox{0.8}{\tt 0xc0000009} & 32 & R/W & Master Stall Counter \\\hline
1627
MPSTL  & \scalebox{0.8}{\tt 0xc000000a} & 32 & R/W & Master Pre--Fetch Stall Counter \\\hline
1628
MICNT  & \scalebox{0.8}{\tt 0xc000000b} & 32 & R/W & Master Instruction Counter\\\hline
1629
UTASK  & \scalebox{0.8}{\tt 0xc000000c} & 32 & R/W & User Task Clock Counter \\\hline
1630
UMSTL  & \scalebox{0.8}{\tt 0xc000000d} & 32 & R/W & User Stall Counter \\\hline
1631
UPSTL  & \scalebox{0.8}{\tt 0xc000000e} & 32 & R/W & User Pre--Fetch Stall Counter \\\hline
1632
UICNT  & \scalebox{0.8}{\tt 0xc000000f} & 32 & R/W & User Instruction Counter\\\hline
1633 36 dgisselq
DMACTRL  & \scalebox{0.8}{\tt 0xc0000010} & 32 & R/W & DMA Control Register\\\hline
1634
DMALEN  & \scalebox{0.8}{\tt 0xc0000011} & 32 & R/W & DMA total transfer length\\\hline
1635
DMASRC  & \scalebox{0.8}{\tt 0xc0000012} & 32 & R/W & DMA source address\\\hline
1636
DMADST  & \scalebox{0.8}{\tt 0xc0000013} & 32 & R/W & DMA destination address\\\hline
1637 32 dgisselq
% Cache  & \scalebox{0.8}{\tt 0xc0100000} & & & Base address of the Cache memory\\\hline
1638 24 dgisselq
\end{reglist}
1639
\caption{Zip System Internal/Peripheral Registers}\label{tbl:zpregs}
1640
\end{center}\end{table}
1641 33 dgisselq
and the two debug registers shown in Tbl.~\ref{tbl:dbgregs}.
1642 24 dgisselq
\begin{table}[htbp]
1643
\begin{center}\begin{reglist}
1644
ZIPCTRL & 0 & 32 & R/W & Debug Control Register \\\hline
1645
ZIPDATA & 1 & 32 & R/W & Debug Data Register \\\hline
1646
\end{reglist}
1647
\caption{Zip System Debug Registers}\label{tbl:dbgregs}
1648
\end{center}\end{table}
1649
 
1650 33 dgisselq
\section{Peripheral Registers}
1651
The peripheral registers, listed in Tbl.~\ref{tbl:zpregs}, are shown in the
1652
CPU's address space.  These may be accessed by the CPU at these addresses,
1653
and when so accessed will respond as described in Chapt.~\ref{chap:periph}.
1654
These registers will be discussed briefly again here.
1655 24 dgisselq
 
1656 33 dgisselq
The Zip CPU Interrupt controller has four different types of bits, as shown in
1657
Tbl.~\ref{tbl:picbits}.
1658
\begin{table}\begin{center}
1659
\begin{bitlist}
1660
31 & R/W & Master Interrupt Enable\\\hline
1661
30\ldots 16 & R/W & Interrupt Enables, write '1' to change\\\hline
1662
15 & R & Current Master Interrupt State\\\hline
1663
15\ldots 0 & R/W & Input Interrupt states, write '1' to clear\\\hline
1664
\end{bitlist}
1665
\caption{Interrupt Controller Register Bits}\label{tbl:picbits}
1666
\end{center}\end{table}
1667
The high order bit, or bit--31, is the master interrupt enable bit.  When this
1668
bit is set, then any time an interrupt occurs the CPU will be interrupted and
1669
will switch to supervisor mode, etc.
1670
 
1671
Bits 30~\ldots 16 are interrupt enable bits.  Should the interrupt line go
1672
ghile while enabled, an interrupt will be generated.  To set an interrupt enable
1673
bit, one needs to write the master interrupt enable while writing a `1' to this
1674
the bit.  To clear, one need only write a `0' to the master interrupt enable,
1675
while leaving this line high.
1676
 
1677
Bits 15\ldots 0 are the current state of the interrupt vector.  Interrupt lines
1678
trip when they go high, and remain tripped until they are acknowledged.  If
1679
the interrupt goes high for longer than one pulse, it may be high when a clear
1680
is requested.  If so, the interrupt will not clear.  The line must go low
1681
again before the status bit can be cleared.
1682
 
1683
As an example, consider the following scenario where the Zip CPU supports four
1684
interrupts, 3\ldots0.
1685
\begin{enumerate}
1686
\item The Supervisor will first, while in the interrupts disabled mode,
1687
        write a {\tt 32'h800f000f} to the controller.  The supervisor may then
1688
        switch to the user state with interrupts enabled.
1689
\item When an interrupt occurs, the supervisor will switch to the interrupt
1690
        state.  It will then cycle through the interrupt bits to learn which
1691
        interrupt handler to call.
1692
\item If the interrupt handler expects more interrupts, it will clear its
1693
        current interrupt when it is done handling the interrupt in question.
1694
        To do this, it will write a '1' to the low order interrupt mask,
1695
        such as writing a {\tt 32'h80000001}.
1696
\item If the interrupt handler does not expect any more interrupts, it will
1697
        instead clear the interrupt from the controller by writing a
1698
        {\tt 32'h00010001} to the controller.
1699
\item Once all interrupts have been handled, the supervisor will write a
1700
        {\tt 32'h80000000} to the interrupt register to re-enable interrupt
1701
        generation.
1702
\item The supervisor should also check the user trap bit, and possible soft
1703
        interrupt bits here, but this action has nothing to do with the
1704
        interrupt control register.
1705
\item The supervisor will then leave interrupt mode, possibly adjusting
1706
        whichever task is running, by executing a return from interrupt
1707
        command.
1708
\end{enumerate}
1709
 
1710
Leaving the interrupt controller, we show the timer registers bit definitions
1711
in Tbl.~\ref{tbl:tmrbits}.
1712
\begin{table}\begin{center}
1713
\begin{bitlist}
1714
31 & R/W & Auto-Reload\\\hline
1715
30\ldots 0 & R/W & Current timer value\\\hline
1716
\end{bitlist}
1717
\caption{Timer Register Bits}\label{tbl:tmrbits}
1718
\end{center}\end{table}
1719
As you may recall, the timer just counts down to zero and then trips an
1720
interrupt.  Writing to the current timer value sets that value, and reading
1721
from it returns that value.  Writing to the current timer value while also
1722
setting the auto--reload bit will send the timer into an auto--reload mode.
1723
In this mode, upon setting its interrupt bit for one cycle, the timer will
1724
also reset itself back to the value of the timer that was written to it when
1725
the auto--reload option was written to it.  To clear and stop the timer,
1726
just simply write a `32'h00' to this register.
1727
 
1728
The Jiffies register is somewhat similar in that the register always changes.
1729
In this case, the register counts up, whereas the timer always counted down.
1730
Reads from this register, as shown in Tbl.~\ref{tbl:jiffybits},
1731
\begin{table}\begin{center}
1732
\begin{bitlist}
1733
31\ldots 0 & R & Current jiffy value\\\hline
1734
31\ldots 0 & W & Value/time of next interrupt\\\hline
1735
\end{bitlist}
1736
\caption{Jiffies Register Bits}\label{tbl:jiffybits}
1737
\end{center}\end{table}
1738
always return the time value contained in the register.  Writes greater than
1739
the current Jiffy value, that is where the new value minus the old value is
1740
greater than zero while ignoring truncation, will set a new Jiffy interrupt
1741
time.  At that time, the Jiffy vector will clear, and another interrupt time
1742
may either be written to it, or it will just continue counting without
1743
activating any more interrupts.
1744
 
1745
The Zip CPU also supports several counter peripherals, mostly in the way of
1746
process accounting.  This peripherals have a single register associated with
1747
them, shown in Tbl.~\ref{tbl:ctrbits}.
1748
\begin{table}\begin{center}
1749
\begin{bitlist}
1750
31\ldots 0 & R/W & Current counter value\\\hline
1751
\end{bitlist}
1752
\caption{Counter Register Bits}\label{tbl:ctrbits}
1753
\end{center}\end{table}
1754
Writes to this register set the new counter value.  Reads read the current
1755
counter value.
1756
 
1757
The current design operation of these counters is that of performance counting.
1758
Two sets of four registers are available for keeping track of performance.
1759
The first is a task counter.  This just counts clock ticks.  The second
1760
counter is a prefetch stall counter, then an master stall counter.  These
1761
allow the CPU to be evaluated as to how efficient it is.  The fourth and
1762
final counter is an instruction counter, which counts how many instructions the
1763
CPU has issued.
1764
 
1765
It is envisioned that these counters will be used as follows: First, every time
1766
a master counter rolls over, the supervisor (Operating System) will record
1767
the fact.  Second, whenever activating a user task, the Operating System will
1768
set the four user counters to zero.  When the user task has completed, the
1769
Operating System will read the timers back off, to determine how much of the
1770
CPU the process had consumed.
1771
 
1772 36 dgisselq
The final peripheral to discuss is the DMA controller.  This controller
1773
has four registers.  Of these four, the length, source and destination address
1774
registers should need no further explanation.  They are full 32--bit registers
1775
specifying the entire transfer length, the starting address to read from, and
1776
the starting address to write to.  The registers can be written to when the
1777
DMA is idle, and read at any time.  The control register, however, will need
1778
some more explanation.
1779
 
1780
The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.
1781
\begin{table}\begin{center}
1782
\begin{bitlist}
1783
31 & R & DMA Active\\\hline
1784 39 dgisselq
30 & R & Wishbone error, transaction aborted.  This bit is cleared the next time
1785
        this register is written to.\\\hline
1786 36 dgisselq
29 & R/W & Set to '1' to prevent the controller from incrementing the source address, '0' for normal memory copy. \\\hline
1787 39 dgisselq
28 & R/W & Set to '1' to prevent the controller from incrementing the
1788 36 dgisselq
        destination address, '0' for normal memory copy. \\\hline
1789
27 \ldots 16 & W & The DMA Key.  Write a 12'hfed to these bits to start the
1790
        activate any DMA transfer.  \\\hline
1791
27 & R & Always reads '0', to force the deliberate writing of the key. \\\hline
1792
26 \ldots 16 & R & Indicates the number of items in the transfer buffer that
1793
        have yet to be written. \\\hline
1794
15 & R/W & Set to '1' to trigger on an interrupt, or '0' to start immediately
1795
        upon receiving a valid key.\\\hline
1796
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
1797
9\ldots 0 & R/W & Intermediate transfer length minus one.  Thus, to transfer
1798
        one item at a time set this value to 0. To transfer 1024 at a time,
1799
        set it to 1024.\\\hline
1800
\end{bitlist}
1801
\caption{DMA Control Register Bits}\label{tbl:dmacbits}
1802
\end{center}\end{table}
1803
This control register has been designed so that the common case of memory
1804
access need only set the key and the transfer length.  Hence, writing a
1805
\hbox{32'h0fed03ff} to the control register will start any memory transfer.
1806
On the other hand, if you wished to read from a serial port (constant address)
1807
and put the result into a buffer every time a word was available, you
1808
might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
1809
have a serial port wired to the zero bit of this interrupt control.  (The
1810
DMA controller does not use the interrupt controller, and cannot clear
1811
interrupts.)  As a third example, if you wished to write to an external
1812
FIFO anytime it was less than half full (had fewer than 512 items), and
1813
interrupt line 2 indicated this condition, you might wish to issue a
1814
\hbox{32'h1fed8dff} to this port.
1815
 
1816 33 dgisselq
\section{Debug Port Registers}
1817
Accessing the Zip System via the debug port isn't as straight forward as
1818
accessing the system via the wishbone bus.  The debug port itself has been
1819
reduced to two addresses, as outlined earlier in Tbl.~\ref{tbl:dbgregs}.
1820
Access to the Zip System begins with the Debug Control register, shown in
1821
Tbl.~\ref{tbl:dbgctrl}.
1822
\begin{table}\begin{center}
1823
\begin{bitlist}
1824
31\ldots 14 & R & Reserved\\\hline
1825
13 & R & CPU GIE setting\\\hline
1826
12 & R & CPU is sleeping\\\hline
1827
11 & W & Command clear PF cache\\\hline
1828
10 & R/W & Command HALT, Set to '1' to halt the CPU\\\hline
1829
9 & R & Stall Status, '1' if CPU is busy\\\hline
1830 36 dgisselq
8 & R/W & Step Command, set to '1' to step the CPU, also sets the halt bit\\\hline
1831 33 dgisselq
7 & R & Interrupt Request \\\hline
1832
6 & R/W & Command RESET \\\hline
1833
5\ldots 0 & R/W & Debug Register Address \\\hline
1834
\end{bitlist}
1835
\caption{Debug Control Register Bits}\label{tbl:dbgctrl}
1836
\end{center}\end{table}
1837
 
1838
The first step in debugging access is to determine whether or not the CPU
1839
is halted, and to halt it if not.  To do this, first write a '1' to the
1840
Command HALT bit.  This will halt the CPU and place it into debug mode.
1841
Once the CPU is halted, the stall status bit will drop to zero.  Thus,
1842
if bit 10 is high and bit 9 low, the debug port is open to examine the
1843
internal state of the CPU.
1844
 
1845
At this point, the external debugger may examine internal state information
1846
from within the CPU.  To do this, first write again to the command register
1847
a value (with command halt still high) containing the address of an internal
1848
register of interest in the bottom 6~bits.  Internal registers that may be
1849
accessed this way are listed in Tbl.~\ref{tbl:dbgaddrs}.
1850
\begin{table}\begin{center}
1851
\begin{reglist}
1852
sR0 & 0 & 32 & R/W & Supervisor Register R0 \\\hline
1853
sR1 & 0 & 32 & R/W & Supervisor Register R1 \\\hline
1854
sSP & 13 & 32 & R/W & Supervisor Stack Pointer\\\hline
1855
sCC & 14 & 32 & R/W & Supervisor Condition Code Register \\\hline
1856
sPC & 15 & 32 & R/W & Supervisor Program Counter\\\hline
1857
uR0 & 16 & 32 & R/W & User Register R0 \\\hline
1858
uR1 & 17 & 32 & R/W & User Register R1 \\\hline
1859
uSP & 29 & 32 & R/W & User Stack Pointer\\\hline
1860
uCC & 30 & 32 & R/W & User Condition Code Register \\\hline
1861
uPC & 31 & 32 & R/W & User Program Counter\\\hline
1862
PIC & 32 & 32 & R/W & Primary Interrupt Controller \\\hline
1863
WDT & 33 & 32 & R/W & Watchdog Timer\\\hline
1864
CTRIC & 35 & 32 & R/W & Secondary Interrupt Controller\\\hline
1865
TMRA & 36 & 32 & R/W & Timer A\\\hline
1866
TMRB & 37 & 32 & R/W & Timer B\\\hline
1867
TMRC & 38 & 32 & R/W & Timer C\\\hline
1868
JIFF & 39 & 32 & R/W & Jiffies peripheral\\\hline
1869
MTASK & 40 & 32 & R/W & Master task clock counter\\\hline
1870
MMSTL & 41 & 32 & R/W & Master memory stall counter\\\hline
1871
MPSTL & 42 & 32 & R/W & Master Pre-Fetch Stall counter\\\hline
1872
MICNT & 43 & 32 & R/W & Master instruction counter\\\hline
1873
UTASK & 44 & 32 & R/W & User task clock counter\\\hline
1874
UMSTL & 45 & 32 & R/W & User memory stall counter\\\hline
1875
UPSTL & 46 & 32 & R/W & User Pre-Fetch Stall counter\\\hline
1876
UICNT & 47 & 32 & R/W & User instruction counter\\\hline
1877 39 dgisselq
DMACMD & 48 & 32 & R/W & DMA command and status register\\\hline
1878
DMALEN & 49 & 32 & R/W & DMA transfer length\\\hline
1879
DMARD & 50 & 32 & R/W & DMA read address\\\hline
1880
DMAWR & 51 & 32 & R/W & DMA write address\\\hline
1881 33 dgisselq
\end{reglist}
1882
\caption{Debug Register Addresses}\label{tbl:dbgaddrs}
1883
\end{center}\end{table}
1884
Primarily, these ``registers'' include access to the entire CPU register
1885 36 dgisselq
set, as well as the internal peripherals.  To read one of these registers
1886 33 dgisselq
once the address is set, simply issue a read from the data port.  To write
1887
one of these registers or peripheral ports, simply write to the data port
1888
after setting the proper address.
1889
 
1890
In this manner, all of the CPU's internal state may be read and adjusted.
1891
 
1892
As an example of how to use this, consider what would happen in the case
1893
of an external break point.  If and when the CPU hits a break point that
1894
causes it to halt, the Command HALT bit will activate on its own, the CPU
1895
will then raise an external interrupt line and wait for a debugger to examine
1896
its state.  After examining the state, the debugger will need to remove
1897
the breakpoint by writing a different instruction into memory and by writing
1898
to the command register while holding the clear cache, command halt, and
1899
step CPU bits high, (32'hd00).  The debugger may then replace the breakpoint
1900
now that the CPU has gone beyond it, and clear the cache again (32'h500).
1901
 
1902
To leave this debug mode, simply write a `32'h0' value to the command register.
1903
 
1904
\chapter{Wishbone Datasheets}\label{chap:wishbone}
1905 32 dgisselq
The Zip System supports two wishbone ports, a slave debug port and a master
1906 21 dgisselq
port for the system itself.  These are shown in Tbl.~\ref{tbl:wishbone-slave}
1907
\begin{table}[htbp]
1908
\begin{center}
1909
\begin{wishboneds}
1910
Revision level of wishbone & WB B4 spec \\\hline
1911
Type of interface & Slave, Read/Write, single words only \\\hline
1912 24 dgisselq
Address Width & 1--bit \\\hline
1913 21 dgisselq
Port size & 32--bit \\\hline
1914
Port granularity & 32--bit \\\hline
1915
Maximum Operand Size & 32--bit \\\hline
1916
Data transfer ordering & (Irrelevant) \\\hline
1917
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
1918
Signal Names & \begin{tabular}{ll}
1919
                Signal Name & Wishbone Equivalent \\\hline
1920
                {\tt i\_clk} & {\tt CLK\_I} \\
1921
                {\tt i\_dbg\_cyc} & {\tt CYC\_I} \\
1922
                {\tt i\_dbg\_stb} & {\tt STB\_I} \\
1923
                {\tt i\_dbg\_we} & {\tt WE\_I} \\
1924
                {\tt i\_dbg\_addr} & {\tt ADR\_I} \\
1925
                {\tt i\_dbg\_data} & {\tt DAT\_I} \\
1926
                {\tt o\_dbg\_ack} & {\tt ACK\_O} \\
1927
                {\tt o\_dbg\_stall} & {\tt STALL\_O} \\
1928
                {\tt o\_dbg\_data} & {\tt DAT\_O}
1929
                \end{tabular}\\\hline
1930
\end{wishboneds}
1931 22 dgisselq
\caption{Wishbone Datasheet for the Debug Interface}\label{tbl:wishbone-slave}
1932 21 dgisselq
\end{center}\end{table}
1933
and Tbl.~\ref{tbl:wishbone-master} respectively.
1934
\begin{table}[htbp]
1935
\begin{center}
1936
\begin{wishboneds}
1937
Revision level of wishbone & WB B4 spec \\\hline
1938 24 dgisselq
Type of interface & Master, Read/Write, single cycle or pipelined\\\hline
1939
Address Width & 32--bit bits \\\hline
1940 21 dgisselq
Port size & 32--bit \\\hline
1941
Port granularity & 32--bit \\\hline
1942
Maximum Operand Size & 32--bit \\\hline
1943
Data transfer ordering & (Irrelevant) \\\hline
1944
Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline
1945
Signal Names & \begin{tabular}{ll}
1946
                Signal Name & Wishbone Equivalent \\\hline
1947
                {\tt i\_clk} & {\tt CLK\_O} \\
1948
                {\tt o\_wb\_cyc} & {\tt CYC\_O} \\
1949
                {\tt o\_wb\_stb} & {\tt STB\_O} \\
1950
                {\tt o\_wb\_we} & {\tt WE\_O} \\
1951
                {\tt o\_wb\_addr} & {\tt ADR\_O} \\
1952
                {\tt o\_wb\_data} & {\tt DAT\_O} \\
1953
                {\tt i\_wb\_ack} & {\tt ACK\_I} \\
1954
                {\tt i\_wb\_stall} & {\tt STALL\_I} \\
1955
                {\tt i\_wb\_data} & {\tt DAT\_I}
1956
                \end{tabular}\\\hline
1957
\end{wishboneds}
1958 22 dgisselq
\caption{Wishbone Datasheet for the CPU as Master}\label{tbl:wishbone-master}
1959 21 dgisselq
\end{center}\end{table}
1960
I do not recommend that you connect these together through the interconnect.
1961 24 dgisselq
Rather, the debug port of the CPU should be accessible regardless of the state
1962
of the master bus.
1963 21 dgisselq
 
1964 24 dgisselq
You may wish to notice that neither the {\tt ERR} nor the {\tt RETRY} wires
1965
have been implemented.  What this means is that the CPU is currently unable
1966
to detect a bus error condition, and so may stall indefinitely (hang) should
1967
it choose to access a value not on the bus, or a peripheral that is not
1968
yet properly configured.
1969 21 dgisselq
 
1970
\chapter{Clocks}\label{chap:clocks}
1971
 
1972 32 dgisselq
This core is based upon the Basys--3 development board sold by Digilent.
1973
The Basys--3 development board contains one external 100~MHz clock, which is
1974 36 dgisselq
sufficient to run the Zip CPU core.
1975 21 dgisselq
\begin{table}[htbp]
1976
\begin{center}
1977
\begin{clocklist}
1978
i\_clk & External & 100~MHz & 100~MHz & System clock.\\\hline
1979
\end{clocklist}
1980
\caption{List of Clocks}\label{tbl:clocks}
1981
\end{center}\end{table}
1982
I hesitate to suggest that the core can run faster than 100~MHz, since I have
1983
had struggled with various timing violations to keep it at 100~MHz.  So, for
1984
now, I will only state that it can run at 100~MHz.
1985
 
1986
 
1987
\chapter{I/O Ports}\label{chap:ioports}
1988 33 dgisselq
The I/O ports to the Zip CPU may be grouped into three categories.  The first
1989
is that of the master wishbone used by the CPU, then the slave wishbone used
1990
to command the CPU via a debugger, and then the rest.  The first two of these
1991
were already discussed in the wishbone chapter.  They are listed here
1992
for completeness in Tbl.~\ref{tbl:iowb-master}
1993
\begin{table}
1994
\begin{center}\begin{portlist}
1995
{\tt o\_wb\_cyc}   &  1 & Output & Indicates an active Wishbone cycle\\\hline
1996
{\tt o\_wb\_stb}   &  1 & Output & WB Strobe signal\\\hline
1997
{\tt o\_wb\_we}    &  1 & Output & Write enable\\\hline
1998
{\tt o\_wb\_addr}  & 32 & Output & Bus address \\\hline
1999
{\tt o\_wb\_data}  & 32 & Output & Data on WB write\\\hline
2000
{\tt i\_wb\_ack}   &  1 & Input  & Slave has completed a R/W cycle\\\hline
2001
{\tt i\_wb\_stall} &  1 & Input  & WB bus slave not ready\\\hline
2002
{\tt i\_wb\_data}  & 32 & Input  & Incoming bus data\\\hline
2003
\end{portlist}\caption{CPU Master Wishbone I/O Ports}\label{tbl:iowb-master}\end{center}\end{table}
2004
and~\ref{tbl:iowb-slave} respectively.
2005
\begin{table}
2006
\begin{center}\begin{portlist}
2007
{\tt i\_wb\_cyc}   &  1 & Input & Indicates an active Wishbone cycle\\\hline
2008
{\tt i\_wb\_stb}   &  1 & Input & WB Strobe signal\\\hline
2009
{\tt i\_wb\_we}    &  1 & Input & Write enable\\\hline
2010
{\tt i\_wb\_addr}  &  1 & Input & Bus address, command or data port \\\hline
2011
{\tt i\_wb\_data}  & 32 & Input & Data on WB write\\\hline
2012
{\tt o\_wb\_ack}   &  1 & Output  & Slave has completed a R/W cycle\\\hline
2013
{\tt o\_wb\_stall} &  1 & Output  & WB bus slave not ready\\\hline
2014
{\tt o\_wb\_data}  & 32 & Output  & Incoming bus data\\\hline
2015
\end{portlist}\caption{CPU Debug Wishbone I/O Ports}\label{tbl:iowb-slave}\end{center}\end{table}
2016 21 dgisselq
 
2017 33 dgisselq
There are only four other lines to the CPU: the external clock, external
2018
reset, incoming external interrupt line(s), and the outgoing debug interrupt
2019
line.  These are shown in Tbl.~\ref{tbl:ioports}.
2020
\begin{table}
2021
\begin{center}\begin{portlist}
2022
{\tt i\_clk} & 1 & Input & The master CPU clock \\\hline
2023
{\tt i\_rst} & 1 & Input &  Active high reset line \\\hline
2024
{\tt i\_ext\_int} & 1\ldots 6 & Input &  Incoming external interrupts \\\hline
2025
{\tt o\_ext\_int} & 1 & Output & CPU Halted interrupt \\\hline
2026
\end{portlist}\caption{I/O Ports}\label{tbl:ioports}\end{center}\end{table}
2027
The clock line was discussed briefly in Chapt.~\ref{chap:clocks}.  We
2028
typically run it at 100~MHz.  The reset line is an active high reset.  When
2029
asserted, the CPU will start running again from its reset address in
2030
memory.  Further, depending upon how the CPU is configured and specifically on
2031
the {\tt START\_HALTED} parameter, it may or may not start running
2032
automatically.  The {\tt i\_ext\_int} line is for an external interrupt.  This
2033
line may be as wide as 6~external interrupts, depending upon the setting of
2034
the {\tt EXTERNAL\_INTERRUPTS} line.  As currently configured, the ZipSystem
2035
only supports one such interrupt line by default.  For us, this line is the
2036
output of another interrupt controller, but that's a board specific setup
2037
detail.  Finally, the Zip System produces one external interrupt whenever
2038
the CPU halts to wait for the debugger.
2039
 
2040 36 dgisselq
\chapter{Initial Assessment}\label{chap:assessment}
2041
 
2042
Having now worked with the Zip CPU for a while, it is worth offering an
2043
honest assessment of how well it works and how well it was designed. At the
2044
end of this assessment, I will propose some changes that may take place in a
2045
later version of this Zip CPU to make it better.
2046
 
2047
\section{The Good}
2048
\begin{itemize}
2049
\item The Zip CPU is light weight and fully featured as it exists today. For
2050
        anyone who wishes to build a general purpose CPU and then to
2051
        experiment with building and adding particular features, the Zip CPU
2052
        makes a good starting point--it is fairly simple. Modifications should
2053
        be simple enough.
2054
\item As an estimate of the ``weight'' of this implementation, the CPU has
2055
        cost me less than 150 hours to implement from its inception.
2056
\item The Zip CPU was designed to be an implementable soft core that could be
2057
        placed within an FPGA, controlling actions internal to the FPGA. It
2058
        fits this role rather nicely. It does not fit the role of a system on
2059
        a chip very well, but then it was never intended to be a system on a
2060
        chip but rather a system within a chip.
2061
\item The extremely simplified instruction set of the Zip CPU was a good
2062
        choice. Although it does not have many of the commonly used
2063
        instructions, PUSH, POP, JSR, and RET among them, the simplified
2064
        instruction set has demonstrated an amazing versatility. I will contend
2065
        therefore and for anyone who will listen, that this instruction set
2066
        offers a full and complete capability for whatever a user might wish
2067
        to do with two exceptions: bytewise character access and accelerated
2068
        floating-point support.
2069
\item This simplified instruction set is easy to decode.
2070
\item The simplified bus transactions (32-bit words only) were also very easy
2071
        to implement.
2072
\item The novel approach of having a single interrupt vector, which just
2073
        brings the CPU back to the instruction it left off at within the last
2074
        interrupt context doesn't appear to have been that much of a problem.
2075
        If most modern systems handle interrupt vectoring in software anyway,
2076
        why maintain hardware support for it?
2077
\item My goal of a high rate of instructions per clock may not be the proper
2078
        measure. For example, if instructions are being read from a SPI flash
2079
        device, such as is common among FPGA implementations, these same
2080
        instructions may suffer stalls of between 64 and 128 cycles per
2081
        instruction just to read the instruction from the flash. Executing the
2082
        instruction in a single clock cycle is no longer the appropriate
2083
        measure. At the same time, it should be possible to use the DMA
2084
        peripheral to copy instructions from the FLASH to a temporary memory
2085
        location, after which they may be executed at a single instruction
2086
        cycle per access again.
2087
\end{itemize}
2088
 
2089
\section{The Not so Good}
2090
\begin{itemize}
2091
\item While one of the stated goals was to use a small amount of logic,
2092
        3k~LUTs isn't that impressively small. Indeed, it's really much
2093
        too expensive when compared against other 8 and 16-bit CPUs that have
2094
        less than 1k LUTs.
2095
 
2096
        Still, \ldots it's not bad, it's just not astonishingly good.
2097
 
2098
\item The fact that the instruction width equals the bus width means that the
2099
        instruction fetch cycle will always be interfering with any load or
2100
        store memory operation, with the only exception being if the
2101
        instruction is already in the cache.  {\em This has become the
2102
        fundamental limit on the speed and performance of the CPU!}
2103
        Those familiar with the Von--Neumann approach of sharing a bus
2104
        between data and instructions will not be surprised by this assessment.
2105
 
2106
        This could be fixed in one of three ways: the instruction set
2107
        architecture could be modified to handle Very Long Instruction Words
2108
        (VLIW) so that each 32--bit word would encode two or more instructions,
2109
        the instruction fetch bus width could be increased from 32--bits to
2110
        64--bits or more, or the instruction bus could be separated from the
2111
        data bus.  Any and all of these approaches would increase the overall
2112
        LUT count.
2113
 
2114
\item The (non-existant) floating point unit was an after-thought, isn't even
2115
        built as a potential option, and most likely won't support the full
2116
        IEEE standard set of FPU instructions--even for single point precision.
2117
        This (non-existant) capability would benefit the most from an
2118
        out-of-order execution capability, which the Zip CPU does not have.
2119
 
2120
        Still, sharing FPU registers with the main register set was a good
2121
        idea and worth preserving, as it simplifies context swapping.
2122
 
2123
        Perhaps this really isn't a problem, but rather a feature.  By not
2124
        implementing FPU instructions, the Zip CPU maintains a lower LUT count
2125
        than it would have if it did implement these instructions.
2126
 
2127
\item The CPU has no character support. This is both good and bad.
2128
        Realistically, the CPU works just fine without it. Characters can be
2129
        supported as subsets of 32-bit words without any problem. Practically,
2130
        though, it will make compiling non-Zip CPU code difficult--especially
2131
        anything that assumes sizeof(int)=4*sizeof(char), or that tries to
2132
        create unions with characters and integers and then attempts to
2133
        reference the address of the characters within that union.
2134
 
2135
\item The Zip CPU does not support a data cache. One can still be built
2136
        externally, but this is a limitation of the CPU proper as built.
2137
        Further, under the theory of the Zip CPU design (that of an embedded
2138
        soft-core processor within an FPGA, where any ``address'' may reference
2139
        either memory or a peripheral that may have side-effects), any data
2140
        cache would need to be based upon an initial knowledge of whether or
2141
        not it is supporting memory (cachable) or peripherals. This knowledge
2142
        must exist somewhere, and that somewhere is currently (and by design)
2143
        external to the CPU.
2144
 
2145
        This may also be written off as a ``feature'' of the Zip CPU, since
2146
        the addition of a data cache can greatly increase the LUT count of
2147
        a soft core.
2148
 
2149
\item Many other instruction sets offer three operand instructions, whereas
2150
        the Zip CPU only offers two operand instructions. This means that it
2151
        takes the Zip CPU more instructions to do many of the same operations.
2152
        The good part of this is that it gives the Zip CPU a greater amount of
2153
        flexibility in its immediate operand mode, although that increased
2154
        flexibility isn't necessarily as valuable as one might like.
2155
 
2156
\item The Zip CPU does not currently detect and trap on either illegal
2157
        instructions or bus errors.  Attempts to access non--existent
2158
        memory quietly return erroneous results, rather than halting the
2159
        process (user mode) or halting or resetting the CPU (supervisor mode).
2160
 
2161
\item The Zip CPU doesn't support out of order execution. I suppose it could
2162
        be modified to do so, but then it would no longer be the ``simple''
2163
        and low LUT count CPU it was designed to be. The two primary results
2164
        are that 1) loads may unnecessarily stall the CPU, even if other
2165
        things could be done while waiting for the load to complete, 2)
2166
        bus errors on stores will never be caught at the point of the error,
2167
        and 3) branch prediction becomes more difficult.
2168
 
2169
\item Although switching to an interrupt context in the Zip CPU design doesn't
2170
        require a tremendous swapping of registers, in reality it still
2171
        does--since any task swap still requires saving and restoring all
2172
        16~user registers. That's a lot of memory movement just to service
2173
        an interrupt.
2174
 
2175
\item The Zip CPU is by no means generic: it will never handle addresses
2176
        larger than 32-bits (16GB) without a complete and total redesign.
2177
        This may limit its utility as a generic CPU in the future, although
2178
        as an embedded CPU within an FPGA this isn't really much of a limit
2179
        or restriction.
2180
 
2181
\item While the Zip CPU has its own assembler, it has no linker and does not
2182
        (yet) support a compiler. The standard C library is an even longer
2183
        shot. My dream of having binutils and gcc support has not been
2184
        realized and at this rate may not be realized. (I've been intimidated
2185
        by the challenge everytime I've looked through those codes.)
2186
 
2187 39 dgisselq
\iffalse
2188 36 dgisselq
\item While the Wishbone Bus (B4) supports a pipelined mode with single cycle
2189
        execution, the Zip CPU is unable to exploit this parallelism. Instead,
2190
        apart from the DMA and the pipelined prefetch, all loads and stores
2191
        are single wishbone bus operations requiring a minimum of 3 clocks.
2192
        (In practice, this has turned into 7-clocks.)
2193 39 dgisselq
        % Addressed, 20150929
2194 36 dgisselq
 
2195
\item There is no control over whether or not an instruction sets the
2196
        condition codes--certain instructions always set the condition codes,
2197
        other instructions never set them. This effectively limits conditional
2198
        instructions to a single instruction only (with two or more
2199
        instructions as an exception), as the first instruction that sets
2200
        condition codes will break the condition code chain.
2201
 
2202
        {\em (A proposed change below address this.)}
2203
 
2204
\item Using the CC register as a trap address was a bad idea--it limits the CC
2205
        registers ability to be used in future expansion, such as by adding
2206
        exception indication flags: bus error, floating point exception, etc.
2207
 
2208
        {\em (This can be changed by a different O/S implementation of the trap
2209
        instruction.)}
2210
\item The current implementation suffers from too many stalls on any
2211
        branch--even if the branch is known early on.
2212
 
2213
        {\em (This is addressed in proposals below.)}
2214
        % Addressed, 20150918
2215
 
2216
\item In a similar fashion, a switch to interrupt context forces the pipeline
2217
        to be cleared, whereas it might make more sense to just continue
2218
        executing the instructions already in the pipeline while the prefetch
2219
        stage is working on switching to the interrupt context.
2220
 
2221
        {\em (Also addressed in proposals below.)}
2222
        % This should happen so rarely that it is not really a problem
2223
\fi
2224
 
2225
\end{itemize}
2226
 
2227
\section{The Next Generation}
2228
This section could also be labeled as my ``To do'' list.
2229
 
2230
Given the feedback listed above, perhaps its time to consider what changes could be made to improve the Zip CPU in the future. I offer the following as proposals:
2231
 
2232
\begin{itemize}
2233
\item {\bf Remove the low LUT goal.} It wasn't really achieved, and the
2234
        proposals below will only increase the amount of logic the Zip CPU
2235
        requires.  While I expect that the Zip CPU will always be somewhat
2236
        of a light weight, it will never be the smallest kid on the block.
2237
 
2238
        I'm actually struggling with this idea.  The whole goal of the Zip
2239
        CPU was to be light weight.  Wouldn't it make more sense to create and
2240
        maintain options whereby it would remain lightweight?  For example, if
2241
        the process accounting registers are anything but light weight, why
2242
        keep them?  Why not instead make some compile flags that just turn them
2243
        off, keeping the CPU lightweight?  The same holds for the prefetch
2244
        cache.
2245
 
2246 39 dgisselq
\item The `{\tt .V}' condition was never used in any code other than my test
2247
        code.  Suggest changing it to a `{\tt .LE}' condition, which seems
2248
        to be more useful.
2249
 
2250
\item {\bf Consider a more traditional Instruction Cache.}  The current
2251
        pipelined instruction cache just reads a window of memory into
2252
        its cache.  If the CPU leaves that window, the entire cache is
2253
        invalidated.  A more traditional cache, however, might allow
2254
        common subroutines to stay within the cache without invalidating the
2255
        entire cache structure.
2256
 
2257 36 dgisselq
\iffalse
2258
\item {\bf Adjust the Zip CPU so that conditional instructions do not set
2259
        flags}, although they may explicitly set condition codes if writing
2260
        to the CC register.
2261
 
2262
        This is a simple change to the core, and may show up in new releases.
2263
        % Fixed, 20150918
2264
 
2265
\item Add in an {\bf unpredictable branch delay slot}, so that on any branch
2266
        the delay slot may or may not be executed before the branch.
2267
        Instructions that do not depend upon the branch, and that should be
2268
        executed were the branch not taken, could be placed into the delay
2269
        slot. Thus, if the branch isn't taken, we wouldn't suffer the stall,
2270
        whereas it wouldn't affect the timing of the branch if taken. It would
2271
        just do something irrelevant.
2272
 
2273
        % Changes made, 20150918, make this option no longer relevant
2274
 
2275
\item {\bf Re-engineer Branch Processing.}  There's no reason why a {\tt BRA}
2276
        instruction should create five stall cycles.  The decode stage, plus
2277
        the prefetch engine, should be able to drop this number of stalls via
2278
        better branch handling.
2279
 
2280
        Indeed, this could turn into a simple means of branch prediction:
2281
        if {\tt BRA} suffered a single stall only, whereas {\tt BRA.C}
2282
        suffered five stalls, then {\tt BRA.!C} followed by {\tt BRA} would
2283
        be faster than a {\tt BRA.C} instruction.  This would then allow a
2284
        compiler to do explicit branch optimizations.
2285
 
2286
        Of course, longer branches using {\tt ADD X,PC} would still not be
2287
        optimized.
2288
 
2289
        % DONE: 20150918 -- to include the ADD X,PC instructions
2290
 
2291
\item {\bf Request bus access for Load/Store two cycles earlier.}  The problem
2292
        here is the contention for the bus between the memory unit and the
2293
        prefetch unit.  Currently, the memory unit must ask the prefetch
2294
        unit to release the bus if it is in the middle of a bus cycle.  At this
2295
        point, the prefetch drops the {\tt STB} line on the next clock and must
2296
        then wait for the last {\tt ACK} before releasing the bus.  If the
2297
        request takes one clock, dropping the strobe line the next, waiting
2298
        for an acknowledgement takes another, and then the bus must be idle
2299
        for one cycle before starting again, these extra cycles add up.
2300
        It should be possible to tell the prefetch stage to give up the bus
2301
        as soon as the decoder knows the instruction will need the bus.
2302
        Indeed, if done in the decode stage, this might drop the seven cycle
2303
        access down by two cycles.
2304
        % FIXED: 20150918
2305
 
2306
\item {\bf Very Long Instruction Word (VLIW).}  Now, to speed up operation, I
2307
        propose that the Zip CPU instruction set be modified towards a Very
2308
        Long Instruction Word (VLIW) implementation. In this implementation,
2309
        an instruction word may contain either one or two separate
2310
        instructions. The first instruction would take up the high order bits,
2311
        the second optional instruction the lower 16-bits. Further, I propose
2312
        that any of the ALU instructions (SUB through LSR) automatically have
2313
        a second instruction whenever their operand `B' is a register, and use
2314
        the full 20-bit immediate if not. This will effectively eliminate the
2315
        register plus immediate mode for all of these instructions.
2316
 
2317
        This is the minimal required change to increase the number of
2318
        instructions per clock cycle. Other changes would need to take place
2319
        as well to support this. These include:
2320
        \begin{itemize}
2321
        \item Instruction words containing two instructions would take two
2322
                clocks to complete, while requiring only a single cycle
2323
                instruction fetch.
2324
        \item Instructions preceded by a label in the asseembler must always
2325
                start in the high order word.
2326
        \item VLIW's, once started, must always execute to completion. The
2327
                upper word may set the PC, the lower word may not. Regardless
2328
                of whether the upper word sets the PC, the lower word must
2329
                still be guaranteed to complete before the PC changes. On any
2330
                switch to (or from) interrupt context, both instructions must
2331
                complete or none of the instructions in the word shall
2332
                complete prior to the switch.
2333
        \item STEP commands and BREAK instructions will only take place after
2334
                the entire word is executed.
2335
        \end{itemize}
2336
 
2337
        If done well, the assembler should be able to handle these changes
2338
        with the biggest impacts to the user being increased performance and
2339
        a loss of the register plus immediate ALU modes. (These weren't really
2340
        relevant for the XOR, OR, AND, etc. operations anyway.) Machine code
2341
        compatibility will not be maintained.
2342
 
2343
        A proposed secondary instruction set might consist of: a four bit
2344
        operand (any of the prior instructions would be supported, with some
2345
        exceptions such as moves to and from user registers while in
2346
        supervisor mode not being supported), a 4-bit register result (PC not
2347
        allowed), a 3-bit conditional (identical to the conditional for the
2348
        upper word), a single bit for whether or not an immediate is present
2349
        or not, followed by either a 4-bit register or a 4-bit signed
2350
        immediate. The multiply instruction would steal the immediate flag to
2351
        be used as a sign indication, forcing both operands to be registers
2352
        without any immediate offsets.
2353
 
2354
        {\em Initial conversion of several library functions to this secondary
2355
        instruction set has demonstrated little to no gain.   The problem was
2356
        that the new instruction set was made by joining a rarely used
2357
        instruction (ALU with register and not immediate) with a more common
2358
        instruction.  The utility was then limited by the utility of the rare
2359
        instrction, which limited the impact of the entire approach.  }
2360
\else
2361
\item {\bf Very Long Instruction Word (VLIW).}  The goal here would be to
2362
        create a new instruction set whereby two instructions would be encoded
2363
        in each 32--bit word.  While this may speed up
2364
        CPU operation, it would necessitate an instruction redesign.
2365
\fi
2366
 
2367
\end{itemize}
2368
 
2369
 
2370 21 dgisselq
% Appendices
2371
% Index
2372
\end{document}
2373
 
2374
 

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