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[/] [zipcpu/] [trunk/] [rtl/] [README.md] - Blame information for rev 209

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1 209 dgisselq
This directory contains three sub-directories:
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- [core](core), where all of the actual components to the CPU proper are contained
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- [peripherals](peripherals), where several common CPU peripherals are kept.  These aren't really external peripherals per se, although they may be implemented as such.  Rather, these peripherals are components that are important to the CPU's functionality.  As such, they are often distributed with the CPU proper, and used internally by supervisor programs.
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- [ex](ex), where some general wishbone cores are kept, such as arbiters, delays, and even where I keep a copy of the formal wishbone properties.
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Within this ZipCPU RTL directory are just the two primary wrappers for the
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ZipCPU: [ZipBones](zipbones.v) and [ZipSystem](zipsystem.v).  These wrappers
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connect an external wishbone slave interface to the debugging port of the
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CPU, so that the CPU can be reset, started, stopped, and in general debugged.
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The [ZipBones](./zipbones.v) would be the appropriate wrapper if you want the
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CPU to fit in the tightest space possible (Ex: Digilent's [CMod
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S6](https://github.com/ZipCPU/s6soc)).
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Use the [ZipSystem](./zipsystem.v) if you want to give the CPU some
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basic peripherals, such as:
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- 2x [Interrupt controllers](./peripherals/icontrol.v)
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- [Timers](peripherals/ziptimer), and an [experimental timer called zipjiffies](peripherals/zipjiffies.v) that's been with the CPU for some time
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- [Performance counters](peripherals/zipcounter.v), to measure your performance
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- A [Direct Memory Access Controller](./peripherals/wbdmac.v)
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- Or even the [Memory Management Unit](./peripherals/zipmmu.v)
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If you are just looking for the CPU's code itself, check out
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[zipcpu.v](core/zipcpu.v)
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within the
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[core](core) subdirectory.
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That's of the main core of the ZipCPU itself.
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