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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbdblpriarb.v] - Blame information for rev 36

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1 36 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbdblpriarb.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This should almost be identical to the priority arbiter, save
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//              for a simple diffence: it allows the arbitration of two
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//      separate wishbone buses.  The purpose of this is to push the address
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//      resolution back one cycle, so that by the first clock visible to this
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//      core, it is known which of two parts of the bus the desired address
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//      will be on, save that we still use the arbiter since the underlying
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//      device doesn't know that there are two wishbone buses.
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//
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//      So at this point we've deviated from the WB spec somewhat, by allowing
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//      two CYC and two STB lines.  Everything else is the same.  This allows
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//      (in this case the Zip CPU) to determine whether or not the access
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//      will be to the local ZipSystem bus or the external WB bus on the clock
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//      before the local bus access, otherwise peripherals were needing to do
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//      multiple device selection comparisons/test within a clock: 1) is this
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//      for the local or external bus, and 2) is this referencing me as a
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//      peripheral.  This then caused the ZipCPU to fail all timing specs.
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//      By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the
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//      determination of local vs external can be made one clock earlier
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//      where there's still time for the logic, and the second comparison
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//      now has time to complete.
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//
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//      So let me try to explain this again.  To use this arbiter, one of the
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//      two masters sets CYC and STB before, only the master determines which
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//      of two address spaces the CYC and STB apply to before the clock and
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//      only sets the appropriate CYC and STB lines.  Then, on the clock tick,
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//      the arbiter determines who gets *both* busses, as they both share every
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//      other WB line. Thus, only one of CYC_A and CYC_B going out will ever
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//      be high at a given time.
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//
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//      Hopefully this makes more sense than it sounds. If not, check out the
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//      code below for a better explanation.
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//
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//      20150919 -- Added supported for the WB error signal.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  wbdblpriarb(i_clk, i_rst,
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        // Bus A
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        i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
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        // Bus B
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        i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
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        // Both buses
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        o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat,
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                i_ack, i_stall, i_err);
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        parameter                       DW=32, AW=32;
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        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
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        // what it would (might) do to the synchronous reset signal, i_rst.
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        input                           i_clk, i_rst;
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        // Bus A
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        input                           i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
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        input           [(AW-1):0]       i_a_adr;
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        input           [(DW-1):0]       i_a_dat;
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        output  wire                    o_a_ack, o_a_stall, o_a_err;
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        // Bus B
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        input                           i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
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        input           [(AW-1):0]       i_b_adr;
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        input           [(DW-1):0]       i_b_dat;
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        output  wire                    o_b_ack, o_b_stall, o_b_err;
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        // 
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        output  wire                    o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
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        output  wire    [(AW-1):0]       o_adr;
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        output  wire    [(DW-1):0]       o_dat;
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        input                           i_ack, i_stall, i_err;
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        // All of our logic is really captured in the 'r_a_owner' register.
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        // This register determines who owns the bus.  If no one is requesting
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        // the bus, ownership goes to A on the next clock.  Otherwise, if B is 
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        // requesting the bus and A is not, then ownership goes to not A on
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        // the next clock.  (Sounds simple ...)
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        //
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        // The CYC logic is here to make certain that, by the time we determine
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        // who the bus owner is, we can do so based upon determined criteria.
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        assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
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        assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
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        reg     r_a_owner;
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        initial r_a_owner = 1'b1;
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        always @(posedge i_clk)
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                if (i_rst)
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                        r_a_owner <= 1'b1;
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                else if ((~o_cyc_a)&&(~o_cyc_b))
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                        r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1;
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        // Realistically, if neither master owns the bus, the output is a
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        // don't care.  Thus we trigger off whether or not 'A' owns the bus.
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        // If 'B' owns it all we care is that 'A' does not.  Likewise, if 
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        // neither owns the bus than the values on these various lines are
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        // irrelevant.
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        assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
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        assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
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        assign o_we    = (r_a_owner) ? i_a_we    : i_b_we;
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        assign o_adr   = (r_a_owner) ? i_a_adr   : i_b_adr;
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        assign o_dat   = (r_a_owner) ? i_a_dat   : i_b_dat;
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        // We cannot allow the return acknowledgement to ever go high if
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        // the master in question does not own the bus.  Hence we force it
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        // low if the particular master doesn't own the bus.
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        assign  o_a_ack   = ( r_a_owner) ? i_ack   : 1'b0;
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        assign  o_b_ack   = (~r_a_owner) ? i_ack   : 1'b0;
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        // Stall must be asserted on the same cycle the input master asserts
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        // the bus, if the bus isn't granted to him.
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        assign  o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
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        assign  o_b_stall = (~r_a_owner) ? i_stall : 1'b1;
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        //
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        // These error lines will be implemented soon, as soon as the rest of
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        // the Zip CPU is ready to support them.
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        //
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        assign  o_a_err = ( r_a_owner) ? i_err : 1'b0;
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        assign  o_b_err = (~r_a_owner) ? i_err : 1'b0;
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endmodule
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