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1 36 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbpriarbiter.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is a priority bus arbiter.  It allows two separate wishbone
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//              masters to connect to the same bus, while also guaranteeing
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//              that one master can have the bus with no delay any time the
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//              other master is not using the bus.  The goal is to eliminate
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//              the combinatorial logic required in the other wishbone
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//              arbiter, while still guarateeing access time for the priority
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//              channel.
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//
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//              The core logic works like this:
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//
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//              1. When no one requests the bus, 'A' is granted the bus and
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//                      guaranteed that any access will go right through.
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//              2. If 'B' requests the bus (asserts cyc), and the bus is idle,
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//                      then 'B' will be granted the bus.
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//              3. Bus grants last as long as the 'cyc' line is high.
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//              4. Once 'cyc' is dropped, the bus returns to 'A' as the owner.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  wbpriarbiter(i_clk, i_rst,
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        // Bus A
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        i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
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        // Bus B
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        i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
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        // Both buses
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        o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err);
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        parameter                       DW=32, AW=32;
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        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
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        // what it would (might) do to the synchronous reset signal, i_rst.
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        input                           i_clk, i_rst;
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        // Bus A
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        input                           i_a_cyc, i_a_stb, i_a_we;
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        input           [(AW-1):0]       i_a_adr;
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        input           [(DW-1):0]       i_a_dat;
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        output  wire                    o_a_ack, o_a_stall, o_a_err;
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        // Bus B
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        input                           i_b_cyc, i_b_stb, i_b_we;
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        input           [(AW-1):0]       i_b_adr;
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        input           [(DW-1):0]       i_b_dat;
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        output  wire                    o_b_ack, o_b_stall, o_b_err;
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        // 
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        output  wire                    o_cyc, o_stb, o_we;
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        output  wire    [(AW-1):0]       o_adr;
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        output  wire    [(DW-1):0]       o_dat;
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        input                           i_ack, i_stall, i_err;
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        // Go high immediately (new cycle) if ...
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        //      Previous cycle was low and *someone* is requesting a bus cycle
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        // Go low immadiately if ...
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        //      We were just high and the owner no longer wants the bus
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        // WISHBONE Spec recommends no logic between a FF and the o_cyc
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        //      This violates that spec.  (Rec 3.15, p35)
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        assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc;
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        reg     r_a_owner;
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        initial r_a_owner = 1'b1;
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        always @(posedge i_clk)
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                if (~i_b_cyc)
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                        r_a_owner <= 1'b1;
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                else if ((i_b_cyc)&&(~i_a_cyc))
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                        r_a_owner <= 1'b0;
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        // Realistically, if neither master owns the bus, the output is a
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        // don't care.  Thus we trigger off whether or not 'A' owns the bus.
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        // If 'B' owns it all we care is that 'A' does not.  Likewise, if 
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        // neither owns the bus than the values on the various lines are
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        // irrelevant.
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        assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb;
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        assign o_we  = (r_a_owner) ? i_a_we  : i_b_we;
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        assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
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        assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
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        // We cannot allow the return acknowledgement to ever go high if
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        // the master in question does not own the bus.  Hence we force it
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        // low if the particular master doesn't own the bus.
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        assign  o_a_ack   = ( r_a_owner) ? i_ack   : 1'b0;
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        assign  o_b_ack   = (~r_a_owner) ? i_ack   : 1'b0;
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        // Stall must be asserted on the same cycle the input master asserts
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        // the bus, if the bus isn't granted to him.
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        assign  o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
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        assign  o_b_stall = (~r_a_owner) ? i_stall : 1'b1;
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        // 
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        // 
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        assign  o_a_err = ( r_a_owner) ? i_err : 1'b0;
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        assign  o_b_err = (~r_a_owner) ? i_err : 1'b0;
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endmodule
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