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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Blame information for rev 209

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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    cpuops.v
4
//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the ZipCPU ALU function.  It handles all of the
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//              instruction opcodes 0-13.  (14-15 are divide opcodes).
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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//
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`include "cpudefs.v"
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//
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module  cpuops(i_clk,i_reset, i_stb, i_op, i_a, i_b, o_c, o_f, o_valid,
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                        o_busy);
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        parameter               IMPLEMENT_MPY = `OPT_MULTIPLY;
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        parameter       [0:0]     OPT_SHIFTS = 1'b1;
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        input   wire    i_clk, i_reset, i_stb;
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        input   wire    [3:0]    i_op;
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        input   wire    [31:0]   i_a, i_b;
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        output  reg     [31:0]   o_c;
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        output  wire    [3:0]    o_f;
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        output  reg             o_valid;
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        output  wire            o_busy;
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        genvar  k;
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        // Shift register pre-logic
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        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
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        generate if (OPT_SHIFTS)
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        begin : IMPLEMENT_SHIFTS
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                wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
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                assign  w_pre_asr_input = { i_a, 1'b0 };
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                assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
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                assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
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                                        : w_pre_asr_shifted;// ASR
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                assign  w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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                                        :((i_b[5])?{32'h0,i_a[31]}
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                                        : ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
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                assign  w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
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                                        :((i_b[5])?{i_a[0], 32'h0}
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                                        : ({1'b0, i_a } << i_b[4:0]));   // LSL
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        end else begin : NO_SHIFTS
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                assign  w_asr_result = {   i_a[31], i_a[31:0] };
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                assign  w_lsr_result = {      1'b0, i_a[31:0] };
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                assign  w_lsl_result = { i_a[31:0],      1'b0 };
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81
        end endgenerate
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        //
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        // Bit reversal pre-logic
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        wire    [31:0]   w_brev_result;
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        generate
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        for(k=0; k<32; k=k+1)
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        begin : bit_reversal_cpuop
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                assign w_brev_result[k] = i_b[31-k];
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        end endgenerate
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        // Prelogic for our flags registers
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        wire    z, n, v;
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        reg     c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
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        always @(posedge i_clk)
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        if (i_stb) // 1 LUT
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                set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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                        ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
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                        ||(i_op == 4'h6) // LSL
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                        ||(i_op == 4'h5)); // LSR
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        always @(posedge i_clk)
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        if (i_stb) // 1 LUT
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                keep_sgn_on_ovfl<=
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                        (((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
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                        ||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
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        wire    [63:0]   mpy_result; // Where we dump the multiply result
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        wire    mpyhi;          // Return the high half of the multiply
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        wire    mpybusy;        // The multiply is busy if true
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        wire    mpydone;        // True if we'll be valid on the next clock;
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        // A 4-way multiplexer can be done in one 6-LUT.
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        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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        //      the Xilinx multiplexer fabric that follows.
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        // Given that we wish to apply this multiplexer approach to 33-bits,
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        // this will cost a minimum of 132 6-LUTs.
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119
        wire    this_is_a_multiply_op;
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        assign  this_is_a_multiply_op = (i_stb)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
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        //
123
        // Pull in the multiply logic from elsewhere
124
        //
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`ifdef  FORMAL
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`define MPYOP   abs_mpy
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`else
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`define MPYOP   mpyop
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`endif
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        `MPYOP #(.IMPLEMENT_MPY(IMPLEMENT_MPY)) thempy(i_clk, i_reset, this_is_a_multiply_op, i_op[1:0],
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                i_a, i_b, mpydone, mpybusy, mpy_result, mpyhi);
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133
        //
134
        // The master ALU case statement
135
        //
136
        always @(posedge i_clk)
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        if (i_stb)
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        begin
139
                pre_sign <= (i_a[31]);
140
                c <= 1'b0;
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                casez(i_op)
142
                4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
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                4'b0001:   o_c   <= i_a & i_b;          // BTST/And
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                4'b0010:{c,o_c } <= i_a + i_b;          // Add
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                4'b0011:   o_c   <= i_a | i_b;          // Or
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                4'b0100:   o_c   <= i_a ^ i_b;          // Xor
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                4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
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                4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
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                4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
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                4'b1000:   o_c   <= w_brev_result;      // BREV
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                4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
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                4'b1010:   o_c   <= mpy_result[63:32];  // MPYHU
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                4'b1011:   o_c   <= mpy_result[63:32];  // MPYHS
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                4'b1100:   o_c   <= mpy_result[31:0];    // MPY
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                default:   o_c   <= i_b;                // MOV, LDI
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                endcase
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        end else // if (mpydone)
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                // set the output based upon the multiply result
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                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
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        reg     r_busy;
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        initial r_busy = 1'b0;
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        always @(posedge i_clk)
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        if (i_reset)
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                r_busy <= 1'b0;
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        else if (IMPLEMENT_MPY > 1)
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                r_busy <= ((i_stb)&&(this_is_a_multiply_op))||mpybusy;
168
        else
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                r_busy <= 1'b0;
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        assign  o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
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173
 
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        assign  z = (o_c == 32'h0000);
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        assign  n = (o_c[31]);
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        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
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        wire    vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
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        assign  o_f = { v, n^vx, c, z };
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        initial o_valid = 1'b0;
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        always @(posedge i_clk)
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        if (i_reset)
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                o_valid <= 1'b0;
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        else if (IMPLEMENT_MPY <= 1)
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                o_valid <= (i_stb);
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        else
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                o_valid <=((i_stb)&&(!this_is_a_multiply_op))||(mpydone);
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`ifdef  FORMAL
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        initial assume(i_reset);
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        reg     f_past_valid;
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        initial f_past_valid = 1'b0;
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        always @(posedge i_clk)
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                f_past_valid = 1'b1;
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198
`define ASSERT  assert
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`ifdef  CPUOPS
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`define ASSUME  assume
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`else
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`define ASSUME  assert
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`endif
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        // No request should be given us if/while we are busy
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        always @(posedge i_clk)
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        if (o_busy)
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                `ASSUME(!i_stb);
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        // Following any request other than a multiply request, we should
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        // respond in the next cycle
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(o_busy))&&(!$past(this_is_a_multiply_op)))
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                `ASSERT(!o_busy);
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        // Valid and busy can never both be asserted
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        always @(posedge i_clk)
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                `ASSERT((!o_valid)||(!r_busy));
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        // Following any busy, we should always become valid
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        always @(posedge i_clk)
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        if ((f_past_valid)&&($past(o_busy))&&(!o_busy))
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                `ASSERT($past(i_reset) || o_valid);
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        // Check the shift values
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        always @(posedge i_clk)
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        if ((f_past_valid)&&($past(i_stb)))
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        begin
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                if (($past(|i_b[31:6]))||($past(i_b[5:0])>6'd32))
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                begin
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                        assert(($past(i_op)!=4'h5)
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                                        ||({o_c,c}=={(33){1'b0}}));
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                        assert(($past(i_op)!=4'h6)
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                                        ||({c,o_c}=={(33){1'b0}}));
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                        assert(($past(i_op)!=4'h7)
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                                        ||({o_c,c}=={(33){$past(i_a[31])}}));
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                end else if ($past(i_b[5:0]==6'd32))
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                begin
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                        assert(($past(i_op)!=4'h5)
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                                ||(o_c=={(32){1'b0}}));
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                        assert(($past(i_op)!=4'h6)
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                                ||(o_c=={(32){1'b0}}));
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                        assert(($past(i_op)!=4'h7)
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                                ||(o_c=={(32){$past(i_a[31])}}));
245
                end if ($past(i_b)==0)
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                begin
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                        assert(($past(i_op)!=4'h5)
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                                ||({o_c,c}=={$past(i_a), 1'b0}));
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                        assert(($past(i_op)!=4'h6)
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                                ||({c,o_c}=={1'b0, $past(i_a)}));
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                        assert(($past(i_op)!=4'h7)
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                                ||({o_c,c}=={$past(i_a), 1'b0}));
253
                end if ($past(i_b)==1)
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                begin
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                        assert(($past(i_op)!=4'h5)
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                                ||({o_c,c}=={1'b0, $past(i_a)}));
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                        assert(($past(i_op)!=4'h6)
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                                ||({c,o_c}=={$past(i_a),1'b0}));
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                        assert(($past(i_op)!=4'h7)
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                                ||({o_c,c}=={$past(i_a[31]),$past(i_a)}));
261
                end if ($past(i_b)==2)
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                begin
263
                        assert(($past(i_op)!=4'h5)
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                                ||({o_c,c}=={2'b0, $past(i_a[31:1])}));
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                        assert(($past(i_op)!=4'h6)
266
                                ||({c,o_c}=={$past(i_a[30:0]),2'b0}));
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                        assert(($past(i_op)!=4'h7)
268
                                ||({o_c,c}=={{(2){$past(i_a[31])}},$past(i_a[31:1])}));
269
                end if ($past(i_b)==31)
270
                begin
271
                        assert(($past(i_op)!=4'h5)
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                                ||({o_c,c}=={31'b0, $past(i_a[31:30])}));
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                        assert(($past(i_op)!=4'h6)
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                                ||({c,o_c}=={$past(i_a[1:0]),31'b0}));
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                        assert(($past(i_op)!=4'h7)
276
                                ||({o_c,c}=={{(31){$past(i_a[31])}},$past(i_a[31:30])}));
277
                end
278
        end
279
`endif
280 2 dgisselq
endmodule
281 209 dgisselq
//
282
// iCE40        NoMPY,w/Shift   NoMPY,w/o Shift
283
//  SB_CARRY             64              64
284
//  SB_DFFE               3               3
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//  SB_DFFESR             1               1
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//  SB_DFFSR             33              33
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//  SB_LUT4             748             323

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