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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    cpuops.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     This is the ZipCPU ALU function.  It handles all of the
//              instruction opcodes 0-13.  (14-15 are divide opcodes).
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype        none
//
//
`include "cpudefs.v"
//
module  cpuops(i_clk,i_reset, i_stb, i_op, i_a, i_b, o_c, o_f, o_valid,
                        o_busy);
        parameter               IMPLEMENT_MPY = `OPT_MULTIPLY;
        parameter       [0:0]     OPT_SHIFTS = 1'b1;
        input   wire    i_clk, i_reset, i_stb;
        input   wire    [3:0]    i_op;
        input   wire    [31:0]   i_a, i_b;
        output  reg     [31:0]   o_c;
        output  wire    [3:0]    o_f;
        output  reg             o_valid;
        output  wire            o_busy;
 
        genvar  k;
 
        // Shift register pre-logic
        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
        generate if (OPT_SHIFTS)
        begin : IMPLEMENT_SHIFTS
                wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
                assign  w_pre_asr_input = { i_a, 1'b0 };
                assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
                assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
                                        : w_pre_asr_shifted;// ASR
                assign  w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
                                        :((i_b[5])?{32'h0,i_a[31]}
 
                                        : ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
                assign  w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
                                        :((i_b[5])?{i_a[0], 32'h0}
                                        : ({1'b0, i_a } << i_b[4:0]));   // LSL
        end else begin : NO_SHIFTS
 
                assign  w_asr_result = {   i_a[31], i_a[31:0] };
                assign  w_lsr_result = {      1'b0, i_a[31:0] };
                assign  w_lsl_result = { i_a[31:0],      1'b0 };
 
        end endgenerate
 
        //
        // Bit reversal pre-logic
        wire    [31:0]   w_brev_result;
        generate
        for(k=0; k<32; k=k+1)
        begin : bit_reversal_cpuop
                assign w_brev_result[k] = i_b[31-k];
        end endgenerate
 
        // Prelogic for our flags registers
        wire    z, n, v;
        reg     c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
        always @(posedge i_clk)
        if (i_stb) // 1 LUT
                set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                        ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                        ||(i_op == 4'h6) // LSL
                        ||(i_op == 4'h5)); // LSR
 
        always @(posedge i_clk)
        if (i_stb) // 1 LUT
                keep_sgn_on_ovfl<=
                        (((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                        ||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
 
        wire    [63:0]   mpy_result; // Where we dump the multiply result
        wire    mpyhi;          // Return the high half of the multiply
        wire    mpybusy;        // The multiply is busy if true
        wire    mpydone;        // True if we'll be valid on the next clock;
 
        // A 4-way multiplexer can be done in one 6-LUT.
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
        //      the Xilinx multiplexer fabric that follows.
        // Given that we wish to apply this multiplexer approach to 33-bits,
        // this will cost a minimum of 132 6-LUTs.
 
        wire    this_is_a_multiply_op;
        assign  this_is_a_multiply_op = (i_stb)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
 
        //
        // Pull in the multiply logic from elsewhere
        //
`ifdef  FORMAL
`define MPYOP   abs_mpy
`else
`define MPYOP   mpyop
`endif
        `MPYOP #(.IMPLEMENT_MPY(IMPLEMENT_MPY)) thempy(i_clk, i_reset, this_is_a_multiply_op, i_op[1:0],
                i_a, i_b, mpydone, mpybusy, mpy_result, mpyhi);
 
        //
        // The master ALU case statement
        //
        always @(posedge i_clk)
        if (i_stb)
        begin
                pre_sign <= (i_a[31]);
                c <= 1'b0;
                casez(i_op)
                4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
                4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                4'b0010:{c,o_c } <= i_a + i_b;          // Add
                4'b0011:   o_c   <= i_a | i_b;          // Or
                4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                4'b1000:   o_c   <= w_brev_result;      // BREV
                4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                4'b1010:   o_c   <= mpy_result[63:32];  // MPYHU
                4'b1011:   o_c   <= mpy_result[63:32];  // MPYHS
                4'b1100:   o_c   <= mpy_result[31:0];    // MPY
                default:   o_c   <= i_b;                // MOV, LDI
                endcase
        end else // if (mpydone)
                // set the output based upon the multiply result
                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
 
        reg     r_busy;
        initial r_busy = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
                r_busy <= 1'b0;
        else if (IMPLEMENT_MPY > 1)
                r_busy <= ((i_stb)&&(this_is_a_multiply_op))||mpybusy;
        else
                r_busy <= 1'b0;
 
        assign  o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
 
 
        assign  z = (o_c == 32'h0000);
        assign  n = (o_c[31]);
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
        wire    vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
 
        assign  o_f = { v, n^vx, c, z };
 
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
                o_valid <= 1'b0;
        else if (IMPLEMENT_MPY <= 1)
                o_valid <= (i_stb);
        else
                o_valid <=((i_stb)&&(!this_is_a_multiply_op))||(mpydone);
 
`ifdef  FORMAL
        initial assume(i_reset);
        reg     f_past_valid;
 
        initial f_past_valid = 1'b0;
        always @(posedge i_clk)
                f_past_valid = 1'b1;
 
`define ASSERT  assert
`ifdef  CPUOPS
`define ASSUME  assume
`else
`define ASSUME  assert
`endif
 
        // No request should be given us if/while we are busy
        always @(posedge i_clk)
        if (o_busy)
                `ASSUME(!i_stb);
 
        // Following any request other than a multiply request, we should
        // respond in the next cycle
        always @(posedge i_clk)
        if ((f_past_valid)&&(!$past(o_busy))&&(!$past(this_is_a_multiply_op)))
                `ASSERT(!o_busy);
 
        // Valid and busy can never both be asserted
        always @(posedge i_clk)
                `ASSERT((!o_valid)||(!r_busy));
 
        // Following any busy, we should always become valid
        always @(posedge i_clk)
        if ((f_past_valid)&&($past(o_busy))&&(!o_busy))
                `ASSERT($past(i_reset) || o_valid);
 
        // Check the shift values
        always @(posedge i_clk)
        if ((f_past_valid)&&($past(i_stb)))
        begin
                if (($past(|i_b[31:6]))||($past(i_b[5:0])>6'd32))
                begin
                        assert(($past(i_op)!=4'h5)
                                        ||({o_c,c}=={(33){1'b0}}));
                        assert(($past(i_op)!=4'h6)
                                        ||({c,o_c}=={(33){1'b0}}));
                        assert(($past(i_op)!=4'h7)
                                        ||({o_c,c}=={(33){$past(i_a[31])}}));
                end else if ($past(i_b[5:0]==6'd32))
                begin
                        assert(($past(i_op)!=4'h5)
                                ||(o_c=={(32){1'b0}}));
                        assert(($past(i_op)!=4'h6)
                                ||(o_c=={(32){1'b0}}));
                        assert(($past(i_op)!=4'h7)
                                ||(o_c=={(32){$past(i_a[31])}}));
                end if ($past(i_b)==0)
                begin
                        assert(($past(i_op)!=4'h5)
                                ||({o_c,c}=={$past(i_a), 1'b0}));
                        assert(($past(i_op)!=4'h6)
                                ||({c,o_c}=={1'b0, $past(i_a)}));
                        assert(($past(i_op)!=4'h7)
                                ||({o_c,c}=={$past(i_a), 1'b0}));
                end if ($past(i_b)==1)
                begin
                        assert(($past(i_op)!=4'h5)
                                ||({o_c,c}=={1'b0, $past(i_a)}));
                        assert(($past(i_op)!=4'h6)
                                ||({c,o_c}=={$past(i_a),1'b0}));
                        assert(($past(i_op)!=4'h7)
                                ||({o_c,c}=={$past(i_a[31]),$past(i_a)}));
                end if ($past(i_b)==2)
                begin
                        assert(($past(i_op)!=4'h5)
                                ||({o_c,c}=={2'b0, $past(i_a[31:1])}));
                        assert(($past(i_op)!=4'h6)
                                ||({c,o_c}=={$past(i_a[30:0]),2'b0}));
                        assert(($past(i_op)!=4'h7)
                                ||({o_c,c}=={{(2){$past(i_a[31])}},$past(i_a[31:1])}));
                end if ($past(i_b)==31)
                begin
                        assert(($past(i_op)!=4'h5)
                                ||({o_c,c}=={31'b0, $past(i_a[31:30])}));
                        assert(($past(i_op)!=4'h6)
                                ||({c,o_c}=={$past(i_a[1:0]),31'b0}));
                        assert(($past(i_op)!=4'h7)
                                ||({o_c,c}=={{(31){$past(i_a[31])}},$past(i_a[31:30])}));
                end
        end
`endif
endmodule
//
// iCE40        NoMPY,w/Shift   NoMPY,w/o Shift
//  SB_CARRY             64              64
//  SB_DFFE               3               3
//  SB_DFFESR             1               1
//  SB_DFFSR             33              33
//  SB_LUT4             748             323

Line No.	Rev	Author	Line
1	201	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2	2	dgisselq	`//`
3			`// Filename: cpuops.v`
4			`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7	209	dgisselq	`// Purpose: This is the ZipCPU ALU function. It handles all of the`
8			`// instruction opcodes 0-13. (14-15 are divide opcodes).`
9	2	dgisselq	`//`
10	69	dgisselq	`//`
11	2	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
12	69	dgisselq	`// Gisselquist Technology, LLC`
13	2	dgisselq	`//`
14	201	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
15	2	dgisselq	`//`
16	209	dgisselq	`// Copyright (C) 2015-2019, Gisselquist Technology, LLC`
17	2	dgisselq	`//`
18			`// This program is free software (firmware): you can redistribute it and/or`
19			`// modify it under the terms of the GNU General Public License as published`
20			`// by the Free Software Foundation, either version 3 of the License, or (at`
21			`// your option) any later version.`
22			`//`
23			`// This program is distributed in the hope that it will be useful, but WITHOUT`
24			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
25			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
26			`// for more details.`
27			`//`
28	201	dgisselq	`// You should have received a copy of the GNU General Public License along`
29			`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
30			`// target there if the PDF file isn't present.) If not, see`
31			`// <http://www.gnu.org/licenses/> for a copy.`
32			`//`
33	2	dgisselq	`// License: GPL, v3, as defined and found on www.gnu.org,`
34			`// http://www.gnu.org/licenses/gpl.html`
35			`//`
36			`//`
37	201	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
38	2	dgisselq	`//`
39	209	dgisselq	`//`
40			`default_nettype none
41			`//`
42			`//`
43	193	dgisselq	`include "cpudefs.v"
44			`//`
45	209	dgisselq	`module cpuops(i_clk,i_reset, i_stb, i_op, i_a, i_b, o_c, o_f, o_valid,`
46	193	dgisselq	`o_busy);`
47	209	dgisselq	parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
48			`parameter [0:0] OPT_SHIFTS = 1'b1;`
49			`input wire i_clk, i_reset, i_stb;`
50			`input wire [3:0] i_op;`
51			`input wire [31:0] i_a, i_b;`
52	2	dgisselq	`output reg [31:0] o_c;`
53			`output wire [3:0] o_f;`
54			`output reg o_valid;`
55	71	dgisselq	`output wire o_busy;`
56	2	dgisselq
57	209	dgisselq	`genvar k;`
58
59	62	dgisselq	`// Shift register pre-logic`
60	175	dgisselq	`wire [32:0] w_lsr_result, w_asr_result, w_lsl_result;`
61	209	dgisselq	`generate if (OPT_SHIFTS)`
62			`begin : IMPLEMENT_SHIFTS`
63			`wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted;`
64			`assign w_pre_asr_input = { i_a, 1'b0 };`
65			`assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];`
66			`assign w_asr_result = (\|i_b[31:5])? {(33){i_a[31]}}`
67			`: w_pre_asr_shifted;// ASR`
68			`assign w_lsr_result = ((\|i_b[31:6])\|\|(i_b[5]&&(i_b[4:0]!=0)))? 33'h00`
69			`:((i_b[5])?{32'h0,i_a[31]}`
70	2	dgisselq
71	209	dgisselq	`: ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR`
72			`assign w_lsl_result = ((\|i_b[31:6])\|\|(i_b[5]&&(i_b[4:0]!=0)))? 33'h00`
73			`:((i_b[5])?{i_a[0], 32'h0}`
74			`: ({1'b0, i_a } << i_b[4:0])); // LSL`
75			`end else begin : NO_SHIFTS`
76
77			`assign w_asr_result = { i_a[31], i_a[31:0] };`
78			`assign w_lsr_result = { 1'b0, i_a[31:0] };`
79			`assign w_lsl_result = { i_a[31:0], 1'b0 };`
80
81			`end endgenerate`
82
83			`//`
84	69	dgisselq	`// Bit reversal pre-logic`
85			`wire [31:0] w_brev_result;`
86			`generate`
87			`for(k=0; k<32; k=k+1)`
88	80	dgisselq	`begin : bit_reversal_cpuop`
89	69	dgisselq	`assign w_brev_result[k] = i_b[31-k];`
90	80	dgisselq	`end endgenerate`
91	25	dgisselq
92	69	dgisselq	`// Prelogic for our flags registers`
93	2	dgisselq	`wire z, n, v;`
94	201	dgisselq	`reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl;`
95	2	dgisselq	`always @(posedge i_clk)`
96	209	dgisselq	`if (i_stb) // 1 LUT`
97			`set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP`
98			`\|\|((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD`
99			`\|\|(i_op == 4'h6) // LSL`
100			`\|\|(i_op == 4'h5)); // LSR`
101
102	201	dgisselq	`always @(posedge i_clk)`
103	209	dgisselq	`if (i_stb) // 1 LUT`
104			`keep_sgn_on_ovfl<=`
105			`(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP`
106			`\|\|((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD`
107	56	dgisselq
108	193	dgisselq	`wire [63:0] mpy_result; // Where we dump the multiply result`
109	209	dgisselq	`wire mpyhi; // Return the high half of the multiply`
110	193	dgisselq	`wire mpybusy; // The multiply is busy if true`
111			`wire mpydone; // True if we'll be valid on the next clock;`
112	62	dgisselq
113			`// A 4-way multiplexer can be done in one 6-LUT.`
114			`// A 16-way multiplexer can therefore be done in 4x 6-LUT's with`
115	209	dgisselq	`// the Xilinx multiplexer fabric that follows.`
116	62	dgisselq	`// Given that we wish to apply this multiplexer approach to 33-bits,`
117			`// this will cost a minimum of 132 6-LUTs.`
118	193	dgisselq
119			`wire this_is_a_multiply_op;`
120	209	dgisselq	`assign this_is_a_multiply_op = (i_stb)&&((i_op[3:1]==3'h5)\|\|(i_op[3:0]==4'hc));`
121	193	dgisselq
122	209	dgisselq	`//`
123			`// Pull in the multiply logic from elsewhere`
124			`//`
125			`ifdef FORMAL
126			`define MPYOP abs_mpy
127	193	dgisselq	`else
128	209	dgisselq	`define MPYOP mpyop
129	133	dgisselq	`endif
130	209	dgisselq	`MPYOP #(.IMPLEMENT_MPY(IMPLEMENT_MPY)) thempy(i_clk, i_reset, this_is_a_multiply_op, i_op[1:0],
131			`i_a, i_b, mpydone, mpybusy, mpy_result, mpyhi);`
132	193	dgisselq
133			`//`
134			`// The master ALU case statement`
135			`//`
136			`always @(posedge i_clk)`
137	209	dgisselq	`if (i_stb)`
138	193	dgisselq	`begin`
139			`pre_sign <= (i_a[31]);`
140			`c <= 1'b0;`
141			`casez(i_op)`
142			`4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB`
143			`4'b0001: o_c <= i_a & i_b; // BTST/And`
144			`4'b0010:{c,o_c } <= i_a + i_b; // Add`
145			`4'b0011: o_c <= i_a \| i_b; // Or`
146			`4'b0100: o_c <= i_a ^ i_b; // Xor`
147			`4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR`
148			`4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL`
149			`4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR`
150	201	dgisselq	`4'b1000: o_c <= w_brev_result; // BREV`
151	193	dgisselq	`4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO`
152	201	dgisselq	`4'b1010: o_c <= mpy_result[63:32]; // MPYHU`
153			`4'b1011: o_c <= mpy_result[63:32]; // MPYHS`
154			`4'b1100: o_c <= mpy_result[31:0]; // MPY`
155	193	dgisselq	`default: o_c <= i_b; // MOV, LDI`
156			`endcase`
157			`end else // if (mpydone)`
158	209	dgisselq	`// set the output based upon the multiply result`
159	193	dgisselq	`o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];`
160	56	dgisselq
161	193	dgisselq	`reg r_busy;`
162			`initial r_busy = 1'b0;`
163			`always @(posedge i_clk)`
164	209	dgisselq	`if (i_reset)`
165			`r_busy <= 1'b0;`
166			`else if (IMPLEMENT_MPY > 1)`
167			`r_busy <= ((i_stb)&&(this_is_a_multiply_op))\|\|mpybusy;`
168			`else`
169			`r_busy <= 1'b0;`
170
171	193	dgisselq	`assign o_busy = (r_busy); // \|\|((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));`
172
173
174	2	dgisselq	`assign z = (o_c == 32'h0000);`
175			`assign n = (o_c[31]);`
176			`assign v = (set_ovfl)&&(pre_sign != o_c[31]);`
177	201	dgisselq	`wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);`
178	2	dgisselq
179	201	dgisselq	`assign o_f = { v, n^vx, c, z };`
180	2	dgisselq
181			`initial o_valid = 1'b0;`
182			`always @(posedge i_clk)`
183	209	dgisselq	`if (i_reset)`
184			`o_valid <= 1'b0;`
185			`else if (IMPLEMENT_MPY <= 1)`
186			`o_valid <= (i_stb);`
187			`else`
188			`o_valid <=((i_stb)&&(!this_is_a_multiply_op))\|\|(mpydone);`
189	193	dgisselq
190	209	dgisselq	`ifdef FORMAL
191			`initial assume(i_reset);`
192			`reg f_past_valid;`
193
194			`initial f_past_valid = 1'b0;`
195			`always @(posedge i_clk)`
196			`f_past_valid = 1'b1;`
197
198			`define ASSERT assert
199			`ifdef CPUOPS
200			`define ASSUME assume
201			`else
202			`define ASSUME assert
203			`endif
204
205			`// No request should be given us if/while we are busy`
206			`always @(posedge i_clk)`
207			`if (o_busy)`
208			`ASSUME(!i_stb);
209
210			`// Following any request other than a multiply request, we should`
211			`// respond in the next cycle`
212			`always @(posedge i_clk)`
213			`if ((f_past_valid)&&(!$past(o_busy))&&(!$past(this_is_a_multiply_op)))`
214			`ASSERT(!o_busy);
215
216			`// Valid and busy can never both be asserted`
217			`always @(posedge i_clk)`
218			`ASSERT((!o_valid)\|\|(!r_busy));
219
220			`// Following any busy, we should always become valid`
221			`always @(posedge i_clk)`
222			`if ((f_past_valid)&&($past(o_busy))&&(!o_busy))`
223			`ASSERT($past(i_reset) \|\| o_valid);
224
225			`// Check the shift values`
226			`always @(posedge i_clk)`
227			`if ((f_past_valid)&&($past(i_stb)))`
228			`begin`
229			`if (($past(\|i_b[31:6]))\|\|($past(i_b[5:0])>6'd32))`
230			`begin`
231			`assert(($past(i_op)!=4'h5)`
232			`\|\|({o_c,c}=={(33){1'b0}}));`
233			`assert(($past(i_op)!=4'h6)`
234			`\|\|({c,o_c}=={(33){1'b0}}));`
235			`assert(($past(i_op)!=4'h7)`
236			`\|\|({o_c,c}=={(33){$past(i_a[31])}}));`
237			`end else if ($past(i_b[5:0]==6'd32))`
238			`begin`
239			`assert(($past(i_op)!=4'h5)`
240			`\|\|(o_c=={(32){1'b0}}));`
241			`assert(($past(i_op)!=4'h6)`
242			`\|\|(o_c=={(32){1'b0}}));`
243			`assert(($past(i_op)!=4'h7)`
244			`\|\|(o_c=={(32){$past(i_a[31])}}));`
245			`end if ($past(i_b)==0)`
246			`begin`
247			`assert(($past(i_op)!=4'h5)`
248			`\|\|({o_c,c}=={$past(i_a), 1'b0}));`
249			`assert(($past(i_op)!=4'h6)`
250			`\|\|({c,o_c}=={1'b0, $past(i_a)}));`
251			`assert(($past(i_op)!=4'h7)`
252			`\|\|({o_c,c}=={$past(i_a), 1'b0}));`
253			`end if ($past(i_b)==1)`
254			`begin`
255			`assert(($past(i_op)!=4'h5)`
256			`\|\|({o_c,c}=={1'b0, $past(i_a)}));`
257			`assert(($past(i_op)!=4'h6)`
258			`\|\|({c,o_c}=={$past(i_a),1'b0}));`
259			`assert(($past(i_op)!=4'h7)`
260			`\|\|({o_c,c}=={$past(i_a[31]),$past(i_a)}));`
261			`end if ($past(i_b)==2)`
262			`begin`
263			`assert(($past(i_op)!=4'h5)`
264			`\|\|({o_c,c}=={2'b0, $past(i_a[31:1])}));`
265			`assert(($past(i_op)!=4'h6)`
266			`\|\|({c,o_c}=={$past(i_a[30:0]),2'b0}));`
267			`assert(($past(i_op)!=4'h7)`
268			`\|\|({o_c,c}=={{(2){$past(i_a[31])}},$past(i_a[31:1])}));`
269			`end if ($past(i_b)==31)`
270			`begin`
271			`assert(($past(i_op)!=4'h5)`
272			`\|\|({o_c,c}=={31'b0, $past(i_a[31:30])}));`
273			`assert(($past(i_op)!=4'h6)`
274			`\|\|({c,o_c}=={$past(i_a[1:0]),31'b0}));`
275			`assert(($past(i_op)!=4'h7)`
276			`\|\|({o_c,c}=={{(31){$past(i_a[31])}},$past(i_a[31:30])}));`
277			`end`
278			`end`
279			`endif
280	2	dgisselq	`endmodule`
281	209	dgisselq	`//`
282			`// iCE40 NoMPY,w/Shift NoMPY,w/o Shift`
283			`// SB_CARRY 64 64`
284			`// SB_DFFE 3 3`
285			`// SB_DFFESR 1 1`
286			`// SB_DFFSR 33 33`
287			`// SB_LUT4 748 323`

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