OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Blame information for rev 118

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 69 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    idecode.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This RTL file specifies how instructions are to be decoded
8
//              into their underlying meanings.  This is specifically a version
9
//      designed to support a "Next Generation", or "Version 2" instruction
10
//      set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
11
//      in cpudefs.v.
12
//
13
//      I expect to (eventually) retire the old instruction set, at which point
14
//      this will become the default instruction set decoder.
15
//
16
//
17
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
//
41
//
42
`define CPU_CC_REG      4'he
43
`define CPU_PC_REG      4'hf
44
//
45
`include "cpudefs.v"
46
//
47
//
48
//
49
module  idecode(i_clk, i_rst, i_ce, i_stalled,
50
                i_instruction, i_gie, i_pc, i_pf_valid,
51
                        i_illegal,
52
                o_phase, o_illegal,
53
                o_pc, o_gie,
54
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
55
                o_cond, o_wF,
56
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
57
                o_wR, o_rA, o_rB,
58 105 dgisselq
                o_early_branch, o_branch_pc, o_ljmp,
59 71 dgisselq
                o_pipe
60 69 dgisselq
                );
61
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
62
                        IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
63
        input                   i_clk, i_rst, i_ce, i_stalled;
64
        input   [31:0]           i_instruction;
65
        input                   i_gie;
66
        input   [(AW-1):0]       i_pc;
67
        input                   i_pf_valid, i_illegal;
68
        output  wire            o_phase;
69
        output  reg             o_illegal;
70
        output  reg     [(AW-1):0]       o_pc;
71
        output  reg             o_gie;
72
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
73
        output  wire    [31:0]   o_I;
74
        output  reg             o_zI;
75
        output  reg     [3:0]    o_cond;
76
        output  reg             o_wF;
77
        output  reg     [3:0]    o_op;
78
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break, o_lock;
79
        output  reg             o_wR, o_rA, o_rB;
80
        output  wire            o_early_branch;
81
        output  wire    [(AW-1):0]       o_branch_pc;
82 105 dgisselq
        output  wire            o_ljmp;
83 71 dgisselq
        output  reg             o_pipe;
84 69 dgisselq
 
85
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
86
        wire                    o_dcd_early_branch;
87
        wire    [(AW-1):0]       o_dcd_branch_pc;
88
        reg     o_dcdI, o_dcdIz;
89
 
90
 
91
        wire    [4:0]    w_op;
92
        wire            w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
93
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
94
        wire            w_dcdR_pc, w_dcdR_cc;
95
        wire            w_dcdA_pc, w_dcdA_cc;
96
        wire            w_dcdB_pc, w_dcdB_cc;
97
        wire    [3:0]    w_cond;
98
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
99
        wire            w_wR, w_rA, w_rB, w_wR_n;
100 105 dgisselq
        wire            w_ljmp;
101 118 dgisselq
        wire    [31:0]   iword;
102 69 dgisselq
 
103
 
104
`ifdef  OPT_VLIW
105
        reg     [16:0]   r_nxt_half;
106
        assign  iword = (o_phase)
107
                                // set second half as a NOOP ... but really 
108
                                // shouldn't matter
109
                        ? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
110
                        : i_instruction;
111
`else
112
        assign  iword = { 1'b0, i_instruction[30:0] };
113
`endif
114
 
115 118 dgisselq
        generate
116
        if (EARLY_BRANCHING != 0)
117
                assign  w_ljmp = (iword == 32'h7c87c000);
118
        else
119
                assign  w_ljmp = 1'b0;
120
        endgenerate
121
 
122
 
123 69 dgisselq
        assign  w_op= iword[26:22];
124
        assign  w_mov    = (w_op      == 5'h0f);
125
        assign  w_ldi    = (w_op[4:1] == 4'hb);
126
        assign  w_cmptst = (w_op[4:1] == 4'h8);
127
        assign  w_ldixx  = (w_op[4:1] == 4'h4);
128
        assign  w_ALU    = (~w_op[4]);
129
 
130
        // 4 LUTs
131
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
132
                                iword[30:27] };
133
        // 4 LUTs
134
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
135
                                iword[17:14] };
136
 
137
        // 0 LUTs
138
        assign  w_dcdA = w_dcdR;
139
        // 2 LUTs, 1 delay each
140 105 dgisselq
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
141 69 dgisselq
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
142
        // 0 LUTs
143
        assign  w_dcdA_pc = w_dcdR_pc;
144
        assign  w_dcdA_cc = w_dcdR_cc;
145
        // 2 LUTs, 1 delays each
146
        assign  w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
147
        assign  w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
148
 
149
        // Under what condition will we execute this
150
        // instruction?  Only the load immediate instruction
151
        // is completely unconditional.
152
        //
153
        // 3+4 LUTs
154
        assign  w_cond = (w_ldi) ? 4'h8 :
155
                        (iword[31])?{(iword[20:19]==2'b00),
156
                                        1'b0,iword[20:19]}
157
                        : { (iword[21:19]==3'h0), iword[21:19] };
158
 
159
        // 1 LUT
160
        assign  w_dcdM    = (w_op[4:1] == 4'h9);
161
        // 1 LUT
162
        assign  w_dcdDV   = (w_op[4:1] == 4'ha);
163
        // 1 LUT
164
        assign  w_dcdFP   = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
165
        // 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
166
        //      Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
167
        assign  w_rA     = (w_dcdFP)
168
                                // Divide's read A
169
                                ||(w_dcdDV)
170
                                // ALU read's A, unless it's a MOV to A
171
                                // This includes LDIHI/LDILO
172
                                ||((~w_op[4])&&(w_op[3:0]!=4'hf))
173
                                // STO's read A
174
                                ||((w_dcdM)&&(w_op[0]))
175
                                // Test/compares
176
                                ||(w_op[4:1]== 4'h8);
177
        // 1 LUTs -- do we read a register for operand B?  Specifically, do
178
        // we need to stall if the register is not (yet) ready?
179
        assign  w_rB     = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx)));
180
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
181
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
182
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
183
                                ||(w_cmptst);
184
        assign  w_wR     = ~w_wR_n;
185 90 dgisselq
        //
186
        // 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
187 69 dgisselq
        //      
188
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
189 90 dgisselq
        //      and writes to the PC/CC register(s).
190 69 dgisselq
        assign  w_wF     = (w_cmptst)
191
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
192 90 dgisselq
                                ||((w_ALU)&&(~w_mov)&&(~w_ldixx)
193
                                        &&(iword[30:28] != 3'h7))));
194 69 dgisselq
 
195
        // Bottom 13 bits: no LUT's
196
        // w_dcd[12: 0] -- no LUTs
197
        // w_dcd[   13] -- 2 LUTs
198
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
199
        // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
200
        reg     [22:0]   r_I;
201
        wire    [22:0]   w_I, w_fullI;
202
        wire            w_Iz;
203
 
204
        assign  w_fullI = (w_ldi) ? { iword[22:0] } // LDI
205
                        :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
206
                        :((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
207
                        : { {(23-14){iword[13]}}, iword[13:0] }
208
                        ));
209
 
210
`ifdef  OPT_VLIW
211
        wire    [5:0]    w_halfI;
212
        assign  w_halfI = (w_ldi) ? iword[5:0]
213
                                :((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
214
        assign  w_I  = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
215
`else
216
        assign  w_I  = w_fullI;
217
`endif
218
        assign  w_Iz = (w_I == 0);
219
 
220
 
221
`ifdef  OPT_VLIW
222
        //
223
        // The o_phase parameter is special.  It needs to let the software
224
        // following know that it cannot break/interrupt on an o_phase asserted
225
        // instruction, lest the break take place between the first and second
226
        // half of a VLIW instruction.  To do this, o_phase must be asserted
227
        // when the first instruction half is valid, but not asserted on either
228
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
229
        reg     r_phase;
230
        initial r_phase = 1'b0;
231
        always @(posedge i_clk)
232
                if (i_rst) // When no instruction is in the pipe, phase is zero
233
                        r_phase <= 1'b0;
234
                else if (i_ce)
235
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
236
        // Phase is '1' on the first instruction of a two-part set
237
        // But, due to the delay in processing, it's '1' when our output is
238
        // valid for that first part, but that'll be the same time we
239
        // are processing the second part ... so it may look to us like a '1'
240
        // on the second half of processing.
241
 
242
        assign  o_phase = r_phase;
243
`else
244
        assign  o_phase = 1'b0;
245
`endif
246
 
247
 
248 71 dgisselq
        initial o_illegal = 1'b0;
249 69 dgisselq
        always @(posedge i_clk)
250 71 dgisselq
                if (i_rst)
251
                        o_illegal <= 1'b0;
252
                else if (i_ce)
253 69 dgisselq
                begin
254
`ifdef  OPT_VLIW
255 71 dgisselq
                        o_illegal <= (i_illegal);
256 69 dgisselq
`else
257
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
258
`endif
259
                        if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
260
                                o_illegal <= 1'b1;
261
 
262
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
263
                                o_illegal <= 1'b1;
264
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
265
                                o_illegal <= 1'b1;
266
 
267
 
268
                        if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
269
                                o_illegal <= 1'b1;
270
                        else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
271
                                o_illegal <= 1'b1;
272
 
273 71 dgisselq
                        if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
274
                                &&(
275
                                        (w_op[2:0] != 3'h2)      // LOCK
276
                                        &&(w_op[2:0] != 3'h1)    // BREAK
277
                                        &&(w_op[2:0] != 3'h0)))  // NOOP
278
                                o_illegal <= 1'b1;
279
                end
280
 
281
 
282
        always @(posedge i_clk)
283
                if (i_ce)
284
                begin
285
`ifdef  OPT_VLIW
286
                        if (~o_phase)
287
                        begin
288
                                o_gie<= i_gie;
289
                                // i.e. dcd_pc+1
290
                                o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
291
                        end
292
`else
293
                        o_gie<= i_gie;
294
                        o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
295
`endif
296
 
297 69 dgisselq
                        // Under what condition will we execute this
298
                        // instruction?  Only the load immediate instruction
299
                        // is completely unconditional.
300
                        o_cond <= w_cond;
301
                        // Don't change the flags on conditional instructions,
302
                        // UNLESS: the conditional instruction was a CMP
303
                        // or TST instruction.
304
                        o_wF <= w_wF;
305
 
306
                        // Record what operation/op-code (4-bits) we are doing
307
                        //      Note that LDI magically becomes a MOV
308
                        //      instruction here.  That way it's a pass through
309
                        //      the ALU.  Likewise, the two compare instructions
310
                        //      CMP and TST becomes SUB and AND here as well.
311
                        // We keep only the bottom four bits, since we've
312
                        // already done the rest of the decode necessary to 
313
                        // settle between the other instructions.  For example,
314
                        // o_FP plus these four bits uniquely defines the FP
315
                        // instruction, o_DV plus the bottom of these defines
316
                        // the divide, etc.
317
                        o_op <= (w_ldi)? 4'hf:w_op[3:0];
318
 
319
                        // Default values
320
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
321
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
322
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
323
                        o_wR  <= w_wR;
324
                        o_rA  <= w_rA;
325
                        o_rB  <= w_rB;
326
                        r_I    <= w_I;
327
                        o_zI   <= w_Iz;
328
 
329
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
330
                        o_M    <=  w_dcdM;
331
                        o_DV   <=  w_dcdDV;
332
                        o_FP   <=  w_dcdFP;
333
 
334
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
335
                        o_lock  <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
336
`ifdef  OPT_VLIW
337
                        r_nxt_half <= { iword[31], iword[13:5],
338
                                ((iword[21])? iword[20:19] : 2'h0),
339
                                iword[4:0] };
340
`endif
341
                end
342
 
343
        generate
344
        if (EARLY_BRANCHING!=0)
345
        begin
346 105 dgisselq
                reg                     r_early_branch, r_ljmp;
347 69 dgisselq
                reg     [(AW-1):0]       r_branch_pc;
348 105 dgisselq
 
349
                initial r_ljmp = 1'b0;
350 69 dgisselq
                always @(posedge i_clk)
351 105 dgisselq
                        if (i_rst)
352
                                r_ljmp <= 1'b0;
353
                        else if ((i_ce)&&(i_pf_valid))
354
                                r_ljmp <= (w_ljmp);
355
                assign  o_ljmp = r_ljmp;
356
 
357
                always @(posedge i_clk)
358
                if (i_rst)
359
                        r_early_branch <= 1'b0;
360
                else if ((i_ce)&&(i_pf_valid))
361 90 dgisselq
                begin
362 105 dgisselq
                        if (r_ljmp)
363
                                // LOD (PC),PC
364
                                r_early_branch <= 1'b1;
365
                        else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
366 69 dgisselq
                        begin
367 90 dgisselq
                                if (w_op[4:1] == 4'hb) // LDI to PC
368 105 dgisselq
                                        // LDI x,PC
369 69 dgisselq
                                        r_early_branch     <= 1'b1;
370 105 dgisselq
                                else if ((w_op[4:0]==5'h02)&&(~iword[18]))
371
                                        // Add x,PC
372 69 dgisselq
                                        r_early_branch     <= 1'b1;
373 105 dgisselq
                                else begin
374 69 dgisselq
                                        r_early_branch     <= 1'b0;
375
                                end
376 90 dgisselq
                        end else
377
                                r_early_branch <= 1'b0;
378 105 dgisselq
                end else if (i_ce)
379
                        r_early_branch <= 1'b0;
380
 
381 69 dgisselq
                always @(posedge i_clk)
382
                        if (i_ce)
383
                        begin
384 105 dgisselq
                                if (r_ljmp)
385
                                        r_branch_pc <= iword[(AW-1):0];
386
                                else if (w_op[4:1] == 4'hb) // LDI
387 90 dgisselq
                                        r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
388
                                else // Add x,PC
389
                                r_branch_pc <= i_pc
390 105 dgisselq
                                        + {{(AW-17){iword[17]}},iword[16:0]}
391 90 dgisselq
                                        + {{(AW-1){1'b0}},1'b1};
392 69 dgisselq
                        end
393
 
394
                assign  o_early_branch     = r_early_branch;
395
                assign  o_branch_pc        = r_branch_pc;
396
        end else begin
397
                assign  o_early_branch = 1'b0;
398
                assign  o_branch_pc = {(AW){1'b0}};
399 105 dgisselq
                assign  o_ljmp = 1'b0;
400 69 dgisselq
        end endgenerate
401
 
402 71 dgisselq
 
403
        // To be a pipeable operation there must be ...
404
        //      1. Two valid adjacent instructions
405
        //      2. Both must be memory operations, of the same time (both lods
406
        //              or both stos)
407
        //      3. Both must use the same register base address
408
        //      4. Both must be to the same address, or the address incremented
409
        //              by one
410
        // Note that we're not using iword here ... there's a lot of logic
411
        // taking place, and it's only valid if the new word is not compressed.
412
        //
413
        reg     r_valid;
414
        always @(posedge i_clk)
415
                if (i_ce)
416
                        o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
417
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
418
                                &&(i_instruction[17:14] == o_dcdB[3:0])
419
                                &&(i_gie == o_gie)
420
                                &&((i_instruction[21:19]==o_cond[2:0])
421
                                        ||(o_cond[2:0] == 3'h0))
422
                                &&((i_instruction[13:0]==r_I[13:0])
423
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
424
        always @(posedge i_clk)
425
                if (i_rst)
426
                        r_valid <= 1'b0;
427 105 dgisselq
                else if ((i_ce)&&(o_ljmp))
428
                        r_valid <= 1'b0;
429 71 dgisselq
                else if ((i_ce)&&(i_pf_valid))
430
                        r_valid <= 1'b1;
431
                else if (~i_stalled)
432
                        r_valid <= 1'b0;
433
 
434
 
435 69 dgisselq
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
436
 
437
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.