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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Blame information for rev 178

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1 69 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    idecode.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This RTL file specifies how instructions are to be decoded
8
//              into their underlying meanings.  This is specifically a version
9
//      designed to support a "Next Generation", or "Version 2" instruction
10
//      set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
11
//      in cpudefs.v.
12
//
13
//      I expect to (eventually) retire the old instruction set, at which point
14
//      this will become the default instruction set decoder.
15
//
16
//
17
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////////
21
//
22 160 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
23 69 dgisselq
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
//
41
//
42
`define CPU_CC_REG      4'he
43
`define CPU_PC_REG      4'hf
44
//
45
`include "cpudefs.v"
46
//
47
//
48
//
49
module  idecode(i_clk, i_rst, i_ce, i_stalled,
50
                i_instruction, i_gie, i_pc, i_pf_valid,
51
                        i_illegal,
52
                o_phase, o_illegal,
53
                o_pc, o_gie,
54
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
55
                o_cond, o_wF,
56
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
57
                o_wR, o_rA, o_rB,
58 105 dgisselq
                o_early_branch, o_branch_pc, o_ljmp,
59 71 dgisselq
                o_pipe
60 69 dgisselq
                );
61
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
62
                        IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
63
        input                   i_clk, i_rst, i_ce, i_stalled;
64
        input   [31:0]           i_instruction;
65
        input                   i_gie;
66
        input   [(AW-1):0]       i_pc;
67
        input                   i_pf_valid, i_illegal;
68
        output  wire            o_phase;
69
        output  reg             o_illegal;
70
        output  reg     [(AW-1):0]       o_pc;
71
        output  reg             o_gie;
72
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
73
        output  wire    [31:0]   o_I;
74
        output  reg             o_zI;
75
        output  reg     [3:0]    o_cond;
76
        output  reg             o_wF;
77
        output  reg     [3:0]    o_op;
78 130 dgisselq
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break;
79
        output  wire            o_lock;
80 69 dgisselq
        output  reg             o_wR, o_rA, o_rB;
81
        output  wire            o_early_branch;
82
        output  wire    [(AW-1):0]       o_branch_pc;
83 105 dgisselq
        output  wire            o_ljmp;
84 138 dgisselq
        output  wire            o_pipe;
85 69 dgisselq
 
86
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
87
        wire                    o_dcd_early_branch;
88
        wire    [(AW-1):0]       o_dcd_branch_pc;
89
        reg     o_dcdI, o_dcdIz;
90 130 dgisselq
`ifdef  OPT_PIPELINED
91 160 dgisselq
        reg     r_lock;
92 130 dgisselq
`endif
93 160 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
94
        reg     r_pipe;
95
`endif
96 69 dgisselq
 
97
 
98
        wire    [4:0]    w_op;
99 138 dgisselq
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
100 69 dgisselq
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
101
        wire            w_dcdR_pc, w_dcdR_cc;
102
        wire            w_dcdA_pc, w_dcdA_cc;
103
        wire            w_dcdB_pc, w_dcdB_cc;
104
        wire    [3:0]    w_cond;
105
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
106
        wire            w_wR, w_rA, w_rB, w_wR_n;
107 178 dgisselq
        wire            w_ljmp, w_ljmp_dly;
108 118 dgisselq
        wire    [31:0]   iword;
109 69 dgisselq
 
110
 
111
`ifdef  OPT_VLIW
112
        reg     [16:0]   r_nxt_half;
113
        assign  iword = (o_phase)
114
                                // set second half as a NOOP ... but really 
115
                                // shouldn't matter
116
                        ? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
117
                        : i_instruction;
118
`else
119
        assign  iword = { 1'b0, i_instruction[30:0] };
120
`endif
121
 
122 118 dgisselq
        generate
123
        if (EARLY_BRANCHING != 0)
124
                assign  w_ljmp = (iword == 32'h7c87c000);
125
        else
126
                assign  w_ljmp = 1'b0;
127
        endgenerate
128
 
129
 
130 69 dgisselq
        assign  w_op= iword[26:22];
131
        assign  w_mov    = (w_op      == 5'h0f);
132
        assign  w_ldi    = (w_op[4:1] == 4'hb);
133 130 dgisselq
        assign  w_brev   = (w_op      == 5'hc);
134 69 dgisselq
        assign  w_cmptst = (w_op[4:1] == 4'h8);
135 130 dgisselq
        assign  w_ldilo  = (w_op[4:0] == 5'h9);
136 69 dgisselq
        assign  w_ALU    = (~w_op[4]);
137
 
138
        // 4 LUTs
139 138 dgisselq
        //
140
        // Two parts to the result register: the register set, given for
141
        // moves in i_word[18] but only for the supervisor, and the other
142
        // four bits encoded in the instruction.
143
        //
144 69 dgisselq
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
145
                                iword[30:27] };
146 138 dgisselq
        // 2 LUTs
147
        //
148
        // If the result register is either CC or PC, and this would otherwise
149
        // be a floating point instruction with floating point opcode of 0,
150
        // then this is a NOOP.
151 178 dgisselq
        assign  w_noop   = (w_op[4:0] == 5'h18)&&(
152
                        ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
153
                        ||(IMPLEMENT_FPU==0));
154 138 dgisselq
 
155 69 dgisselq
        // 4 LUTs
156
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
157
                                iword[17:14] };
158
 
159
        // 0 LUTs
160
        assign  w_dcdA = w_dcdR;
161
        // 2 LUTs, 1 delay each
162 105 dgisselq
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
163 69 dgisselq
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
164
        // 0 LUTs
165
        assign  w_dcdA_pc = w_dcdR_pc;
166
        assign  w_dcdA_cc = w_dcdR_cc;
167
        // 2 LUTs, 1 delays each
168
        assign  w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
169
        assign  w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
170
 
171
        // Under what condition will we execute this
172
        // instruction?  Only the load immediate instruction
173
        // is completely unconditional.
174
        //
175
        // 3+4 LUTs
176
        assign  w_cond = (w_ldi) ? 4'h8 :
177
                        (iword[31])?{(iword[20:19]==2'b00),
178
                                        1'b0,iword[20:19]}
179
                        : { (iword[21:19]==3'h0), iword[21:19] };
180
 
181
        // 1 LUT
182
        assign  w_dcdM    = (w_op[4:1] == 4'h9);
183
        // 1 LUT
184
        assign  w_dcdDV   = (w_op[4:1] == 4'ha);
185
        // 1 LUT
186
        assign  w_dcdFP   = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
187
        // 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
188
        //      Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
189
        assign  w_rA     = (w_dcdFP)
190
                                // Divide's read A
191
                                ||(w_dcdDV)
192
                                // ALU read's A, unless it's a MOV to A
193
                                // This includes LDIHI/LDILO
194
                                ||((~w_op[4])&&(w_op[3:0]!=4'hf))
195
                                // STO's read A
196
                                ||((w_dcdM)&&(w_op[0]))
197
                                // Test/compares
198
                                ||(w_op[4:1]== 4'h8);
199
        // 1 LUTs -- do we read a register for operand B?  Specifically, do
200
        // we need to stall if the register is not (yet) ready?
201 130 dgisselq
        assign  w_rB     = (w_mov)||((iword[18])&&(~w_ldi));
202 69 dgisselq
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
203
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
204
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
205
                                ||(w_cmptst);
206
        assign  w_wR     = ~w_wR_n;
207 90 dgisselq
        //
208
        // 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
209 69 dgisselq
        //      
210
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
211 90 dgisselq
        //      and writes to the PC/CC register(s).
212 69 dgisselq
        assign  w_wF     = (w_cmptst)
213
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
214 130 dgisselq
                                ||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev)
215 90 dgisselq
                                        &&(iword[30:28] != 3'h7))));
216 69 dgisselq
 
217
        // Bottom 13 bits: no LUT's
218
        // w_dcd[12: 0] -- no LUTs
219
        // w_dcd[   13] -- 2 LUTs
220
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
221
        // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
222
        reg     [22:0]   r_I;
223
        wire    [22:0]   w_I, w_fullI;
224
        wire            w_Iz;
225
 
226
        assign  w_fullI = (w_ldi) ? { iword[22:0] } // LDI
227
                        :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
228
                        :((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
229
                        : { {(23-14){iword[13]}}, iword[13:0] }
230
                        ));
231
 
232
`ifdef  OPT_VLIW
233
        wire    [5:0]    w_halfI;
234
        assign  w_halfI = (w_ldi) ? iword[5:0]
235
                                :((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
236
        assign  w_I  = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
237
`else
238
        assign  w_I  = w_fullI;
239
`endif
240
        assign  w_Iz = (w_I == 0);
241
 
242
 
243
`ifdef  OPT_VLIW
244
        //
245
        // The o_phase parameter is special.  It needs to let the software
246
        // following know that it cannot break/interrupt on an o_phase asserted
247
        // instruction, lest the break take place between the first and second
248
        // half of a VLIW instruction.  To do this, o_phase must be asserted
249
        // when the first instruction half is valid, but not asserted on either
250
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
251
        reg     r_phase;
252
        initial r_phase = 1'b0;
253
        always @(posedge i_clk)
254 178 dgisselq
                if ((i_rst) // When no instruction is in the pipe, phase is zero
255
                        ||(o_early_branch)||(w_ljmp_dly))
256 69 dgisselq
                        r_phase <= 1'b0;
257 178 dgisselq
                else if ((i_ce)&&(i_pf_valid))
258 69 dgisselq
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
259
        // Phase is '1' on the first instruction of a two-part set
260
        // But, due to the delay in processing, it's '1' when our output is
261
        // valid for that first part, but that'll be the same time we
262
        // are processing the second part ... so it may look to us like a '1'
263
        // on the second half of processing.
264
 
265
        assign  o_phase = r_phase;
266
`else
267
        assign  o_phase = 1'b0;
268
`endif
269
 
270
 
271 71 dgisselq
        initial o_illegal = 1'b0;
272 69 dgisselq
        always @(posedge i_clk)
273 71 dgisselq
                if (i_rst)
274
                        o_illegal <= 1'b0;
275
                else if (i_ce)
276 69 dgisselq
                begin
277
`ifdef  OPT_VLIW
278 71 dgisselq
                        o_illegal <= (i_illegal);
279 69 dgisselq
`else
280
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
281
`endif
282 178 dgisselq
                        if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08)))
283 69 dgisselq
                                o_illegal <= 1'b1;
284
 
285
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
286
                                o_illegal <= 1'b1;
287
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
288
                                o_illegal <= 1'b1;
289
 
290
 
291
                        if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
292
                                o_illegal <= 1'b1;
293
                        else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
294
                                o_illegal <= 1'b1;
295
 
296 71 dgisselq
                        if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
297
                                &&(
298 130 dgisselq
                                        (w_op[2:0] != 3'h1)      // BREAK
299
`ifdef  OPT_PIPELINED
300
                                        &&(w_op[2:0] != 3'h2)    // LOCK
301
`endif
302 71 dgisselq
                                        &&(w_op[2:0] != 3'h0)))  // NOOP
303
                                o_illegal <= 1'b1;
304
                end
305
 
306
 
307
        always @(posedge i_clk)
308
                if (i_ce)
309
                begin
310
`ifdef  OPT_VLIW
311
                        if (~o_phase)
312
                        begin
313
                                o_gie<= i_gie;
314
                                // i.e. dcd_pc+1
315
                                o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
316
                        end
317
`else
318
                        o_gie<= i_gie;
319
                        o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
320
`endif
321
 
322 69 dgisselq
                        // Under what condition will we execute this
323
                        // instruction?  Only the load immediate instruction
324
                        // is completely unconditional.
325
                        o_cond <= w_cond;
326
                        // Don't change the flags on conditional instructions,
327
                        // UNLESS: the conditional instruction was a CMP
328
                        // or TST instruction.
329
                        o_wF <= w_wF;
330
 
331
                        // Record what operation/op-code (4-bits) we are doing
332
                        //      Note that LDI magically becomes a MOV
333
                        //      instruction here.  That way it's a pass through
334
                        //      the ALU.  Likewise, the two compare instructions
335
                        //      CMP and TST becomes SUB and AND here as well.
336
                        // We keep only the bottom four bits, since we've
337
                        // already done the rest of the decode necessary to 
338
                        // settle between the other instructions.  For example,
339
                        // o_FP plus these four bits uniquely defines the FP
340
                        // instruction, o_DV plus the bottom of these defines
341
                        // the divide, etc.
342 138 dgisselq
                        o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0];
343 69 dgisselq
 
344
                        // Default values
345
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
346
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
347
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
348
                        o_wR  <= w_wR;
349
                        o_rA  <= w_rA;
350
                        o_rB  <= w_rB;
351
                        r_I    <= w_I;
352
                        o_zI   <= w_Iz;
353
 
354 138 dgisselq
                        // Turn a NOOP into an ALU operation--subtract in 
355
                        // particular, although it doesn't really matter as long
356
                        // as it doesn't take longer than one clock.  Note
357
                        // also that this depends upon not setting any registers
358
                        // or flags, which should already be true.
359
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT
360 69 dgisselq
                        o_M    <=  w_dcdM;
361
                        o_DV   <=  w_dcdDV;
362
                        o_FP   <=  w_dcdFP;
363 178 dgisselq
 
364
                        o_break <= (w_op[4:0]==5'b11001)&&(
365
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
366
                                ||(IMPLEMENT_FPU==0));
367 130 dgisselq
`ifdef  OPT_PIPELINED
368 178 dgisselq
                        r_lock  <= (w_op[4:0]==5'b11010)&&(
369
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
370
                                ||(IMPLEMENT_FPU==0));
371 130 dgisselq
`endif
372 69 dgisselq
`ifdef  OPT_VLIW
373
                        r_nxt_half <= { iword[31], iword[13:5],
374
                                ((iword[21])? iword[20:19] : 2'h0),
375
                                iword[4:0] };
376
`endif
377
                end
378
 
379 130 dgisselq
`ifdef  OPT_PIPELINED
380
        assign  o_lock = r_lock;
381
`else
382
        assign  o_lock = 1'b0;
383
`endif
384
 
385 69 dgisselq
        generate
386
        if (EARLY_BRANCHING!=0)
387
        begin
388 105 dgisselq
                reg                     r_early_branch, r_ljmp;
389 69 dgisselq
                reg     [(AW-1):0]       r_branch_pc;
390 105 dgisselq
 
391
                initial r_ljmp = 1'b0;
392 69 dgisselq
                always @(posedge i_clk)
393 105 dgisselq
                        if (i_rst)
394
                                r_ljmp <= 1'b0;
395
                        else if ((i_ce)&&(i_pf_valid))
396
                                r_ljmp <= (w_ljmp);
397
                assign  o_ljmp = r_ljmp;
398
 
399
                always @(posedge i_clk)
400
                if (i_rst)
401
                        r_early_branch <= 1'b0;
402
                else if ((i_ce)&&(i_pf_valid))
403 90 dgisselq
                begin
404 105 dgisselq
                        if (r_ljmp)
405
                                // LOD (PC),PC
406
                                r_early_branch <= 1'b1;
407
                        else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
408 69 dgisselq
                        begin
409 90 dgisselq
                                if (w_op[4:1] == 4'hb) // LDI to PC
410 105 dgisselq
                                        // LDI x,PC
411 69 dgisselq
                                        r_early_branch     <= 1'b1;
412 105 dgisselq
                                else if ((w_op[4:0]==5'h02)&&(~iword[18]))
413
                                        // Add x,PC
414 69 dgisselq
                                        r_early_branch     <= 1'b1;
415 105 dgisselq
                                else begin
416 69 dgisselq
                                        r_early_branch     <= 1'b0;
417
                                end
418 90 dgisselq
                        end else
419
                                r_early_branch <= 1'b0;
420 105 dgisselq
                end else if (i_ce)
421
                        r_early_branch <= 1'b0;
422
 
423 69 dgisselq
                always @(posedge i_clk)
424
                        if (i_ce)
425
                        begin
426 105 dgisselq
                                if (r_ljmp)
427
                                        r_branch_pc <= iword[(AW-1):0];
428
                                else if (w_op[4:1] == 4'hb) // LDI
429 90 dgisselq
                                        r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
430
                                else // Add x,PC
431
                                r_branch_pc <= i_pc
432 105 dgisselq
                                        + {{(AW-17){iword[17]}},iword[16:0]}
433 90 dgisselq
                                        + {{(AW-1){1'b0}},1'b1};
434 69 dgisselq
                        end
435
 
436 178 dgisselq
                assign  w_ljmp_dly         = r_ljmp;
437 69 dgisselq
                assign  o_early_branch     = r_early_branch;
438
                assign  o_branch_pc        = r_branch_pc;
439
        end else begin
440 178 dgisselq
                assign  w_ljmp_dly         = 1'b0;
441 69 dgisselq
                assign  o_early_branch = 1'b0;
442
                assign  o_branch_pc = {(AW){1'b0}};
443 105 dgisselq
                assign  o_ljmp = 1'b0;
444 69 dgisselq
        end endgenerate
445
 
446 71 dgisselq
 
447
        // To be a pipeable operation there must be ...
448
        //      1. Two valid adjacent instructions
449
        //      2. Both must be memory operations, of the same time (both lods
450
        //              or both stos)
451
        //      3. Both must use the same register base address
452
        //      4. Both must be to the same address, or the address incremented
453
        //              by one
454
        // Note that we're not using iword here ... there's a lot of logic
455
        // taking place, and it's only valid if the new word is not compressed.
456
        //
457
        reg     r_valid;
458 160 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
459 138 dgisselq
        initial r_pipe = 1'b0;
460 71 dgisselq
        always @(posedge i_clk)
461
                if (i_ce)
462 138 dgisselq
                        r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
463 71 dgisselq
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
464
                                &&(i_instruction[17:14] == o_dcdB[3:0])
465 130 dgisselq
                                &&(i_instruction[17:14] != o_dcdA[3:0])
466 71 dgisselq
                                &&(i_gie == o_gie)
467
                                &&((i_instruction[21:19]==o_cond[2:0])
468
                                        ||(o_cond[2:0] == 3'h0))
469
                                &&((i_instruction[13:0]==r_I[13:0])
470
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
471 138 dgisselq
        assign o_pipe = r_pipe;
472
`else
473
        assign o_pipe = 1'b0;
474
`endif
475
 
476 71 dgisselq
        always @(posedge i_clk)
477
                if (i_rst)
478
                        r_valid <= 1'b0;
479 105 dgisselq
                else if ((i_ce)&&(o_ljmp))
480
                        r_valid <= 1'b0;
481 71 dgisselq
                else if ((i_ce)&&(i_pf_valid))
482
                        r_valid <= 1'b1;
483
                else if (~i_stalled)
484
                        r_valid <= 1'b0;
485
 
486
 
487 69 dgisselq
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
488
 
489
endmodule

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