OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Blame information for rev 205

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 69 dgisselq
//
3
// Filename:    idecode.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This RTL file specifies how instructions are to be decoded
8
//              into their underlying meanings.  This is specifically a version
9
//      designed to support a "Next Generation", or "Version 2" instruction
10
//      set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
11
//      in cpudefs.v.
12
//
13
//      I expect to (eventually) retire the old instruction set, at which point
14
//      this will become the default instruction set decoder.
15
//
16
//
17
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Technology, LLC
19
//
20 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
21 69 dgisselq
//
22 201 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
23 69 dgisselq
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34 201 dgisselq
// You should have received a copy of the GNU General Public License along
35
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
36
// target there if the PDF file isn't present.)  If not, see
37
// <http://www.gnu.org/licenses/> for a copy.
38
//
39 69 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
40
//              http://www.gnu.org/licenses/gpl.html
41
//
42
//
43 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
44 69 dgisselq
//
45
//
46
//
47 201 dgisselq
`define CPU_SP_REG      4'hd
48 69 dgisselq
`define CPU_CC_REG      4'he
49
`define CPU_PC_REG      4'hf
50
//
51
`include "cpudefs.v"
52
//
53
//
54
//
55
module  idecode(i_clk, i_rst, i_ce, i_stalled,
56
                i_instruction, i_gie, i_pc, i_pf_valid,
57
                        i_illegal,
58 205 dgisselq
                o_valid,
59 69 dgisselq
                o_phase, o_illegal,
60
                o_pc, o_gie,
61
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
62
                o_cond, o_wF,
63
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
64
                o_wR, o_rA, o_rB,
65 105 dgisselq
                o_early_branch, o_branch_pc, o_ljmp,
66 201 dgisselq
                o_pipe,
67
                o_sim, o_sim_immv
68 69 dgisselq
                );
69
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
70
                        IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
71
        input                   i_clk, i_rst, i_ce, i_stalled;
72
        input   [31:0]           i_instruction;
73
        input                   i_gie;
74
        input   [(AW-1):0]       i_pc;
75
        input                   i_pf_valid, i_illegal;
76 205 dgisselq
        output  wire            o_valid, o_phase;
77 69 dgisselq
        output  reg             o_illegal;
78 201 dgisselq
        output  reg     [AW:0]   o_pc;
79 69 dgisselq
        output  reg             o_gie;
80
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
81
        output  wire    [31:0]   o_I;
82
        output  reg             o_zI;
83
        output  reg     [3:0]    o_cond;
84
        output  reg             o_wF;
85
        output  reg     [3:0]    o_op;
86 130 dgisselq
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break;
87
        output  wire            o_lock;
88 69 dgisselq
        output  reg             o_wR, o_rA, o_rB;
89
        output  wire            o_early_branch;
90
        output  wire    [(AW-1):0]       o_branch_pc;
91 105 dgisselq
        output  wire            o_ljmp;
92 138 dgisselq
        output  wire            o_pipe;
93 201 dgisselq
        output  reg             o_sim           /* verilator public_flat */;
94
        output  reg     [22:0]   o_sim_immv      /* verilator public_flat */;
95 69 dgisselq
 
96
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
97
        wire                    o_dcd_early_branch;
98
        wire    [(AW-1):0]       o_dcd_branch_pc;
99
        reg     o_dcdI, o_dcdIz;
100 130 dgisselq
`ifdef  OPT_PIPELINED
101 160 dgisselq
        reg     r_lock;
102 130 dgisselq
`endif
103 160 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
104
        reg     r_pipe;
105
`endif
106 69 dgisselq
 
107
 
108
        wire    [4:0]    w_op;
109 205 dgisselq
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev,
110
                        w_noop, w_lock;
111 69 dgisselq
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
112
        wire            w_dcdR_pc, w_dcdR_cc;
113
        wire            w_dcdA_pc, w_dcdA_cc;
114
        wire            w_dcdB_pc, w_dcdB_cc;
115
        wire    [3:0]    w_cond;
116 205 dgisselq
        wire            w_wF, w_mem, w_sto, w_div, w_fpu;
117 69 dgisselq
        wire            w_wR, w_rA, w_rB, w_wR_n;
118 201 dgisselq
        wire            w_ljmp, w_ljmp_dly, w_cis_ljmp;
119 118 dgisselq
        wire    [31:0]   iword;
120 69 dgisselq
 
121
 
122 201 dgisselq
`ifdef  OPT_CIS
123
        reg     [15:0]   r_nxt_half;
124 69 dgisselq
        assign  iword = (o_phase)
125 201 dgisselq
                                // set second half as a NOOP ... but really
126 69 dgisselq
                                // shouldn't matter
127 201 dgisselq
                        ? { r_nxt_half[15:0], i_instruction[15:0] }
128 69 dgisselq
                        : i_instruction;
129
`else
130
        assign  iword = { 1'b0, i_instruction[30:0] };
131
`endif
132
 
133 118 dgisselq
        generate
134
        if (EARLY_BRANCHING != 0)
135 201 dgisselq
        begin
136
`ifdef  OPT_CIS
137
                reg     r_pre_ljmp;
138
                always @(posedge i_clk)
139
                if ((i_rst)||(o_early_branch))
140
                        r_pre_ljmp <= 1'b0;
141
                else if ((i_ce)&&(i_pf_valid))
142
                        r_pre_ljmp <= (!o_phase)&&(i_instruction[31])
143
                                &&(i_instruction[14:0] == 15'h7cf8);
144
                else if (i_ce)
145
                        r_pre_ljmp <= 1'b0;
146
 
147
                assign  w_cis_ljmp = r_pre_ljmp;
148
`else
149
                assign  w_cis_ljmp = 1'b0;
150
`endif
151
                // 0.1111.10010.000.1.1111.000000000...
152
                // 0111.1100.1000.0111.11000....
153 118 dgisselq
                assign  w_ljmp = (iword == 32'h7c87c000);
154 201 dgisselq
        end else begin
155
                assign  w_cis_ljmp = 1'b0;
156 118 dgisselq
                assign  w_ljmp = 1'b0;
157 201 dgisselq
        end
158 118 dgisselq
        endgenerate
159
 
160 201 dgisselq
`ifdef  OPT_CIS
161
`ifdef  VERILATOR
162
        wire    [4:0]    w_cis_op;
163
        always @(iword)
164
                if (!iword[31])
165
                        w_cis_op = w_op;
166
                else case(iword[26:24])
167
                3'h0: w_cis_op = 5'h00;
168
                3'h1: w_cis_op = 5'h01;
169
                3'h2: w_cis_op = 5'h02;
170
                3'h3: w_cis_op = 5'h10;
171
                3'h4: w_cis_op = 5'h12;
172
                3'h5: w_cis_op = 5'h13;
173
                3'h6: w_cis_op = 5'h18;
174
                3'h7: w_cis_op = 5'h0d;
175
                endcase
176
`else
177
        reg     [4:0]    w_cis_op;
178
        always @(iword,w_op)
179
                if (!iword[31])
180
                        w_cis_op <= w_op;
181
                else case(iword[26:24])
182
                3'h0: w_cis_op <= 5'h00;
183
                3'h1: w_cis_op <= 5'h01;
184
                3'h2: w_cis_op <= 5'h02;
185
                3'h3: w_cis_op <= 5'h10;
186
                3'h4: w_cis_op <= 5'h12;
187
                3'h5: w_cis_op <= 5'h13;
188
                3'h6: w_cis_op <= 5'h18;
189
                3'h7: w_cis_op <= 5'h0d;
190
                endcase
191
`endif
192
`else
193
        wire    [4:0]    w_cis_op;
194
        assign  w_cis_op = w_op;
195
`endif
196 118 dgisselq
 
197 69 dgisselq
        assign  w_op= iword[26:22];
198 201 dgisselq
        assign  w_mov    = (w_cis_op      == 5'h0d);
199
        assign  w_ldi    = (w_cis_op[4:1] == 4'hc);
200
        assign  w_brev   = (w_cis_op      == 5'h8);
201
        assign  w_cmptst = (w_cis_op[4:1] == 4'h8);
202
        assign  w_ldilo  = (w_cis_op[4:0] == 5'h9);
203
        assign  w_ALU    = (!w_cis_op[4]) // anything with [4]==0, but ...
204
                                &&(w_cis_op[3:1] != 3'h7); // not the divide
205 69 dgisselq
 
206 201 dgisselq
 
207
        // w_dcdR (4 LUTs)
208 138 dgisselq
        //
209 201 dgisselq
        // What register will we be placing results into (if at all)?
210
        //
211 138 dgisselq
        // Two parts to the result register: the register set, given for
212 201 dgisselq
        // moves in iword[18] but only for the supervisor, and the other
213 138 dgisselq
        // four bits encoded in the instruction.
214
        //
215 201 dgisselq
        assign  w_dcdR = { ((!iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
216 69 dgisselq
                                iword[30:27] };
217 138 dgisselq
        // 2 LUTs
218
        //
219
        // If the result register is either CC or PC, and this would otherwise
220
        // be a floating point instruction with floating point opcode of 0,
221
        // then this is a NOOP.
222 205 dgisselq
        assign  w_lock   = (!iword[31])&&(w_op[4:0]==5'h1d)&&(
223
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
224
                                ||(IMPLEMENT_FPU==0));
225 201 dgisselq
        assign  w_noop   = (!iword[31])&&(w_op[4:0] == 5'h1f)&&(
226 178 dgisselq
                        ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
227
                        ||(IMPLEMENT_FPU==0));
228 138 dgisselq
 
229 201 dgisselq
        // dcdB - What register is used in the opB?
230
        //
231
        assign w_dcdB[4] = ((!iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie;
232
        assign w_dcdB[3:0]= (iword[31])
233
                                ? (((!iword[23])&&(iword[26:25]==2'b10))
234
                                        ? `CPU_SP_REG : iword[22:19])
235
                                : iword[17:14];
236 69 dgisselq
 
237
        // 0 LUTs
238 201 dgisselq
        assign  w_dcdA = w_dcdR;        // on ZipCPU, A is always result reg
239 69 dgisselq
        // 2 LUTs, 1 delay each
240 105 dgisselq
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
241 69 dgisselq
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
242
        // 0 LUTs
243
        assign  w_dcdA_pc = w_dcdR_pc;
244
        assign  w_dcdA_cc = w_dcdR_cc;
245
        // 2 LUTs, 1 delays each
246 201 dgisselq
        assign  w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == `CPU_PC_REG);
247
        assign  w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == `CPU_CC_REG);
248 69 dgisselq
 
249
        // Under what condition will we execute this
250
        // instruction?  Only the load immediate instruction
251
        // is completely unconditional.
252
        //
253
        // 3+4 LUTs
254 201 dgisselq
        assign  w_cond = ((w_ldi)||(iword[31])) ? 4'h8 :
255
                        { (iword[21:19]==3'h0), iword[21:19] };
256 69 dgisselq
 
257
        // 1 LUT
258 201 dgisselq
        assign  w_mem    = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00);
259
        assign  w_sto     = (w_mem)&&( w_cis_op[0]);
260 69 dgisselq
        // 1 LUT
261 201 dgisselq
        assign  w_div     = (!iword[31])&&(w_op[4:1] == 4'h7);
262
        // 2 LUTs
263
        assign  w_fpu   = (!iword[31])&&(w_op[4:3] == 2'b11)
264
                                &&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00);
265
        //
266
        // rA - do we need to read register A?
267
        assign  w_rA = // Floating point reads reg A
268
                        ((w_fpu)&&(w_cis_op[4:1] != 4'hf))
269
                        // Divide's read A
270
                        ||(w_div)
271
                        // ALU ops read A,
272
                        //      except for MOV's and BREV's which don't
273
                        ||((w_ALU)&&(!w_brev)&&(!w_mov))
274
                        // STO's read A
275
                        ||(w_sto)
276
                        // Test/compares
277
                        ||(w_cmptst);
278
        // rB -- do we read a register for operand B?  Specifically, do we
279
        // add the registers value to the immediate to create opB?
280
        assign  w_rB     = (w_mov)
281
                                ||((!iword[31])&&(iword[18])&&(!w_ldi))
282
                                ||(( iword[31])&&(iword[23])&&(!w_ldi))
283
                                // If using compressed instruction sets,
284
                                // we *always* read on memory operands.
285
                                ||(( iword[31])&&(w_mem));
286
        // wR -- will we be writing our result back?
287
        // wR_n = !wR
288 69 dgisselq
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
289 201 dgisselq
        assign  w_wR_n   = (w_sto)
290
                                ||((!iword[31])&&(w_cis_op[4:3]==2'b11)
291
                                        &&(w_cis_op[2:1]!=2'b00)
292
                                        &&(w_dcdR[3:1]==3'h7))
293 69 dgisselq
                                ||(w_cmptst);
294
        assign  w_wR     = ~w_wR_n;
295 90 dgisselq
        //
296 201 dgisselq
        // wF -- do we write flags when we are done?
297
        //
298 69 dgisselq
        assign  w_wF     = (w_cmptst)
299 201 dgisselq
                        ||((w_cond[3])&&((w_fpu)||(w_div)
300
                                ||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev)
301
                                        &&(w_dcdR[3:1] != 3'h7))));
302 69 dgisselq
 
303
        // Bottom 13 bits: no LUT's
304
        // w_dcd[12: 0] -- no LUTs
305
        // w_dcd[   13] -- 2 LUTs
306
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
307
        // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
308
        reg     [22:0]   r_I;
309
        wire    [22:0]   w_I, w_fullI;
310
        wire            w_Iz;
311
 
312
        assign  w_fullI = (w_ldi) ? { iword[22:0] } // LDI
313 201 dgisselq
                        // MOVE immediates have one less bit
314
                        :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] }
315
                        // Normal Op-B immediate ... 18 or 14 bits
316 69 dgisselq
                        :((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
317
                        : { {(23-14){iword[13]}}, iword[13:0] }
318
                        ));
319
 
320 201 dgisselq
`ifdef  OPT_CIS
321
        wire    [7:0]    w_halfbits;
322
        assign  w_halfbits = iword[23:16];
323
 
324
        wire    [7:0]    w_halfI;
325
        assign  w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0]
326
                        :(w_halfbits[7])?
327
                                { {(6){w_halfbits[2]}}, w_halfbits[1:0]}
328
                                :{ w_halfbits[6], w_halfbits[6:0] };
329
        assign  w_I  = (iword[31])?{{(23-8){w_halfI[7]}}, w_halfI }:w_fullI;
330 69 dgisselq
`else
331
        assign  w_I  = w_fullI;
332
`endif
333
        assign  w_Iz = (w_I == 0);
334
 
335
 
336 201 dgisselq
`ifdef  OPT_CIS
337 69 dgisselq
        //
338
        // The o_phase parameter is special.  It needs to let the software
339
        // following know that it cannot break/interrupt on an o_phase asserted
340
        // instruction, lest the break take place between the first and second
341 201 dgisselq
        // half of a CIS instruction.  To do this, o_phase must be asserted
342 69 dgisselq
        // when the first instruction half is valid, but not asserted on either
343
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
344
        reg     r_phase;
345
        initial r_phase = 1'b0;
346
        always @(posedge i_clk)
347 178 dgisselq
                if ((i_rst) // When no instruction is in the pipe, phase is zero
348
                        ||(o_early_branch)||(w_ljmp_dly))
349 69 dgisselq
                        r_phase <= 1'b0;
350 178 dgisselq
                else if ((i_ce)&&(i_pf_valid))
351 201 dgisselq
                        r_phase <= (o_phase)? 1'b0
352
                                : ((i_instruction[31])&&(i_pf_valid));
353
                else if (i_ce)
354
                        r_phase <= 1'b0;
355 69 dgisselq
        // Phase is '1' on the first instruction of a two-part set
356
        // But, due to the delay in processing, it's '1' when our output is
357
        // valid for that first part, but that'll be the same time we
358
        // are processing the second part ... so it may look to us like a '1'
359
        // on the second half of processing.
360
 
361
        assign  o_phase = r_phase;
362
`else
363
        assign  o_phase = 1'b0;
364
`endif
365
 
366
 
367 71 dgisselq
        initial o_illegal = 1'b0;
368 69 dgisselq
        always @(posedge i_clk)
369 71 dgisselq
                if (i_rst)
370
                        o_illegal <= 1'b0;
371
                else if (i_ce)
372 69 dgisselq
                begin
373 201 dgisselq
`ifdef  OPT_CIS
374 71 dgisselq
                        o_illegal <= (i_illegal);
375 69 dgisselq
`else
376
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
377
`endif
378 201 dgisselq
                        if ((IMPLEMENT_MPY==0)&&((w_cis_op[4:1]==4'h5)||(w_cis_op[4:0]==5'h0c)))
379 69 dgisselq
                                o_illegal <= 1'b1;
380
 
381 201 dgisselq
                        if ((IMPLEMENT_DIVIDE==0)&&(w_div))
382 69 dgisselq
                                o_illegal <= 1'b1;
383 201 dgisselq
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_div)&&(w_dcdR[3:1]==3'h7))
384 69 dgisselq
                                o_illegal <= 1'b1;
385
 
386
 
387 201 dgisselq
                        if ((IMPLEMENT_FPU==0)&&(w_fpu))
388 69 dgisselq
                                o_illegal <= 1'b1;
389
 
390 201 dgisselq
                        if ((w_cis_op[4:3]==2'b11)&&(w_cis_op[2:1]!=2'b00)
391
                                &&(w_dcdR[3:1]==3'h7)
392 71 dgisselq
                                &&(
393 201 dgisselq
                                        (w_cis_op[2:0] != 3'h4)  // BREAK
394 130 dgisselq
`ifdef  OPT_PIPELINED
395 201 dgisselq
                                        &&(w_cis_op[2:0] != 3'h5)        // LOCK
396 130 dgisselq
`endif
397 201 dgisselq
                                        // SIM instructions are always illegal
398
                                        &&(w_cis_op[2:0] != 3'h7)))      // NOOP
399 71 dgisselq
                                o_illegal <= 1'b1;
400
                end
401
 
402
 
403
        always @(posedge i_clk)
404
                if (i_ce)
405
                begin
406 201 dgisselq
`ifdef  OPT_CIS
407
                        if (!o_phase)
408 71 dgisselq
                                o_gie<= i_gie;
409 201 dgisselq
 
410 205 dgisselq
                        if (iword[31])
411
                        begin
412
                                if (o_phase)
413
                                        o_pc <= o_pc + 1'b1;
414
                                else if (i_pf_valid)
415
                                        o_pc <= { i_pc, 1'b1 };
416
                        end else begin
417
                                // The normal, non-CIS case
418 201 dgisselq
                                o_pc <= { i_pc + 1'b1, 1'b0 };
419 205 dgisselq
                        end
420 71 dgisselq
`else
421
                        o_gie<= i_gie;
422 201 dgisselq
                        o_pc <= { i_pc + 1'b1, 1'b0 };
423 71 dgisselq
`endif
424
 
425 69 dgisselq
                        // Under what condition will we execute this
426
                        // instruction?  Only the load immediate instruction
427
                        // is completely unconditional.
428
                        o_cond <= w_cond;
429
                        // Don't change the flags on conditional instructions,
430
                        // UNLESS: the conditional instruction was a CMP
431
                        // or TST instruction.
432
                        o_wF <= w_wF;
433
 
434
                        // Record what operation/op-code (4-bits) we are doing
435
                        //      Note that LDI magically becomes a MOV
436
                        //      instruction here.  That way it's a pass through
437
                        //      the ALU.  Likewise, the two compare instructions
438
                        //      CMP and TST becomes SUB and AND here as well.
439
                        // We keep only the bottom four bits, since we've
440 201 dgisselq
                        // already done the rest of the decode necessary to
441 69 dgisselq
                        // settle between the other instructions.  For example,
442
                        // o_FP plus these four bits uniquely defines the FP
443
                        // instruction, o_DV plus the bottom of these defines
444
                        // the divide, etc.
445 201 dgisselq
                        o_op <= ((w_ldi)||(w_noop))? 4'hd : w_cis_op[3:0];
446 69 dgisselq
 
447
                        // Default values
448
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
449
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
450
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
451
                        o_wR  <= w_wR;
452
                        o_rA  <= w_rA;
453
                        o_rB  <= w_rB;
454
                        r_I    <= w_I;
455
                        o_zI   <= w_Iz;
456
 
457 201 dgisselq
                        // Turn a NOOP into an ALU operation--subtract in
458 138 dgisselq
                        // particular, although it doesn't really matter as long
459
                        // as it doesn't take longer than one clock.  Note
460
                        // also that this depends upon not setting any registers
461
                        // or flags, which should already be true.
462 201 dgisselq
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop);
463
                        o_M    <=  w_mem;
464
                        o_DV   <=  w_div;
465
                        o_FP   <=  w_fpu;
466
 
467
                        o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&(
468 178 dgisselq
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
469
                                ||(IMPLEMENT_FPU==0));
470 130 dgisselq
`ifdef  OPT_PIPELINED
471 205 dgisselq
                        r_lock  <= w_lock;
472 130 dgisselq
`endif
473 201 dgisselq
`ifdef  OPT_CIS
474
                        r_nxt_half <= { iword[31], iword[14:0] };
475 69 dgisselq
`endif
476 201 dgisselq
 
477
`ifdef  VERILATOR
478
                        // Support the SIM instruction(s)
479
                        o_sim <= (!iword[31])&&(w_op[4:1] == 4'hf)
480
                                &&(w_dcdR[3:1] == 3'h7);
481
`else
482
                        o_sim <= 1'b0;
483
`endif
484
                        o_sim_immv <= iword[22:0];
485 69 dgisselq
                end
486
 
487 130 dgisselq
`ifdef  OPT_PIPELINED
488
        assign  o_lock = r_lock;
489
`else
490
        assign  o_lock = 1'b0;
491
`endif
492
 
493 69 dgisselq
        generate
494
        if (EARLY_BRANCHING!=0)
495
        begin
496 105 dgisselq
                reg                     r_early_branch, r_ljmp;
497 69 dgisselq
                reg     [(AW-1):0]       r_branch_pc;
498 105 dgisselq
 
499
                initial r_ljmp = 1'b0;
500 69 dgisselq
                always @(posedge i_clk)
501 105 dgisselq
                        if (i_rst)
502
                                r_ljmp <= 1'b0;
503 201 dgisselq
`ifdef  OPT_CIS
504
                        else if ((i_ce)&&(o_phase))
505
                                r_ljmp <= w_cis_ljmp;
506
`endif
507 105 dgisselq
                        else if ((i_ce)&&(i_pf_valid))
508
                                r_ljmp <= (w_ljmp);
509
                assign  o_ljmp = r_ljmp;
510
 
511
                always @(posedge i_clk)
512
                if (i_rst)
513
                        r_early_branch <= 1'b0;
514
                else if ((i_ce)&&(i_pf_valid))
515 90 dgisselq
                begin
516 105 dgisselq
                        if (r_ljmp)
517
                                // LOD (PC),PC
518
                                r_early_branch <= 1'b1;
519 201 dgisselq
                        else if ((!iword[31])&&(iword[30:27]==`CPU_PC_REG)
520
                                        &&(w_cond[3]))
521 69 dgisselq
                        begin
522 201 dgisselq
                                if ((w_op[4:0]==5'h02)&&(!iword[18]))
523 105 dgisselq
                                        // Add x,PC
524 69 dgisselq
                                        r_early_branch     <= 1'b1;
525 201 dgisselq
                                else
526 69 dgisselq
                                        r_early_branch     <= 1'b0;
527 90 dgisselq
                        end else
528
                                r_early_branch <= 1'b0;
529 105 dgisselq
                end else if (i_ce)
530
                        r_early_branch <= 1'b0;
531
 
532 69 dgisselq
                always @(posedge i_clk)
533
                        if (i_ce)
534
                        begin
535 105 dgisselq
                                if (r_ljmp)
536 201 dgisselq
                                        r_branch_pc <= iword[(AW+1):2];
537 90 dgisselq
                                else // Add x,PC
538
                                r_branch_pc <= i_pc
539 201 dgisselq
                                        + {{(AW-15){iword[17]}},iword[16:2]}
540 90 dgisselq
                                        + {{(AW-1){1'b0}},1'b1};
541 69 dgisselq
                        end
542
 
543 178 dgisselq
                assign  w_ljmp_dly         = r_ljmp;
544 69 dgisselq
                assign  o_early_branch     = r_early_branch;
545
                assign  o_branch_pc        = r_branch_pc;
546
        end else begin
547 178 dgisselq
                assign  w_ljmp_dly         = 1'b0;
548 69 dgisselq
                assign  o_early_branch = 1'b0;
549
                assign  o_branch_pc = {(AW){1'b0}};
550 105 dgisselq
                assign  o_ljmp = 1'b0;
551 69 dgisselq
        end endgenerate
552
 
553 71 dgisselq
 
554
        // To be a pipeable operation there must be ...
555
        //      1. Two valid adjacent instructions
556
        //      2. Both must be memory operations, of the same time (both lods
557
        //              or both stos)
558
        //      3. Both must use the same register base address
559
        //      4. Both must be to the same address, or the address incremented
560
        //              by one
561
        // Note that we're not using iword here ... there's a lot of logic
562
        // taking place, and it's only valid if the new word is not compressed.
563
        //
564
        reg     r_valid;
565 160 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
566 138 dgisselq
        initial r_pipe = 1'b0;
567 71 dgisselq
        always @(posedge i_clk)
568
                if (i_ce)
569 201 dgisselq
                        r_pipe <= (r_valid)&&((i_pf_valid)||(o_phase))
570
                                // Both must be memory operations
571
                                &&(w_mem)&&(o_M)
572
                                // Both must be writes, or both stores
573
                                &&(o_op[0] == w_cis_op[0])
574
                                // Both must be register ops
575
                                &&(w_rB)
576
                                // Both must use the same register for B
577
                                &&(w_dcdB[3:0] == o_dcdB[3:0])
578
                                // But ... the result can never be B
579
                                &&((o_op[0])
580
                                        ||(w_dcdB[3:0] != o_dcdA[3:0]))
581
                                // Needs to be to the mode, supervisor or user
582 71 dgisselq
                                &&(i_gie == o_gie)
583 201 dgisselq
                                // Same condition, or no condition before
584 71 dgisselq
                                &&((i_instruction[21:19]==o_cond[2:0])
585
                                        ||(o_cond[2:0] == 3'h0))
586 201 dgisselq
                                // Same immediate
587
                                &&((w_I[13:2]==r_I[13:2])
588
                                        ||({1'b0, w_I[13:2]}==(r_I[13:2]+12'h1)));
589 138 dgisselq
        assign o_pipe = r_pipe;
590
`else
591
        assign o_pipe = 1'b0;
592
`endif
593
 
594 71 dgisselq
        always @(posedge i_clk)
595
                if (i_rst)
596
                        r_valid <= 1'b0;
597 205 dgisselq
                else if (i_ce)
598
                        r_valid <= ((i_pf_valid)||(o_phase)||(i_illegal))
599
                                        &&(!o_ljmp)&&(!o_early_branch);
600
                else if (!i_stalled)
601 105 dgisselq
                        r_valid <= 1'b0;
602 71 dgisselq
 
603 205 dgisselq
        assign  o_valid = r_valid;
604 201 dgisselq
 
605 205 dgisselq
 
606 69 dgisselq
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
607
 
608
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.