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[/] [zipcpu/] [trunk/] [rtl/] [core/] [iscachable.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    iscachable.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     A helper function to both dcache and its formal properties,
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//              used to determine when a particular address is cachable.  This
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//      module must be built of entirely combinatorial logic and nothing more.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2018-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  iscachable(i_addr, o_cachable);
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        parameter       ADDRESS_WIDTH=30;
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        localparam      AW = ADDRESS_WIDTH; // Just for ease of notation below
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        parameter [AW-1:0]       SDRAM_ADDR  = 0, SDRAM_MASK = 0;
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        parameter [AW-1:0]       BKRAM_ADDR = 30'h4000000,
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                                BKRAM_MASK = 30'h4000000;
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        parameter [AW-1:0]       FLASH_ADDR  = 0, FLASH_MASK  = 0;
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        input   wire    [AW-1:0] i_addr;
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        output  reg                     o_cachable;
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        always @(*)
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        begin
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                o_cachable = 1'b0;
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                if ((SDRAM_ADDR !=0)&&((i_addr & SDRAM_MASK)== SDRAM_ADDR))
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                        o_cachable = 1'b1;
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                else if ((FLASH_ADDR !=0)&&((i_addr & FLASH_MASK)== FLASH_ADDR))
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                        o_cachable = 1'b1;
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                else if ((BKRAM_ADDR !=0)&&((i_addr & BKRAM_MASK)== BKRAM_ADDR))
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                        o_cachable = 1'b1;
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        end
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endmodule

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