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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Blame information for rev 36

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1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    memops.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     A memory unit to support a CPU.
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//
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//      In the interests of code simplicity, this memory operator is 
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//      susceptible to unknown results should a new command be sent to it
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//      before it completes the last one.  Unpredictable results might then
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//      occurr.
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//
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//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
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//              error signal).
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  memops(i_clk, i_rst, i_stb,
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                i_op, i_addr, i_data, i_oreg,
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                        o_busy, o_valid, o_err, o_wreg, o_result,
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                o_wb_cyc_gbl, o_wb_cyc_lcl,
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                        o_wb_stb_gbl, o_wb_stb_lcl,
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                        o_wb_we, o_wb_addr, o_wb_data,
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                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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        input                   i_clk, i_rst;
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        input                   i_stb;
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        // CPU interface
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        input                   i_op;
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        input           [31:0]   i_addr;
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        input           [31:0]   i_data;
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        input           [4:0]    i_oreg;
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        // CPU outputs
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        output  wire            o_busy;
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        output  reg             o_valid;
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        output  reg             o_err;
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        output  reg     [4:0]    o_wreg;
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        output  reg     [31:0]   o_result;
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        // Wishbone outputs
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        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
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        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
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        output  reg     [31:0]   o_wb_addr, o_wb_data;
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        // Wishbone inputs
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        input                   i_wb_ack, i_wb_stall, i_wb_err;
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        input           [31:0]   i_wb_data;
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        wire    gbl_stb, lcl_stb;
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        assign  lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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        assign  gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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        always @(posedge i_clk)
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                if (i_rst)
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                begin
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                        o_wb_cyc_gbl <= 1'b0;
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                        o_wb_cyc_lcl <= 1'b0;
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                end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
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                begin
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                        if ((i_wb_ack)||(i_wb_err))
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                        begin
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                                o_wb_cyc_gbl <= 1'b0;
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                                o_wb_cyc_lcl <= 1'b0;
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                        end
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                end else if (i_stb) // New memory operation
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                begin // Grab the wishbone
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                        o_wb_cyc_lcl <= lcl_stb;
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                        o_wb_cyc_gbl <= gbl_stb;
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                end
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        always @(posedge i_clk)
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                if (o_wb_cyc_gbl)
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                        o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
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                else
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                        o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation
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        always @(posedge i_clk)
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                if (o_wb_cyc_lcl)
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                        o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
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                else
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                        o_wb_stb_lcl  <= lcl_stb; // Grab wishbone on new operation
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        always @(posedge i_clk)
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                if (i_stb)
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                begin
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                        o_wb_we   <= i_op;
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                        o_wb_data <= i_data;
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                        o_wb_addr <= i_addr;
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                end
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        initial o_valid = 1'b0;
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        always @(posedge i_clk)
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                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
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        initial o_err = 1'b0;
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        always @(posedge i_clk)
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                o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
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        assign  o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
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        always @(posedge i_clk)
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                if (i_stb)
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                        o_wreg    <= i_oreg;
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        always @(posedge i_clk)
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                if (i_wb_ack)
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                        o_result <= i_wb_data;
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endmodule

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