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[/] [zipcpu/] [trunk/] [rtl/] [core/] [mpyop.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    mpyop.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This code has been pulled from the cpuops.v file so as to
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//              encapsulate the multiply component--the one component that
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//      (can't be) formally verified well, and so must be abstracted away.
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//      This separation was done to support potential future abstraction.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  mpyop(i_clk,i_reset, i_stb, i_op, i_a, i_b, o_valid, o_busy, o_result, o_hi);
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        // The following parameter selects which multiply algorithm we use.
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        // Timing performance is strictly dependent upon it.
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        parameter       IMPLEMENT_MPY = 1;
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        input   wire            i_clk, i_reset, i_stb;
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        input   wire    [1:0]    i_op; // 2'b00=MPY, 2'b10=MPYUHI, 2'b11=MPYSHI
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        input   wire    [31:0]   i_a, i_b;
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        output  wire            o_valid; // True if we'll be valid on the next clock;
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        output  wire            o_busy; // The multiply is busy if true
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        output  wire    [63:0]   o_result; // Where we dump the multiply result
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        output  reg             o_hi;   // Return the high half of the multiply
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        // A 4-way multiplexer can be done in one 6-LUT.
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        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
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        //      the Xilinx multiplexer fabric that follows. 
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        // Given that we wish to apply this multiplexer approach to 33-bits,
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        // this will cost a minimum of 132 6-LUTs.
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// i_stb instead of this_is_a_multiply_op
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// o_result
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// o_busy
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// o_done
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        generate
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        if (IMPLEMENT_MPY == 0)
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        begin : MPYNONE // No multiply support.
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                assign  o_result   = 64'h00;
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                assign  o_busy     = 1'b0;
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                assign  o_valid    = i_stb;
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                always @(*) o_hi = 1'b0; // Not needed
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`ifdef  VERILATOR
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                // verilator lint_off UNUSED
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                wire    [32+32+5-1:0]    mpy_unused;
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                assign  mpy_unused = { i_clk, i_reset, i_stb, i_op, i_a, i_b };
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                // verilator lint_on  UNUSED
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`endif
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        end else begin : IMPY
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        if (IMPLEMENT_MPY == 1)
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        begin : MPY1CK // Our single clock option (no extra clocks)
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                wire    signed  [63:0]   w_mpy_a_input, w_mpy_b_input;
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                assign  w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
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                assign  w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
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                assign  o_result = w_mpy_a_input * w_mpy_b_input;
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                assign  o_busy  = 1'b0;
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                assign  o_valid = 1'b0;
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                always @(*) o_hi = i_op[1];
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`ifdef  VERILATOR
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                // verilator lint_off UNUSED
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                wire    [3:0]    mpy_unused;
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                assign  mpy_unused = { i_clk, i_reset, i_stb, i_op[1] };
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                // verilator lint_on  UNUSED
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`endif
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        end else begin: MPN1
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        if (IMPLEMENT_MPY == 2)
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        begin : MPY2CK // Our two clock option (ALU must pause for 1 clock)
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                reg     signed  [63:0]   r_mpy_a_input, r_mpy_b_input;
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                always @(posedge i_clk)
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                begin
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                        r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
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                        r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
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                end
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                assign  o_result = r_mpy_a_input * r_mpy_b_input;
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                assign  o_busy  = 1'b0;
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                reg     mpypipe;
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                initial mpypipe = 1'b0;
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                always @(posedge i_clk)
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                        if (i_reset)
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                                mpypipe <= 1'b0;
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                        else
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                                mpypipe <= (i_stb);
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                assign  o_valid = mpypipe; // this_is_a_multiply_op;
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                always @(posedge i_clk)
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                if (i_stb)
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                        o_hi  <= i_op[1];
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        end else begin : MPN2
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        if (IMPLEMENT_MPY == 3)
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        begin : MPY3CK // Our three clock option (ALU pauses for 2 clocks)
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                reg     signed  [63:0]   r_smpy_result;
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                reg             [63:0]   r_umpy_result;
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                reg     signed  [31:0]   r_mpy_a_input, r_mpy_b_input;
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                reg             [1:0]    mpypipe;
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                reg             [1:0]    r_sgn;
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                initial mpypipe = 2'b0;
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                always @(posedge i_clk)
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                        if (i_reset)
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                                mpypipe <= 2'b0;
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                        else
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                        mpypipe <= { mpypipe[0], i_stb };
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                // First clock
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                always @(posedge i_clk)
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                begin
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                        r_mpy_a_input <= i_a[31:0];
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                        r_mpy_b_input <= i_b[31:0];
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                        r_sgn <= { r_sgn[0], i_op[0] };
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                end
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                // Second clock
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`ifdef  VERILATOR
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                wire    signed  [63:0]   s_mpy_a_input, s_mpy_b_input;
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                wire            [63:0]   u_mpy_a_input, u_mpy_b_input;
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                assign  s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input};
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                assign  s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input};
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                assign  u_mpy_a_input = {32'h00,r_mpy_a_input};
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                assign  u_mpy_b_input = {32'h00,r_mpy_b_input};
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                always @(posedge i_clk)
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                        r_smpy_result <= s_mpy_a_input * s_mpy_b_input;
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                always @(posedge i_clk)
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                        r_umpy_result <= u_mpy_a_input * u_mpy_b_input;
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`else
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                wire            [31:0]   u_mpy_a_input, u_mpy_b_input;
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                assign  u_mpy_a_input = r_mpy_a_input;
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                assign  u_mpy_b_input = r_mpy_b_input;
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                always @(posedge i_clk)
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                        r_smpy_result <= r_mpy_a_input * r_mpy_b_input;
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                always @(posedge i_clk)
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                        r_umpy_result <= u_mpy_a_input * u_mpy_b_input;
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`endif
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                always @(posedge i_clk)
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                if (i_stb)
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                        o_hi  <= i_op[1];
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                assign  o_busy  = mpypipe[0];
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                assign  o_result = (r_sgn[1])?r_smpy_result:r_umpy_result;
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                assign  o_valid = mpypipe[1];
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                // Results are then set on the third clock
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        end else begin : MPN3
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        if (IMPLEMENT_MPY == 4)
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        begin : MPY4CK // The three clock option
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                reg     [63:0]   r_mpy_result;
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                reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
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                reg             r_mpy_signed;
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                reg     [2:0]    mpypipe;
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197
                // First clock, latch in the inputs
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                initial mpypipe = 3'b0;
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                always @(posedge i_clk)
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                begin
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                        // mpypipe indicates we have a multiply in the
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                        // pipeline.  In this case, the multiply
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                        // pipeline is a two stage pipeline, so we need 
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                        // two bits in the pipe.
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                        if (i_reset)
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                                mpypipe <= 3'h0;
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                        else begin
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                                mpypipe[0] <= i_stb;
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                                mpypipe[1] <= mpypipe[0];
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                                mpypipe[2] <= mpypipe[1];
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                        end
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                        if (i_op[0]) // i.e. if signed multiply
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                        begin
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                                r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
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                                r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
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                        end else begin
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                                r_mpy_a_input <= i_a[31:0];
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                                r_mpy_b_input <= i_b[31:0];
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                        end
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                        // The signed bit really only matters in the
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                        // case of 64 bit multiply.  We'll keep track
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                        // of it, though, and pretend in all other
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                        // cases.
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                        r_mpy_signed  <= i_op[0];
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227
                        if (i_stb)
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                                o_hi  <= i_op[1];
229
                end
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                assign  o_busy  = |mpypipe[1:0];
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                assign  o_valid = mpypipe[2];
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                // Second clock, do the multiplies, get the "partial
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                // products".  Here, we break our input up into two
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                // halves, 
237
                //
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                //   A  = (2^16 ah + al)
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                //   B  = (2^16 bh + bl)
240
                //
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                // and use these to compute partial products.
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                //
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                //   AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl)
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                //
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                // Since we're following the FOIL algorithm to get here,
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                // we'll name these partial products according to FOIL.
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                //
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                // The trick is what happens if A or B is signed.  In
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                // those cases, the real value of A will not be given by
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                //      A = (2^16 ah + al)
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                // but rather
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                //      A = (2^16 ah[31^] + al) - 2^31
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                //  (where we have flipped the sign bit of A)
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                // and so ...
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                //
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                // AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31)
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                //      = 2^32(ah*bh)
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                //              +2^16 (ah*bl+al*bh)
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                //              +(al*bl)
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                //              - 2^31 (2^16 bh+bl + 2^16 ah+al)
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                //              - 2^62
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                //      = 2^32(ah*bh)
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                //              +2^16 (ah*bl+al*bh)
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                //              +(al*bl)
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                //              - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31)
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                //
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                reg     [31:0]   pp_f, pp_l; // F and L from FOIL
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                reg     [32:0]   pp_oi; // The O and I from FOIL
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                reg     [32:0]   pp_s;
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                always @(posedge i_clk)
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                begin
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                        pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16];
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                        pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0]
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                                + r_mpy_a_input[15: 0]*r_mpy_b_input[31:16];
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                        pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0];
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                        // And a special one for the sign
277
                        if (r_mpy_signed)
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                                pp_s <= 32'h8000_0000-(
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                                        r_mpy_a_input[31:0]
280
                                        + r_mpy_b_input[31:0]);
281
                        else
282
                                pp_s <= 33'h0;
283
                end
284
 
285
                // Third clock, add the results and produce a product
286
                always @(posedge i_clk)
287
                begin
288
                        r_mpy_result[15:0] <= pp_l[15:0];
289
                        r_mpy_result[63:16] <=
290
                                { 32'h00, pp_l[31:16] }
291
                                + { 15'h00, pp_oi }
292
                                + { pp_s, 15'h00 }
293
                                + { pp_f, 16'h00 };
294
                end
295
 
296
                assign  o_result = r_mpy_result;
297
                // Fourth clock -- results are clocked into writeback
298
        end else begin : MPYSLOW
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300
                // verilator lint_off UNUSED
301
                wire            unused_aux;
302
                wire    [65:0]   full_result;
303
                // verilator lint_on  UNUSED
304
 
305
                slowmpy #(.LGNA(6), .NA(33)) slowmpyi(i_clk, i_reset, i_stb,
306
                        { (i_op[0])&(i_a[31]), i_a },
307
                        { (i_op[0])&(i_b[31]), i_b }, 1'b0, o_busy,
308
                                o_valid, full_result, unused_aux);
309
 
310
                assign  o_result = full_result[63:0];
311
 
312
                always @(posedge i_clk)
313
                if (i_stb)
314
                        o_hi  <= i_op[1];
315
 
316
        end end end end end
317
        endgenerate // All possible multiply results have been determined
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endmodule

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