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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Blame information for rev 105

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1 69 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    pfcache.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Keeping our CPU fed with instructions, at one per clock and
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//              with no stalls.  An unusual feature of this cache is the
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//      requirement that the entire cache may be cleared (if necessary).
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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module  pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
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                        // i_early_branch, i_from_addr,
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                        i_stall_n, i_pc, o_i, o_pc, o_v,
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                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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                        o_illegal);
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        parameter       LGCACHELEN = 8, ADDRESS_WIDTH=24,
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                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
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                        CW=LGCACHELEN, PW=LGCACHELEN-5;
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        input                           i_clk, i_rst, i_new_pc;
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        input                           i_clear_cache;
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        input                           i_stall_n;
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        input           [(AW-1):0]       i_pc;
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        output  reg     [(BUSW-1):0]     o_i;
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        output  reg     [(AW-1):0]       o_pc;
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        output  wire                    o_v;
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        //
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        output  reg             o_wb_cyc, o_wb_stb;
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        output  wire            o_wb_we;
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        output  reg     [(AW-1):0]       o_wb_addr;
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        output  wire    [(BUSW-1):0]     o_wb_data;
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        //
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        input                           i_wb_ack, i_wb_stall, i_wb_err;
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        input           [(BUSW-1):0]     i_wb_data;
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        //
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        output  reg                     o_illegal;
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        // Fixed bus outputs: we read from the bus only, never write.
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        // Thus the output data is ... irrelevant and don't care.  We set it
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        // to zero just to set it to something.
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        assign  o_wb_we = 1'b0;
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        assign  o_wb_data = 0;
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        reg                     r_v;
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        (* ram_style = "distributed" *)
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        reg     [(BUSW-1):0]     cache   [0:((1<<CW)-1)];
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        reg     [(AW-CW-1):0]    tags    [0:((1<<(CW-PW))-1)];
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        reg     [((1<<(CW-PW))-1):0]     vmask;
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        reg     [(AW-1):0]       lastpc;
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        reg     [(CW-1):0]       rdaddr;
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        reg     [(AW-1):CW]     tagval;
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        wire    [(AW-1):PW]     lasttag;
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        reg     [(AW-1):PW]     illegal_cache;
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        initial o_i = 32'h76_00_00_00;  // A NOOP instruction
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        initial o_pc = 0;
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        always @(posedge i_clk)
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                if (~r_v)
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                begin
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                        o_i <= cache[lastpc[(CW-1):0]];
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                        o_pc <= lastpc;
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                end else if ((i_stall_n)||(i_new_pc))
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                begin
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                        o_i <= cache[i_pc[(CW-1):0]];
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                        o_pc <= i_pc;
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                end
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        initial tagval = 0;
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        always @(posedge i_clk)
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                if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
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                                &&(i_wb_ack)&&(~i_wb_err))
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                        // Our tag value changes any time we finish reading a
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                        // new cache line
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                        tagval <= o_wb_addr[(AW-1):CW];
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                else if ((i_stall_n)&&(~o_wb_cyc))
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                        // Otherwise, as long as we're not reading new stuff,
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                        // the tag line changes any time the pipeline steps
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                        // forwards.  Our purpose here is primarily just to 
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                        // catch sudden changes.  The result is that walking
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                        // from one cache line to the next will cost a clock.
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                        tagval <= tags[i_pc[(CW-1):PW]];
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        // i_pc will only increment when everything else isn't stalled, thus
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        // we can set it without worrying about that.   Doing this enables
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        // us to work in spite of stalls.  For example, if the next address
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        // isn't valid, but the decoder is stalled, get the next address
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        // anyway.
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        initial lastpc = 0;
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        always @(posedge i_clk)
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                if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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                        lastpc <= i_pc;
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        assign  lasttag = lastpc[(AW-1):PW];
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        // initial      lasttag = 0;
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        // always @(posedge i_clk)
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                // if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
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                        // lasttag <= i_pc[(AW-1):PW];
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        wire    r_v_from_pc, r_v_from_last;
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        assign  r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
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                                &&(tagval == i_pc[(AW-1):CW])
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                                &&(vmask[i_pc[(CW-1):PW]]));
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        assign  r_v_from_last = (
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                                //(lastpc[(AW-1):PW] == lasttag)&&
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                                (tagval == lastpc[(AW-1):CW])
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                                &&(vmask[lastpc[(CW-1):PW]]));
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        reg     [1:0]    delay;
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        initial delay = 2'h3;
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        initial r_v = 1'b0;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
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                begin
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                        r_v <= r_v_from_pc;
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                        delay <= 2'h2;
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                end else if (~r_v) begin // Otherwise, r_v was true and we were
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                        r_v <= r_v_from_last;   // stalled, hence only if ~r_v
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                        if (o_wb_cyc)
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                                delay <= 2'h2;
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                        else if (delay != 0)
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                                delay <= delay + 2'b11; // i.e. delay -= 1;
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                end
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        assign  o_v = (r_v)&&(~i_new_pc);
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        initial o_wb_cyc  = 1'b0;
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        initial o_wb_stb  = 1'b0;
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        initial o_wb_addr = {(AW){1'b0}};
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        initial rdaddr    = 0;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_clear_cache))
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                begin
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                        o_wb_cyc <= 1'b0;
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                        o_wb_stb <= 1'b0;
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                end else if (o_wb_cyc)
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                begin
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                        if ((o_wb_stb)&&(~i_wb_stall))
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                        begin
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                                if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
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                                        o_wb_stb <= 1'b0;
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                                else
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                                        o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
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                        end
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                        if (i_wb_ack)
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                        begin
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                                rdaddr <= rdaddr + 1;
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                                if (rdaddr[(PW-1):0] == {(PW){1'b1}})
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                                        tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
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                        end
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                        if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
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                                o_wb_cyc <= 1'b0;
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                        // else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
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                        //      tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
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                end else if ((~r_v)&&(delay==0)
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                        &&((tagval != lastpc[(AW-1):CW])
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                                ||(~vmask[lastpc[(CW-1):PW]]))
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                        &&(~o_illegal))
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                begin
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                        o_wb_cyc  <= 1'b1;
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                        o_wb_stb  <= 1'b1;
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                        o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
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                        rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
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                end
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        // Can't initialize an array, so leave cache uninitialized
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        always @(posedge i_clk)
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                if ((o_wb_cyc)&&(i_wb_ack))
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                        cache[rdaddr] <= i_wb_data;
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        // VMask ... is a section loaded?
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        initial vmask = 0;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_clear_cache))
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                        vmask <= 0;
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                else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
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                        vmask[lastpc[(CW-1):PW]] <= 1'b0;
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                else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
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                        vmask[rdaddr[(CW-1):PW]] <= 1'b1;
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        reg     illegal_valid;
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        initial illegal_cache = 0;
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        initial illegal_valid = 0;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_clear_cache))
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                begin
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                        illegal_cache <= 0;
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                        illegal_valid <= 0;
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                end else if ((o_wb_cyc)&&(i_wb_err))
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                begin
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                        illegal_cache <= lastpc[(AW-1):PW];
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                        illegal_valid <= 1'b1;
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                end
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        initial o_illegal = 1'b0;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_clear_cache))
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                        o_illegal <= 1'b0;
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                else
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                        o_illegal <= (illegal_valid)
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                                &&(tagval == i_pc[(AW-1):CW])
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                                &&(illegal_cache == i_pc[(AW-1):PW]);
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endmodule

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