URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Blame information for rev 88

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////////
//
// Filename:    pfcache.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
//              with no stalls.  An unusual feature of this cache is the
//      requirement that the entire cache may be cleared (if necessary).
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
module  pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
                        // i_early_branch, i_from_addr,
                        i_stall_n, i_pc, o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
                        o_illegal);
        parameter       LGCACHELEN = 8, ADDRESS_WIDTH=24,
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
                        CW=LGCACHELEN, PW=LGCACHELEN-5;
        input                           i_clk, i_rst, i_new_pc;
        input                           i_clear_cache;
        input                           i_stall_n;
        input           [(AW-1):0]       i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(AW-1):0]       o_pc;
        output  wire                    o_v;
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        input                           i_wb_ack, i_wb_stall, i_wb_err;
        input           [(BUSW-1):0]     i_wb_data;
        //
        output  reg                     o_illegal;
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
 
        reg                     r_v;
        (* ram_style = "distributed" *)
        reg     [(BUSW-1):0]     cache   [0:((1<<CW)-1)];
        reg     [(AW-CW-1):0]    tags    [0:((1<<(CW-PW))-1)];
        reg     [((1<<(CW-PW))-1):0]     vmask;
 
        reg     [(AW-1):0]       lastpc;
        reg     [(CW-1):0]       rdaddr;
        reg     [(AW-1):CW]     tagval;
        wire    [(AW-1):PW]     lasttag;
        reg     [(AW-1):PW]     illegal_cache;
 
        initial o_i = 32'h76_00_00_00;  // A NOOP instruction
        initial o_pc = 0;
        always @(posedge i_clk)
                if (~r_v)
                begin
                        o_i <= cache[lastpc[(CW-1):0]];
                        o_pc <= lastpc;
                end else if ((i_stall_n)||(i_new_pc))
                begin
                        o_i <= cache[i_pc[(CW-1):0]];
                        o_pc <= i_pc;
                end
 
        initial tagval = 0;
        always @(posedge i_clk)
                if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
                                &&(i_wb_ack)&&(~i_wb_err))
                        // Our tag value changes any time we finish reading a
                        // new cache line
                        tagval <= o_wb_addr[(AW-1):CW];
                else if ((i_stall_n)&&(~o_wb_cyc))
                        // Otherwise, as long as we're not reading new stuff,
                        // the tag line changes any time the pipeline steps
                        // forwards.  Our purpose here is primarily just to 
                        // catch sudden changes.  The result is that walking
                        // from one cache line to the next will cost a clock.
                        tagval <= tags[i_pc[(CW-1):PW]];
 
        // i_pc will only increment when everything else isn't stalled, thus
        // we can set it without worrying about that.   Doing this enables
        // us to work in spite of stalls.  For example, if the next address
        // isn't valid, but the decoder is stalled, get the next address
        // anyway.
        initial lastpc = 0;
        always @(posedge i_clk)
                if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                        lastpc <= i_pc;
 
        assign  lasttag = lastpc[(AW-1):PW];
        // initial      lasttag = 0;
        // always @(posedge i_clk)
                // if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
                        // lasttag <= i_pc[(AW-1):PW];
 
        wire    r_v_from_pc, r_v_from_last;
        assign  r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
                                &&(tagval == i_pc[(AW-1):CW])
                                &&(vmask[i_pc[(CW-1):PW]]));
        assign  r_v_from_last = (
                                //(lastpc[(AW-1):PW] == lasttag)&&
                                (tagval == lastpc[(AW-1):CW])
                                &&(vmask[lastpc[(CW-1):PW]]));
 
        reg     [1:0]    delay;
 
        initial delay = 2'h3;
        initial r_v = 1'b0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)||(i_new_pc)||((r_v)&&(i_stall_n)))
                begin
                        r_v <= r_v_from_pc;
                        delay <= 2'h2;
                end else if (~r_v) begin // Otherwise, r_v was true and we were
                        r_v <= r_v_from_last;   // stalled, hence only if ~r_v
                        if (o_wb_cyc)
                                delay <= 2'h2;
                        else if (delay != 0)
                                delay <= delay + 2'b11; // i.e. delay -= 1;
                end
 
        assign  o_v = (r_v)&&(~i_new_pc);
 
 
        initial o_wb_cyc  = 1'b0;
        initial o_wb_stb  = 1'b0;
        initial o_wb_addr = {(AW){1'b0}};
        initial rdaddr    = 0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                end else if (o_wb_cyc)
                begin
                        if ((o_wb_stb)&&(~i_wb_stall))
                        begin
                                if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
                                        o_wb_stb <= 1'b0;
                                else
                                        o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
                        end
 
                        if (i_wb_ack)
                        begin
                                rdaddr <= rdaddr + 1;
                                if (rdaddr[(PW-1):0] == {(PW){1'b1}})
                                        tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
                        end
 
                        if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err))
                                o_wb_cyc <= 1'b0;
 
                        // else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
                        //      tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
 
                end else if ((~r_v)&&(delay==0)
                        &&((tagval != lastpc[(AW-1):CW])
                                ||(~vmask[lastpc[(CW-1):PW]]))
                        &&(~o_illegal))
                begin
                        o_wb_cyc  <= 1'b1;
                        o_wb_stb  <= 1'b1;
                        o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
                        rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
                end
 
        // Can't initialize an array, so leave cache uninitialized
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[rdaddr] <= i_wb_data;
 
        // VMask ... is a section loaded?
        initial vmask = 0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                        vmask <= 0;
                else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
                        vmask[lastpc[(CW-1):PW]] <= 1'b0;
                else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
                        vmask[rdaddr[(CW-1):PW]] <= 1'b1;
 
        reg     illegal_valid;
        initial illegal_cache = 0;
        initial illegal_valid = 0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                begin
                        illegal_cache <= 0;
                        illegal_valid <= 0;
                end else if ((o_wb_cyc)&&(i_wb_err))
                begin
                        illegal_cache <= lastpc[(AW-1):PW];
                        illegal_valid <= 1'b1;
                end
 
        initial o_illegal = 1'b0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                        o_illegal <= 1'b0;
                else
                        o_illegal <= (illegal_valid)
                                &&(tagval == i_pc[(AW-1):CW])
                                &&(illegal_cache == i_pc[(AW-1):PW]);
 
endmodule

Line No.	Rev	Author	Line
1	69	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3	82	dgisselq	`// Filename: pfcache.v`
4	69	dgisselq	`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7			`// Purpose: Keeping our CPU fed with instructions, at one per clock and`
8			`// with no stalls. An unusual feature of this cache is the`
9			`// requirement that the entire cache may be cleared (if necessary).`
10			`//`
11			`// Creator: Dan Gisselquist, Ph.D.`
12			`// Gisselquist Technology, LLC`
13			`//`
14			`////////////////////////////////////////////////////////////////////////////////`
15			`//`
16			`// Copyright (C) 2015, Gisselquist Technology, LLC`
17			`//`
18			`// This program is free software (firmware): you can redistribute it and/or`
19			`// modify it under the terms of the GNU General Public License as published`
20			`// by the Free Software Foundation, either version 3 of the License, or (at`
21			`// your option) any later version.`
22			`//`
23			`// This program is distributed in the hope that it will be useful, but WITHOUT`
24			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
25			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
26			`// for more details.`
27			`//`
28			`// License: GPL, v3, as defined and found on www.gnu.org,`
29			`// http://www.gnu.org/licenses/gpl.html`
30			`//`
31			`//`
32			`////////////////////////////////////////////////////////////////////////////////`
33			`//`
34			`module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,`
35			`// i_early_branch, i_from_addr,`
36			`i_stall_n, i_pc, o_i, o_pc, o_v,`
37			`o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,`
38			`i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,`
39			`o_illegal);`
40			`parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,`
41			`CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,`
42			`CW=LGCACHELEN, PW=LGCACHELEN-5;`
43			`input i_clk, i_rst, i_new_pc;`
44			`input i_clear_cache;`
45			`input i_stall_n;`
46			`input [(AW-1):0] i_pc;`
47			`output reg [(BUSW-1):0] o_i;`
48			`output reg [(AW-1):0] o_pc;`
49			`output wire o_v;`
50			`//`
51			`output reg o_wb_cyc, o_wb_stb;`
52			`output wire o_wb_we;`
53			`output reg [(AW-1):0] o_wb_addr;`
54			`output wire [(BUSW-1):0] o_wb_data;`
55			`//`
56			`input i_wb_ack, i_wb_stall, i_wb_err;`
57			`input [(BUSW-1):0] i_wb_data;`
58			`//`
59			`output reg o_illegal;`
60
61			`// Fixed bus outputs: we read from the bus only, never write.`
62			`// Thus the output data is ... irrelevant and don't care. We set it`
63			`// to zero just to set it to something.`
64			`assign o_wb_we = 1'b0;`
65			`assign o_wb_data = 0;`
66
67			`reg r_v;`
68			`(* ram_style = "distributed" *)`
69			`reg [(BUSW-1):0] cache [0:((1<<CW)-1)];`
70			`reg [(AW-CW-1):0] tags [0:((1<<(CW-PW))-1)];`
71			`reg [((1<<(CW-PW))-1):0] vmask;`
72
73			`reg [(AW-1):0] lastpc;`
74			`reg [(CW-1):0] rdaddr;`
75			`reg [(AW-1):CW] tagval;`
76	82	dgisselq	`wire [(AW-1):PW] lasttag;`
77			`reg [(AW-1):PW] illegal_cache;`
78	69	dgisselq
79			`initial o_i = 32'h76_00_00_00; // A NOOP instruction`
80			`initial o_pc = 0;`
81			`always @(posedge i_clk)`
82			`if (~r_v)`
83			`begin`
84			`o_i <= cache[lastpc[(CW-1):0]];`
85			`o_pc <= lastpc;`
86			`end else if ((i_stall_n)\|\|(i_new_pc))`
87			`begin`
88			`o_i <= cache[i_pc[(CW-1):0]];`
89			`o_pc <= i_pc;`
90			`end`
91
92			`initial tagval = 0;`
93			`always @(posedge i_clk)`
94	82	dgisselq	`if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})`
95			`&&(i_wb_ack)&&(~i_wb_err))`
96			`// Our tag value changes any time we finish reading a`
97			`// new cache line`
98			`tagval <= o_wb_addr[(AW-1):CW];`
99			`else if ((i_stall_n)&&(~o_wb_cyc))`
100			`// Otherwise, as long as we're not reading new stuff,`
101			`// the tag line changes any time the pipeline steps`
102			`// forwards. Our purpose here is primarily just to`
103			`// catch sudden changes. The result is that walking`
104			`// from one cache line to the next will cost a clock.`
105	69	dgisselq	`tagval <= tags[i_pc[(CW-1):PW]];`
106
107			`// i_pc will only increment when everything else isn't stalled, thus`
108			`// we can set it without worrying about that. Doing this enables`
109			`// us to work in spite of stalls. For example, if the next address`
110			`// isn't valid, but the decoder is stalled, get the next address`
111			`// anyway.`
112			`initial lastpc = 0;`
113			`always @(posedge i_clk)`
114	71	dgisselq	`if (((r_v)&&(i_stall_n))\|\|(i_clear_cache)\|\|(i_new_pc))`
115	69	dgisselq	`lastpc <= i_pc;`
116
117	82	dgisselq	`assign lasttag = lastpc[(AW-1):PW];`
118			`// initial lasttag = 0;`
119			`// always @(posedge i_clk)`
120			`// if (((r_v)&&(i_stall_n))\|\|(i_clear_cache)\|\|(i_new_pc))`
121			`// lasttag <= i_pc[(AW-1):PW];`
122	69	dgisselq
123			`wire r_v_from_pc, r_v_from_last;`
124			`assign r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)`
125			`&&(tagval == i_pc[(AW-1):CW])`
126			`&&(vmask[i_pc[(CW-1):PW]]));`
127	82	dgisselq	`assign r_v_from_last = (`
128			`//(lastpc[(AW-1):PW] == lasttag)&&`
129			`(tagval == lastpc[(AW-1):CW])`
130	69	dgisselq	`&&(vmask[lastpc[(CW-1):PW]]));`
131
132			`reg [1:0] delay;`
133
134			`initial delay = 2'h3;`
135			`initial r_v = 1'b0;`
136			`always @(posedge i_clk)`
137	71	dgisselq	`if ((i_rst)\|\|(i_clear_cache)\|\|(i_new_pc)\|\|((r_v)&&(i_stall_n)))`
138	69	dgisselq	`begin`
139			`r_v <= r_v_from_pc;`
140			`delay <= 2'h2;`
141	71	dgisselq	`end else if (~r_v) begin // Otherwise, r_v was true and we were`
142			`r_v <= r_v_from_last; // stalled, hence only if ~r_v`
143	69	dgisselq	`if (o_wb_cyc)`
144			`delay <= 2'h2;`
145			`else if (delay != 0)`
146	88	dgisselq	`delay <= delay + 2'b11; // i.e. delay -= 1;`
147	69	dgisselq	`end`
148
149			`assign o_v = (r_v)&&(~i_new_pc);`
150
151
152			`initial o_wb_cyc = 1'b0;`
153			`initial o_wb_stb = 1'b0;`
154			`initial o_wb_addr = {(AW){1'b0}};`
155			`initial rdaddr = 0;`
156			`always @(posedge i_clk)`
157			`if ((i_rst)\|\|(i_clear_cache))`
158			`begin`
159			`o_wb_cyc <= 1'b0;`
160			`o_wb_stb <= 1'b0;`
161			`end else if (o_wb_cyc)`
162			`begin`
163			`if ((o_wb_stb)&&(~i_wb_stall))`
164			`begin`
165			`if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})`
166			`o_wb_stb <= 1'b0;`
167			`else`
168			`o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;`
169			`end`
170
171			`if (i_wb_ack)`
172	82	dgisselq	`begin`
173	69	dgisselq	`rdaddr <= rdaddr + 1;`
174	82	dgisselq	`if (rdaddr[(PW-1):0] == {(PW){1'b1}})`
175			`tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];`
176			`end`
177
178			`if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))\|\|(i_wb_err))`
179	69	dgisselq	`o_wb_cyc <= 1'b0;`
180	82	dgisselq
181	69	dgisselq	`// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})`
182			`// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];`
183
184			`end else if ((~r_v)&&(delay==0)`
185			`&&((tagval != lastpc[(AW-1):CW])`
186	71	dgisselq	`\|\|(~vmask[lastpc[(CW-1):PW]]))`
187			`&&(~o_illegal))`
188	69	dgisselq	`begin`
189			`o_wb_cyc <= 1'b1;`
190			`o_wb_stb <= 1'b1;`
191			`o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };`
192			`rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };`
193			`end`
194
195			`// Can't initialize an array, so leave cache uninitialized`
196			`always @(posedge i_clk)`
197			`if ((o_wb_cyc)&&(i_wb_ack))`
198			`cache[rdaddr] <= i_wb_data;`
199
200			`// VMask ... is a section loaded?`
201			`initial vmask = 0;`
202			`always @(posedge i_clk)`
203			`if ((i_rst)\|\|(i_clear_cache))`
204			`vmask <= 0;`
205			`else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))`
206			`vmask[lastpc[(CW-1):PW]] <= 1'b0;`
207			`else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))`
208			`vmask[rdaddr[(CW-1):PW]] <= 1'b1;`
209
210	71	dgisselq	`reg illegal_valid;`
211	69	dgisselq	`initial illegal_cache = 0;`
212	71	dgisselq	`initial illegal_valid = 0;`
213	69	dgisselq	`always @(posedge i_clk)`
214			`if ((i_rst)\|\|(i_clear_cache))`
215	71	dgisselq	`begin`
216	69	dgisselq	`illegal_cache <= 0;`
217	71	dgisselq	`illegal_valid <= 0;`
218			`end else if ((o_wb_cyc)&&(i_wb_err))`
219			`begin`
220	69	dgisselq	`illegal_cache <= lastpc[(AW-1):PW];`
221	71	dgisselq	`illegal_valid <= 1'b1;`
222			`end`
223	69	dgisselq
224			`initial o_illegal = 1'b0;`
225			`always @(posedge i_clk)`
226	71	dgisselq	`if ((i_rst)\|\|(i_clear_cache))`
227			`o_illegal <= 1'b0;`
228			`else`
229			`o_illegal <= (illegal_valid)`
230			`&&(tagval == i_pc[(AW-1):CW])`
231			`&&(illegal_cache == i_pc[(AW-1):PW]);`
232	69	dgisselq
233			`endmodule`

Browse

Tools

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pfcache.v] - Blame information for rev 88