URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log


////////////////////////////////////////////////////////////////////////////////
//
// Filename:    pipefetch.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
//              with no stalls, can be quite a chore.  Worse, the Wishbone
//              takes a couple of cycles just to read one instruction from
//              the bus.  However, if we use pipeline accesses to the Wishbone
//              bus, then we can read more and faster.  Further, if we cache
//              these results so that we have them before we need them, then
//              we have a chance of keeping our CPU from stalling.  Those are
//              the purposes of this instruction fetch module: 1) Pipeline
//              wishbone accesses, and 2) an instruction cache.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        BUSW=32;
        input                           i_clk, i_rst, i_new_pc,
                                        i_clear_cache, i_stall_n;
        input           [(BUSW-1):0]     i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_pc;
        output  wire                    o_v;
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        input                   i_wb_ack, i_wb_stall;
        input           [(BUSW-1):0]     i_wb_data;
        //
        // Is the (data) memory unit also requesting access to the bus?
        input                           i_wb_request;
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
 
        reg     [(BUSW-1):0]             r_cache_base;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
 
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
 
        reg                     r_addr_set;
        reg     [(BUSW-1):0]     r_addr;
 
        wire    [(BUSW-1):0]     bus_nvalid;
        assign  bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
 
        // What are some of the conditions for which we need to restart the
        // cache?
        wire    w_pc_out_of_bounds;
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
                                        ||(i_pc < r_cache_base)
                                        ||(i_pc >= r_cache_base + CACHELEN)));
        wire    w_ran_off_end_of_cache;
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
                                        ||(r_addr >= r_cache_base + CACHELEN)));
        wire    w_running_out_of_cache;
        assign  w_running_out_of_cache = (r_addr_set)
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
                                                + (1<<(LGCACHELEN-1)));
        initial r_nvalid = 0;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        begin
                if ((i_rst)||(i_clear_cache))
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                        // r_cache_base <= RESET_ADDRESS;
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                //              &&(i_pc >= r_cache_base)
                //              &&(i_pc < r_cache_base + bus_nvalid))
                // begin
                        // The new instruction is in our cache, do nothing
                        // with the bus here.
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
                begin
                        // We need to abandon our bus action to start over in
                        // a new region, setting up a new cache.  This may
                        // happen mid cycle while waiting for a result.  By
                        // dropping o_wb_cyc, we state that we are no longer
                        // interested in that result--whatever it might be.
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
                begin
                        // Restart a bus cycle that was interrupted when the
                        // data section wanted access to our bus.
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= r_cache_base + bus_nvalid;
                end else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                begin
                        // Start a bus transaction
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        // r_nvalid <= 0;
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                        // r_cache_offset <= 0;
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                begin
                        // If we're using the last quarter of the cache, then
                        // let's start a bus transaction to extend the cache.
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
                        // r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
                end else if (o_wb_cyc)
                begin
                        // This handles everything ... but the case where
                        // while reading we need to extend our cache.
                        if ((o_wb_stb)&&(~i_wb_stall))
                        begin
                                // o_wb_addr <= o_wb_addr + 1;
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
                                        ||(i_wb_request))
                                        o_wb_stb <= 1'b0;
                        end
 
                        if (i_wb_ack)
                        begin
                                // r_nvalid <= r_nvalid + 1;
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                        o_wb_cyc <= 1'b0;
                        end
                end
        end
 
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                else if ((o_wb_cyc)&&(i_wb_ack))
                        r_nvalid <= r_nvalid+1;
 
        always @(posedge i_clk)
                if (i_clear_cache)
                        r_cache_base <= i_pc;
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)
                                ||(w_ran_off_end_of_cache)))
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
 
        always @(posedge i_clk)
                if (i_clear_cache)
                        r_cache_offset <= 0;
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)
                                ||(w_ran_off_end_of_cache)))
                        r_cache_offset <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
        always @(posedge i_clk)
                if (i_clear_cache)
                        o_wb_addr <= i_pc;
                else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                                        ||(w_ran_off_end_of_cache)))
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                        o_wb_addr <= o_wb_addr + 1;
 
        initial r_acks_waiting = 0;
        always @(posedge i_clk)
                if (~o_wb_cyc)
                        r_acks_waiting <= 0;
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                        r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                                r_acks_waiting <= r_acks_waiting - 1;
 
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
                                        <= i_wb_data;
 
        initial r_addr_set = 1'b0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                        r_addr_set <= 1'b0;
                else if (i_new_pc)
                        r_addr_set <= 1'b1;
 
        // Now, read from the cache
        wire    w_cv;   // Cache valid, address is in the cache
        reg     r_cv;
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
                        &&(r_addr-r_cache_base < bus_nvalid));
        always @(posedge i_clk)
                r_cv <= (~i_new_pc)&&(w_cv);
        assign  o_v = (r_cv)&&(~i_new_pc);
 
        always @(posedge i_clk)
                if (i_new_pc)
                        r_addr <= i_pc;
                else if ((i_stall_n)&&(w_cv))
                        r_addr <= r_addr + 1;
 
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
        always @(posedge i_clk)
                if (i_stall_n)
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
                if (i_stall_n)
                        o_pc <= r_addr;
 
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3	3	dgisselq	`// Filename: pipefetch.v`
4	2	dgisselq	`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7	3	dgisselq	`// Purpose: Keeping our CPU fed with instructions, at one per clock and`
8			`// with no stalls, can be quite a chore. Worse, the Wishbone`
9			`// takes a couple of cycles just to read one instruction from`
10			`// the bus. However, if we use pipeline accesses to the Wishbone`
11			`// bus, then we can read more and faster. Further, if we cache`
12			`// these results so that we have them before we need them, then`
13			`// we have a chance of keeping our CPU from stalling. Those are`
14			`// the purposes of this instruction fetch module: 1) Pipeline`
15			`// wishbone accesses, and 2) an instruction cache.`
16	2	dgisselq	`//`
17			`// Creator: Dan Gisselquist, Ph.D.`
18			`// Gisselquist Tecnology, LLC`
19			`//`
20			`////////////////////////////////////////////////////////////////////////////////`
21			`//`
22			`// Copyright (C) 2015, Gisselquist Technology, LLC`
23			`//`
24			`// This program is free software (firmware): you can redistribute it and/or`
25			`// modify it under the terms of the GNU General Public License as published`
26			`// by the Free Software Foundation, either version 3 of the License, or (at`
27			`// your option) any later version.`
28			`//`
29			`// This program is distributed in the hope that it will be useful, but WITHOUT`
30			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
31			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
32			`// for more details.`
33			`//`
34			`// License: GPL, v3, as defined and found on www.gnu.org,`
35			`// http://www.gnu.org/licenses/gpl.html`
36			`//`
37			`//`
38			`////////////////////////////////////////////////////////////////////////////////`
39			`//`
40	18	dgisselq	`module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,`
41	2	dgisselq	`o_i, o_pc, o_v,`
42			`o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,`
43	3	dgisselq	`i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);`
44			`parameter RESET_ADDRESS=32'h0010_0000,`
45			`LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),`
46			`BUSW=32;`
47	18	dgisselq	`input i_clk, i_rst, i_new_pc,`
48			`i_clear_cache, i_stall_n;`
49	2	dgisselq	`input [(BUSW-1):0] i_pc;`
50			`output reg [(BUSW-1):0] o_i;`
51			`output reg [(BUSW-1):0] o_pc;`
52			`output wire o_v;`
53			`//`
54			`output reg o_wb_cyc, o_wb_stb;`
55			`output wire o_wb_we;`
56			`output reg [(BUSW-1):0] o_wb_addr;`
57			`output wire [(BUSW-1):0] o_wb_data;`
58			`//`
59			`input i_wb_ack, i_wb_stall;`
60			`input [(BUSW-1):0] i_wb_data;`
61	3	dgisselq	`//`
62			`// Is the (data) memory unit also requesting access to the bus?`
63			`input i_wb_request;`
64	2	dgisselq
65			`// Fixed bus outputs: we read from the bus only, never write.`
66			`// Thus the output data is ... irrelevant and don't care. We set it`
67			`// to zero just to set it to something.`
68			`assign o_wb_we = 1'b0;`
69			`assign o_wb_data = 0;`
70
71	3	dgisselq	`reg [(BUSW-1):0] r_cache_base;`
72	2	dgisselq	`reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;`
73			`reg [(BUSW-1):0] cache[0:(CACHELEN-1)];`
74
75	3	dgisselq	`reg [(LGCACHELEN-1):0] r_cache_offset;`
76	2	dgisselq
77			`reg r_addr_set;`
78			`reg [(BUSW-1):0] r_addr;`
79
80			`wire [(BUSW-1):0] bus_nvalid;`
81			`assign bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };`
82
83	3	dgisselq	`// What are some of the conditions for which we need to restart the`
84			`// cache?`
85			`wire w_pc_out_of_bounds;`
86			`assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)`
87			`\|\|(i_pc < r_cache_base)`
88			`\|\|(i_pc >= r_cache_base + CACHELEN)));`
89			`wire w_ran_off_end_of_cache;`
90			`assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)`
91			`\|\|(r_addr >= r_cache_base + CACHELEN)));`
92			`wire w_running_out_of_cache;`
93			`assign w_running_out_of_cache = (r_addr_set)`
94			`&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))`
95			`+ (1<<(LGCACHELEN-1)));`
96	2	dgisselq	`initial r_nvalid = 0;`
97	3	dgisselq	`initial r_cache_base = RESET_ADDRESS;`
98	2	dgisselq	`always @(posedge i_clk)`
99			`begin`
100	18	dgisselq	`if ((i_rst)\|\|(i_clear_cache))`
101	3	dgisselq	`begin`
102	2	dgisselq	`o_wb_cyc <= 1'b0;`
103	18	dgisselq	`o_wb_stb <= 1'b0;`
104	3	dgisselq	`// r_cache_base <= RESET_ADDRESS;`
105			`// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)`
106			`// &&(i_pc >= r_cache_base)`
107			`// &&(i_pc < r_cache_base + bus_nvalid))`
108			`// begin`
109	2	dgisselq	`// The new instruction is in our cache, do nothing`
110			`// with the bus here.`
111	3	dgisselq	`end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))`
112	2	dgisselq	`begin`
113			`// We need to abandon our bus action to start over in`
114			`// a new region, setting up a new cache. This may`
115			`// happen mid cycle while waiting for a result. By`
116			`// dropping o_wb_cyc, we state that we are no longer`
117			`// interested in that result--whatever it might be.`
118			`o_wb_cyc <= 1'b0;`
119			`o_wb_stb <= 1'b0;`
120	3	dgisselq	`end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))`
121			`begin`
122			`// Restart a bus cycle that was interrupted when the`
123			`// data section wanted access to our bus.`
124			`o_wb_cyc <= 1'b1;`
125			`o_wb_stb <= 1'b1;`
126			`// o_wb_addr <= r_cache_base + bus_nvalid;`
127	2	dgisselq	`end else if ((~o_wb_cyc)&&(`
128	3	dgisselq	`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
129	2	dgisselq	`begin`
130			`// Start a bus transaction`
131			`o_wb_cyc <= 1'b1;`
132			`o_wb_stb <= 1'b1;`
133	3	dgisselq	`// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;`
134			`// r_nvalid <= 0;`
135			`// r_cache_base <= (i_new_pc) ? i_pc : r_addr;`
136			`// r_cache_offset <= 0;`
137			`end else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
138	2	dgisselq	`begin`
139			`// If we're using the last quarter of the cache, then`
140			`// let's start a bus transaction to extend the cache.`
141			`o_wb_cyc <= 1'b1;`
142			`o_wb_stb <= 1'b1;`
143	3	dgisselq	`// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));`
144			`// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));`
145			`// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));`
146			`// r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));`
147	2	dgisselq	`end else if (o_wb_cyc)`
148			`begin`
149			`// This handles everything ... but the case where`
150			`// while reading we need to extend our cache.`
151			`if ((o_wb_stb)&&(~i_wb_stall))`
152			`begin`
153	3	dgisselq	`// o_wb_addr <= o_wb_addr + 1;`
154			`if ((o_wb_addr - r_cache_base >= CACHELEN-1)`
155			`\|\|(i_wb_request))`
156	2	dgisselq	`o_wb_stb <= 1'b0;`
157			`end`
158
159			`if (i_wb_ack)`
160			`begin`
161	3	dgisselq	`// r_nvalid <= r_nvalid + 1;`
162	2	dgisselq	`if ((r_acks_waiting == 1)&&(~o_wb_stb))`
163			`o_wb_cyc <= 1'b0;`
164			`end`
165			`end`
166			`end`
167
168	3	dgisselq	`always @(posedge i_clk)`
169	18	dgisselq	`if ((i_rst)\|\|(i_clear_cache)) // Required, so we can reload memoy and then reset`
170	11	dgisselq	`r_nvalid <= 0;`
171			`else if ((~o_wb_cyc)&&(`
172	3	dgisselq	`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
173			`r_nvalid <= 0;`
174			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
175			`r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));`
176			`else if ((o_wb_cyc)&&(i_wb_ack))`
177			`r_nvalid <= r_nvalid+1;`
178
179			`always @(posedge i_clk)`
180	18	dgisselq	`if (i_clear_cache)`
181			`r_cache_base <= i_pc;`
182			`else if ((~o_wb_cyc)&&(`
183			`(w_pc_out_of_bounds)`
184			`\|\|(w_ran_off_end_of_cache)))`
185	3	dgisselq	`r_cache_base <= (i_new_pc) ? i_pc : r_addr;`
186			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
187			`r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));`
188
189			`always @(posedge i_clk)`
190	18	dgisselq	`if (i_clear_cache)`
191	3	dgisselq	`r_cache_offset <= 0;`
192	18	dgisselq	`else if ((~o_wb_cyc)&&(`
193			`(w_pc_out_of_bounds)`
194			`\|\|(w_ran_off_end_of_cache)))`
195			`r_cache_offset <= 0;`
196	3	dgisselq	`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
197			`r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));`
198
199			`always @(posedge i_clk)`
200	18	dgisselq	`if (i_clear_cache)`
201			`o_wb_addr <= i_pc;`
202			`else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)`
203	3	dgisselq	`\|\|(w_ran_off_end_of_cache)))`
204			`o_wb_addr <= (i_new_pc) ? i_pc : r_addr;`
205			`else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))`
206			`o_wb_addr <= o_wb_addr + 1;`
207
208			`initial r_acks_waiting = 0;`
209			`always @(posedge i_clk)`
210			`if (~o_wb_cyc)`
211			`r_acks_waiting <= 0;`
212			`else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))`
213			`r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);`
214			`else if ((i_wb_ack)&&((~o_wb_stb)\|\|(i_wb_stall)))`
215			`r_acks_waiting <= r_acks_waiting - 1;`
216
217			`always @(posedge i_clk)`
218			`if ((o_wb_cyc)&&(i_wb_ack))`
219			`cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]`
220			`<= i_wb_data;`
221
222	2	dgisselq	`initial r_addr_set = 1'b0;`
223			`always @(posedge i_clk)`
224	18	dgisselq	`if ((i_rst)\|\|(i_clear_cache))`
225	2	dgisselq	`r_addr_set <= 1'b0;`
226			`else if (i_new_pc)`
227			`r_addr_set <= 1'b1;`
228
229			`// Now, read from the cache`
230			`wire w_cv; // Cache valid, address is in the cache`
231			`reg r_cv;`
232			`assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)`
233			`&&(r_addr-r_cache_base < bus_nvalid));`
234			`always @(posedge i_clk)`
235			`r_cv <= (~i_new_pc)&&(w_cv);`
236			`assign o_v = (r_cv)&&(~i_new_pc);`
237
238			`always @(posedge i_clk)`
239			`if (i_new_pc)`
240			`r_addr <= i_pc;`
241			`else if ((i_stall_n)&&(w_cv))`
242			`r_addr <= r_addr + 1;`
243
244			`wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;`
245			`assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];`
246	3	dgisselq	`assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;`
247	2	dgisselq	`always @(posedge i_clk)`
248			`if (i_stall_n)`
249			`o_i <= cache[c_rdaddr];`
250			`always @(posedge i_clk)`
251			`if (i_stall_n)`
252			`o_pc <= r_addr;`
253
254			`endmodule`

Browse

Tools

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Blame information for rev 18