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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipemem.v] - Blame information for rev 63

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1 49 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    pipemem.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     A memory unit to support a CPU, this time one supporting
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//              pipelined wishbone memory accesses.  The goal is to be able
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//      to issue one pipelined wishbone access per clock, and (given the memory
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//      is fast enough) to be able to read the results back at one access per
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//      clock.  This renders on-chip memory fast enough to handle single cycle
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//      (pipelined) access.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  pipemem(i_clk, i_rst, i_pipe_stb,
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                i_op, i_addr, i_data, i_oreg,
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                        o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
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                o_wb_cyc_gbl, o_wb_cyc_lcl,
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                        o_wb_stb_gbl, o_wb_stb_lcl,
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                        o_wb_we, o_wb_addr, o_wb_data,
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                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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        parameter       ADDRESS_WIDTH = 24, AW=ADDRESS_WIDTH;
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        input                   i_clk, i_rst;
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        input                   i_pipe_stb;
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        // CPU interface
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        input                   i_op;
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        input           [31:0]   i_addr;
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        input           [31:0]   i_data;
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        input           [4:0]    i_oreg;
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        // CPU outputs
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        output  wire            o_busy;
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        output  wire            o_pipe_stalled;
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        output  reg             o_valid;
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        output  reg             o_err;
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        output  reg     [4:0]    o_wreg;
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        output  reg     [31:0]   o_result;
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        // Wishbone outputs
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        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
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        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
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        output  reg     [(AW-1):0]       o_wb_addr;
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        output  reg     [31:0]   o_wb_data;
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        // Wishbone inputs
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        input                   i_wb_ack, i_wb_stall, i_wb_err;
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        input           [31:0]   i_wb_data;
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        reg     [3:0]            rdaddr, wraddr;
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        wire    [3:0]            nxt_rdaddr;
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        reg     [(5-1):0]        fifo_oreg [0:15];
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        initial rdaddr = 0;
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        initial wraddr = 0;
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        always @(posedge i_clk)
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                fifo_oreg[wraddr] <= i_oreg;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_wb_err))
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                        wraddr <= 0;
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                else if (i_pipe_stb)
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                        wraddr <= wraddr + 4'h1;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_wb_err))
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                        rdaddr <= 0;
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                else if ((i_wb_ack)&&(cyc))
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                        rdaddr <= rdaddr + 4'h1;
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        assign  nxt_rdaddr = rdaddr + 4'h1;
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        reg     cyc;
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        wire    gbl_stb, lcl_stb;
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        assign  lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
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        assign  gbl_stb = (~lcl_stb);
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                        //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
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        initial cyc = 0;
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        initial o_wb_cyc_lcl = 0;
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        initial o_wb_cyc_gbl = 0;
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        always @(posedge i_clk)
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                if (i_rst)
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                begin
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                        o_wb_cyc_gbl <= 1'b0;
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                        o_wb_cyc_lcl <= 1'b0;
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                        o_wb_stb_gbl <= 1'b0;
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                        o_wb_stb_lcl <= 1'b0;
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                        cyc <= 1'b0;
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                end else if (cyc)
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                begin
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                        if ((~i_wb_stall)&&(~i_pipe_stb))
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                        begin
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                                o_wb_stb_gbl <= 1'b0;
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                                o_wb_stb_lcl <= 1'b0;
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                        // end else if ((i_pipe_stb)&&(~i_wb_stall))
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                        // begin
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                                // o_wb_addr <= i_addr[(AW-1):0];
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                                // o_wb_data <= i_data;
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                        end
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                        if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
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                        begin
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                                o_wb_cyc_gbl <= 1'b0;
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                                o_wb_cyc_lcl <= 1'b0;
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                                cyc <= 1'b0;
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                        end
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                end else if (i_pipe_stb) // New memory operation
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                begin // Grab the wishbone
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                        o_wb_cyc_lcl <= lcl_stb;
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                        o_wb_cyc_gbl <= gbl_stb;
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                        o_wb_stb_lcl <= lcl_stb;
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                        o_wb_stb_gbl <= gbl_stb;
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                        cyc <= 1'b1;
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                        // o_wb_addr <= i_addr[(AW-1):0];
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                        // o_wb_data <= i_data;
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                        // o_wb_we <= i_op
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                end
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        always @(posedge i_clk)
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                if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall))
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                begin
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                        o_wb_addr <= i_addr[(AW-1):0];
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                        o_wb_data <= i_data;
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                end else if ((~cyc)&&(i_pipe_stb))
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                begin
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                        o_wb_addr <= i_addr[(AW-1):0];
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                        o_wb_data <= i_data;
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                end
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        always @(posedge i_clk)
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                if ((i_pipe_stb)&&(~cyc))
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                        o_wb_we   <= i_op;
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        initial o_valid = 1'b0;
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        always @(posedge i_clk)
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                o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
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        initial o_err = 1'b0;
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        always @(posedge i_clk)
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                o_err <= (cyc)&&(i_wb_err);
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        assign  o_busy = cyc;
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        always @(posedge i_clk)
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                o_wreg <= fifo_oreg[rdaddr];
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        always @(posedge i_clk)
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                if (i_wb_ack)
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                        o_result <= i_wb_data;
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        assign  o_pipe_stalled = (cyc)
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                        &&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
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endmodule

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