OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Blame information for rev 36

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    prefetch.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is a very simple instruction fetch approach.  It gets
8
//              one instruction at a time.  Future versions should pipeline
9
//              fetches and perhaps even cache results--this doesn't do that.
10
//              It should, however, be simple enough to get things running.
11
//
12
//              The interface is fascinating.  The 'i_pc' input wire is just
13
//              a suggestion of what to load.  Other wires may be loaded
14
//              instead. i_pc is what must be output, not necessarily input.
15
//
16 36 dgisselq
//      20150919 -- Added support for the WB error signal.  When reading an
17
//              instruction results in this signal being raised, the pipefetch
18
//              module will set an illegal instruction flag to be returned to
19
//              the CPU together with the instruction.  Hence, the ZipCPU
20
//              can trap on it if necessary.
21
//
22 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
23
//              Gisselquist Tecnology, LLC
24
//
25
////////////////////////////////////////////////////////////////////////////////
26
//
27
// Copyright (C) 2015, Gisselquist Technology, LLC
28
//
29
// This program is free software (firmware): you can redistribute it and/or
30
// modify it under the terms of  the GNU General Public License as published
31
// by the Free Software Foundation, either version 3 of the License, or (at
32
// your option) any later version.
33
//
34
// This program is distributed in the hope that it will be useful, but WITHOUT
35
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
36
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
37
// for more details.
38
//
39
// License:     GPL, v3, as defined and found on www.gnu.org,
40
//              http://www.gnu.org/licenses/gpl.html
41
//
42
//
43
////////////////////////////////////////////////////////////////////////////////
44
//
45
// Flash requires a minimum of 4 clocks per byte to read, so that would be
46
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
47
// mode which this prefetch does not support.  In non--pipelined mode, the
48
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
49
// or 72 clocks to fetch one instruction.
50
module  prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
51 36 dgisselq
                        o_i, o_pc, o_aux, o_valid, o_illegal,
52 2 dgisselq
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
53 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
54 2 dgisselq
        parameter               AW = 1;
55
        input                   i_clk, i_rst, i_ce;
56
        input           [31:0]   i_pc;
57
        input   [(AW-1):0]       i_aux;
58
        output  reg     [31:0]   o_i;
59
        output  reg     [31:0]   o_pc;
60
        output  reg [(AW-1):0]   o_aux;
61 36 dgisselq
        output  wire            o_valid, o_illegal;
62 2 dgisselq
        // Wishbone outputs
63
        output  reg             o_wb_cyc, o_wb_stb;
64
        output  wire            o_wb_we;
65
        output  reg     [31:0]   o_wb_addr;
66
        output  wire    [31:0]   o_wb_data;
67
        // And return inputs
68 36 dgisselq
        input                   i_wb_ack, i_wb_stall, i_wb_err;
69 2 dgisselq
        input           [31:0]   i_wb_data;
70
 
71
        assign  o_wb_we = 1'b0;
72
        assign  o_wb_data = 32'h0000;
73
 
74
        // Let's build it simple and upgrade later: For each instruction
75
        // we do one bus cycle to get the instruction.  Later we should
76
        // pipeline this, but for now let's just do one at a time.
77
        initial o_wb_cyc = 1'b0;
78
        initial o_wb_stb = 1'b0;
79
        initial o_wb_addr= 0;
80
        always @(posedge i_clk)
81
                if (i_rst)
82
                begin
83
                        o_wb_cyc <= 1'b0;
84
                        if (o_wb_cyc)
85
                                o_wb_addr <= 0;
86
                end else if ((i_ce)&&(~o_wb_cyc)&&(o_wb_addr == i_pc))
87
                begin // Single value cache check
88
                        o_aux   <= i_aux;
89
                        // o_i was already set during the last bus cycle
90
                end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
91
                begin
92
                        o_wb_cyc <= 1'b1;
93
                        o_wb_stb <= 1'b1;
94
                        o_wb_addr <= i_pc;
95
                        o_aux   <= i_aux;
96
                end else if (o_wb_cyc) // Independent of ce
97
                begin
98
                        if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
99
                                o_wb_stb <= 1'b0;
100
                        if (i_wb_ack)
101
                                o_wb_cyc <= 1'b0;
102
                end
103
 
104
        always @(posedge i_clk)
105
                if ((o_wb_cyc)&&(i_wb_ack))
106
                        o_i <= i_wb_data;
107
        always @(posedge i_clk)
108
                if ((o_wb_cyc)&&(i_wb_ack))
109
                        o_pc <= o_wb_addr;
110
 
111
        assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc);
112 36 dgisselq
        assign o_illegal = (o_wb_cyc)&&(i_wb_err);
113 2 dgisselq
 
114
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.