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[/] [zipcpu/] [trunk/] [rtl/] [core/] [slowmpy.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    slowmpy.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is a signed (OPT_SIGNED=1) or unsigned (OPT_SIGNED=0)
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//              multiply designed for low logic and slow data signals.  It
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//      takes one clock per bit plus two more to complete the multiply.
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//
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//      The OPT_SIGNED version of this algorithm was found on Wikipedia at
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//      https://en.wikipedia.org/wiki/Binary_multiplier.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2018-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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//
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module  slowmpy(i_clk, i_reset, i_stb, i_a, i_b, i_aux, o_busy,
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                o_done, o_p, o_aux);
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        parameter                       LGNA = 6;
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        parameter       [LGNA:0] NA = 33;
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        parameter       [0:0]             OPT_SIGNED = 1'b1;
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        localparam      NB = NA;        // Must be = NA for OPT_SIGNED to work
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        //
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        input   wire    i_clk, i_reset;
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        //
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        input   wire    i_stb;
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        input   wire    signed  [(NA-1):0]       i_a;
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        input   wire    signed  [(NB-1):0]       i_b;
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        input   wire                            i_aux;
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        output  reg                             o_busy, o_done;
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        output  reg     signed  [(NA+NB-1):0]    o_p;
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        output  reg                             o_aux;
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        reg     [LGNA-1:0]       count;
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        reg     [NA-1:0] p_a;
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        reg     [NB-1:0] p_b;
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        reg     [NA+NB-1:0]      partial;
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        reg                     aux;
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        reg     almost_done;
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        wire    pre_done;
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        assign  pre_done = (count == 0);
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        initial almost_done = 1'b0;
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        always @(posedge i_clk)
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                almost_done <= (!i_reset)&&(o_busy)&&(pre_done);
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        initial aux    = 0;
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        initial o_done = 0;
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        initial o_busy = 0;
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        always @(posedge i_clk)
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        if (i_reset)
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        begin
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                aux    <= 0;
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                o_done <= 0;
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                o_busy <= 0;
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        end else if ((!o_busy)&&(i_stb))
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        begin
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                o_done <= 0;
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                o_busy <= 1;
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                aux    <= i_aux;
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        end else if ((o_busy)&&(almost_done))
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        begin
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                o_done <= 1;
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                o_busy <= 0;
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        end else
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                o_done <= 0;
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        wire    [NA-1:0] pwire;
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        assign  pwire = (p_b[0] ? p_a : 0);
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        always @(posedge i_clk)
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        if (!o_busy)
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        begin
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                count <= NA[LGNA-1:0]-1;
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                partial <= 0;
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                p_a <= i_a;
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                p_b <= i_b;
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        end else begin
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                p_b <= (p_b >> 1);
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                // partial[NA+NB-1:NB] <= partial[NA+NB
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                partial[NB-2:0] <= partial[NB-1:1];
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                if ((OPT_SIGNED)&&(pre_done))
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                        partial[NA+NB-1:NB-1] <= { 1'b0, partial[NA+NB-1:NB]} +
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                                { 1'b0, pwire[NA-1], ~pwire[NA-2:0] };
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                else if (OPT_SIGNED)
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                        partial[NA+NB-1:NB-1] <= {1'b0,partial[NA+NB-1:NB]} +
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                                { 1'b0, !pwire[NA-1], pwire[NA-2:0] };
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                else
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                        partial[NA+NB-1:NB-1] <= {1'b0, partial[NA+NB-1:NB]}
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                                + ((p_b[0]) ? {1'b0,p_a} : 0);
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                count <= count - 1;
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        end
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        always @(posedge i_clk)
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        if (almost_done)
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        begin
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                if (OPT_SIGNED)
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                        o_p   <= partial[NA+NB-1:0]
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                                + {1'b1,{(NA-2){1'b0}},1'b1, {(NB){1'b0}}};
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                else
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                        o_p   <= partial[NA+NB-1:0];
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                o_aux <= aux;
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        end
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`ifdef  FORMAL
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`define ASSERT  assert
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`ifdef  SLOWMPY
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`define ASSUME  assume
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`else
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`define ASSUME  assert
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`endif
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        reg     f_past_valid;
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        initial f_past_valid = 1'b0;
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        always @(posedge i_clk)
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                f_past_valid <= 1'b1;
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        initial assume(i_reset);
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        always @(*)
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        if (!f_past_valid)
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                `ASSUME(i_reset);
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        always @(posedge i_clk)
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        if ((!f_past_valid)||($past(i_reset)))
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        begin
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                `ASSERT(almost_done == 0);
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                `ASSERT(o_done == 0);
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                `ASSERT(o_busy == 0);
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                `ASSERT(aux == 0);
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        end
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        // Assumptions about our inputs
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(i_reset))&&($past(i_stb))&&($past(o_busy)))
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        begin
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                `ASSUME(i_stb);
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                `ASSUME($stable(i_a));
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                `ASSUME($stable(i_b));
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        end
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        //
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        // For now, just formally verify our internal signaling
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        //
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        always @(posedge i_clk)
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                `ASSERT(almost_done == (o_busy&&(&count)));
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        always @(*)
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                if (!(&count[LGNA-1:1])||(count[0]))
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                        `ASSERT(!o_done);
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        always @(posedge i_clk)
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        if (o_done)
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                `ASSERT(!o_busy);
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        always @(posedge i_clk)
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        if (!o_busy)
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                `ASSERT(!almost_done);
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        reg     [NA-1:0] f_a, f_b;
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        always @(posedge i_clk)
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        if ((i_stb)&&(!o_busy))
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        begin
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                f_a <= i_a;
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                f_b <= i_b;
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        end
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        always @(*)
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        if (o_done)
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        begin
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                if ((f_a == 0)||(f_b == 0))
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                        `ASSERT(o_p == 0);
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                else
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                        `ASSERT(o_p[NA+NB-1] == f_a[NA-1] ^ f_b[NA-1]);
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        end
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        always @(posedge i_clk)
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                cover(o_done);
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        reg     f_past_done;
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        initial f_past_done = 1'b0;
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        always @(posedge i_clk)
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        if (o_done)
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                f_past_done = 1'b1;
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        always @(posedge i_clk)
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                cover((o_done)&&(f_past_done));
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`endif
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endmodule

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