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///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, there are only 16 instruction types supported.
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory. 
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//
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//              2. Instruction Decode
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//
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//              3. Read Operands
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//
25
//              4. Apply Instruction
26
//
27
//              4. Write-back Results
28
//
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//      Further information about the inner workings of this CPU may be
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//      found in the spec.pdf file.  (The documentation within this file
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//      had become out of date and out of sync with the spec.pdf, so look
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//      to the spec.pdf for accurate and up to date information.)
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//
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//
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//      In general, the pipelining is controlled by three pieces of logic
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//      per stage: _ce, _stall, and _valid.  _valid means that the stage
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//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
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//      The difference between these control signals allows individual stages
41
//      to propagate instructions independently.  In general, the logic works
42
//      as:
43
//
44
//
45
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
46
//
47
//
48
//      always @(posedge i_clk)
49
//              if ((i_rst)||(clear_pipeline))
50
//                      (n)_valid = 0
51
//              else if (n)_ce
52
//                      (n)_valid = 1
53
//              else if (n+1)_ce
54
//                      (n)_valid = 0
55
//
56
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
57
//                      || (  (n)_valid && (n+1)_stall );
58
//
59
//      and ...
60
//
61
//      always @(posedge i_clk)
62
//              if (n)_ce
63
//                      (n)_variable = ... whatever logic for this stage
64
//
65
//      Note that a stage can stall even if no instruction is loaded into
66
//      it.
67
//
68
//
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// Creator:     Dan Gisselquist, Ph.D.
70 69 dgisselq
//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
73
//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
85
//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
88
//
89
//
90
///////////////////////////////////////////////////////////////////////////////
91
//
92 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
93
// fetches are more complicated and therefore use more FPGA resources, while
94
// single fetches will cause the CPU to stall for about 5 stalls each 
95
// instruction cycle, effectively reducing the instruction count per clock to
96
// about 0.2.  However, the area cost may be worth it.  Consider:
97
//
98
//      Slice LUTs              ZipSystem       ZipCPU
99
//      Single Fetching         2521            1734
100
//      Pipelined fetching      2796            2046
101
//
102
//
103
//
104 25 dgisselq
`define CPU_CC_REG      4'he
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`define CPU_PC_REG      4'hf
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`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
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`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
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// Compile time defines
116 56 dgisselq
//
117
`include "cpudefs.v"
118
//
119 65 dgisselq
//
120 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
122 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
125
                // CPU interface to the wishbone bus
126 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
128
                        o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_data,
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                        i_wb_err,
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                // Accounting/CPU usage interface
132 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
137 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
138 69 dgisselq
                        LGICACHE=6;
139 56 dgisselq
`ifdef  OPT_MULTIPLY
140 132 dgisselq
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
141 56 dgisselq
`else
142
        parameter       IMPLEMENT_MPY = 0;
143
`endif
144 71 dgisselq
`ifdef  OPT_DIVIDE
145
        parameter       IMPLEMENT_DIVIDE = 1;
146
`else
147
        parameter       IMPLEMENT_DIVIDE = 0;
148
`endif
149
`ifdef  OPT_IMPLEMENT_FPU
150
        parameter       IMPLEMENT_FPU = 1,
151
`else
152
        parameter       IMPLEMENT_FPU = 0,
153
`endif
154 69 dgisselq
                        IMPLEMENT_LOCK=1;
155
`ifdef  OPT_EARLY_BRANCHING
156
        parameter       EARLY_BRANCHING = 1;
157
`else
158
        parameter       EARLY_BRANCHING = 0;
159
`endif
160
        parameter       AW=ADDRESS_WIDTH;
161 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
162
        // Debug interface -- inputs
163 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
164 2 dgisselq
        input           [4:0]    i_dbg_reg;
165
        input                   i_dbg_we;
166
        input           [31:0]   i_dbg_data;
167
        // Debug interface -- outputs
168
        output  reg             o_dbg_stall;
169
        output  reg     [31:0]   o_dbg_reg;
170 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
171 2 dgisselq
        output  wire            o_break;
172
        // Wishbone interface -- outputs
173 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
174
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
175 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
176
        output  wire    [31:0]   o_wb_data;
177 2 dgisselq
        // Wishbone interface -- inputs
178
        input                   i_wb_ack, i_wb_stall;
179
        input           [31:0]   i_wb_data;
180 36 dgisselq
        input                   i_wb_err;
181 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
182 9 dgisselq
        output  wire            o_op_stall;
183 2 dgisselq
        output  wire            o_pf_stall;
184 9 dgisselq
        output  wire            o_i_count;
185 56 dgisselq
        //
186 65 dgisselq
`ifdef  DEBUG_SCOPE
187 56 dgisselq
        output  reg     [31:0]   o_debug;
188 65 dgisselq
`endif
189 2 dgisselq
 
190 25 dgisselq
 
191 2 dgisselq
        // Registers
192 56 dgisselq
        //
193
        //      The distributed RAM style comment is necessary on the
194
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
195
        // set and in the process ruining everything else.  It basically
196
        // optimizes logic away, to where it no longer works.  The logic
197
        // as described herein will work, this just makes sure XST implements
198
        // that logic.
199
        //
200
        (* ram_style = "distributed" *)
201 2 dgisselq
        reg     [31:0]   regset [0:31];
202 9 dgisselq
 
203
        // Condition codes
204 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
205
        reg     [3:0]    flags, iflags;
206 83 dgisselq
        wire    [13:0]   w_uflags, w_iflags;
207 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
208 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
209 65 dgisselq
        reg             ill_err_u, ill_err_i;
210 38 dgisselq
`else
211 65 dgisselq
        wire            ill_err_u, ill_err_i;
212 36 dgisselq
`endif
213 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
214 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
215
        wire            ifpu_err_flag, ufpu_err_flag;
216
        wire            ihalt_phase, uhalt_phase;
217 2 dgisselq
 
218 9 dgisselq
        // The master chip enable
219
        wire            master_ce;
220 2 dgisselq
 
221
        //
222
        //
223
        //      PIPELINE STAGE #1 :: Prefetch
224
        //              Variable declarations
225
        //
226 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
227 69 dgisselq
        reg     new_pc;
228 18 dgisselq
        wire    clear_pipeline;
229 69 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
230 9 dgisselq
 
231
        wire            dcd_stalled;
232 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
233 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
234
        wire    [31:0]           pf_data;
235
        wire    [31:0]           instruction;
236
        wire    [(AW-1):0]       instruction_pc;
237 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
238 2 dgisselq
 
239
        //
240
        //
241
        //      PIPELINE STAGE #2 :: Instruction Decode
242
        //              Variable declarations
243
        //
244
        //
245 83 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu;
246 69 dgisselq
        reg             opvalid_div, opvalid_fpu;
247
        wire            op_stall, dcd_ce, dcd_phase;
248
        wire    [3:0]    dcdOp;
249
        wire    [4:0]    dcdA, dcdB, dcdR;
250
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
251
        wire    [3:0]    dcdF;
252
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
253
                                dcdALU, dcdM, dcdDV, dcdFP,
254 71 dgisselq
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
255 105 dgisselq
                                dcd_pipe, dcd_ljmp;
256 69 dgisselq
        reg             r_dcdvalid;
257
        wire            dcdvalid;
258
        wire    [(AW-1):0]       dcd_pc;
259
        wire    [31:0]   dcdI;
260
        wire            dcd_zI; // true if dcdI == 0
261 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
262
 
263 69 dgisselq
        wire    dcd_illegal;
264
        wire                    dcd_early_branch;
265 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
266 2 dgisselq
 
267
 
268
        //
269
        //
270
        //      PIPELINE STAGE #3 :: Read Operands
271
        //              Variable declarations
272
        //
273
        //
274
        //
275
        // Now, let's read our operands
276
        reg     [4:0]    alu_reg;
277
        reg     [3:0]    opn;
278
        reg     [4:0]    opR;
279 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
280
        reg     [(AW-1):0]       op_pc;
281 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
282 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
283 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
284 83 dgisselq
        wire    [13:0]   opFl;
285 56 dgisselq
        reg     [5:0]    r_opF;
286
        wire    [7:0]    opF;
287 132 dgisselq
        wire            op_ce, op_phase, op_pipe;
288 56 dgisselq
        // Some pipeline control wires
289 69 dgisselq
`ifdef  OPT_PIPELINED
290 56 dgisselq
        reg     opA_alu, opA_mem;
291
        reg     opB_alu, opB_mem;
292
`endif
293 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
294 36 dgisselq
        reg     op_illegal;
295
`endif
296 69 dgisselq
        reg     op_break;
297
        wire    op_lock;
298 2 dgisselq
 
299
 
300
        //
301
        //
302
        //      PIPELINE STAGE #4 :: ALU / Memory
303
        //              Variable declarations
304
        //
305
        //
306 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
307 145 dgisselq
        reg             r_alu_pc_valid, mem_pc_valid;
308
        wire            alu_pc_valid;
309 69 dgisselq
        wire            alu_phase;
310 2 dgisselq
        wire            alu_ce, alu_stall;
311
        wire    [31:0]   alu_result;
312
        wire    [3:0]    alu_flags;
313 71 dgisselq
        wire            alu_valid, alu_busy;
314 2 dgisselq
        wire            set_cond;
315
        reg             alu_wr, alF_wr, alu_gie;
316 56 dgisselq
        wire            alu_illegal_op;
317 38 dgisselq
        wire            alu_illegal;
318 2 dgisselq
 
319
 
320
 
321
        wire    mem_ce, mem_stalled;
322 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
323
        wire    mem_pipe_stalled;
324
`endif
325 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
326
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
327 48 dgisselq
        wire    [4:0]            mem_wreg;
328 9 dgisselq
 
329 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
330
        wire    [(AW-1):0]       mem_addr;
331
        wire    [31:0]           mem_data, mem_result;
332 2 dgisselq
 
333 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
334
        wire    [31:0]   div_result;
335
        wire    [3:0]    div_flags;
336 2 dgisselq
 
337 69 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
338
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
339
                                &&(set_cond);
340 2 dgisselq
 
341 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
342
        wire    [31:0]   fpu_result;
343
        wire    [3:0]    fpu_flags;
344
 
345
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
346
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
347
                                &&(set_cond);
348
 
349
 
350 2 dgisselq
        //
351
        //
352
        //      PIPELINE STAGE #5 :: Write-back
353
        //              Variable declarations
354
        //
355 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
356 2 dgisselq
        wire    [4:0]    wr_reg_id;
357
        wire    [31:0]   wr_reg_vl;
358
        wire    w_switch_to_interrupt, w_release_from_interrupt;
359 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
360 2 dgisselq
 
361
 
362
 
363
        //
364
        //      MASTER: clock enable.
365
        //
366 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
367 2 dgisselq
 
368
 
369
        //
370
        //      PIPELINE STAGE #1 :: Prefetch
371
        //              Calculate stall conditions
372 65 dgisselq
        //
373
        //      These are calculated externally, within the prefetch module.
374
        //
375 2 dgisselq
 
376
        //
377
        //      PIPELINE STAGE #2 :: Instruction Decode
378
        //              Calculate stall conditions
379 69 dgisselq
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
380 145 dgisselq
 
381 69 dgisselq
`ifdef  OPT_PIPELINED
382
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
383
`else
384
        // If not pipelined, there will be no opvalid_ anything, and the
385
        // op_stall will be false, dcdX_stall will be false, thus we can simply
386
        // do a ...
387
        assign          dcd_stalled = 1'b0;
388
`endif
389 2 dgisselq
        //
390
        //      PIPELINE STAGE #3 :: Read Operands
391
        //              Calculate stall conditions
392 69 dgisselq
        wire    op_lock_stall;
393
`ifdef  OPT_PIPELINED
394
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
395
                        // Stall if we're stopped, and not allowed to execute
396
                        // an instruction
397
                        // (~master_ce)         // Already captured in alu_stall
398
                        //
399 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
400
                        //      i.e. if the memory is busy, or we are single
401 69 dgisselq
                        //      stepping.  This also includes our stalls for
402
                        //      op_break and op_lock, so we don't need to
403
                        //      include those as well here.
404 83 dgisselq
                        // This also includes whether or not the divide or
405
                        // floating point units are busy.
406
                        (alu_stall)
407 56 dgisselq
                        //
408
                        // Stall if we are going into memory with an operation
409
                        //      that cannot be pipelined, and the memory is
410
                        //      already busy
411 83 dgisselq
                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
412 69 dgisselq
                        )
413
                        ||(dcdvalid)&&(
414 71 dgisselq
                                // Stall if we need to wait for an operand A
415 69 dgisselq
                                // to be ready to read
416 71 dgisselq
                                (dcdA_stall)
417 69 dgisselq
                                // Likewise for B, also includes logic
418
                                // regarding immediate offset (register must
419
                                // be in register file if we need to add to
420
                                // an immediate)
421
                                ||(dcdB_stall)
422
                                // Or if we need to wait on flags to work on the
423
                                // CC register
424
                                ||(dcdF_stall)
425
                        );
426 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
427 65 dgisselq
`else
428 69 dgisselq
        assign  op_stall = (opvalid)&&(~master_ce);
429 145 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
430 65 dgisselq
`endif
431 2 dgisselq
 
432
        //
433
        //      PIPELINE STAGE #4 :: ALU / Memory
434
        //              Calculate stall conditions
435 36 dgisselq
        //
436
        // 1. Basic stall is if the previous stage is valid and the next is
437
        //      busy.  
438
        // 2. Also stall if the prior stage is valid and the master clock enable
439
        //      is de-selected
440 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
441
        //      since we don't know if it'll put us to sleep or not.
442 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
443
        //      through the ALU.  Break instructions are not allowed through
444
        //      the ALU.
445 69 dgisselq
`ifdef  OPT_PIPELINED
446 71 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
447 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
448
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
449
                                &&(wr_write_cc)) // Case 3
450 69 dgisselq
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
451
                        ||((opvalid)&&(op_break))
452
                        ||(div_busy)||(fpu_busy);
453 71 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
454 69 dgisselq
                                &&(~alu_stall)
455
                                &&(~clear_pipeline);
456
`else
457
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
458
                                ||((opvalid_alu)&&(op_break));
459 145 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
460 69 dgisselq
`endif
461 2 dgisselq
        //
462 65 dgisselq
 
463
        //
464
        // Note: if you change the conditions for mem_ce, you must also change
465
        // alu_pc_valid.
466
        //
467 69 dgisselq
`ifdef  OPT_PIPELINED
468
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
469 71 dgisselq
                        &&(~clear_pipeline);
470 69 dgisselq
`else
471
        // If we aren't pipelined, then no one will be changing what's in the
472
        // pipeline (i.e. clear_pipeline), while our only instruction goes
473
        // through the ... pipeline.
474 145 dgisselq
        //
475
        // However, in hind sight this logic didn't work.  What happens when
476
        // something gets in the pipeline and then (due to interrupt or some
477
        // such) needs to be voided?  Thus we avoid simplification and keep
478
        // what worked here.
479
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
480
                        &&(~clear_pipeline);
481 69 dgisselq
`endif
482 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
483 71 dgisselq
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
484 38 dgisselq
                                (mem_pipe_stalled)
485
                                ||((~op_pipe)&&(mem_busy))
486 69 dgisselq
                                ||(div_busy)
487
                                ||(fpu_busy)
488 38 dgisselq
                                // Stall waiting for flags to be valid
489
                                // Or waiting for a write to the PC register
490
                                // Or CC register, since that can change the
491
                                //  PC as well
492
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
493
                                        &&((wr_write_pc)||(wr_write_cc)))));
494
`else
495 69 dgisselq
`ifdef  OPT_PIPELINED
496 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
497 2 dgisselq
                                (~master_ce)
498
                                // Stall waiting for flags to be valid
499
                                // Or waiting for a write to the PC register
500 25 dgisselq
                                // Or CC register, since that can change the
501
                                //  PC as well
502
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
503 69 dgisselq
`else
504
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
505 38 dgisselq
`endif
506 69 dgisselq
`endif
507 2 dgisselq
 
508
 
509
        //
510
        //
511
        //      PIPELINE STAGE #1 :: Prefetch
512
        //
513
        //
514 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
515 9 dgisselq
        wire            pf_ce;
516
 
517 145 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
518 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
519 145 dgisselq
                        pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
520 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
521 36 dgisselq
                                        pf_valid, pf_illegal,
522
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
523
                                pf_ack, pf_stall, pf_err, i_wb_data);
524 69 dgisselq
 
525
        initial r_dcdvalid = 1'b0;
526
        always @(posedge i_clk)
527 145 dgisselq
                if ((i_rst)||(clear_pipeline))
528 69 dgisselq
                        r_dcdvalid <= 1'b0;
529
                else if (dcd_ce)
530 105 dgisselq
                        r_dcdvalid <= (pf_valid);
531
                else if (op_ce)
532 69 dgisselq
                        r_dcdvalid <= 1'b0;
533
        assign  dcdvalid = r_dcdvalid;
534
 
535 2 dgisselq
`else // Pipe fetch
536 69 dgisselq
 
537
`ifdef  OPT_TRADITIONAL_PFCACHE
538
        pfcache #(LGICACHE, ADDRESS_WIDTH)
539 105 dgisselq
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
540 69 dgisselq
                                        i_clear_pf_cache,
541
                                // dcd_pc,
542
                                ~dcd_stalled,
543 105 dgisselq
                                ((dcd_early_branch)&&(~clear_pipeline))
544 69 dgisselq
                                        ? dcd_branch_pc:pf_pc,
545
                                instruction, instruction_pc, pf_valid,
546
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
547
                                        pf_ack, pf_stall, pf_err, i_wb_data,
548
                                pf_illegal);
549
`else
550 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
551 105 dgisselq
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
552 36 dgisselq
                                        i_clear_pf_cache, ~dcd_stalled,
553
                                        (new_pc)?pf_pc:dcd_branch_pc,
554 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
555
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
556 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
557 69 dgisselq
//`ifdef        OPT_PRECLEAR_BUS
558
                                //((dcd_clear_bus)&&(dcdvalid))
559
                                //||((op_clear_bus)&&(opvalid))
560
                                //||
561
//`endif
562 36 dgisselq
                                (mem_cyc_lcl)||(mem_cyc_gbl),
563
                                pf_illegal);
564 69 dgisselq
`endif
565 2 dgisselq
        assign  instruction_gie = gie;
566
 
567 69 dgisselq
        initial r_dcdvalid = 1'b0;
568 2 dgisselq
        always @(posedge i_clk)
569 69 dgisselq
                if ((i_rst)||(clear_pipeline))
570
                        r_dcdvalid <= 1'b0;
571 2 dgisselq
                else if (dcd_ce)
572 145 dgisselq
                        r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
573 69 dgisselq
                else if (op_ce)
574
                        r_dcdvalid <= 1'b0;
575
        assign  dcdvalid = r_dcdvalid;
576 36 dgisselq
`endif
577 2 dgisselq
 
578 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
579
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
580
                        IMPLEMENT_FPU)
581
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
582
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
583
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
584
                        dcd_illegal, dcd_pc, dcd_gie,
585
                        { dcdR_cc, dcdR_pc, dcdR },
586
                        { dcdA_cc, dcdA_pc, dcdA },
587
                        { dcdB_cc, dcdB_pc, dcdB },
588
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
589
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
590
                        dcdR_wr,dcdA_rd, dcdB_rd,
591
                        dcd_early_branch,
592 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
593 71 dgisselq
                        dcd_pipe);
594 36 dgisselq
`else
595 69 dgisselq
        idecode_deprecated
596
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
597
                        IMPLEMENT_FPU)
598
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
599
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
600
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
601
                        dcd_illegal, dcd_pc, dcd_gie,
602
                        { dcdR_cc, dcdR_pc, dcdR },
603
                        { dcdA_cc, dcdA_pc, dcdA },
604
                        { dcdB_cc, dcdB_pc, dcdB },
605
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
606
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
607
                        dcdR_wr,dcdA_rd, dcdB_rd,
608
                        dcd_early_branch,
609 71 dgisselq
                        dcd_branch_pc,
610
                        dcd_pipe);
611 105 dgisselq
        assign  dcd_ljmp = 1'b0;
612 36 dgisselq
`endif
613 2 dgisselq
 
614 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
615 132 dgisselq
        reg             r_op_pipe;
616 2 dgisselq
 
617 132 dgisselq
        initial r_op_pipe = 1'b0;
618 38 dgisselq
        // To be a pipeable operation, there must be 
619
        //      two valid adjacent instructions
620
        //      Both must be memory instructions
621
        //      Both must be writes, or both must be reads
622
        //      Both operations must be to the same identical address,
623
        //              or at least a single (one) increment above that address
624 71 dgisselq
        //
625
        // However ... we need to know this before this clock, hence this is
626
        // calculated in the instruction decoder.
627 38 dgisselq
        always @(posedge i_clk)
628
                if (op_ce)
629 132 dgisselq
                        r_op_pipe <= dcd_pipe;
630 145 dgisselq
                else if (mem_ce) // Clear us any time an op_ is clocked in
631
                        r_op_pipe <= 1'b0;
632 132 dgisselq
        assign  op_pipe = r_op_pipe;
633
`else
634
        assign  op_pipe = 1'b0;
635 38 dgisselq
`endif
636
 
637 2 dgisselq
        //
638
        //
639
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
640
        //
641
        //
642 25 dgisselq
        assign  w_opA = regset[dcdA];
643
        assign  w_opB = regset[dcdB];
644 56 dgisselq
 
645 132 dgisselq
        wire    [8:0]    w_cpu_info;
646
        assign  w_cpu_info = {
647
`ifdef  OPT_ILLEGAL_INSTRUCTION
648
        1'b1,
649
`else
650
        1'b0,
651
`endif
652
`ifdef  OPT_MULTIPLY
653
        1'b1,
654
`else
655
        1'b0,
656
`endif
657
`ifdef  OPT_DIVIDE
658
        1'b1,
659
`else
660
        1'b0,
661
`endif
662
`ifdef  OPT_IMPLEMENT_FPU
663
        1'b1,
664
`else
665
        1'b0,
666
`endif
667
`ifdef  OPT_PIPELINED
668
        1'b1,
669
`else
670
        1'b0,
671
`endif
672
`ifdef  OPT_TRADITIONAL_CACHE
673
        1'b1,
674
`else
675
        1'b0,
676
`endif
677
`ifdef  OPT_EARLY_BRANCHING
678
        1'b1,
679
`else
680
        1'b0,
681
`endif
682
`ifdef  OPT_PIPELINED_BUS_ACCESS
683
        1'b1,
684
`else
685
        1'b0,
686
`endif
687
`ifdef  OPT_VLIW
688
        1'b1
689
`else
690
        1'b0
691
`endif
692
        };
693
 
694 56 dgisselq
        wire    [31:0]   w_pcA_v;
695
        generate
696
        if (AW < 32)
697
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
698
        else
699
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
700
        endgenerate
701 71 dgisselq
 
702
`ifdef  OPT_PIPELINED
703
        reg     [4:0]    opA_id, opB_id;
704
        reg             opA_rd, opB_rd;
705 2 dgisselq
        always @(posedge i_clk)
706 71 dgisselq
                if (op_ce)
707
                begin
708
                        opA_id <= dcdA;
709
                        opB_id <= dcdB;
710
                        opA_rd <= dcdA_rd;
711
                        opB_rd <= dcdB_rd;
712
                end
713
`endif
714
 
715
        always @(posedge i_clk)
716 2 dgisselq
                if (op_ce) // &&(dcdvalid))
717
                begin
718
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
719
                                r_opA <= wr_reg_vl;
720 25 dgisselq
                        else if (dcdA_pc)
721 56 dgisselq
                                r_opA <= w_pcA_v;
722 25 dgisselq
                        else if (dcdA_cc)
723 132 dgisselq
                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
724 2 dgisselq
                        else
725 25 dgisselq
                                r_opA <= w_opA;
726 69 dgisselq
`ifdef  OPT_PIPELINED
727 71 dgisselq
                end else
728 48 dgisselq
                begin // We were going to pick these up when they became valid,
729
                        // but for some reason we're stuck here as they became
730
                        // valid.  Pick them up now anyway
731 71 dgisselq
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
732
                                // r_opA <= wr_reg_vl;
733
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
734 48 dgisselq
                                r_opA <= wr_reg_vl;
735 56 dgisselq
`endif
736 2 dgisselq
                end
737 56 dgisselq
 
738 69 dgisselq
        wire    [31:0]   w_opBnI, w_pcB_v;
739 56 dgisselq
        generate
740
        if (AW < 32)
741
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
742
        else
743
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
744
        endgenerate
745
 
746 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
747 56 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
748
                : ((dcdB_pc) ? w_pcB_v
749 132 dgisselq
                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
750
                        (dcdB[4])?w_uflags:w_iflags}
751 56 dgisselq
                : w_opB)));
752
 
753 2 dgisselq
        always @(posedge i_clk)
754
                if (op_ce) // &&(dcdvalid))
755 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
756 69 dgisselq
`ifdef  OPT_PIPELINED
757 71 dgisselq
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
758 48 dgisselq
                        r_opB <= wr_reg_vl;
759 56 dgisselq
`endif
760 2 dgisselq
 
761
        // The logic here has become more complex than it should be, no thanks
762
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
763
        // be two sets of four bits: the top bits specify what bits matter, the
764
        // bottom specify what those top bits must equal.  However, two of
765
        // conditions check whether bits are on, and those are the only two
766
        // conditions checking those bits.  Therefore, Vivado complains that
767
        // these two bits are redundant.  Hence the convoluted expression
768
        // below, arriving at what we finally want in the (now wire net)
769
        // opF.
770
        always @(posedge i_clk)
771
                if (op_ce)
772 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
773 2 dgisselq
                        case(dcdF[2:0])
774 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
775 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
776
                        // These were remapped as part of the new instruction
777
                        // set in order to make certain that the low order
778
                        // two bits contained the most commonly used 
779
                        // conditions: Always, LT, Z, and NZ.
780
                        3'h1:   r_opF <= 6'h24; // LT
781
                        3'h2:   r_opF <= 6'h11; // Z
782
                        3'h3:   r_opF <= 6'h10; // NE
783
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
784
                        3'h5:   r_opF <= 6'h20; // GE (!N)
785
`else
786 56 dgisselq
                        3'h1:   r_opF <= 6'h11; // Z
787
                        3'h2:   r_opF <= 6'h10; // NE
788
                        3'h3:   r_opF <= 6'h20; // GE (!N)
789
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
790
                        3'h5:   r_opF <= 6'h24; // LT
791 69 dgisselq
`endif
792 56 dgisselq
                        3'h6:   r_opF <= 6'h02; // C
793
                        3'h7:   r_opF <= 6'h08; // V
794 2 dgisselq
                        endcase
795 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
796 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
797 2 dgisselq
 
798 69 dgisselq
        wire    w_opvalid;
799 105 dgisselq
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
800 36 dgisselq
        initial opvalid     = 1'b0;
801
        initial opvalid_alu = 1'b0;
802
        initial opvalid_mem = 1'b0;
803 91 dgisselq
        initial opvalid_div = 1'b0;
804
        initial opvalid_fpu = 1'b0;
805 2 dgisselq
        always @(posedge i_clk)
806
                if (i_rst)
807 25 dgisselq
                begin
808
                        opvalid     <= 1'b0;
809
                        opvalid_alu <= 1'b0;
810
                        opvalid_mem <= 1'b0;
811
                end else if (op_ce)
812
                begin
813 2 dgisselq
                        // Do we have a valid instruction?
814
                        //   The decoder may vote to stall one of its
815
                        //   instructions based upon something we currently
816
                        //   have in our queue.  This instruction must then
817
                        //   move forward, and get a stall cycle inserted.
818
                        //   Hence, the test on dcd_stalled here.  If we must
819
                        //   wait until our operands are valid, then we aren't
820
                        //   valid yet until then.
821 69 dgisselq
                        opvalid<= w_opvalid;
822 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
823 69 dgisselq
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
824
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
825
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
826
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
827 36 dgisselq
`else
828 69 dgisselq
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
829
                        opvalid_mem <= (dcdM)&&(w_opvalid);
830
                        opvalid_div <= (dcdDV)&&(w_opvalid);
831
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
832 36 dgisselq
`endif
833 69 dgisselq
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
834 25 dgisselq
                begin
835
                        opvalid     <= 1'b0;
836
                        opvalid_alu <= 1'b0;
837
                        opvalid_mem <= 1'b0;
838 69 dgisselq
                        opvalid_div <= 1'b0;
839
                        opvalid_fpu <= 1'b0;
840 25 dgisselq
                end
841 2 dgisselq
 
842
        // Here's part of our debug interface.  When we recognize a break
843
        // instruction, we set the op_break flag.  That'll prevent this
844
        // instruction from entering the ALU, and cause an interrupt before
845
        // this instruction.  Thus, returning to this code will cause the
846
        // break to repeat and continue upon return.  To get out of this
847
        // condition, replace the break instruction with what it is supposed
848
        // to be, step through it, and then replace it back.  In this fashion,
849
        // a debugger can step through code.
850 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
851
        initial op_break = 1'b0;
852 2 dgisselq
        always @(posedge i_clk)
853 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
854
                else if (op_ce) op_break <= (dcd_break);
855
                else if ((clear_pipeline)||(~opvalid))
856
                                op_break <= 1'b0;
857 2 dgisselq
 
858 69 dgisselq
`ifdef  OPT_PIPELINED
859
        generate
860
        if (IMPLEMENT_LOCK != 0)
861
        begin
862
                reg     r_op_lock, r_op_lock_stall;
863
 
864
                initial r_op_lock_stall = 1'b0;
865
                always @(posedge i_clk)
866
                        if (i_rst)
867
                                r_op_lock_stall <= 1'b0;
868
                        else
869
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
870
                                                ||(~dcdvalid)||(~pf_valid);
871
 
872
                assign  op_lock_stall = r_op_lock_stall;
873
 
874
                initial r_op_lock = 1'b0;
875
                always @(posedge i_clk)
876
                        if (i_rst)
877
                                r_op_lock <= 1'b0;
878 132 dgisselq
                        else if (op_ce)
879
                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);
880 69 dgisselq
                assign  op_lock = r_op_lock;
881
 
882
        end else begin
883
                assign  op_lock_stall = 1'b0;
884
                assign  op_lock = 1'b0;
885
        end endgenerate
886
 
887
`else
888
        assign op_lock_stall = 1'b0;
889
        assign op_lock       = 1'b0;
890
`endif
891
 
892 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
893 71 dgisselq
        initial op_illegal = 1'b0;
894 2 dgisselq
        always @(posedge i_clk)
895 71 dgisselq
                if ((i_rst)||(clear_pipeline))
896
                        op_illegal <= 1'b0;
897
                else if(op_ce)
898 69 dgisselq
`ifdef  OPT_PIPELINED
899
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
900
`else
901
                        op_illegal <= (dcd_illegal)||(dcd_lock);
902 36 dgisselq
`endif
903 69 dgisselq
`endif
904 36 dgisselq
 
905 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
906
        // set, dcd_early_branch will simply be a wire connected to zero and
907
        // this logic should just optimize.
908
        always @(posedge i_clk)
909
                if (op_ce)
910
                begin
911 83 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
912
                                &&(~dcd_early_branch)&&(~dcd_illegal);
913
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
914 71 dgisselq
                end
915 69 dgisselq
 
916 36 dgisselq
        always @(posedge i_clk)
917 2 dgisselq
                if (op_ce)
918
                begin
919
                        opn    <= dcdOp;        // Which ALU operation?
920 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
921 2 dgisselq
                        // What register will these results be written into?
922 69 dgisselq
                        opR    <= dcdR;
923
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
924 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
925
                        op_gie <= dcd_gie;
926
 
927 69 dgisselq
 
928 2 dgisselq
                        //
929 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
930 2 dgisselq
                end
931
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
932
 
933 69 dgisselq
`ifdef  OPT_VLIW
934
        reg     r_op_phase;
935
        initial r_op_phase = 1'b0;
936
        always @(posedge i_clk)
937
                if ((i_rst)||(clear_pipeline))
938
                        r_op_phase <= 1'b0;
939
                else if (op_ce)
940
                        r_op_phase <= dcd_phase;
941
        assign  op_phase = r_op_phase;
942
`else
943
        assign  op_phase = 1'b0;
944
`endif
945
 
946 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
947
        // register set but in special registers of their own.  So step one
948
        // is to select the right register.  Step to is to replace that
949
        // register with the results of an ALU or memory operation, if such
950
        // results are now available.  Otherwise, we'd need to insert a wait
951
        // state of some type.
952
        //
953
        // The alternative approach would be to define some sort of
954
        // op_stall wire, which would stall any upstream stage.
955
        // We'll create a flag here to start our coordination.  Once we
956
        // define this flag to something other than just plain zero, then
957
        // the stalls will already be in place.
958 69 dgisselq
`ifdef  OPT_PIPELINED
959 83 dgisselq
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
960 71 dgisselq
                        ?  wr_reg_vl : r_opA;
961 56 dgisselq
`else
962
        assign  opA = r_opA;
963
`endif
964 48 dgisselq
 
965 69 dgisselq
`ifdef  OPT_PIPELINED
966 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
967
        //      AND ... something that may write a register is running
968
        //      AND (series of conditions here ...)
969
        //              The operation might set flags, and we wish to read the
970
        //                      CC register
971
        //              OR ... (No other conditions)
972
        assign  dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
973
                                &&((opvalid)||(mem_rdbusy)
974
                                        ||(div_busy)||(fpu_busy))
975
                                &&((opF_wr)&&(dcdA_cc));
976 56 dgisselq
`else
977 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
978
        assign  dcdA_stall = 1'b0;
979 56 dgisselq
`endif
980 36 dgisselq
 
981 69 dgisselq
`ifdef  OPT_PIPELINED
982 71 dgisselq
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
983
                        ? wr_reg_vl: r_opB;
984 56 dgisselq
`else
985
        assign  opB = r_opB;
986
`endif
987
 
988 69 dgisselq
`ifdef  OPT_PIPELINED
989 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
990
        //      AND ... something that may write a (unknown) register is running
991
        //      AND (series of conditions here ...)
992
        //              The operation might set flags, and we wish to read the
993
        //                      CC register
994
        //              OR the operation might set register B, and we still need
995
        //                      a clock to add the offset to it
996
        assign  dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
997
                                // If the op stage isn't valid, yet something
998
                                // is running, then it must have been valid.
999
                                // We'll use the last values from that stage
1000
                                // (opR_wr, opF_wr, opR) in our logic below.
1001
                                &&((opvalid)||(mem_rdbusy)
1002 132 dgisselq
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
1003 83 dgisselq
                                &&(
1004 145 dgisselq
                                // Okay, what happens if the result register
1005
                                // from instruction 1 becomes the input for
1006
                                // instruction two, *and* there's an immediate
1007
                                // offset in instruction two?  In that case, we
1008
                                // need an extra clock between the two 
1009
                                // instructions to calculate the base plus 
1010
                                // offset.
1011
                                //
1012
                                // What if instruction 1 (or before) is in a
1013
                                // memory pipeline?  We may no longer know what
1014
                                // the register was!  We will then need  to 
1015
                                // blindly wait.  We'll temper this only waiting
1016
                                // if we're not piping this new instruction.
1017
                                // If we were piping, the pipe logic in the
1018
                                // decode circuit has told us that the hazard
1019
                                // is clear, so we're okay then.
1020
                                //
1021 132 dgisselq
                                ((~dcd_zI)&&(
1022
                                        ((opR == dcdB)&&(opR_wr))
1023 145 dgisselq
                                        ||((mem_rdbusy)&&(~dcd_pipe))
1024
                                        ))
1025 83 dgisselq
                                // Stall following any instruction that will
1026
                                // set the flags, if we're going to need the
1027
                                // flags (CC) register for opB.
1028
                                ||((opF_wr)&&(dcdB_cc))
1029 38 dgisselq
                                // Stall on any ongoing memory operation that
1030 71 dgisselq
                                // will write to opB -- captured above
1031
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
1032
                                );
1033 91 dgisselq
        assign  dcdF_stall = ((~dcdF[3])
1034
                                        ||((dcdA_rd)&&(dcdA_cc))
1035
                                        ||((dcdB_rd)&&(dcdB_cc)))
1036
                                        &&(opvalid)&&(opR_cc);
1037
                                // &&(dcdvalid) is checked for elsewhere
1038 56 dgisselq
`else
1039 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
1040
        // hazard without the pipeline?
1041
        assign  dcdB_stall = 1'b0;
1042 91 dgisselq
        assign  dcdF_stall = 1'b0;
1043 56 dgisselq
`endif
1044 2 dgisselq
        //
1045
        //
1046
        //      PIPELINE STAGE #4 :: Apply Instruction
1047
        //
1048
        //
1049 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
1050 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1051 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
1052 71 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op,
1053
                        alu_busy);
1054 69 dgisselq
`else
1055
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1056
                        (opvalid_alu), opn, opA, opB,
1057
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
1058 71 dgisselq
        assign  alu_busy = 1'b0;
1059 69 dgisselq
`endif
1060 2 dgisselq
 
1061 69 dgisselq
        generate
1062
        if (IMPLEMENT_DIVIDE != 0)
1063
        begin
1064 83 dgisselq
                div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
1065 69 dgisselq
                        opA, opB, div_busy, div_valid, div_error, div_result,
1066
                        div_flags);
1067
        end else begin
1068
                assign  div_error = 1'b1;
1069
                assign  div_busy  = 1'b0;
1070
                assign  div_valid = 1'b0;
1071
                assign  div_result= 32'h00;
1072
                assign  div_flags = 4'h0;
1073
        end endgenerate
1074
 
1075
        generate
1076
        if (IMPLEMENT_FPU != 0)
1077
        begin
1078
                //
1079
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1080
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1081
                //      fpu_flags);
1082
                //
1083
                assign  fpu_error = 1'b1;
1084
                assign  fpu_busy  = 1'b0;
1085
                assign  fpu_valid = 1'b0;
1086
                assign  fpu_result= 32'h00;
1087
                assign  fpu_flags = 4'h0;
1088
        end else begin
1089
                assign  fpu_error = 1'b1;
1090
                assign  fpu_busy  = 1'b0;
1091
                assign  fpu_valid = 1'b0;
1092
                assign  fpu_result= 32'h00;
1093
                assign  fpu_flags = 4'h0;
1094
        end endgenerate
1095
 
1096
 
1097 2 dgisselq
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1098
        initial alF_wr   = 1'b0;
1099
        initial alu_wr   = 1'b0;
1100
        always @(posedge i_clk)
1101
                if (i_rst)
1102
                begin
1103
                        alu_wr   <= 1'b0;
1104
                        alF_wr   <= 1'b0;
1105
                end else if (alu_ce)
1106
                begin
1107 65 dgisselq
                        // alu_reg <= opR;
1108 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1109
                        alF_wr  <= (opF_wr)&&(set_cond);
1110 71 dgisselq
                end else if (~alu_busy) begin
1111 2 dgisselq
                        // These are strobe signals, so clear them if not
1112
                        // set for any particular clock
1113 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1114 2 dgisselq
                        alF_wr <= 1'b0;
1115
                end
1116 69 dgisselq
 
1117
`ifdef  OPT_VLIW
1118
        reg     r_alu_phase;
1119
        initial r_alu_phase = 1'b0;
1120 2 dgisselq
        always @(posedge i_clk)
1121 69 dgisselq
                if (i_rst)
1122
                        r_alu_phase <= 1'b0;
1123
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
1124
                        r_alu_phase <= op_phase;
1125
        assign  alu_phase = r_alu_phase;
1126
`else
1127
        assign  alu_phase = 1'b0;
1128
`endif
1129
 
1130
        always @(posedge i_clk)
1131
                if ((alu_ce)||(div_ce)||(fpu_ce))
1132 65 dgisselq
                        alu_reg <= opR;
1133
                else if ((i_halt)&&(i_dbg_we))
1134
                        alu_reg <= i_dbg_reg;
1135 69 dgisselq
 
1136 132 dgisselq
        //
1137
        // DEBUG Register write access starts here
1138
        //
1139 65 dgisselq
        reg             dbgv;
1140
        initial dbgv = 1'b0;
1141
        always @(posedge i_clk)
1142
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
1143 132 dgisselq
        reg     [31:0]   dbg_val;
1144 65 dgisselq
        always @(posedge i_clk)
1145 132 dgisselq
                dbg_val <= i_dbg_data;
1146
        always @(posedge i_clk)
1147 2 dgisselq
                if ((alu_ce)||(mem_ce))
1148
                        alu_gie  <= op_gie;
1149
        always @(posedge i_clk)
1150 65 dgisselq
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1151
                                &&(~mem_stalled)))
1152 2 dgisselq
                        alu_pc  <= op_pc;
1153 65 dgisselq
 
1154 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1155 56 dgisselq
        reg     r_alu_illegal;
1156
        initial r_alu_illegal = 0;
1157 38 dgisselq
        always @(posedge i_clk)
1158 71 dgisselq
                if (clear_pipeline)
1159
                        r_alu_illegal <= 1'b0;
1160
                else if ((alu_ce)||(mem_ce))
1161 56 dgisselq
                        r_alu_illegal <= op_illegal;
1162
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1163 38 dgisselq
`endif
1164
 
1165 145 dgisselq
        initial r_alu_pc_valid = 1'b0;
1166 132 dgisselq
        initial mem_pc_valid = 1'b0;
1167 2 dgisselq
        always @(posedge i_clk)
1168 132 dgisselq
                if (i_rst)
1169 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1170
                else if (alu_ce) // Includes && (~alu_clear_pipeline)
1171
                        r_alu_pc_valid <= 1'b1;
1172
                else if ((~alu_busy)||(clear_pipeline))
1173
                        r_alu_pc_valid <= 1'b0;
1174
        assign  alu_pc_valid = (r_alu_pc_valid)&&(~alu_busy);
1175 132 dgisselq
        always @(posedge i_clk)
1176
                if (i_rst)
1177
                        mem_pc_valid <= 1'b0;
1178
                else
1179
                        mem_pc_valid <= (mem_ce);
1180 2 dgisselq
 
1181 69 dgisselq
        wire    bus_lock;
1182
`ifdef  OPT_PIPELINED
1183
        generate
1184
        if (IMPLEMENT_LOCK != 0)
1185
        begin
1186 132 dgisselq
                reg     [1:0]    r_bus_lock;
1187
                initial r_bus_lock = 2'b00;
1188 69 dgisselq
                always @(posedge i_clk)
1189
                        if (i_rst)
1190 132 dgisselq
                                r_bus_lock <= 2'b00;
1191 69 dgisselq
                        else if ((op_ce)&&(op_lock))
1192 132 dgisselq
                                r_bus_lock <= 2'b11;
1193
                        else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
1194
                                r_bus_lock <= r_bus_lock + 2'b11;
1195
                assign  bus_lock = |r_bus_lock;
1196 69 dgisselq
        end else begin
1197
                assign  bus_lock = 1'b0;
1198
        end endgenerate
1199
`else
1200
        assign  bus_lock = 1'b0;
1201
`endif
1202
 
1203 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1204 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1205 38 dgisselq
                                (opn[0]), opB, opA, opR,
1206
                                mem_busy, mem_pipe_stalled,
1207
                                mem_valid, bus_err, mem_wreg, mem_result,
1208
                        mem_cyc_gbl, mem_cyc_lcl,
1209
                                mem_stb_gbl, mem_stb_lcl,
1210
                                mem_we, mem_addr, mem_data,
1211
                                mem_ack, mem_stall, mem_err, i_wb_data);
1212
 
1213
`else // PIPELINED_BUS_ACCESS
1214 71 dgisselq
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1215 2 dgisselq
                                (opn[0]), opB, opA, opR,
1216 38 dgisselq
                                mem_busy,
1217
                                mem_valid, bus_err, mem_wreg, mem_result,
1218 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1219
                                mem_stb_gbl, mem_stb_lcl,
1220
                                mem_we, mem_addr, mem_data,
1221
                                mem_ack, mem_stall, mem_err, i_wb_data);
1222 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1223 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1224 2 dgisselq
 
1225
        // Either the prefetch or the instruction gets the memory bus, but 
1226
        // never both.
1227 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1228 36 dgisselq
                // Memory access to the arbiter, priority position
1229
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1230
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1231 2 dgisselq
                // Prefetch access to the arbiter
1232 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1233
                        pf_ack, pf_stall, pf_err,
1234 2 dgisselq
                // Common wires, in and out, of the arbiter
1235 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1236
                        o_wb_we, o_wb_addr, o_wb_data,
1237
                        i_wb_ack, i_wb_stall, i_wb_err);
1238 2 dgisselq
 
1239 132 dgisselq
 
1240
 
1241 2 dgisselq
        //
1242
        //
1243 132 dgisselq
        //
1244
        //
1245
        //
1246
        //
1247
        //
1248
        //
1249 2 dgisselq
        //      PIPELINE STAGE #5 :: Write-back results
1250
        //
1251
        //
1252
        // This stage is not allowed to stall.  If results are ready to be
1253
        // written back, they are written back at all cost.  Sleepy CPU's
1254
        // won't prevent write back, nor debug modes, halting the CPU, nor
1255
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1256
        // as knowinig something is available for writeback.
1257
 
1258
        //
1259
        // Write back to our generic register set ...
1260
        // When shall we write back?  On one of two conditions
1261
        //      Note that the flags needed to be checked before issuing the
1262
        //      bus instruction, so they don't need to be checked here.
1263
        //      Further, alu_wr includes (set_cond), so we don't need to
1264
        //      check for that here either.
1265 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1266 132 dgisselq
        assign  wr_reg_ce = (dbgv)||(~alu_illegal)&&
1267 83 dgisselq
                        (((alu_wr)&&(~clear_pipeline)
1268
                                &&((alu_valid)||(div_valid)||(fpu_valid)))
1269
                        ||(mem_valid));
1270 36 dgisselq
`else
1271 132 dgisselq
        assign  wr_reg_ce = (dbgv)||((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
1272 36 dgisselq
`endif
1273 2 dgisselq
        // Which register shall be written?
1274 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1275
        //              One or PC, one for CC, and one for GIE match
1276 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1277
        //      FPU operation.
1278 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1279 25 dgisselq
        // Are we writing to the CC register?
1280
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1281 2 dgisselq
        // Are we writing to the PC?
1282
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1283
        // What value to write?
1284 71 dgisselq
        assign  wr_reg_vl = ((mem_valid) ? mem_result
1285
                                :((div_valid|fpu_valid))
1286
                                        ? ((div_valid) ? div_result:fpu_result)
1287
                                :((dbgv) ? dbg_val : alu_result));
1288 2 dgisselq
        always @(posedge i_clk)
1289
                if (wr_reg_ce)
1290
                        regset[wr_reg_id] <= wr_reg_vl;
1291
 
1292
        //
1293
        // Write back to the condition codes/flags register ...
1294
        // When shall we write to our flags register?  alF_wr already
1295
        // includes the set condition ...
1296 69 dgisselq
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1297 83 dgisselq
        assign  w_uflags = { uhalt_phase, ufpu_err_flag,
1298 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1299
                        1'b0, step, 1'b1, sleep,
1300
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1301 83 dgisselq
        assign  w_iflags = { ihalt_phase, ifpu_err_flag,
1302 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1303
                        break_en, 1'b0, 1'b0, sleep,
1304
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1305 69 dgisselq
 
1306
 
1307 2 dgisselq
        // What value to write?
1308
        always @(posedge i_clk)
1309
                // If explicitly writing the register itself
1310 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1311 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1312
                // Otherwise if we're setting the flags from an ALU operation
1313
                else if ((wr_flags_ce)&&(alu_gie))
1314 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1315
                                : alu_flags);
1316 2 dgisselq
 
1317
        always @(posedge i_clk)
1318 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1319 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1320
                else if ((wr_flags_ce)&&(~alu_gie))
1321 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1322
                                : alu_flags);
1323 2 dgisselq
 
1324
        // The 'break' enable  bit.  This bit can only be set from supervisor
1325
        // mode.  It control what the CPU does upon encountering a break
1326
        // instruction.
1327
        //
1328
        // The goal, upon encountering a break is that the CPU should stop and
1329
        // not execute the break instruction, choosing instead to enter into
1330
        // either interrupt mode or halt first.  
1331
        //      if ((break_en) AND (break_instruction)) // user mode or not
1332
        //              HALT CPU
1333
        //      else if (break_instruction) // only in user mode
1334
        //              set an interrupt flag, go to supervisor mode
1335
        //              allow supervisor to step the CPU.
1336
        //      Upon a CPU halt, any break condition will be reset.  The
1337
        //      external debugger will then need to deal with whatever
1338
        //      condition has taken place.
1339
        initial break_en = 1'b0;
1340
        always @(posedge i_clk)
1341
                if ((i_rst)||(i_halt))
1342
                        break_en <= 1'b0;
1343 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1344 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1345 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1346 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1347
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1348 69 dgisselq
                                &&(~div_busy)&&(~fpu_busy)
1349 36 dgisselq
                                &&(~clear_pipeline)
1350
                        ||((~alu_gie)&&(bus_err))
1351 69 dgisselq
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1352
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
1353 71 dgisselq
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
1354 36 dgisselq
`else
1355
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1356
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1357
                                &&(~clear_pipeline))
1358 118 dgisselq
                        ||((~alu_gie)&&(bus_err))
1359
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1360
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));
1361 36 dgisselq
`endif
1362 2 dgisselq
 
1363
 
1364
        // The sleep register.  Setting the sleep register causes the CPU to
1365
        // sleep until the next interrupt.  Setting the sleep register within
1366
        // interrupt mode causes the processor to halt until a reset.  This is
1367 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1368
        // set the sleep bit and switch to supervisor mode in the same 
1369
        // instruction: users are not allowed to halt the CPU.
1370 2 dgisselq
        always @(posedge i_clk)
1371 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1372 2 dgisselq
                        sleep <= 1'b0;
1373 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1374
                        // In supervisor mode, we have no protections.  The
1375
                        // supervisor can set the sleep bit however he wants.
1376 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1377
                        // sleep mode shouold only be possible if the interrupt
1378
                        // flag isn't set.
1379
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
1380
                        //              don't set the sleep bit
1381
                        //      otherwise however it would o.w. be set
1382
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
1383
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
1384 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1385
                        // In user mode, however, you can only set the sleep
1386
                        // mode while remaining in user mode.  You can't switch
1387
                        // to sleep mode *and* supervisor mode at the same
1388
                        // time, lest you halt the CPU.
1389
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1390 2 dgisselq
 
1391
        always @(posedge i_clk)
1392
                if ((i_rst)||(w_switch_to_interrupt))
1393
                        step <= 1'b0;
1394 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1395 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1396 132 dgisselq
                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
1397 2 dgisselq
                        step <= 1'b0;
1398
 
1399
        // The GIE register.  Only interrupts can disable the interrupt register
1400
        assign  w_switch_to_interrupt = (gie)&&(
1401
                        // On interrupt (obviously)
1402 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1403 2 dgisselq
                        // If we are stepping the CPU
1404 132 dgisselq
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
1405 2 dgisselq
                        // If we encounter a break instruction, if the break
1406 36 dgisselq
                        //      enable isn't set.
1407 69 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
1408
                                &&(op_break)&&(~break_en))
1409 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1410 36 dgisselq
                        // On an illegal instruction
1411 71 dgisselq
                        ||((alu_pc_valid)&&(alu_illegal))
1412 36 dgisselq
`endif
1413 71 dgisselq
                        // On division by zero.  If the divide isn't
1414
                        // implemented, div_valid and div_error will be short
1415
                        // circuited and that logic will be bypassed
1416
                        ||((div_valid)&&(div_error))
1417
                        // Same thing on a floating point error.
1418
                        ||((fpu_valid)&&(fpu_error))
1419
                        //      
1420 69 dgisselq
                        ||(bus_err)
1421 2 dgisselq
                        // If we write to the CC register
1422
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1423 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1424 2 dgisselq
                        );
1425
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1426
                        // Then if we write the CC register
1427
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1428 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1429 2 dgisselq
                        );
1430
        always @(posedge i_clk)
1431
                if (i_rst)
1432
                        gie <= 1'b0;
1433
                else if (w_switch_to_interrupt)
1434
                        gie <= 1'b0;
1435
                else if (w_release_from_interrupt)
1436
                        gie <= 1'b1;
1437
 
1438 25 dgisselq
        initial trap = 1'b0;
1439
        always @(posedge i_clk)
1440
                if (i_rst)
1441
                        trap <= 1'b0;
1442 132 dgisselq
                else if (w_release_from_interrupt)
1443
                        trap <= 1'b0;
1444 69 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1445
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
1446 25 dgisselq
                        trap <= 1'b1;
1447 132 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
1448
                        trap <= wr_reg_vl[`CPU_TRAP_BIT];
1449 25 dgisselq
 
1450 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1451 65 dgisselq
        initial ill_err_i = 1'b0;
1452 36 dgisselq
        always @(posedge i_clk)
1453
                if (i_rst)
1454 65 dgisselq
                        ill_err_i <= 1'b0;
1455 132 dgisselq
                // Only the debug interface can clear this bit
1456 65 dgisselq
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1457
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
1458
                        ill_err_i <= 1'b0;
1459 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
1460 65 dgisselq
                        ill_err_i <= 1'b1;
1461
        initial ill_err_u = 1'b0;
1462
        always @(posedge i_clk)
1463
                if (i_rst)
1464
                        ill_err_u <= 1'b0;
1465
                // The bit is automatically cleared on release from interrupt
1466 36 dgisselq
                else if (w_release_from_interrupt)
1467 65 dgisselq
                        ill_err_u <= 1'b0;
1468
                // If the supervisor writes to this register, clearing the
1469
                // bit, then clear it
1470
                else if (((~alu_gie)||(dbgv))
1471
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
1472
                                &&(wr_reg_id[4])&&(wr_write_cc))
1473
                        ill_err_u <= 1'b0;
1474 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
1475 65 dgisselq
                        ill_err_u <= 1'b1;
1476 38 dgisselq
`else
1477 65 dgisselq
        assign ill_err_u = 1'b0;
1478
        assign ill_err_i = 1'b0;
1479 36 dgisselq
`endif
1480 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1481
        // ever set.
1482
        initial ibus_err_flag = 1'b0;
1483 36 dgisselq
        always @(posedge i_clk)
1484
                if (i_rst)
1485 65 dgisselq
                        ibus_err_flag <= 1'b0;
1486
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1487
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
1488
                        ibus_err_flag <= 1'b0;
1489
                else if ((bus_err)&&(~alu_gie))
1490
                        ibus_err_flag <= 1'b1;
1491
        // User bus error flag -- if ever set, it will cause an interrupt to
1492
        // supervisor mode.  
1493
        initial ubus_err_flag = 1'b0;
1494
        always @(posedge i_clk)
1495
                if (i_rst)
1496
                        ubus_err_flag <= 1'b0;
1497 36 dgisselq
                else if (w_release_from_interrupt)
1498 65 dgisselq
                        ubus_err_flag <= 1'b0;
1499
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1500
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
1501
                                &&(wr_reg_id[4])&&(wr_write_cc))
1502
                        ubus_err_flag <= 1'b0;
1503 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1504 65 dgisselq
                        ubus_err_flag <= 1'b1;
1505 36 dgisselq
 
1506 69 dgisselq
        generate
1507
        if (IMPLEMENT_DIVIDE != 0)
1508
        begin
1509
                reg     r_idiv_err_flag, r_udiv_err_flag;
1510
 
1511
                // Supervisor/interrupt divide (by zero) error flag -- this will
1512
                // crash the CPU if ever set.  This bit is thus available for us
1513
                // to be able to tell if/why the CPU crashed.
1514
                initial r_idiv_err_flag = 1'b0;
1515
                always @(posedge i_clk)
1516
                        if (i_rst)
1517
                                r_idiv_err_flag <= 1'b0;
1518
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1519
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
1520
                                r_idiv_err_flag <= 1'b0;
1521
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
1522
                                r_idiv_err_flag <= 1'b1;
1523
                // User divide (by zero) error flag -- if ever set, it will
1524
                // cause a sudden switch interrupt to supervisor mode.  
1525
                initial r_udiv_err_flag = 1'b0;
1526
                always @(posedge i_clk)
1527
                        if (i_rst)
1528
                                r_udiv_err_flag <= 1'b0;
1529
                        else if (w_release_from_interrupt)
1530
                                r_udiv_err_flag <= 1'b0;
1531
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1532
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
1533
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1534
                                r_udiv_err_flag <= 1'b0;
1535
                        else if ((div_error)&&(alu_gie)&&(div_valid))
1536
                                r_udiv_err_flag <= 1'b1;
1537
 
1538
                assign  idiv_err_flag = r_idiv_err_flag;
1539
                assign  udiv_err_flag = r_udiv_err_flag;
1540
        end else begin
1541
                assign  idiv_err_flag = 1'b0;
1542
                assign  udiv_err_flag = 1'b0;
1543
        end endgenerate
1544
 
1545
        generate
1546
        if (IMPLEMENT_FPU !=0)
1547
        begin
1548
                // Supervisor/interrupt floating point error flag -- this will
1549
                // crash the CPU if ever set.
1550
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1551
                initial r_ifpu_err_flag = 1'b0;
1552
                always @(posedge i_clk)
1553
                        if (i_rst)
1554
                                r_ifpu_err_flag <= 1'b0;
1555
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1556
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
1557
                                r_ifpu_err_flag <= 1'b0;
1558
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1559
                                r_ifpu_err_flag <= 1'b1;
1560
                // User floating point error flag -- if ever set, it will cause
1561
                // a sudden switch interrupt to supervisor mode.  
1562
                initial r_ufpu_err_flag = 1'b0;
1563
                always @(posedge i_clk)
1564
                        if (i_rst)
1565
                                r_ufpu_err_flag <= 1'b0;
1566
                        else if (w_release_from_interrupt)
1567
                                r_ufpu_err_flag <= 1'b0;
1568
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1569
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
1570
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1571
                                r_ufpu_err_flag <= 1'b0;
1572
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1573
                                r_ufpu_err_flag <= 1'b1;
1574
 
1575
                assign  ifpu_err_flag = r_ifpu_err_flag;
1576
                assign  ufpu_err_flag = r_ufpu_err_flag;
1577
        end else begin
1578
                assign  ifpu_err_flag = 1'b0;
1579
                assign  ufpu_err_flag = 1'b0;
1580
        end endgenerate
1581
 
1582
`ifdef  OPT_VLIW
1583
        reg             r_ihalt_phase, r_uhalt_phase;
1584
 
1585
        initial r_ihalt_phase = 0;
1586
        initial r_uhalt_phase = 0;
1587
        always @(posedge i_clk)
1588
                if (~alu_gie)
1589
                        r_ihalt_phase <= alu_phase;
1590
        always @(posedge i_clk)
1591
                if (alu_gie)
1592
                        r_uhalt_phase <= alu_phase;
1593
                else if (w_release_from_interrupt)
1594
                        r_uhalt_phase <= 1'b0;
1595
 
1596
        assign  ihalt_phase = r_ihalt_phase;
1597
        assign  uhalt_phase = r_uhalt_phase;
1598
`else
1599
        assign  ihalt_phase = 1'b0;
1600
        assign  uhalt_phase = 1'b0;
1601
`endif
1602
 
1603 2 dgisselq
        //
1604
        // Write backs to the PC register, and general increments of it
1605
        //      We support two: upc and ipc.  If the instruction is normal,
1606
        // we increment upc, if interrupt level we increment ipc.  If
1607
        // the instruction writes the PC, we write whichever PC is appropriate.
1608
        //
1609
        // Do we need to all our partial results from the pipeline?
1610
        // What happens when the pipeline has gie and ~gie instructions within
1611
        // it?  Do we clear both?  What if a gie instruction tries to clear
1612
        // a non-gie instruction?
1613
        always @(posedge i_clk)
1614 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1615 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1616 132 dgisselq
                else if ((alu_gie)&&
1617
                                (((alu_pc_valid)&&(~clear_pipeline))
1618
                                ||(mem_pc_valid)))
1619 2 dgisselq
                        upc <= alu_pc;
1620
 
1621
        always @(posedge i_clk)
1622
                if (i_rst)
1623
                        ipc <= RESET_ADDRESS;
1624
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1625 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1626 132 dgisselq
                else if ((~alu_gie)&&
1627
                                (((alu_pc_valid)&&(~clear_pipeline))
1628
                                ||(mem_pc_valid)))
1629 2 dgisselq
                        ipc <= alu_pc;
1630
 
1631
        always @(posedge i_clk)
1632
                if (i_rst)
1633
                        pf_pc <= RESET_ADDRESS;
1634
                else if (w_switch_to_interrupt)
1635
                        pf_pc <= ipc;
1636
                else if (w_release_from_interrupt)
1637
                        pf_pc <= upc;
1638
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1639 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1640 69 dgisselq
`ifdef  OPT_PIPELINED
1641 105 dgisselq
                else if ((dcd_early_branch)&&(~clear_pipeline))
1642 69 dgisselq
                        pf_pc <= dcd_branch_pc + 1;
1643
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1644 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1645 69 dgisselq
`else
1646 145 dgisselq
                else if ((alu_gie==gie)&&(
1647
                                ((alu_pc_valid)&&(~clear_pipeline))
1648
                                ||(mem_pc_valid)))
1649 69 dgisselq
                        pf_pc <= alu_pc;
1650
`endif
1651 2 dgisselq
 
1652
        initial new_pc = 1'b1;
1653
        always @(posedge i_clk)
1654 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1655 2 dgisselq
                        new_pc <= 1'b1;
1656
                else if (w_switch_to_interrupt)
1657
                        new_pc <= 1'b1;
1658
                else if (w_release_from_interrupt)
1659
                        new_pc <= 1'b1;
1660
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1661
                        new_pc <= 1'b1;
1662
                else
1663
                        new_pc <= 1'b0;
1664
 
1665
        //
1666
        // The debug interface
1667 56 dgisselq
        generate
1668
        if (AW<32)
1669
        begin
1670
                always @(posedge i_clk)
1671 2 dgisselq
                begin
1672
                        o_dbg_reg <= regset[i_dbg_reg];
1673
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1674 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1675 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1676 56 dgisselq
                        begin
1677 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1678 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1679
                        end
1680 2 dgisselq
                end
1681 56 dgisselq
        end else begin
1682
                always @(posedge i_clk)
1683
                begin
1684
                        o_dbg_reg <= regset[i_dbg_reg];
1685
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1686
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1687
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1688
                        begin
1689 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1690 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1691
                        end
1692
                end
1693
        end endgenerate
1694
 
1695 2 dgisselq
        always @(posedge i_clk)
1696 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1697 18 dgisselq
 
1698
        always @(posedge i_clk)
1699 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1700 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1701 132 dgisselq
                        ||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
1702
                        ||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
1703 2 dgisselq
 
1704
        //
1705
        //
1706
        // Produce accounting outputs: Account for any CPU stalls, so we can
1707
        // later evaluate how well we are doing.
1708
        //
1709
        //
1710 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1711 9 dgisselq
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1712 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1713 56 dgisselq
 
1714 65 dgisselq
`ifdef  DEBUG_SCOPE
1715 56 dgisselq
        always @(posedge i_clk)
1716 65 dgisselq
                o_debug <= {
1717 132 dgisselq
                        o_break, i_wb_err, pf_pc[1:0],
1718
                        flags,
1719 56 dgisselq
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1720
                        op_ce, alu_ce, mem_ce,
1721 65 dgisselq
                        //
1722
                        master_ce, opvalid_alu, opvalid_mem,
1723
                        //
1724
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1725
                        mem_we,
1726
                        // ((opvalid_alu)&&(alu_stall))
1727
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1728
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1729
                        // opA[23:20], opA[3:0],
1730 132 dgisselq
                        gie, sleep, wr_reg_ce, wr_reg_vl[4:0]
1731 71 dgisselq
                /*
1732 69 dgisselq
                        i_rst, master_ce, (new_pc),
1733
                        ((dcd_early_branch)&&(dcdvalid)),
1734
                        pf_valid, pf_illegal,
1735
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1736
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1737
                        pf_pc[7:0], pf_addr[7:0]
1738 71 dgisselq
                */
1739 132 dgisselq
                /*
1740
                        i_wb_err, gie, alu_illegal,
1741
                              (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
1742
                        mem_busy,
1743
                                (mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
1744
                                        o_wb_addr[8:0] }
1745
                                        : { instruction[31:21] },
1746
                        pf_valid, (pf_valid) ? alu_pc[14:0]
1747
                                :{ pf_cyc, pf_stb, pf_pc[12:0] }
1748
                */
1749
                /*
1750
                        i_wb_err, gie, new_pc, dcd_early_branch,        // 4
1751
                        pf_valid, pf_cyc, pf_stb, instruction_pc[0],    // 4
1752
                        instruction[30:27],                             // 4
1753
                        dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb,  // 4
1754
                        dcdvalid,
1755
                        ((dcd_early_branch)&&(~clear_pipeline))         // 15
1756
                                        ? dcd_branch_pc[14:0]:pf_pc[14:0]
1757
                */
1758 56 dgisselq
                        };
1759 65 dgisselq
`endif
1760 56 dgisselq
 
1761 2 dgisselq
endmodule

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