OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Blame information for rev 160

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9 56 dgisselq
//      (actual implementation aside ...)  The instruction set is about as
10
//      RISC as you can get, there are only 16 instruction types supported.
11
//      Please see the accompanying spec.pdf file for a description of these
12
//      instructions.
13 2 dgisselq
//
14 56 dgisselq
//      All instructions are 32-bits wide.  All bus accesses, both address and
15
//      data, are 32-bits over a wishbone bus.
16 2 dgisselq
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19 56 dgisselq
//              1. Prefetch, returns the instruction from memory. 
20 2 dgisselq
//
21
//              2. Instruction Decode
22
//
23
//              3. Read Operands
24
//
25
//              4. Apply Instruction
26
//
27
//              4. Write-back Results
28
//
29 56 dgisselq
//      Further information about the inner workings of this CPU may be
30
//      found in the spec.pdf file.  (The documentation within this file
31
//      had become out of date and out of sync with the spec.pdf, so look
32
//      to the spec.pdf for accurate and up to date information.)
33 2 dgisselq
//
34
//
35 69 dgisselq
//      In general, the pipelining is controlled by three pieces of logic
36
//      per stage: _ce, _stall, and _valid.  _valid means that the stage
37
//      holds a valid instruction.  _ce means that the instruction from the
38
//      previous stage is to move into this one, and _stall means that the
39
//      instruction from the previous stage may not move into this one.
40
//      The difference between these control signals allows individual stages
41
//      to propagate instructions independently.  In general, the logic works
42
//      as:
43
//
44
//
45
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
46
//
47
//
48
//      always @(posedge i_clk)
49
//              if ((i_rst)||(clear_pipeline))
50
//                      (n)_valid = 0
51
//              else if (n)_ce
52
//                      (n)_valid = 1
53
//              else if (n+1)_ce
54
//                      (n)_valid = 0
55
//
56
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
57
//                      || (  (n)_valid && (n+1)_stall );
58
//
59
//      and ...
60
//
61
//      always @(posedge i_clk)
62
//              if (n)_ce
63
//                      (n)_variable = ... whatever logic for this stage
64
//
65
//      Note that a stage can stall even if no instruction is loaded into
66
//      it.
67
//
68
//
69 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
70 69 dgisselq
//              Gisselquist Technology, LLC
71 2 dgisselq
//
72
///////////////////////////////////////////////////////////////////////////////
73
//
74 160 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
75 2 dgisselq
//
76
// This program is free software (firmware): you can redistribute it and/or
77
// modify it under the terms of  the GNU General Public License as published
78
// by the Free Software Foundation, either version 3 of the License, or (at
79
// your option) any later version.
80
//
81
// This program is distributed in the hope that it will be useful, but WITHOUT
82
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
83
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
84
// for more details.
85
//
86
// License:     GPL, v3, as defined and found on www.gnu.org,
87
//              http://www.gnu.org/licenses/gpl.html
88
//
89
//
90
///////////////////////////////////////////////////////////////////////////////
91
//
92 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
93
// fetches are more complicated and therefore use more FPGA resources, while
94
// single fetches will cause the CPU to stall for about 5 stalls each 
95
// instruction cycle, effectively reducing the instruction count per clock to
96
// about 0.2.  However, the area cost may be worth it.  Consider:
97
//
98
//      Slice LUTs              ZipSystem       ZipCPU
99
//      Single Fetching         2521            1734
100
//      Pipelined fetching      2796            2046
101
//
102
//
103
//
104 25 dgisselq
`define CPU_CC_REG      4'he
105 2 dgisselq
`define CPU_PC_REG      4'hf
106 69 dgisselq
`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
111 2 dgisselq
`define CPU_BREAK_BIT   7
112 69 dgisselq
`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
113 2 dgisselq
`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
115 36 dgisselq
// Compile time defines
116 56 dgisselq
//
117
`include "cpudefs.v"
118
//
119 65 dgisselq
//
120 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
122 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
124 2 dgisselq
                        o_break,
125
                // CPU interface to the wishbone bus
126 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
128
                        o_wb_we, o_wb_addr, o_wb_data,
129 2 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data,
130 36 dgisselq
                        i_wb_err,
131 2 dgisselq
                // Accounting/CPU usage interface
132 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
137 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
138 69 dgisselq
                        LGICACHE=6;
139 56 dgisselq
`ifdef  OPT_MULTIPLY
140 132 dgisselq
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
141 56 dgisselq
`else
142
        parameter       IMPLEMENT_MPY = 0;
143
`endif
144 71 dgisselq
`ifdef  OPT_DIVIDE
145
        parameter       IMPLEMENT_DIVIDE = 1;
146
`else
147
        parameter       IMPLEMENT_DIVIDE = 0;
148
`endif
149
`ifdef  OPT_IMPLEMENT_FPU
150
        parameter       IMPLEMENT_FPU = 1,
151
`else
152
        parameter       IMPLEMENT_FPU = 0,
153
`endif
154 69 dgisselq
                        IMPLEMENT_LOCK=1;
155
`ifdef  OPT_EARLY_BRANCHING
156
        parameter       EARLY_BRANCHING = 1;
157
`else
158
        parameter       EARLY_BRANCHING = 0;
159
`endif
160
        parameter       AW=ADDRESS_WIDTH;
161 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
162
        // Debug interface -- inputs
163 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
164 2 dgisselq
        input           [4:0]    i_dbg_reg;
165
        input                   i_dbg_we;
166
        input           [31:0]   i_dbg_data;
167
        // Debug interface -- outputs
168 160 dgisselq
        output  wire            o_dbg_stall;
169 2 dgisselq
        output  reg     [31:0]   o_dbg_reg;
170 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
171 2 dgisselq
        output  wire            o_break;
172
        // Wishbone interface -- outputs
173 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
174
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
175 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
176
        output  wire    [31:0]   o_wb_data;
177 2 dgisselq
        // Wishbone interface -- inputs
178
        input                   i_wb_ack, i_wb_stall;
179
        input           [31:0]   i_wb_data;
180 36 dgisselq
        input                   i_wb_err;
181 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
182 9 dgisselq
        output  wire            o_op_stall;
183 2 dgisselq
        output  wire            o_pf_stall;
184 9 dgisselq
        output  wire            o_i_count;
185 56 dgisselq
        //
186 65 dgisselq
`ifdef  DEBUG_SCOPE
187 56 dgisselq
        output  reg     [31:0]   o_debug;
188 65 dgisselq
`endif
189 2 dgisselq
 
190 25 dgisselq
 
191 2 dgisselq
        // Registers
192 56 dgisselq
        //
193
        //      The distributed RAM style comment is necessary on the
194
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
195
        // set and in the process ruining everything else.  It basically
196
        // optimizes logic away, to where it no longer works.  The logic
197
        // as described herein will work, this just makes sure XST implements
198
        // that logic.
199
        //
200
        (* ram_style = "distributed" *)
201 2 dgisselq
        reg     [31:0]   regset [0:31];
202 9 dgisselq
 
203
        // Condition codes
204 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
205
        reg     [3:0]    flags, iflags;
206 83 dgisselq
        wire    [13:0]   w_uflags, w_iflags;
207 160 dgisselq
        reg             trap, break_en, step, gie, sleep, r_halted;
208 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
209 65 dgisselq
        reg             ill_err_u, ill_err_i;
210 38 dgisselq
`else
211 65 dgisselq
        wire            ill_err_u, ill_err_i;
212 36 dgisselq
`endif
213 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
214 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
215
        wire            ifpu_err_flag, ufpu_err_flag;
216
        wire            ihalt_phase, uhalt_phase;
217 2 dgisselq
 
218 9 dgisselq
        // The master chip enable
219
        wire            master_ce;
220 2 dgisselq
 
221
        //
222
        //
223
        //      PIPELINE STAGE #1 :: Prefetch
224
        //              Variable declarations
225
        //
226 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
227 69 dgisselq
        reg     new_pc;
228 18 dgisselq
        wire    clear_pipeline;
229 69 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
230 9 dgisselq
 
231
        wire            dcd_stalled;
232 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
233 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
234
        wire    [31:0]           pf_data;
235
        wire    [31:0]           instruction;
236
        wire    [(AW-1):0]       instruction_pc;
237 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
238 2 dgisselq
 
239
        //
240
        //
241
        //      PIPELINE STAGE #2 :: Instruction Decode
242
        //              Variable declarations
243
        //
244
        //
245 83 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu;
246 69 dgisselq
        reg             opvalid_div, opvalid_fpu;
247
        wire            op_stall, dcd_ce, dcd_phase;
248
        wire    [3:0]    dcdOp;
249
        wire    [4:0]    dcdA, dcdB, dcdR;
250
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
251
        wire    [3:0]    dcdF;
252
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
253
                                dcdALU, dcdM, dcdDV, dcdFP,
254 71 dgisselq
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
255 105 dgisselq
                                dcd_pipe, dcd_ljmp;
256 69 dgisselq
        reg             r_dcdvalid;
257
        wire            dcdvalid;
258
        wire    [(AW-1):0]       dcd_pc;
259
        wire    [31:0]   dcdI;
260
        wire            dcd_zI; // true if dcdI == 0
261 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
262
 
263 69 dgisselq
        wire    dcd_illegal;
264
        wire                    dcd_early_branch;
265 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
266 2 dgisselq
 
267
 
268
        //
269
        //
270
        //      PIPELINE STAGE #3 :: Read Operands
271
        //              Variable declarations
272
        //
273
        //
274
        //
275
        // Now, let's read our operands
276
        reg     [4:0]    alu_reg;
277
        reg     [3:0]    opn;
278
        reg     [4:0]    opR;
279 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
280
        reg     [(AW-1):0]       op_pc;
281 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
282 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
283 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
284 83 dgisselq
        wire    [13:0]   opFl;
285 56 dgisselq
        reg     [5:0]    r_opF;
286
        wire    [7:0]    opF;
287 160 dgisselq
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
288 56 dgisselq
        // Some pipeline control wires
289 69 dgisselq
`ifdef  OPT_PIPELINED
290 56 dgisselq
        reg     opA_alu, opA_mem;
291
        reg     opB_alu, opB_mem;
292
`endif
293 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
294 36 dgisselq
        reg     op_illegal;
295 160 dgisselq
`else
296
        wire    op_illegal;
297
        assign  op_illegal = 1'b0;
298 36 dgisselq
`endif
299 69 dgisselq
        reg     op_break;
300
        wire    op_lock;
301 2 dgisselq
 
302
 
303
        //
304
        //
305
        //      PIPELINE STAGE #4 :: ALU / Memory
306
        //              Variable declarations
307
        //
308
        //
309 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
310 145 dgisselq
        reg             r_alu_pc_valid, mem_pc_valid;
311
        wire            alu_pc_valid;
312 69 dgisselq
        wire            alu_phase;
313 2 dgisselq
        wire            alu_ce, alu_stall;
314
        wire    [31:0]   alu_result;
315
        wire    [3:0]    alu_flags;
316 71 dgisselq
        wire            alu_valid, alu_busy;
317 2 dgisselq
        wire            set_cond;
318
        reg             alu_wr, alF_wr, alu_gie;
319 56 dgisselq
        wire            alu_illegal_op;
320 38 dgisselq
        wire            alu_illegal;
321 2 dgisselq
 
322
 
323
 
324
        wire    mem_ce, mem_stalled;
325 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
326
        wire    mem_pipe_stalled;
327
`endif
328 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
329
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
330 48 dgisselq
        wire    [4:0]            mem_wreg;
331 9 dgisselq
 
332 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
333
        wire    [(AW-1):0]       mem_addr;
334
        wire    [31:0]           mem_data, mem_result;
335 2 dgisselq
 
336 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
337
        wire    [31:0]   div_result;
338
        wire    [3:0]    div_flags;
339 2 dgisselq
 
340 69 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
341
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
342
                                &&(set_cond);
343 2 dgisselq
 
344 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
345
        wire    [31:0]   fpu_result;
346
        wire    [3:0]    fpu_flags;
347
 
348
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
349
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
350
                                &&(set_cond);
351
 
352 160 dgisselq
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
353
        wire    adf_ce, adf_ce_unconditional;
354
        assign  adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
355
                                &&(~opvalid_mem)&&(~mem_rdbusy)&&(~div_busy)
356
                                &&(~fpu_busy);
357
        assign  adf_ce = (adf_ce_unconditional)&&(set_cond);
358 69 dgisselq
 
359 2 dgisselq
        //
360
        //
361
        //      PIPELINE STAGE #5 :: Write-back
362
        //              Variable declarations
363
        //
364 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
365 2 dgisselq
        wire    [4:0]    wr_reg_id;
366 160 dgisselq
        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;
367 2 dgisselq
        wire    w_switch_to_interrupt, w_release_from_interrupt;
368 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
369 2 dgisselq
 
370
 
371
 
372
        //
373
        //      MASTER: clock enable.
374
        //
375 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
376 2 dgisselq
 
377
 
378
        //
379
        //      PIPELINE STAGE #1 :: Prefetch
380
        //              Calculate stall conditions
381 65 dgisselq
        //
382
        //      These are calculated externally, within the prefetch module.
383
        //
384 2 dgisselq
 
385
        //
386
        //      PIPELINE STAGE #2 :: Instruction Decode
387
        //              Calculate stall conditions
388 69 dgisselq
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
389 145 dgisselq
 
390 69 dgisselq
`ifdef  OPT_PIPELINED
391
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
392
`else
393
        // If not pipelined, there will be no opvalid_ anything, and the
394
        // op_stall will be false, dcdX_stall will be false, thus we can simply
395
        // do a ...
396
        assign          dcd_stalled = 1'b0;
397
`endif
398 2 dgisselq
        //
399
        //      PIPELINE STAGE #3 :: Read Operands
400
        //              Calculate stall conditions
401 69 dgisselq
        wire    op_lock_stall;
402
`ifdef  OPT_PIPELINED
403
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
404
                        // Stall if we're stopped, and not allowed to execute
405
                        // an instruction
406
                        // (~master_ce)         // Already captured in alu_stall
407
                        //
408 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
409
                        //      i.e. if the memory is busy, or we are single
410 69 dgisselq
                        //      stepping.  This also includes our stalls for
411
                        //      op_break and op_lock, so we don't need to
412
                        //      include those as well here.
413 83 dgisselq
                        // This also includes whether or not the divide or
414
                        // floating point units are busy.
415
                        (alu_stall)
416 56 dgisselq
                        //
417
                        // Stall if we are going into memory with an operation
418
                        //      that cannot be pipelined, and the memory is
419
                        //      already busy
420 83 dgisselq
                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
421 69 dgisselq
                        )
422
                        ||(dcdvalid)&&(
423 71 dgisselq
                                // Stall if we need to wait for an operand A
424 69 dgisselq
                                // to be ready to read
425 71 dgisselq
                                (dcdA_stall)
426 69 dgisselq
                                // Likewise for B, also includes logic
427
                                // regarding immediate offset (register must
428
                                // be in register file if we need to add to
429
                                // an immediate)
430
                                ||(dcdB_stall)
431
                                // Or if we need to wait on flags to work on the
432
                                // CC register
433
                                ||(dcdF_stall)
434
                        );
435 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
436 160 dgisselq
        // BUT ... op_ce is too complex for many of the data operations.  So
437
        // let's make their circuit enable code simpler.  In particular, if
438
        // op_ doesn't need to be preserved, we can change it all we want
439
        // ... right?  The clear_pipeline code, for example, really only needs
440
        // to determine whether opvalid is true.
441
        assign  op_change_data_ce = (~op_stall);
442 65 dgisselq
`else
443 69 dgisselq
        assign  op_stall = (opvalid)&&(~master_ce);
444 145 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
445 160 dgisselq
        assign  op_change_data_ce = 1'b1;
446 65 dgisselq
`endif
447 2 dgisselq
 
448
        //
449
        //      PIPELINE STAGE #4 :: ALU / Memory
450
        //              Calculate stall conditions
451 36 dgisselq
        //
452
        // 1. Basic stall is if the previous stage is valid and the next is
453
        //      busy.  
454
        // 2. Also stall if the prior stage is valid and the master clock enable
455
        //      is de-selected
456 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
457
        //      since we don't know if it'll put us to sleep or not.
458 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
459
        //      through the ALU.  Break instructions are not allowed through
460
        //      the ALU.
461 69 dgisselq
`ifdef  OPT_PIPELINED
462 71 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
463 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
464
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
465
                                &&(wr_write_cc)) // Case 3
466 69 dgisselq
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
467
                        ||((opvalid)&&(op_break))
468
                        ||(div_busy)||(fpu_busy);
469 160 dgisselq
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
470 69 dgisselq
                                &&(~clear_pipeline);
471
`else
472
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
473
                                ||((opvalid_alu)&&(op_break));
474 145 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
475 69 dgisselq
`endif
476 2 dgisselq
        //
477 65 dgisselq
 
478
        //
479
        // Note: if you change the conditions for mem_ce, you must also change
480
        // alu_pc_valid.
481
        //
482 69 dgisselq
`ifdef  OPT_PIPELINED
483
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
484 71 dgisselq
                        &&(~clear_pipeline);
485 69 dgisselq
`else
486
        // If we aren't pipelined, then no one will be changing what's in the
487
        // pipeline (i.e. clear_pipeline), while our only instruction goes
488
        // through the ... pipeline.
489 145 dgisselq
        //
490
        // However, in hind sight this logic didn't work.  What happens when
491
        // something gets in the pipeline and then (due to interrupt or some
492
        // such) needs to be voided?  Thus we avoid simplification and keep
493
        // what worked here.
494
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
495
                        &&(~clear_pipeline);
496 69 dgisselq
`endif
497 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
498 71 dgisselq
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
499 38 dgisselq
                                (mem_pipe_stalled)
500
                                ||((~op_pipe)&&(mem_busy))
501 69 dgisselq
                                ||(div_busy)
502
                                ||(fpu_busy)
503 38 dgisselq
                                // Stall waiting for flags to be valid
504
                                // Or waiting for a write to the PC register
505
                                // Or CC register, since that can change the
506
                                //  PC as well
507
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
508
                                        &&((wr_write_pc)||(wr_write_cc)))));
509
`else
510 69 dgisselq
`ifdef  OPT_PIPELINED
511 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
512 2 dgisselq
                                (~master_ce)
513
                                // Stall waiting for flags to be valid
514
                                // Or waiting for a write to the PC register
515 25 dgisselq
                                // Or CC register, since that can change the
516
                                //  PC as well
517
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
518 69 dgisselq
`else
519
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
520 38 dgisselq
`endif
521 69 dgisselq
`endif
522 2 dgisselq
 
523
 
524
        //
525
        //
526
        //      PIPELINE STAGE #1 :: Prefetch
527
        //
528
        //
529 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
530 9 dgisselq
        wire            pf_ce;
531
 
532 145 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
533 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
534 145 dgisselq
                        pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
535 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
536 36 dgisselq
                                        pf_valid, pf_illegal,
537
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
538
                                pf_ack, pf_stall, pf_err, i_wb_data);
539 69 dgisselq
 
540
        initial r_dcdvalid = 1'b0;
541
        always @(posedge i_clk)
542 145 dgisselq
                if ((i_rst)||(clear_pipeline))
543 69 dgisselq
                        r_dcdvalid <= 1'b0;
544
                else if (dcd_ce)
545 105 dgisselq
                        r_dcdvalid <= (pf_valid);
546
                else if (op_ce)
547 69 dgisselq
                        r_dcdvalid <= 1'b0;
548
        assign  dcdvalid = r_dcdvalid;
549
 
550 2 dgisselq
`else // Pipe fetch
551 69 dgisselq
 
552
`ifdef  OPT_TRADITIONAL_PFCACHE
553
        pfcache #(LGICACHE, ADDRESS_WIDTH)
554 105 dgisselq
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
555 69 dgisselq
                                        i_clear_pf_cache,
556
                                // dcd_pc,
557
                                ~dcd_stalled,
558 105 dgisselq
                                ((dcd_early_branch)&&(~clear_pipeline))
559 69 dgisselq
                                        ? dcd_branch_pc:pf_pc,
560
                                instruction, instruction_pc, pf_valid,
561
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
562
                                        pf_ack, pf_stall, pf_err, i_wb_data,
563
                                pf_illegal);
564
`else
565 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
566 105 dgisselq
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
567 36 dgisselq
                                        i_clear_pf_cache, ~dcd_stalled,
568
                                        (new_pc)?pf_pc:dcd_branch_pc,
569 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
570
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
571 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
572 69 dgisselq
//`ifdef        OPT_PRECLEAR_BUS
573
                                //((dcd_clear_bus)&&(dcdvalid))
574
                                //||((op_clear_bus)&&(opvalid))
575
                                //||
576
//`endif
577 36 dgisselq
                                (mem_cyc_lcl)||(mem_cyc_gbl),
578
                                pf_illegal);
579 69 dgisselq
`endif
580 2 dgisselq
        assign  instruction_gie = gie;
581
 
582 69 dgisselq
        initial r_dcdvalid = 1'b0;
583 2 dgisselq
        always @(posedge i_clk)
584 69 dgisselq
                if ((i_rst)||(clear_pipeline))
585
                        r_dcdvalid <= 1'b0;
586 2 dgisselq
                else if (dcd_ce)
587 145 dgisselq
                        r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
588 69 dgisselq
                else if (op_ce)
589
                        r_dcdvalid <= 1'b0;
590
        assign  dcdvalid = r_dcdvalid;
591 36 dgisselq
`endif
592 2 dgisselq
 
593 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
594
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
595
                        IMPLEMENT_FPU)
596
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
597
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
598
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
599
                        dcd_illegal, dcd_pc, dcd_gie,
600
                        { dcdR_cc, dcdR_pc, dcdR },
601
                        { dcdA_cc, dcdA_pc, dcdA },
602
                        { dcdB_cc, dcdB_pc, dcdB },
603
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
604
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
605
                        dcdR_wr,dcdA_rd, dcdB_rd,
606
                        dcd_early_branch,
607 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
608 71 dgisselq
                        dcd_pipe);
609 36 dgisselq
`else
610 69 dgisselq
        idecode_deprecated
611
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
612
                        IMPLEMENT_FPU)
613
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
614
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
615
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
616
                        dcd_illegal, dcd_pc, dcd_gie,
617
                        { dcdR_cc, dcdR_pc, dcdR },
618
                        { dcdA_cc, dcdA_pc, dcdA },
619
                        { dcdB_cc, dcdB_pc, dcdB },
620
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
621
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
622
                        dcdR_wr,dcdA_rd, dcdB_rd,
623
                        dcd_early_branch,
624 71 dgisselq
                        dcd_branch_pc,
625
                        dcd_pipe);
626 105 dgisselq
        assign  dcd_ljmp = 1'b0;
627 36 dgisselq
`endif
628 2 dgisselq
 
629 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
630 132 dgisselq
        reg             r_op_pipe;
631 2 dgisselq
 
632 132 dgisselq
        initial r_op_pipe = 1'b0;
633 38 dgisselq
        // To be a pipeable operation, there must be 
634
        //      two valid adjacent instructions
635
        //      Both must be memory instructions
636
        //      Both must be writes, or both must be reads
637
        //      Both operations must be to the same identical address,
638
        //              or at least a single (one) increment above that address
639 71 dgisselq
        //
640
        // However ... we need to know this before this clock, hence this is
641
        // calculated in the instruction decoder.
642 38 dgisselq
        always @(posedge i_clk)
643
                if (op_ce)
644 132 dgisselq
                        r_op_pipe <= dcd_pipe;
645 145 dgisselq
                else if (mem_ce) // Clear us any time an op_ is clocked in
646
                        r_op_pipe <= 1'b0;
647 132 dgisselq
        assign  op_pipe = r_op_pipe;
648
`else
649
        assign  op_pipe = 1'b0;
650 38 dgisselq
`endif
651
 
652 2 dgisselq
        //
653
        //
654
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
655
        //
656
        //
657 25 dgisselq
        assign  w_opA = regset[dcdA];
658
        assign  w_opB = regset[dcdB];
659 56 dgisselq
 
660 132 dgisselq
        wire    [8:0]    w_cpu_info;
661
        assign  w_cpu_info = {
662
`ifdef  OPT_ILLEGAL_INSTRUCTION
663
        1'b1,
664
`else
665
        1'b0,
666
`endif
667
`ifdef  OPT_MULTIPLY
668
        1'b1,
669
`else
670
        1'b0,
671
`endif
672
`ifdef  OPT_DIVIDE
673
        1'b1,
674
`else
675
        1'b0,
676
`endif
677
`ifdef  OPT_IMPLEMENT_FPU
678
        1'b1,
679
`else
680
        1'b0,
681
`endif
682
`ifdef  OPT_PIPELINED
683
        1'b1,
684
`else
685
        1'b0,
686
`endif
687
`ifdef  OPT_TRADITIONAL_CACHE
688
        1'b1,
689
`else
690
        1'b0,
691
`endif
692
`ifdef  OPT_EARLY_BRANCHING
693
        1'b1,
694
`else
695
        1'b0,
696
`endif
697
`ifdef  OPT_PIPELINED_BUS_ACCESS
698
        1'b1,
699
`else
700
        1'b0,
701
`endif
702
`ifdef  OPT_VLIW
703
        1'b1
704
`else
705
        1'b0
706
`endif
707
        };
708
 
709 56 dgisselq
        wire    [31:0]   w_pcA_v;
710
        generate
711
        if (AW < 32)
712
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
713
        else
714
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
715
        endgenerate
716 71 dgisselq
 
717
`ifdef  OPT_PIPELINED
718
        reg     [4:0]    opA_id, opB_id;
719
        reg             opA_rd, opB_rd;
720 2 dgisselq
        always @(posedge i_clk)
721 71 dgisselq
                if (op_ce)
722
                begin
723
                        opA_id <= dcdA;
724
                        opB_id <= dcdB;
725
                        opA_rd <= dcdA_rd;
726
                        opB_rd <= dcdB_rd;
727
                end
728
`endif
729
 
730
        always @(posedge i_clk)
731 160 dgisselq
                if (op_change_data_ce)
732 2 dgisselq
                begin
733
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
734 160 dgisselq
                                r_opA <= wr_gpreg_vl;
735 25 dgisselq
                        else if (dcdA_pc)
736 56 dgisselq
                                r_opA <= w_pcA_v;
737 25 dgisselq
                        else if (dcdA_cc)
738 132 dgisselq
                                r_opA <= { w_cpu_info, w_opA[22:14], (dcdA[4])?w_uflags:w_iflags };
739 2 dgisselq
                        else
740 25 dgisselq
                                r_opA <= w_opA;
741 69 dgisselq
`ifdef  OPT_PIPELINED
742 71 dgisselq
                end else
743 48 dgisselq
                begin // We were going to pick these up when they became valid,
744
                        // but for some reason we're stuck here as they became
745
                        // valid.  Pick them up now anyway
746 71 dgisselq
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
747 160 dgisselq
                                // r_opA <= wr_gpreg_vl;
748 71 dgisselq
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
749 160 dgisselq
                                r_opA <= wr_gpreg_vl;
750 56 dgisselq
`endif
751 2 dgisselq
                end
752 56 dgisselq
 
753 69 dgisselq
        wire    [31:0]   w_opBnI, w_pcB_v;
754 56 dgisselq
        generate
755
        if (AW < 32)
756
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
757
        else
758
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
759
        endgenerate
760
 
761 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
762 160 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
763 56 dgisselq
                : ((dcdB_pc) ? w_pcB_v
764 132 dgisselq
                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:14], // w_opB[31:14],
765
                        (dcdB[4])?w_uflags:w_iflags}
766 56 dgisselq
                : w_opB)));
767
 
768 2 dgisselq
        always @(posedge i_clk)
769 160 dgisselq
                if (op_change_data_ce)
770 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
771 69 dgisselq
`ifdef  OPT_PIPELINED
772 71 dgisselq
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
773 160 dgisselq
                        r_opB <= wr_gpreg_vl;
774 56 dgisselq
`endif
775 2 dgisselq
 
776
        // The logic here has become more complex than it should be, no thanks
777
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
778
        // be two sets of four bits: the top bits specify what bits matter, the
779
        // bottom specify what those top bits must equal.  However, two of
780
        // conditions check whether bits are on, and those are the only two
781
        // conditions checking those bits.  Therefore, Vivado complains that
782
        // these two bits are redundant.  Hence the convoluted expression
783
        // below, arriving at what we finally want in the (now wire net)
784
        // opF.
785
        always @(posedge i_clk)
786 160 dgisselq
                if (op_ce) // Cannot do op_change_data_ce here since opF depends
787
                        // upon being either correct for a valid op, or correct
788
                        // for the last valid op
789 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
790 2 dgisselq
                        case(dcdF[2:0])
791 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
792 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
793
                        // These were remapped as part of the new instruction
794
                        // set in order to make certain that the low order
795
                        // two bits contained the most commonly used 
796
                        // conditions: Always, LT, Z, and NZ.
797
                        3'h1:   r_opF <= 6'h24; // LT
798
                        3'h2:   r_opF <= 6'h11; // Z
799
                        3'h3:   r_opF <= 6'h10; // NE
800
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
801
                        3'h5:   r_opF <= 6'h20; // GE (!N)
802
`else
803 56 dgisselq
                        3'h1:   r_opF <= 6'h11; // Z
804
                        3'h2:   r_opF <= 6'h10; // NE
805
                        3'h3:   r_opF <= 6'h20; // GE (!N)
806
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
807
                        3'h5:   r_opF <= 6'h24; // LT
808 69 dgisselq
`endif
809 56 dgisselq
                        3'h6:   r_opF <= 6'h02; // C
810
                        3'h7:   r_opF <= 6'h08; // V
811 2 dgisselq
                        endcase
812 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
813 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
814 2 dgisselq
 
815 69 dgisselq
        wire    w_opvalid;
816 105 dgisselq
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
817 36 dgisselq
        initial opvalid     = 1'b0;
818
        initial opvalid_alu = 1'b0;
819
        initial opvalid_mem = 1'b0;
820 91 dgisselq
        initial opvalid_div = 1'b0;
821
        initial opvalid_fpu = 1'b0;
822 2 dgisselq
        always @(posedge i_clk)
823
                if (i_rst)
824 25 dgisselq
                begin
825
                        opvalid     <= 1'b0;
826
                        opvalid_alu <= 1'b0;
827
                        opvalid_mem <= 1'b0;
828
                end else if (op_ce)
829
                begin
830 2 dgisselq
                        // Do we have a valid instruction?
831
                        //   The decoder may vote to stall one of its
832
                        //   instructions based upon something we currently
833
                        //   have in our queue.  This instruction must then
834
                        //   move forward, and get a stall cycle inserted.
835
                        //   Hence, the test on dcd_stalled here.  If we must
836
                        //   wait until our operands are valid, then we aren't
837
                        //   valid yet until then.
838 69 dgisselq
                        opvalid<= w_opvalid;
839 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
840 69 dgisselq
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
841
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
842
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
843
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
844 36 dgisselq
`else
845 69 dgisselq
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
846
                        opvalid_mem <= (dcdM)&&(w_opvalid);
847
                        opvalid_div <= (dcdDV)&&(w_opvalid);
848
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
849 36 dgisselq
`endif
850 160 dgisselq
                end else if ((clear_pipeline)||(adf_ce_unconditional)||(mem_ce))
851 25 dgisselq
                begin
852
                        opvalid     <= 1'b0;
853
                        opvalid_alu <= 1'b0;
854
                        opvalid_mem <= 1'b0;
855 69 dgisselq
                        opvalid_div <= 1'b0;
856
                        opvalid_fpu <= 1'b0;
857 25 dgisselq
                end
858 2 dgisselq
 
859
        // Here's part of our debug interface.  When we recognize a break
860
        // instruction, we set the op_break flag.  That'll prevent this
861
        // instruction from entering the ALU, and cause an interrupt before
862
        // this instruction.  Thus, returning to this code will cause the
863
        // break to repeat and continue upon return.  To get out of this
864
        // condition, replace the break instruction with what it is supposed
865
        // to be, step through it, and then replace it back.  In this fashion,
866
        // a debugger can step through code.
867 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
868
        initial op_break = 1'b0;
869 2 dgisselq
        always @(posedge i_clk)
870 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
871
                else if (op_ce) op_break <= (dcd_break);
872
                else if ((clear_pipeline)||(~opvalid))
873
                                op_break <= 1'b0;
874 2 dgisselq
 
875 69 dgisselq
`ifdef  OPT_PIPELINED
876
        generate
877
        if (IMPLEMENT_LOCK != 0)
878
        begin
879
                reg     r_op_lock, r_op_lock_stall;
880
 
881
                initial r_op_lock_stall = 1'b0;
882
                always @(posedge i_clk)
883
                        if (i_rst)
884
                                r_op_lock_stall <= 1'b0;
885
                        else
886
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
887
                                                ||(~dcdvalid)||(~pf_valid);
888
 
889
                assign  op_lock_stall = r_op_lock_stall;
890
 
891
                initial r_op_lock = 1'b0;
892
                always @(posedge i_clk)
893 160 dgisselq
                        if ((i_rst)||(clear_pipeline))
894 69 dgisselq
                                r_op_lock <= 1'b0;
895 132 dgisselq
                        else if (op_ce)
896
                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);
897 69 dgisselq
                assign  op_lock = r_op_lock;
898
 
899
        end else begin
900
                assign  op_lock_stall = 1'b0;
901
                assign  op_lock = 1'b0;
902
        end endgenerate
903
 
904
`else
905
        assign op_lock_stall = 1'b0;
906
        assign op_lock       = 1'b0;
907
`endif
908
 
909 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
910 71 dgisselq
        initial op_illegal = 1'b0;
911 2 dgisselq
        always @(posedge i_clk)
912 71 dgisselq
                if ((i_rst)||(clear_pipeline))
913
                        op_illegal <= 1'b0;
914
                else if(op_ce)
915 69 dgisselq
`ifdef  OPT_PIPELINED
916
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
917
`else
918
                        op_illegal <= (dcd_illegal)||(dcd_lock);
919 36 dgisselq
`endif
920 69 dgisselq
`endif
921 36 dgisselq
 
922 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
923
        // set, dcd_early_branch will simply be a wire connected to zero and
924
        // this logic should just optimize.
925
        always @(posedge i_clk)
926
                if (op_ce)
927
                begin
928 83 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
929
                                &&(~dcd_early_branch)&&(~dcd_illegal);
930
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
931 71 dgisselq
                end
932 69 dgisselq
 
933 36 dgisselq
        always @(posedge i_clk)
934 160 dgisselq
                if (op_change_data_ce)
935 2 dgisselq
                begin
936
                        opn    <= dcdOp;        // Which ALU operation?
937 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
938 2 dgisselq
                        // What register will these results be written into?
939 69 dgisselq
                        opR    <= dcdR;
940
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
941 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
942
                        op_gie <= dcd_gie;
943
 
944 69 dgisselq
 
945 2 dgisselq
                        //
946 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
947 2 dgisselq
                end
948
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
949
 
950 69 dgisselq
`ifdef  OPT_VLIW
951
        reg     r_op_phase;
952
        initial r_op_phase = 1'b0;
953
        always @(posedge i_clk)
954
                if ((i_rst)||(clear_pipeline))
955
                        r_op_phase <= 1'b0;
956 160 dgisselq
                else if (op_change_data_ce)
957 69 dgisselq
                        r_op_phase <= dcd_phase;
958
        assign  op_phase = r_op_phase;
959
`else
960
        assign  op_phase = 1'b0;
961
`endif
962
 
963 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
964
        // register set but in special registers of their own.  So step one
965
        // is to select the right register.  Step to is to replace that
966
        // register with the results of an ALU or memory operation, if such
967
        // results are now available.  Otherwise, we'd need to insert a wait
968
        // state of some type.
969
        //
970
        // The alternative approach would be to define some sort of
971
        // op_stall wire, which would stall any upstream stage.
972
        // We'll create a flag here to start our coordination.  Once we
973
        // define this flag to something other than just plain zero, then
974
        // the stalls will already be in place.
975 69 dgisselq
`ifdef  OPT_PIPELINED
976 83 dgisselq
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
977 160 dgisselq
                        ?  wr_gpreg_vl : r_opA;
978 56 dgisselq
`else
979
        assign  opA = r_opA;
980
`endif
981 48 dgisselq
 
982 69 dgisselq
`ifdef  OPT_PIPELINED
983 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
984
        //      AND ... something that may write a register is running
985
        //      AND (series of conditions here ...)
986
        //              The operation might set flags, and we wish to read the
987
        //                      CC register
988
        //              OR ... (No other conditions)
989
        assign  dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
990
                                &&((opvalid)||(mem_rdbusy)
991
                                        ||(div_busy)||(fpu_busy))
992
                                &&((opF_wr)&&(dcdA_cc));
993 56 dgisselq
`else
994 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
995
        assign  dcdA_stall = 1'b0;
996 56 dgisselq
`endif
997 36 dgisselq
 
998 69 dgisselq
`ifdef  OPT_PIPELINED
999 71 dgisselq
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
1000 160 dgisselq
                        ? wr_gpreg_vl: r_opB;
1001 56 dgisselq
`else
1002
        assign  opB = r_opB;
1003
`endif
1004
 
1005 69 dgisselq
`ifdef  OPT_PIPELINED
1006 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
1007
        //      AND ... something that may write a (unknown) register is running
1008
        //      AND (series of conditions here ...)
1009
        //              The operation might set flags, and we wish to read the
1010
        //                      CC register
1011
        //              OR the operation might set register B, and we still need
1012
        //                      a clock to add the offset to it
1013
        assign  dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
1014
                                // If the op stage isn't valid, yet something
1015
                                // is running, then it must have been valid.
1016
                                // We'll use the last values from that stage
1017
                                // (opR_wr, opF_wr, opR) in our logic below.
1018
                                &&((opvalid)||(mem_rdbusy)
1019 132 dgisselq
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
1020 83 dgisselq
                                &&(
1021 145 dgisselq
                                // Okay, what happens if the result register
1022
                                // from instruction 1 becomes the input for
1023
                                // instruction two, *and* there's an immediate
1024
                                // offset in instruction two?  In that case, we
1025
                                // need an extra clock between the two 
1026
                                // instructions to calculate the base plus 
1027
                                // offset.
1028
                                //
1029
                                // What if instruction 1 (or before) is in a
1030
                                // memory pipeline?  We may no longer know what
1031
                                // the register was!  We will then need  to 
1032
                                // blindly wait.  We'll temper this only waiting
1033
                                // if we're not piping this new instruction.
1034
                                // If we were piping, the pipe logic in the
1035
                                // decode circuit has told us that the hazard
1036
                                // is clear, so we're okay then.
1037
                                //
1038 132 dgisselq
                                ((~dcd_zI)&&(
1039
                                        ((opR == dcdB)&&(opR_wr))
1040 145 dgisselq
                                        ||((mem_rdbusy)&&(~dcd_pipe))
1041
                                        ))
1042 83 dgisselq
                                // Stall following any instruction that will
1043
                                // set the flags, if we're going to need the
1044
                                // flags (CC) register for opB.
1045
                                ||((opF_wr)&&(dcdB_cc))
1046 38 dgisselq
                                // Stall on any ongoing memory operation that
1047 71 dgisselq
                                // will write to opB -- captured above
1048
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
1049
                                );
1050 91 dgisselq
        assign  dcdF_stall = ((~dcdF[3])
1051
                                        ||((dcdA_rd)&&(dcdA_cc))
1052
                                        ||((dcdB_rd)&&(dcdB_cc)))
1053
                                        &&(opvalid)&&(opR_cc);
1054
                                // &&(dcdvalid) is checked for elsewhere
1055 56 dgisselq
`else
1056 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
1057
        // hazard without the pipeline?
1058
        assign  dcdB_stall = 1'b0;
1059 91 dgisselq
        assign  dcdF_stall = 1'b0;
1060 56 dgisselq
`endif
1061 2 dgisselq
        //
1062
        //
1063
        //      PIPELINE STAGE #4 :: Apply Instruction
1064
        //
1065
        //
1066 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
1067 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1068 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
1069 71 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op,
1070
                        alu_busy);
1071 69 dgisselq
`else
1072
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1073
                        (opvalid_alu), opn, opA, opB,
1074
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
1075 71 dgisselq
        assign  alu_busy = 1'b0;
1076 69 dgisselq
`endif
1077 2 dgisselq
 
1078 69 dgisselq
        generate
1079
        if (IMPLEMENT_DIVIDE != 0)
1080
        begin
1081 83 dgisselq
                div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
1082 69 dgisselq
                        opA, opB, div_busy, div_valid, div_error, div_result,
1083
                        div_flags);
1084
        end else begin
1085
                assign  div_error = 1'b1;
1086
                assign  div_busy  = 1'b0;
1087
                assign  div_valid = 1'b0;
1088
                assign  div_result= 32'h00;
1089
                assign  div_flags = 4'h0;
1090
        end endgenerate
1091
 
1092
        generate
1093
        if (IMPLEMENT_FPU != 0)
1094
        begin
1095
                //
1096
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1097
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1098
                //      fpu_flags);
1099
                //
1100
                assign  fpu_error = 1'b1;
1101
                assign  fpu_busy  = 1'b0;
1102
                assign  fpu_valid = 1'b0;
1103
                assign  fpu_result= 32'h00;
1104
                assign  fpu_flags = 4'h0;
1105
        end else begin
1106
                assign  fpu_error = 1'b1;
1107
                assign  fpu_busy  = 1'b0;
1108
                assign  fpu_valid = 1'b0;
1109
                assign  fpu_result= 32'h00;
1110
                assign  fpu_flags = 4'h0;
1111
        end endgenerate
1112
 
1113
 
1114 2 dgisselq
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1115
        initial alF_wr   = 1'b0;
1116
        initial alu_wr   = 1'b0;
1117
        always @(posedge i_clk)
1118
                if (i_rst)
1119
                begin
1120
                        alu_wr   <= 1'b0;
1121
                        alF_wr   <= 1'b0;
1122
                end else if (alu_ce)
1123
                begin
1124 65 dgisselq
                        // alu_reg <= opR;
1125 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1126
                        alF_wr  <= (opF_wr)&&(set_cond);
1127 71 dgisselq
                end else if (~alu_busy) begin
1128 2 dgisselq
                        // These are strobe signals, so clear them if not
1129
                        // set for any particular clock
1130 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1131 2 dgisselq
                        alF_wr <= 1'b0;
1132
                end
1133 69 dgisselq
 
1134
`ifdef  OPT_VLIW
1135
        reg     r_alu_phase;
1136
        initial r_alu_phase = 1'b0;
1137 2 dgisselq
        always @(posedge i_clk)
1138 69 dgisselq
                if (i_rst)
1139
                        r_alu_phase <= 1'b0;
1140 160 dgisselq
                else if ((adf_ce_unconditional)||(mem_ce))
1141 69 dgisselq
                        r_alu_phase <= op_phase;
1142
        assign  alu_phase = r_alu_phase;
1143
`else
1144
        assign  alu_phase = 1'b0;
1145
`endif
1146
 
1147
        always @(posedge i_clk)
1148 160 dgisselq
                if (adf_ce_unconditional)
1149 65 dgisselq
                        alu_reg <= opR;
1150
                else if ((i_halt)&&(i_dbg_we))
1151
                        alu_reg <= i_dbg_reg;
1152 69 dgisselq
 
1153 132 dgisselq
        //
1154
        // DEBUG Register write access starts here
1155
        //
1156 65 dgisselq
        reg             dbgv;
1157
        initial dbgv = 1'b0;
1158
        always @(posedge i_clk)
1159 160 dgisselq
                dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
1160 132 dgisselq
        reg     [31:0]   dbg_val;
1161 65 dgisselq
        always @(posedge i_clk)
1162 132 dgisselq
                dbg_val <= i_dbg_data;
1163
        always @(posedge i_clk)
1164 160 dgisselq
                if ((adf_ce_unconditional)||(mem_ce))
1165 2 dgisselq
                        alu_gie  <= op_gie;
1166
        always @(posedge i_clk)
1167 160 dgisselq
                if ((adf_ce_unconditional)
1168
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1169 65 dgisselq
                                &&(~mem_stalled)))
1170 2 dgisselq
                        alu_pc  <= op_pc;
1171 65 dgisselq
 
1172 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1173 56 dgisselq
        reg     r_alu_illegal;
1174
        initial r_alu_illegal = 0;
1175 38 dgisselq
        always @(posedge i_clk)
1176 71 dgisselq
                if (clear_pipeline)
1177
                        r_alu_illegal <= 1'b0;
1178
                else if ((alu_ce)||(mem_ce))
1179 56 dgisselq
                        r_alu_illegal <= op_illegal;
1180
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1181 38 dgisselq
`endif
1182
 
1183 145 dgisselq
        initial r_alu_pc_valid = 1'b0;
1184 132 dgisselq
        initial mem_pc_valid = 1'b0;
1185 2 dgisselq
        always @(posedge i_clk)
1186 132 dgisselq
                if (i_rst)
1187 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1188 160 dgisselq
                else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
1189 145 dgisselq
                        r_alu_pc_valid <= 1'b1;
1190 160 dgisselq
                else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
1191 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1192 160 dgisselq
        assign  alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
1193 132 dgisselq
        always @(posedge i_clk)
1194
                if (i_rst)
1195
                        mem_pc_valid <= 1'b0;
1196
                else
1197
                        mem_pc_valid <= (mem_ce);
1198 2 dgisselq
 
1199 69 dgisselq
        wire    bus_lock;
1200
`ifdef  OPT_PIPELINED
1201
        generate
1202
        if (IMPLEMENT_LOCK != 0)
1203
        begin
1204 132 dgisselq
                reg     [1:0]    r_bus_lock;
1205
                initial r_bus_lock = 2'b00;
1206 69 dgisselq
                always @(posedge i_clk)
1207
                        if (i_rst)
1208 132 dgisselq
                                r_bus_lock <= 2'b00;
1209 69 dgisselq
                        else if ((op_ce)&&(op_lock))
1210 132 dgisselq
                                r_bus_lock <= 2'b11;
1211
                        else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
1212
                                r_bus_lock <= r_bus_lock + 2'b11;
1213
                assign  bus_lock = |r_bus_lock;
1214 69 dgisselq
        end else begin
1215
                assign  bus_lock = 1'b0;
1216
        end endgenerate
1217
`else
1218
        assign  bus_lock = 1'b0;
1219
`endif
1220
 
1221 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1222 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1223 38 dgisselq
                                (opn[0]), opB, opA, opR,
1224
                                mem_busy, mem_pipe_stalled,
1225
                                mem_valid, bus_err, mem_wreg, mem_result,
1226
                        mem_cyc_gbl, mem_cyc_lcl,
1227
                                mem_stb_gbl, mem_stb_lcl,
1228
                                mem_we, mem_addr, mem_data,
1229
                                mem_ack, mem_stall, mem_err, i_wb_data);
1230
 
1231
`else // PIPELINED_BUS_ACCESS
1232 71 dgisselq
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1233 2 dgisselq
                                (opn[0]), opB, opA, opR,
1234 38 dgisselq
                                mem_busy,
1235
                                mem_valid, bus_err, mem_wreg, mem_result,
1236 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1237
                                mem_stb_gbl, mem_stb_lcl,
1238
                                mem_we, mem_addr, mem_data,
1239
                                mem_ack, mem_stall, mem_err, i_wb_data);
1240 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1241 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1242 2 dgisselq
 
1243
        // Either the prefetch or the instruction gets the memory bus, but 
1244
        // never both.
1245 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1246 36 dgisselq
                // Memory access to the arbiter, priority position
1247
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1248
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1249 2 dgisselq
                // Prefetch access to the arbiter
1250 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1251
                        pf_ack, pf_stall, pf_err,
1252 2 dgisselq
                // Common wires, in and out, of the arbiter
1253 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1254
                        o_wb_we, o_wb_addr, o_wb_data,
1255
                        i_wb_ack, i_wb_stall, i_wb_err);
1256 2 dgisselq
 
1257 132 dgisselq
 
1258
 
1259 2 dgisselq
        //
1260
        //
1261 132 dgisselq
        //
1262
        //
1263
        //
1264
        //
1265
        //
1266
        //
1267 2 dgisselq
        //      PIPELINE STAGE #5 :: Write-back results
1268
        //
1269
        //
1270
        // This stage is not allowed to stall.  If results are ready to be
1271
        // written back, they are written back at all cost.  Sleepy CPU's
1272
        // won't prevent write back, nor debug modes, halting the CPU, nor
1273
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1274
        // as knowinig something is available for writeback.
1275
 
1276
        //
1277
        // Write back to our generic register set ...
1278
        // When shall we write back?  On one of two conditions
1279
        //      Note that the flags needed to be checked before issuing the
1280
        //      bus instruction, so they don't need to be checked here.
1281
        //      Further, alu_wr includes (set_cond), so we don't need to
1282
        //      check for that here either.
1283 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1284 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1285
                                ||((~clear_pipeline)&&(~alu_illegal)
1286
                                        &&(((alu_wr)&&(alu_valid))
1287
                                                ||(div_valid)||(fpu_valid)));
1288 36 dgisselq
`else
1289 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1290
                                ||((~clear_pipeline)
1291
                                        &&(((alu_wr)&&(alu_valid))
1292
                                                ||(div_valid)||(fpu_valid)));
1293 36 dgisselq
`endif
1294 2 dgisselq
        // Which register shall be written?
1295 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1296
        //              One or PC, one for CC, and one for GIE match
1297 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1298
        //      FPU operation.
1299 160 dgisselq
        assign  wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
1300 25 dgisselq
        // Are we writing to the CC register?
1301
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1302 2 dgisselq
        // Are we writing to the PC?
1303
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1304
        // What value to write?
1305 160 dgisselq
        assign  wr_gpreg_vl = ((mem_valid) ? mem_result
1306 71 dgisselq
                                :((div_valid|fpu_valid))
1307
                                        ? ((div_valid) ? div_result:fpu_result)
1308
                                :((dbgv) ? dbg_val : alu_result));
1309 160 dgisselq
        assign  wr_spreg_vl = ((mem_valid) ? mem_result
1310
                                :((dbgv) ? dbg_val : alu_result));
1311 2 dgisselq
        always @(posedge i_clk)
1312
                if (wr_reg_ce)
1313 160 dgisselq
                        regset[wr_reg_id] <= wr_gpreg_vl;
1314 2 dgisselq
 
1315
        //
1316
        // Write back to the condition codes/flags register ...
1317
        // When shall we write to our flags register?  alF_wr already
1318
        // includes the set condition ...
1319 69 dgisselq
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1320 83 dgisselq
        assign  w_uflags = { uhalt_phase, ufpu_err_flag,
1321 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1322
                        1'b0, step, 1'b1, sleep,
1323
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1324 83 dgisselq
        assign  w_iflags = { ihalt_phase, ifpu_err_flag,
1325 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1326
                        break_en, 1'b0, 1'b0, sleep,
1327
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1328 69 dgisselq
 
1329
 
1330 2 dgisselq
        // What value to write?
1331
        always @(posedge i_clk)
1332
                // If explicitly writing the register itself
1333 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1334 160 dgisselq
                        flags <= wr_gpreg_vl[3:0];
1335 2 dgisselq
                // Otherwise if we're setting the flags from an ALU operation
1336
                else if ((wr_flags_ce)&&(alu_gie))
1337 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1338
                                : alu_flags);
1339 2 dgisselq
 
1340
        always @(posedge i_clk)
1341 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1342 160 dgisselq
                        iflags <= wr_gpreg_vl[3:0];
1343 2 dgisselq
                else if ((wr_flags_ce)&&(~alu_gie))
1344 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1345
                                : alu_flags);
1346 2 dgisselq
 
1347
        // The 'break' enable  bit.  This bit can only be set from supervisor
1348
        // mode.  It control what the CPU does upon encountering a break
1349
        // instruction.
1350
        //
1351
        // The goal, upon encountering a break is that the CPU should stop and
1352
        // not execute the break instruction, choosing instead to enter into
1353
        // either interrupt mode or halt first.  
1354
        //      if ((break_en) AND (break_instruction)) // user mode or not
1355
        //              HALT CPU
1356
        //      else if (break_instruction) // only in user mode
1357
        //              set an interrupt flag, go to supervisor mode
1358
        //              allow supervisor to step the CPU.
1359
        //      Upon a CPU halt, any break condition will be reset.  The
1360
        //      external debugger will then need to deal with whatever
1361
        //      condition has taken place.
1362
        initial break_en = 1'b0;
1363
        always @(posedge i_clk)
1364
                if ((i_rst)||(i_halt))
1365
                        break_en <= 1'b0;
1366 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1367 160 dgisselq
                        break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
1368 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1369 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1370
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1371 160 dgisselq
                                &&(~alu_busy)
1372 69 dgisselq
                                &&(~div_busy)&&(~fpu_busy)
1373 36 dgisselq
                                &&(~clear_pipeline)
1374
                        ||((~alu_gie)&&(bus_err))
1375 69 dgisselq
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1376
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
1377 71 dgisselq
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
1378 36 dgisselq
`else
1379
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1380
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1381 160 dgisselq
                                &&(~alu_busy)&&(~div_busy)&&(~fpu_busy)
1382 36 dgisselq
                                &&(~clear_pipeline))
1383 118 dgisselq
                        ||((~alu_gie)&&(bus_err))
1384
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1385
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));
1386 36 dgisselq
`endif
1387 2 dgisselq
 
1388
 
1389
        // The sleep register.  Setting the sleep register causes the CPU to
1390
        // sleep until the next interrupt.  Setting the sleep register within
1391
        // interrupt mode causes the processor to halt until a reset.  This is
1392 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1393
        // set the sleep bit and switch to supervisor mode in the same 
1394
        // instruction: users are not allowed to halt the CPU.
1395 2 dgisselq
        always @(posedge i_clk)
1396 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1397 2 dgisselq
                        sleep <= 1'b0;
1398 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1399
                        // In supervisor mode, we have no protections.  The
1400
                        // supervisor can set the sleep bit however he wants.
1401 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1402
                        // sleep mode shouold only be possible if the interrupt
1403
                        // flag isn't set.
1404 160 dgisselq
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
1405 69 dgisselq
                        //              don't set the sleep bit
1406
                        //      otherwise however it would o.w. be set
1407 160 dgisselq
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
1408
                                &&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
1409
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
1410 25 dgisselq
                        // In user mode, however, you can only set the sleep
1411
                        // mode while remaining in user mode.  You can't switch
1412
                        // to sleep mode *and* supervisor mode at the same
1413
                        // time, lest you halt the CPU.
1414 160 dgisselq
                        sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
1415 2 dgisselq
 
1416
        always @(posedge i_clk)
1417
                if ((i_rst)||(w_switch_to_interrupt))
1418
                        step <= 1'b0;
1419 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1420 160 dgisselq
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
1421 132 dgisselq
                else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
1422 2 dgisselq
                        step <= 1'b0;
1423
 
1424
        // The GIE register.  Only interrupts can disable the interrupt register
1425
        assign  w_switch_to_interrupt = (gie)&&(
1426
                        // On interrupt (obviously)
1427 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1428 2 dgisselq
                        // If we are stepping the CPU
1429 132 dgisselq
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
1430 2 dgisselq
                        // If we encounter a break instruction, if the break
1431 36 dgisselq
                        //      enable isn't set.
1432 69 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
1433
                                &&(op_break)&&(~break_en))
1434 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1435 36 dgisselq
                        // On an illegal instruction
1436 71 dgisselq
                        ||((alu_pc_valid)&&(alu_illegal))
1437 36 dgisselq
`endif
1438 71 dgisselq
                        // On division by zero.  If the divide isn't
1439
                        // implemented, div_valid and div_error will be short
1440
                        // circuited and that logic will be bypassed
1441
                        ||((div_valid)&&(div_error))
1442
                        // Same thing on a floating point error.
1443
                        ||((fpu_valid)&&(fpu_error))
1444
                        //      
1445 69 dgisselq
                        ||(bus_err)
1446 2 dgisselq
                        // If we write to the CC register
1447 160 dgisselq
                        ||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
1448 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1449 2 dgisselq
                        );
1450
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1451
                        // Then if we write the CC register
1452 160 dgisselq
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
1453 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1454 2 dgisselq
                        );
1455
        always @(posedge i_clk)
1456
                if (i_rst)
1457
                        gie <= 1'b0;
1458
                else if (w_switch_to_interrupt)
1459
                        gie <= 1'b0;
1460
                else if (w_release_from_interrupt)
1461
                        gie <= 1'b1;
1462
 
1463 25 dgisselq
        initial trap = 1'b0;
1464
        always @(posedge i_clk)
1465
                if (i_rst)
1466
                        trap <= 1'b0;
1467 132 dgisselq
                else if (w_release_from_interrupt)
1468
                        trap <= 1'b0;
1469 160 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
1470 69 dgisselq
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
1471 25 dgisselq
                        trap <= 1'b1;
1472 132 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_id[4]))
1473 160 dgisselq
                        trap <= wr_spreg_vl[`CPU_TRAP_BIT];
1474 25 dgisselq
 
1475 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1476 65 dgisselq
        initial ill_err_i = 1'b0;
1477 36 dgisselq
        always @(posedge i_clk)
1478
                if (i_rst)
1479 65 dgisselq
                        ill_err_i <= 1'b0;
1480 132 dgisselq
                // Only the debug interface can clear this bit
1481 65 dgisselq
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1482 160 dgisselq
                                &&(~wr_spreg_vl[`CPU_ILL_BIT]))
1483 65 dgisselq
                        ill_err_i <= 1'b0;
1484 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
1485 65 dgisselq
                        ill_err_i <= 1'b1;
1486
        initial ill_err_u = 1'b0;
1487
        always @(posedge i_clk)
1488
                if (i_rst)
1489
                        ill_err_u <= 1'b0;
1490
                // The bit is automatically cleared on release from interrupt
1491 36 dgisselq
                else if (w_release_from_interrupt)
1492 65 dgisselq
                        ill_err_u <= 1'b0;
1493
                // If the supervisor writes to this register, clearing the
1494
                // bit, then clear it
1495
                else if (((~alu_gie)||(dbgv))
1496 160 dgisselq
                                &&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_ILL_BIT])
1497 65 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1498
                        ill_err_u <= 1'b0;
1499 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
1500 65 dgisselq
                        ill_err_u <= 1'b1;
1501 38 dgisselq
`else
1502 65 dgisselq
        assign ill_err_u = 1'b0;
1503
        assign ill_err_i = 1'b0;
1504 36 dgisselq
`endif
1505 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1506
        // ever set.
1507
        initial ibus_err_flag = 1'b0;
1508 36 dgisselq
        always @(posedge i_clk)
1509
                if (i_rst)
1510 65 dgisselq
                        ibus_err_flag <= 1'b0;
1511
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1512 160 dgisselq
                                &&(~wr_spreg_vl[`CPU_BUSERR_BIT]))
1513 65 dgisselq
                        ibus_err_flag <= 1'b0;
1514
                else if ((bus_err)&&(~alu_gie))
1515
                        ibus_err_flag <= 1'b1;
1516
        // User bus error flag -- if ever set, it will cause an interrupt to
1517
        // supervisor mode.  
1518
        initial ubus_err_flag = 1'b0;
1519
        always @(posedge i_clk)
1520
                if (i_rst)
1521
                        ubus_err_flag <= 1'b0;
1522 36 dgisselq
                else if (w_release_from_interrupt)
1523 65 dgisselq
                        ubus_err_flag <= 1'b0;
1524
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1525 160 dgisselq
                                &&(~wr_spreg_vl[`CPU_BUSERR_BIT])
1526 65 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1527
                        ubus_err_flag <= 1'b0;
1528 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1529 65 dgisselq
                        ubus_err_flag <= 1'b1;
1530 36 dgisselq
 
1531 69 dgisselq
        generate
1532
        if (IMPLEMENT_DIVIDE != 0)
1533
        begin
1534
                reg     r_idiv_err_flag, r_udiv_err_flag;
1535
 
1536
                // Supervisor/interrupt divide (by zero) error flag -- this will
1537
                // crash the CPU if ever set.  This bit is thus available for us
1538
                // to be able to tell if/why the CPU crashed.
1539
                initial r_idiv_err_flag = 1'b0;
1540
                always @(posedge i_clk)
1541
                        if (i_rst)
1542
                                r_idiv_err_flag <= 1'b0;
1543
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1544 160 dgisselq
                                        &&(~wr_spreg_vl[`CPU_DIVERR_BIT]))
1545 69 dgisselq
                                r_idiv_err_flag <= 1'b0;
1546
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
1547
                                r_idiv_err_flag <= 1'b1;
1548
                // User divide (by zero) error flag -- if ever set, it will
1549
                // cause a sudden switch interrupt to supervisor mode.  
1550
                initial r_udiv_err_flag = 1'b0;
1551
                always @(posedge i_clk)
1552
                        if (i_rst)
1553
                                r_udiv_err_flag <= 1'b0;
1554
                        else if (w_release_from_interrupt)
1555
                                r_udiv_err_flag <= 1'b0;
1556
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1557 160 dgisselq
                                        &&(~wr_spreg_vl[`CPU_DIVERR_BIT])
1558 69 dgisselq
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1559
                                r_udiv_err_flag <= 1'b0;
1560
                        else if ((div_error)&&(alu_gie)&&(div_valid))
1561
                                r_udiv_err_flag <= 1'b1;
1562
 
1563
                assign  idiv_err_flag = r_idiv_err_flag;
1564
                assign  udiv_err_flag = r_udiv_err_flag;
1565
        end else begin
1566
                assign  idiv_err_flag = 1'b0;
1567
                assign  udiv_err_flag = 1'b0;
1568
        end endgenerate
1569
 
1570
        generate
1571
        if (IMPLEMENT_FPU !=0)
1572
        begin
1573
                // Supervisor/interrupt floating point error flag -- this will
1574
                // crash the CPU if ever set.
1575
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1576
                initial r_ifpu_err_flag = 1'b0;
1577
                always @(posedge i_clk)
1578
                        if (i_rst)
1579
                                r_ifpu_err_flag <= 1'b0;
1580
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1581 160 dgisselq
                                        &&(~wr_spreg_vl[`CPU_FPUERR_BIT]))
1582 69 dgisselq
                                r_ifpu_err_flag <= 1'b0;
1583
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1584
                                r_ifpu_err_flag <= 1'b1;
1585
                // User floating point error flag -- if ever set, it will cause
1586
                // a sudden switch interrupt to supervisor mode.  
1587
                initial r_ufpu_err_flag = 1'b0;
1588
                always @(posedge i_clk)
1589
                        if (i_rst)
1590
                                r_ufpu_err_flag <= 1'b0;
1591
                        else if (w_release_from_interrupt)
1592
                                r_ufpu_err_flag <= 1'b0;
1593
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1594 160 dgisselq
                                        &&(~wr_spreg_vl[`CPU_FPUERR_BIT])
1595 69 dgisselq
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1596
                                r_ufpu_err_flag <= 1'b0;
1597
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1598
                                r_ufpu_err_flag <= 1'b1;
1599
 
1600
                assign  ifpu_err_flag = r_ifpu_err_flag;
1601
                assign  ufpu_err_flag = r_ufpu_err_flag;
1602
        end else begin
1603
                assign  ifpu_err_flag = 1'b0;
1604
                assign  ufpu_err_flag = 1'b0;
1605
        end endgenerate
1606
 
1607
`ifdef  OPT_VLIW
1608
        reg             r_ihalt_phase, r_uhalt_phase;
1609
 
1610
        initial r_ihalt_phase = 0;
1611
        initial r_uhalt_phase = 0;
1612
        always @(posedge i_clk)
1613
                if (~alu_gie)
1614
                        r_ihalt_phase <= alu_phase;
1615
        always @(posedge i_clk)
1616
                if (alu_gie)
1617
                        r_uhalt_phase <= alu_phase;
1618
                else if (w_release_from_interrupt)
1619
                        r_uhalt_phase <= 1'b0;
1620
 
1621
        assign  ihalt_phase = r_ihalt_phase;
1622
        assign  uhalt_phase = r_uhalt_phase;
1623
`else
1624
        assign  ihalt_phase = 1'b0;
1625
        assign  uhalt_phase = 1'b0;
1626
`endif
1627
 
1628 2 dgisselq
        //
1629
        // Write backs to the PC register, and general increments of it
1630
        //      We support two: upc and ipc.  If the instruction is normal,
1631
        // we increment upc, if interrupt level we increment ipc.  If
1632
        // the instruction writes the PC, we write whichever PC is appropriate.
1633
        //
1634
        // Do we need to all our partial results from the pipeline?
1635
        // What happens when the pipeline has gie and ~gie instructions within
1636
        // it?  Do we clear both?  What if a gie instruction tries to clear
1637
        // a non-gie instruction?
1638
        always @(posedge i_clk)
1639 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1640 160 dgisselq
                        upc <= wr_spreg_vl[(AW-1):0];
1641 132 dgisselq
                else if ((alu_gie)&&
1642
                                (((alu_pc_valid)&&(~clear_pipeline))
1643
                                ||(mem_pc_valid)))
1644 2 dgisselq
                        upc <= alu_pc;
1645
 
1646
        always @(posedge i_clk)
1647
                if (i_rst)
1648
                        ipc <= RESET_ADDRESS;
1649
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1650 160 dgisselq
                        ipc <= wr_spreg_vl[(AW-1):0];
1651 132 dgisselq
                else if ((~alu_gie)&&
1652
                                (((alu_pc_valid)&&(~clear_pipeline))
1653
                                ||(mem_pc_valid)))
1654 2 dgisselq
                        ipc <= alu_pc;
1655
 
1656
        always @(posedge i_clk)
1657
                if (i_rst)
1658
                        pf_pc <= RESET_ADDRESS;
1659
                else if (w_switch_to_interrupt)
1660
                        pf_pc <= ipc;
1661
                else if (w_release_from_interrupt)
1662
                        pf_pc <= upc;
1663
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1664 160 dgisselq
                        pf_pc <= wr_spreg_vl[(AW-1):0];
1665 69 dgisselq
`ifdef  OPT_PIPELINED
1666 105 dgisselq
                else if ((dcd_early_branch)&&(~clear_pipeline))
1667 69 dgisselq
                        pf_pc <= dcd_branch_pc + 1;
1668
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1669 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1670 69 dgisselq
`else
1671 145 dgisselq
                else if ((alu_gie==gie)&&(
1672
                                ((alu_pc_valid)&&(~clear_pipeline))
1673
                                ||(mem_pc_valid)))
1674 69 dgisselq
                        pf_pc <= alu_pc;
1675
`endif
1676 2 dgisselq
 
1677
        initial new_pc = 1'b1;
1678
        always @(posedge i_clk)
1679 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1680 2 dgisselq
                        new_pc <= 1'b1;
1681
                else if (w_switch_to_interrupt)
1682
                        new_pc <= 1'b1;
1683
                else if (w_release_from_interrupt)
1684
                        new_pc <= 1'b1;
1685
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1686
                        new_pc <= 1'b1;
1687
                else
1688
                        new_pc <= 1'b0;
1689
 
1690
        //
1691
        // The debug interface
1692 56 dgisselq
        generate
1693
        if (AW<32)
1694
        begin
1695
                always @(posedge i_clk)
1696 2 dgisselq
                begin
1697
                        o_dbg_reg <= regset[i_dbg_reg];
1698
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1699 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1700 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1701 56 dgisselq
                        begin
1702 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1703 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1704
                        end
1705 2 dgisselq
                end
1706 56 dgisselq
        end else begin
1707
                always @(posedge i_clk)
1708
                begin
1709
                        o_dbg_reg <= regset[i_dbg_reg];
1710
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1711
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1712
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1713
                        begin
1714 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1715 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1716
                        end
1717
                end
1718
        end endgenerate
1719
 
1720 2 dgisselq
        always @(posedge i_clk)
1721 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1722 18 dgisselq
 
1723
        always @(posedge i_clk)
1724 160 dgisselq
                r_halted <= (i_halt)&&(
1725 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1726 160 dgisselq
                        ||(alu_busy)||(div_busy)||(fpu_busy)
1727 132 dgisselq
                        ||((~opvalid)&&(~i_rst)&&(~dcd_illegal))
1728
                        ||((~dcdvalid)&&(~i_rst)&&(~pf_illegal)));
1729 160 dgisselq
        assign  o_dbg_stall = r_halted;
1730 2 dgisselq
 
1731
        //
1732
        //
1733
        // Produce accounting outputs: Account for any CPU stalls, so we can
1734
        // later evaluate how well we are doing.
1735
        //
1736
        //
1737 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1738 9 dgisselq
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1739 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1740 56 dgisselq
 
1741 65 dgisselq
`ifdef  DEBUG_SCOPE
1742 56 dgisselq
        always @(posedge i_clk)
1743 65 dgisselq
                o_debug <= {
1744 132 dgisselq
                        o_break, i_wb_err, pf_pc[1:0],
1745
                        flags,
1746 56 dgisselq
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1747
                        op_ce, alu_ce, mem_ce,
1748 65 dgisselq
                        //
1749
                        master_ce, opvalid_alu, opvalid_mem,
1750
                        //
1751
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1752
                        mem_we,
1753
                        // ((opvalid_alu)&&(alu_stall))
1754
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1755
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1756
                        // opA[23:20], opA[3:0],
1757 160 dgisselq
                        gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
1758 71 dgisselq
                /*
1759 69 dgisselq
                        i_rst, master_ce, (new_pc),
1760
                        ((dcd_early_branch)&&(dcdvalid)),
1761
                        pf_valid, pf_illegal,
1762
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1763
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1764
                        pf_pc[7:0], pf_addr[7:0]
1765 71 dgisselq
                */
1766 132 dgisselq
                /*
1767
                        i_wb_err, gie, alu_illegal,
1768
                              (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
1769
                        mem_busy,
1770
                                (mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
1771
                                        o_wb_addr[8:0] }
1772
                                        : { instruction[31:21] },
1773
                        pf_valid, (pf_valid) ? alu_pc[14:0]
1774
                                :{ pf_cyc, pf_stb, pf_pc[12:0] }
1775
                */
1776
                /*
1777
                        i_wb_err, gie, new_pc, dcd_early_branch,        // 4
1778
                        pf_valid, pf_cyc, pf_stb, instruction_pc[0],    // 4
1779
                        instruction[30:27],                             // 4
1780
                        dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb,  // 4
1781
                        dcdvalid,
1782
                        ((dcd_early_branch)&&(~clear_pipeline))         // 15
1783
                                        ? dcd_branch_pc[14:0]:pf_pc[14:0]
1784
                */
1785 56 dgisselq
                        };
1786 65 dgisselq
`endif
1787 56 dgisselq
 
1788 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.