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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9
//              The instruction set is about as RISC as you can get, there are
10
//              only 16 instruction types supported (of which one isn't yet
11
//              supported ...)  Please see the accompanying iset.html file
12
//              for a description of these instructions.
13
//
14
//              All instructions are 32-bits wide.  All bus accesses, both
15
//              address and data, are 32-bits over a wishbone bus.
16
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19
//              1. Prefetch, returns the instruction from memory.  On the
20
//              Basys board that I'm working on, one instruction may be
21
//              issued every 20 clocks or so, unless and until I implement a
22
//              cache or local memory.
23
//
24
//              2. Instruction Decode
25
//
26
//              3. Read Operands
27
//
28
//              4. Apply Instruction
29
//
30
//              4. Write-back Results
31
//
32
//      A lot of difficult work has been placed into the pipeline stall
33
//      handling.  My original proposal was not to allow pipeline stalls at all.
34
//      The idea would be that the CPU would just run every clock and whatever
35
//      stalled answer took place would just get fixed a clock or two later,
36
//      meaning that the compiler could just schedule everything out.
37
//      This idea died at the memory interface, which can take a variable
38
//      amount of time to read or write any value, thus the whole CPU needed
39
//      to stall on a stalled memory access.
40
//
41
//      My next idea was to just let things complete.  I.e., once an instrution
42
//      starts, it continues to completion no matter what and we go on.  This
43
//      failed at writing the PC.  If the PC gets written in something such as
44
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
45
//      later, if whether or not something happens in those clocks depends
46
//      upon the instruction fetch filling the pipeline, then the CPU has a
47
//      non-deterministic behavior.
48
//
49
//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
51
//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
53
//      read or a write, there is no undoing it--since peripherals on the
54
//      bus may act upon the answer with whatever side effects they might
55
//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
94
// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
99
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
104
//              http://www.gnu.org/licenses/gpl.html
105
//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109
`define CPU_PC_REG      4'hf
110
`define CPU_CC_REG      4'he
111
`define CPU_BREAK_BIT   7
112
`define CPU_STEP_BIT    6
113
`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
115
module  zipcpu(i_clk, i_rst, i_interrupt,
116
                // Debug interface
117
                i_halt, i_dbg_reg, i_dbg_we, i_dbg_data,
118
                        o_dbg_stall, o_dbg_reg,
119
                        o_break,
120
                // CPU interface to the wishbone bus
121
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
122
                        i_wb_ack, i_wb_stall, i_wb_data,
123
                // Accounting/CPU usage interface
124
                o_mem_stall, o_pf_stall, o_alu_stall);
125
        parameter       RESET_ADDRESS=32'h0100000;
126
        input                   i_clk, i_rst, i_interrupt;
127
        // Debug interface -- inputs
128
        input                   i_halt;
129
        input           [4:0]    i_dbg_reg;
130
        input                   i_dbg_we;
131
        input           [31:0]   i_dbg_data;
132
        // Debug interface -- outputs
133
        output  reg             o_dbg_stall;
134
        output  reg     [31:0]   o_dbg_reg;
135
        output  wire            o_break;
136
        // Wishbone interface -- outputs
137
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
138
        output  wire    [31:0]   o_wb_addr, o_wb_data;
139
        // Wishbone interface -- inputs
140
        input                   i_wb_ack, i_wb_stall;
141
        input           [31:0]   i_wb_data;
142
        // Accounting outputs ... to help us count stalls and usage
143
        output  wire            o_mem_stall;
144
        output  wire            o_pf_stall;
145
        output  wire            o_alu_stall;
146
 
147
 
148
        // Registers
149
        reg     [31:0]   regset [0:31];
150
        reg     [3:0]    flags, iflags;  // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
151
        wire            master_ce;
152
        wire    [7:0]    w_uflags, w_iflags;
153
        reg             step, gie, sleep, break_en;
154
 
155
        wire    [4:0]    mem_wreg;
156
        wire            mem_busy, mem_rdbusy;
157
 
158
        reg     [31:0]   pf_pc;
159
        reg             new_pc;
160
 
161
        //
162
        //
163
        //      PIPELINE STAGE #1 :: Prefetch
164
        //              Variable declarations
165
        //
166
        wire            pf_ce, dcd_stalled;
167
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
168
        wire    [31:0]   pf_addr, pf_data;
169
        wire    [31:0]   instruction, instruction_pc;
170
        wire    pf_valid, instruction_gie;
171
 
172
        //
173
        //
174
        //      PIPELINE STAGE #2 :: Instruction Decode
175
        //              Variable declarations
176
        //
177
        //
178
        reg             opvalid, op_wr_pc, op_break;
179
        wire            op_stall, dcd_ce;
180
        reg     [3:0]    dcdOp;
181
        reg     [4:0]    dcdA, dcdB;
182
        reg     [3:0]    dcdF;
183
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
184
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
185
        reg     [31:0]   dcd_pc;
186
        reg     [23:0]   r_dcdI;
187
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
188
 
189
 
190
 
191
        //
192
        //
193
        //      PIPELINE STAGE #3 :: Read Operands
194
        //              Variable declarations
195
        //
196
        //
197
        //
198
        // Now, let's read our operands
199
        reg     [4:0]    alu_reg;
200
        reg     [3:0]    opn;
201
        reg     [4:0]    opR;
202
        reg     [1:0]    opA_cc, opB_cc;
203
        reg     [31:0]   r_opA, r_opB, op_pc;
204
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
205
        reg             opR_wr, opM, opF_wr, op_gie,
206
                        opA_rd, opB_rd;
207
        reg     [7:0]    opFl;
208
        // reg  [6:0]   r_opF;
209
        wire    [8:0]    opF;
210
        wire            op_ce;
211
 
212
 
213
 
214
        //
215
        //
216
        //      PIPELINE STAGE #4 :: ALU / Memory
217
        //              Variable declarations
218
        //
219
        //
220
        reg     [31:0]   alu_pc;
221
        reg             alu_pc_valid;;
222
        wire            alu_ce, alu_stall;
223
        wire    [31:0]   alu_result;
224
        wire    [3:0]    alu_flags;
225
        wire            alu_valid;
226
        wire            set_cond;
227
        reg             alu_wr, alF_wr, alu_gie;
228
 
229
 
230
 
231
        wire    mem_ce, mem_stalled;
232
        wire    mem_valid, mem_ack, mem_stall,
233
                mem_cyc, mem_stb, mem_we;
234
        wire    [31:0]   mem_addr, mem_data, mem_result;
235
 
236
 
237
 
238
        //
239
        //
240
        //      PIPELINE STAGE #5 :: Write-back
241
        //              Variable declarations
242
        //
243
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc;
244
        wire    [4:0]    wr_reg_id;
245
        wire    [31:0]   wr_reg_vl;
246
        wire    w_switch_to_interrupt, w_release_from_interrupt;
247
        reg     [31:0]   upc, ipc;
248
 
249
 
250
 
251
        //
252
        //      MASTER: clock enable.
253
        //
254
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep)&&(~mem_rdbusy);
255
 
256
 
257
        //
258
        //      PIPELINE STAGE #1 :: Prefetch
259
        //              Calculate stall conditions
260
        assign          pf_ce = (~dcd_stalled);
261
 
262
        //
263
        //      PIPELINE STAGE #2 :: Instruction Decode
264
        //              Calculate stall conditions
265
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
266
        assign          dcd_stalled = (dcdvalid)&&(
267
                                        (op_stall)
268
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
269
                                        ||((opvalid)&&(op_wr_pc)));
270
        //
271
        //      PIPELINE STAGE #3 :: Read Operands
272
        //              Calculate stall conditions
273
        assign  op_stall = (opvalid)&&(
274
                                ((mem_stalled)&&(opM))
275
                                ||((alu_stall)&&(~opM)));
276
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
277
 
278
        //
279
        //      PIPELINE STAGE #4 :: ALU / Memory
280
        //              Calculate stall conditions
281
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
282
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
283
        assign  alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~new_pc);
284
        //
285
        assign  mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~new_pc)&&(set_cond);
286
        assign  mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
287
                                (~master_ce)
288
                                // Stall waiting for flags to be valid
289
                                ||((~opF[8])&&(
290
                                        ((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))))
291
                                        // Do I need this last condition?
292
                                        //||((wr_flags_ce)&&(alu_gie==op_gie))))
293
                                // Or waiting for a write to the PC register
294
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&(wr_write_pc))));
295
 
296
 
297
        //
298
        //
299
        //      PIPELINE STAGE #1 :: Prefetch
300
        //
301
        //
302
`ifdef  SINGLE_FETCH
303
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
304
                                instruction, instruction_pc, instruction_gie,
305
                                        pf_valid,
306
                                pf_cyc, pf_stb, pf_we, pf_addr,
307
                                        pf_data,
308
                                pf_ack, pf_stall, i_wb_data);
309
`else // Pipe fetch
310
        pipefetch       pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
311
                                        instruction, instruction_pc, pf_valid,
312
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
313
                                pf_ack, pf_stall, i_wb_data);
314
        assign  instruction_gie = gie;
315
`endif
316
 
317
        always @(posedge i_clk)
318
                if (i_rst)
319
                        dcdvalid <= 1'b0;
320
                else if (dcd_ce)
321
                        dcdvalid <= (~new_pc);
322
                else if ((~dcd_stalled)||(new_pc))
323
                        dcdvalid <= 1'b0;
324
 
325
        always @(posedge i_clk)
326
                if (dcd_ce)
327
                begin
328
                        dcd_pc <= instruction_pc+1;
329
 
330
                        // Record what operation we are doing
331
                        dcdOp <= instruction[31:28];
332
 
333
                        // Default values
334
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
335
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
336
                        dcdM    <= 1'b0;
337
                        dcdF_wr <= 1'b1;
338
                        dcd_break <= 1'b0;
339
 
340
                        // Set the condition under which we do this operation
341
                        // The top four bits are a mask, the bottom four the
342
                        // value the flags must equal once anded with the mask
343
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
344
                        casez(instruction[31:28])
345
                        4'h2: begin // Move instruction
346
                                if (~instruction_gie)
347
                                begin
348
                                        dcdA[4] <= instruction[20];
349
                                        dcdB[4] <= instruction[15];
350
                                end
351
                                dcdA_wr <= 1'b1;
352
                                dcdA_rd <= 1'b0;
353
                                dcdB_rd <= 1'b1;
354
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
355
                                dcdF_wr <= 1'b0; // Don't write flags
356
                                end
357
                        4'h3: begin // Load immediate
358
                                dcdA_wr <= 1'b1;
359
                                dcdA_rd <= 1'b0;
360
                                dcdB_rd <= 1'b0;
361
                                r_dcdI <= { instruction[23:0] };
362
                                dcdF_wr <= 1'b0; // Don't write flags
363
                                dcdF    <= 4'h8; // This is unconditional
364
                                dcdOp <= 4'h2;
365
                                end
366
                        4'h4: begin // Load immediate special
367
                                dcdF_wr <= 1'b0; // Don't write flags
368
                                r_dcdI <= { 8'h00, instruction[15:0] };
369
                                if (instruction[27:24] == 4'he)
370
                                begin
371
                                        // NOOP instruction
372
                                        dcdA_wr <= 1'b0;
373
                                        dcdA_rd <= 1'b0;
374
                                        dcdB_rd <= 1'b0;
375
                                        dcdOp <= 4'h2;
376
                                        dcd_break <= 1'b1;//Could be a break ins
377
                                end else if (instruction[27:24] == 4'hf)
378
                                begin // Load partial immediate(s)
379
                                        dcdA_wr <= 1'b1;
380
                                        dcdA_rd <= 1'b1;
381
                                        dcdB_rd <= 1'b0;
382
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
383
                                        dcdOp <= { 3'h3, instruction[20] };
384
                                end else begin
385
                                        ; // Multiply instruction place holder
386
                                end end
387
                        4'b011?: begin // Load/Store
388
                                dcdF_wr <= 1'b0; // Don't write flags
389
                                dcdA_wr <= (~instruction[28]); // Write on loads
390
                                dcdA_rd <= (instruction[28]); // Read on stores
391
                                dcdB_rd <= instruction[20];
392
                                if (instruction[20])
393
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
394
                                else
395
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
396
                                dcdM <= 1'b1; // Memory operation
397
                                end
398
                        default: begin
399
                                dcdA <= { instruction_gie, instruction[27:24] };
400
                                dcdB <= { instruction_gie, instruction[19:16] };
401
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
402
                                dcdA_rd <= 1'b1;
403
                                dcdB_rd <= instruction[20];
404
                                if (instruction[20])
405
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
406
                                else
407
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
408
                                end
409
                        endcase
410
 
411
 
412
                        dcd_gie <= instruction_gie;
413
                end
414
 
415
 
416
        //
417
        //
418
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
419
        //
420
        //
421
 
422
        always @(posedge i_clk)
423
                if (op_ce) // &&(dcdvalid))
424
                begin
425
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
426
                                r_opA <= wr_reg_vl;
427
                        else if (dcdA == { dcd_gie, `CPU_PC_REG })
428
                                r_opA <= dcd_pc;
429
                        else if (dcdA[3:0] == `CPU_PC_REG)
430
                                r_opA <= (dcdA[4])?upc:ipc;
431
                        else
432
                                r_opA <= regset[dcdA];
433
                end
434
        wire    [31:0]   dcdI;
435
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
436
        always @(posedge i_clk)
437
                if (op_ce) // &&(dcdvalid))
438
                begin
439
                        if (~dcdB_rd)
440
                                r_opB <= dcdI;
441
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
442
                                r_opB <= wr_reg_vl + dcdI;
443
                        else if (dcdB == { dcd_gie, `CPU_PC_REG })
444
                                r_opB <= dcd_pc + dcdI;
445
                        else if (dcdB[3:0] == `CPU_PC_REG)
446
                                r_opB <= ((dcdB[4])?upc:ipc) + dcdI;
447
                        else
448
                                r_opB <= regset[dcdB] + dcdI;
449
                end
450
 
451
        // The logic here has become more complex than it should be, no thanks
452
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
453
        // be two sets of four bits: the top bits specify what bits matter, the
454
        // bottom specify what those top bits must equal.  However, two of
455
        // conditions check whether bits are on, and those are the only two
456
        // conditions checking those bits.  Therefore, Vivado complains that
457
        // these two bits are redundant.  Hence the convoluted expression
458
        // below, arriving at what we finally want in the (now wire net)
459
        // opF.
460
`ifdef  NEWCODE
461
        always @(posedge i_clk)
462
                if (op_ce)
463
                begin // Set the flag condition codes
464
                        case(dcdF[2:0])
465
                        3'h0:   r_opF <= 7'h80; // Always
466
                        3'h1:   r_opF <= 7'h11; // Z
467
                        3'h2:   r_opF <= 7'h10; // NE
468
                        3'h3:   r_opF <= 7'h20; // GE (!N)
469
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
470
                        3'h5:   r_opF <= 7'h24; // LT
471
                        3'h6:   r_opF <= 7'h02; // C
472
                        3'h7:   r_opF <= 7'h08; // V
473
                        endcase
474
                end
475
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
476
`else
477
        always @(posedge i_clk)
478
                if (op_ce)
479
                begin // Set the flag condition codes
480
                        case(dcdF[2:0])
481
                        3'h0:   opF <= 9'h100;  // Always
482
                        3'h1:   opF <= 9'h011;  // Z
483
                        3'h2:   opF <= 9'h010;  // NE
484
                        3'h3:   opF <= 9'h040;  // GE (!N)
485
                        3'h4:   opF <= 9'h050;  // GT (!N&!Z)
486
                        3'h5:   opF <= 9'h044;  // LT
487
                        3'h6:   opF <= 9'h022;  // C
488
                        3'h7:   opF <= 9'h088;  // V
489
                        endcase
490
                end
491
`endif
492
 
493
        always @(posedge i_clk)
494
                if (i_rst)
495
                        opvalid <= 1'b0;
496
                else if (op_ce)
497
                        // Do we have a valid instruction?
498
                        //   The decoder may vote to stall one of its
499
                        //   instructions based upon something we currently
500
                        //   have in our queue.  This instruction must then
501
                        //   move forward, and get a stall cycle inserted.
502
                        //   Hence, the test on dcd_stalled here.  If we must
503
                        //   wait until our operands are valid, then we aren't
504
                        //   valid yet until then.
505
                        opvalid<= (~new_pc)&&(dcdvalid)&&(~dcd_stalled);
506
                else if ((~op_stall)||(new_pc))
507
                        opvalid <= 1'b0;
508
 
509
        // Here's part of our debug interface.  When we recognize a break
510
        // instruction, we set the op_break flag.  That'll prevent this
511
        // instruction from entering the ALU, and cause an interrupt before
512
        // this instruction.  Thus, returning to this code will cause the
513
        // break to repeat and continue upon return.  To get out of this
514
        // condition, replace the break instruction with what it is supposed
515
        // to be, step through it, and then replace it back.  In this fashion,
516
        // a debugger can step through code.
517
        always @(posedge i_clk)
518
                if (i_rst)
519
                        op_break <= 1'b0;
520
                else if (op_ce)
521
                        op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
522
                else if ((~op_stall)||(new_pc))
523
                        op_break <= 1'b0;
524
 
525
        always @(posedge i_clk)
526
                if (op_ce)
527
                begin
528
                        opn    <= dcdOp;        // Which ALU operation?
529
                        opM    <= dcdM;         // Is this a memory operation?
530
                        // Will we write the flags/CC Register with our result?
531
                        opF_wr <= dcdF_wr;
532
                        // Will we be writing our results into a register?
533
                        opR_wr <= dcdA_wr;
534
                        // What register will these results be written into?
535
                        opR    <= dcdA;
536
                        // User level (1), vs supervisor (0)/interrupts disabled
537
                        op_gie <= dcd_gie;
538
 
539
                        // We're not done with these yet--we still need them
540
                        // for the unclocked assign.  We need the unclocked
541
                        // assign so that there's no wait state between an
542
                        // ALU or memory result and the next register that may
543
                        // use that value.
544
                        opA_cc <= {dcdA[4], (dcdA[3:0] == `CPU_CC_REG) };
545
                        opA_rd <= dcdA_rd;
546
                        opB_cc <= {dcdB[4], (dcdB[3:0] == `CPU_CC_REG) };
547
                        opB_rd <= dcdB_rd;
548
                        op_pc  <= dcd_pc;
549
                        //
550
                        op_wr_pc <= ((dcdA_wr)&&(dcdA[3:0] == `CPU_PC_REG));
551
                end
552
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
553
 
554
        // This is tricky.  First, the PC and Flags registers aren't kept in
555
        // register set but in special registers of their own.  So step one
556
        // is to select the right register.  Step to is to replace that
557
        // register with the results of an ALU or memory operation, if such
558
        // results are now available.  Otherwise, we'd need to insert a wait
559
        // state of some type.
560
        //
561
        // The alternative approach would be to define some sort of
562
        // op_stall wire, which would stall any upstream stage.
563
        // We'll create a flag here to start our coordination.  Once we
564
        // define this flag to something other than just plain zero, then
565
        // the stalls will already be in place.
566
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&
567
                                (((opvalid)&&(opR_wr)&&(opR == dcdA))
568
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))
569
                                        ||((mem_valid)&&(mem_wreg == dcdA)));
570
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)
571
                                &&(((opvalid)&&(opR_wr)&&(opR == dcdB))
572
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))
573
                                        ||((mem_valid)&&(mem_wreg == dcdB)));
574
        assign  dcdF_stall = (dcdvalid)&&(((dcdF[3])
575
                                        ||(dcdA[3:0]==`CPU_CC_REG)
576
                                        ||(dcdB[3:0]==`CPU_CC_REG))
577
                                &&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
578
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
579
        assign  opA = { r_opA[31:8], ((opA_cc[0]) ?
580
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
581
        assign  opB = { r_opB[31:8], ((opB_cc[0]) ?
582
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
583
 
584
        //
585
        //
586
        //      PIPELINE STAGE #4 :: Apply Instruction
587
        //
588
        //
589
        cpuops  doalu(i_clk, i_rst, alu_ce,
590
                        (opvalid)&&(~opM), opn, opA, opB,
591
                        alu_result, alu_flags, alu_valid);
592
 
593
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
594
        initial alF_wr   = 1'b0;
595
        initial alu_wr   = 1'b0;
596
        always @(posedge i_clk)
597
                if (i_rst)
598
                begin
599
                        alu_wr   <= 1'b0;
600
                        alF_wr   <= 1'b0;
601
                end else if (alu_ce)
602
                begin
603
                        alu_reg <= opR;
604
                        alu_wr  <= (opR_wr)&&(set_cond);
605
                        alF_wr  <= (opF_wr)&&(set_cond);
606
                end else begin
607
                        // These are strobe signals, so clear them if not
608
                        // set for any particular clock
609
                        alu_wr <= 1'b0;
610
                        alF_wr <= 1'b0;
611
                end
612
        always @(posedge i_clk)
613
                if ((alu_ce)||(mem_ce))
614
                        alu_gie  <= op_gie;
615
        always @(posedge i_clk)
616
                if ((alu_ce)||(mem_ce))
617
                        alu_pc  <= op_pc;
618
        initial alu_pc_valid = 1'b0;
619
        always @(posedge i_clk)
620
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~new_pc)
621
                                        &&((~opM)
622
                                                ||(~mem_stalled));
623
 
624
        memops  domem(i_clk, i_rst, mem_ce,
625
                                (opn[0]), opB, opA, opR,
626
                                mem_busy, mem_valid, mem_wreg, mem_result,
627
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
628
                                mem_ack, mem_stall, i_wb_data);
629
        assign  mem_rdbusy = ((mem_cyc)&&(~mem_we));
630
 
631
        // Either the prefetch or the instruction gets the memory bus, but 
632
        // never both.
633
        wbarbiter       #(32,32) pformem(i_clk, i_rst,
634
                // Prefetch access to the arbiter
635
                pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall,
636
                // Memory access to the arbiter
637
                mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall,
638
                // Common wires, in and out, of the arbiter
639
                o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack,
640
                        i_wb_stall);
641
 
642
        //
643
        //
644
        //      PIPELINE STAGE #5 :: Write-back results
645
        //
646
        //
647
        // This stage is not allowed to stall.  If results are ready to be
648
        // written back, they are written back at all cost.  Sleepy CPU's
649
        // won't prevent write back, nor debug modes, halting the CPU, nor
650
        // anything else.  Indeed, the (master_ce) bit is only as relevant
651
        // as knowinig something is available for writeback.
652
 
653
        //
654
        // Write back to our generic register set ...
655
        // When shall we write back?  On one of two conditions
656
        //      Note that the flags needed to be checked before issuing the
657
        //      bus instruction, so they don't need to be checked here.
658
        //      Further, alu_wr includes (set_cond), so we don't need to
659
        //      check for that here either.
660
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
661
        // Which register shall be written?
662
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
663
        // Are we writing to the PC?
664
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
665
        // What value to write?
666
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
667
        always @(posedge i_clk)
668
                if (wr_reg_ce)
669
                        regset[wr_reg_id] <= wr_reg_vl;
670
 
671
        //
672
        // Write back to the condition codes/flags register ...
673
        // When shall we write to our flags register?  alF_wr already
674
        // includes the set condition ...
675
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
676
        assign  w_uflags = { 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
677
        assign  w_iflags = { break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
678
        // What value to write?
679
        always @(posedge i_clk)
680
                // If explicitly writing the register itself
681
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
682
                        flags <= wr_reg_vl[3:0];
683
                // Otherwise if we're setting the flags from an ALU operation
684
                else if ((wr_flags_ce)&&(alu_gie))
685
                        flags <= alu_flags;
686
                else if ((i_halt)&&(i_dbg_we)
687
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
688
                        flags <= i_dbg_data[3:0];
689
 
690
        always @(posedge i_clk)
691
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
692
                        iflags <= wr_reg_vl[3:0];
693
                else if ((wr_flags_ce)&&(~alu_gie))
694
                        iflags <= alu_flags;
695
                else if ((i_halt)&&(i_dbg_we)
696
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
697
                        iflags <= i_dbg_data[3:0];
698
 
699
        // The 'break' enable  bit.  This bit can only be set from supervisor
700
        // mode.  It control what the CPU does upon encountering a break
701
        // instruction.
702
        //
703
        // The goal, upon encountering a break is that the CPU should stop and
704
        // not execute the break instruction, choosing instead to enter into
705
        // either interrupt mode or halt first.  
706
        //      if ((break_en) AND (break_instruction)) // user mode or not
707
        //              HALT CPU
708
        //      else if (break_instruction) // only in user mode
709
        //              set an interrupt flag, go to supervisor mode
710
        //              allow supervisor to step the CPU.
711
        //      Upon a CPU halt, any break condition will be reset.  The
712
        //      external debugger will then need to deal with whatever
713
        //      condition has taken place.
714
        initial break_en = 1'b0;
715
        always @(posedge i_clk)
716
                if ((i_rst)||(i_halt))
717
                        break_en <= 1'b0;
718
                else if ((wr_reg_ce)&&(wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}))
719
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
720
        assign  o_break = (break_en)&&(op_break);
721
 
722
 
723
        // The sleep register.  Setting the sleep register causes the CPU to
724
        // sleep until the next interrupt.  Setting the sleep register within
725
        // interrupt mode causes the processor to halt until a reset.  This is
726
        // a panic/fault halt.
727
        always @(posedge i_clk)
728
                if ((i_rst)||((i_interrupt)&&(gie)))
729
                        sleep <= 1'b0;
730
                else if ((wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG))
731
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
732
                else if ((i_halt)&&(i_dbg_we)
733
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
734
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
735
 
736
        always @(posedge i_clk)
737
                if ((i_rst)||(w_switch_to_interrupt))
738
                        step <= 1'b0;
739
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4:0] == {1'b1,`CPU_CC_REG}))
740
                        step <= wr_reg_vl[`CPU_STEP_BIT];
741
                else if ((i_halt)&&(i_dbg_we)
742
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
743
                        step <= i_dbg_data[`CPU_STEP_BIT];
744
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
745
                        step <= 1'b0;
746
 
747
        // The GIE register.  Only interrupts can disable the interrupt register
748
        assign  w_switch_to_interrupt = (gie)&&(
749
                        // On interrupt (obviously)
750
                        (i_interrupt)
751
                        // If we are stepping the CPU
752
                        ||((master_ce)&&(alu_pc_valid)&&(step))
753
                        // If we encounter a break instruction, if the break
754
                        //      enable isn't not set.
755
                        ||((master_ce)&&(op_break))
756
                        // If we write to the CC register
757
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
758
                                &&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
759
                        // Or if, in debug mode, we write to the CC register
760
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
761
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
762
                        );
763
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
764
                        // Then if we write the CC register
765
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
766
                                &&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
767
                        // Or if, in debug mode, we write the CC register
768
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
769
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
770
                        );
771
        always @(posedge i_clk)
772
                if (i_rst)
773
                        gie <= 1'b0;
774
                else if (w_switch_to_interrupt)
775
                        gie <= 1'b0;
776
                else if (w_release_from_interrupt)
777
                        gie <= 1'b1;
778
 
779
        //
780
        // Write backs to the PC register, and general increments of it
781
        //      We support two: upc and ipc.  If the instruction is normal,
782
        // we increment upc, if interrupt level we increment ipc.  If
783
        // the instruction writes the PC, we write whichever PC is appropriate.
784
        //
785
        // Do we need to all our partial results from the pipeline?
786
        // What happens when the pipeline has gie and ~gie instructions within
787
        // it?  Do we clear both?  What if a gie instruction tries to clear
788
        // a non-gie instruction?
789
        always @(posedge i_clk)
790
                if (i_rst)
791
                        upc <= RESET_ADDRESS;
792
                else if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
793
                        upc <= wr_reg_vl;
794
                else if ((alu_gie)&&(alu_pc_valid))
795
                        upc <= alu_pc;
796
                else if ((i_halt)&&(i_dbg_we)
797
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
798
                        upc <= i_dbg_data;
799
 
800
        always @(posedge i_clk)
801
                if (i_rst)
802
                        ipc <= RESET_ADDRESS;
803
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
804
                        ipc <= wr_reg_vl;
805
                else if ((~alu_gie)&&(alu_pc_valid))
806
                        ipc <= alu_pc;
807
                else if ((i_halt)&&(i_dbg_we)
808
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
809
                        ipc <= i_dbg_data;
810
 
811
        always @(posedge i_clk)
812
                if (i_rst)
813
                        pf_pc <= RESET_ADDRESS;
814
                else if (w_switch_to_interrupt)
815
                        pf_pc <= ipc;
816
                else if (w_release_from_interrupt)
817
                        pf_pc <= upc;
818
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
819
                        pf_pc <= wr_reg_vl;
820
                else if ((i_halt)&&(i_dbg_we)
821
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
822
                        pf_pc <= i_dbg_data;
823
                // else if (pf_ce)
824
                else if (dcd_ce)
825
                        pf_pc <= pf_pc + 1;
826
 
827
        initial new_pc = 1'b1;
828
        always @(posedge i_clk)
829
                if (i_rst)
830
                        new_pc <= 1'b1;
831
                else if (w_switch_to_interrupt)
832
                        new_pc <= 1'b1;
833
                else if (w_release_from_interrupt)
834
                        new_pc <= 1'b1;
835
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
836
                        new_pc <= 1'b1;
837
                else if ((i_halt)&&(i_dbg_we)
838
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
839
                        new_pc <= 1'b1;
840
                else
841
                        new_pc <= 1'b0;
842
 
843
        //
844
        // The debug interface
845
        always @(posedge i_clk)
846
                begin
847
                        o_dbg_reg <= regset[i_dbg_reg];
848
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
849
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
850
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
851
                                o_dbg_reg <= { 25'h00, step, gie, sleep,
852
                                        ((i_dbg_reg[4])?flags:iflags) };
853
                end
854
        always @(posedge i_clk)
855
                o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
856
                        ||((~opvalid)&&(~i_rst))
857
                        ||((~dcdvalid)&&(~i_rst));
858
 
859
        //
860
        //
861
        // Produce accounting outputs: Account for any CPU stalls, so we can
862
        // later evaluate how well we are doing.
863
        //
864
        //
865
        assign  o_mem_stall  = (~i_halt)&&(~sleep)&&(opvalid)&&(mem_busy)
866
                                        &&(~pf_cyc);
867
        assign  o_pf_stall   = (~i_halt)&&(~sleep)&&(((pf_ce)&&(~pf_valid))
868
                                        ||((opvalid)&&(mem_busy)&&(pf_cyc)));
869
        // assign       o_alu_stall  = (~i_halt)&&(~sleep)&&(~mem_busy)&&
870
                                        // ((alu_stall)||(~alu_valid));
871
        assign  o_alu_stall  = alu_pc_valid;
872
endmodule

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