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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, with only 26 instruction types currently supported.
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//      (There are still 8-instruction Op-Codes reserved for floating point,
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//      and 5 which can be used for transactions not requiring registers.)
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
19
//      The Zip CPU is fully pipelined with the following pipeline stages:
20
//
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//              1. Prefetch, returns the instruction from memory.
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//
23
//              2. Instruction Decode
24
//
25
//              3. Read Operands
26
//
27
//              4. Apply Instruction
28
//
29
//              4. Write-back Results
30
//
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//      Further information about the inner workings of this CPU, such as
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//      what causes pipeline stalls, may be found in the spec.pdf file.  (The
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//      documentation within this file had become out of date and out of sync
34
//      with the spec.pdf, so look to the spec.pdf for accurate and up to date
35
//      information.)
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//
37
//
38 69 dgisselq
//      In general, the pipelining is controlled by three pieces of logic
39
//      per stage: _ce, _stall, and _valid.  _valid means that the stage
40
//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
43
//      The difference between these control signals allows individual stages
44
//      to propagate instructions independently.  In general, the logic works
45
//      as:
46
//
47
//
48 205 dgisselq
//      assign  (n)_ce = (n-1)_valid && (!(n)_stall)
49 69 dgisselq
//
50
//
51
//      always @(posedge i_clk)
52
//              if ((i_rst)||(clear_pipeline))
53
//                      (n)_valid = 0
54
//              else if (n)_ce
55
//                      (n)_valid = 1
56
//              else if (n+1)_ce
57
//                      (n)_valid = 0
58
//
59
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
60
//                      || (  (n)_valid && (n+1)_stall );
61
//
62
//      and ...
63
//
64
//      always @(posedge i_clk)
65
//              if (n)_ce
66
//                      (n)_variable = ... whatever logic for this stage
67
//
68
//      Note that a stage can stall even if no instruction is loaded into
69
//      it.
70
//
71
//
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// Creator:     Dan Gisselquist, Ph.D.
73 69 dgisselq
//              Gisselquist Technology, LLC
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//
75 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
77 201 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
83
//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
87
// for more details.
88
//
89 201 dgisselq
// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
92
// <http://www.gnu.org/licenses/> for a copy.
93
//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
96
//
97
//
98 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
99 2 dgisselq
//
100 36 dgisselq
//
101
//
102 25 dgisselq
`define CPU_CC_REG      4'he
103 2 dgisselq
`define CPU_PC_REG      4'hf
104 193 dgisselq
`define CPU_CLRCACHE_BIT 14     // Set to clear the I-cache, automatically clears
105 201 dgisselq
`define CPU_PHASE_BIT   13      // Set if we are executing the latter half of a CIS
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`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
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`define CPU_STEP_BIT    6       // Will step one (or two CIS) instructions
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`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
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// Compile time defines
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//
117
`include "cpudefs.v"
118
//
119 65 dgisselq
//
120 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
122 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
125
                // CPU interface to the wishbone bus
126 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
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                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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                        i_wb_ack, i_wb_stall, i_wb_data,
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                        i_wb_err,
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                // Accounting/CPU usage interface
132 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
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        parameter [31:0] RESET_ADDRESS=32'h0100000;
138
        parameter       ADDRESS_WIDTH=30,
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                        LGICACHE=8;
140 56 dgisselq
`ifdef  OPT_MULTIPLY
141 132 dgisselq
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
142 56 dgisselq
`else
143
        parameter       IMPLEMENT_MPY = 0;
144
`endif
145 71 dgisselq
`ifdef  OPT_DIVIDE
146
        parameter       IMPLEMENT_DIVIDE = 1;
147
`else
148
        parameter       IMPLEMENT_DIVIDE = 0;
149
`endif
150
`ifdef  OPT_IMPLEMENT_FPU
151
        parameter       IMPLEMENT_FPU = 1,
152
`else
153
        parameter       IMPLEMENT_FPU = 0,
154
`endif
155 69 dgisselq
                        IMPLEMENT_LOCK=1;
156
`ifdef  OPT_EARLY_BRANCHING
157
        parameter       EARLY_BRANCHING = 1;
158
`else
159
        parameter       EARLY_BRANCHING = 0;
160
`endif
161 201 dgisselq
        parameter       WITH_LOCAL_BUS = 1;
162 193 dgisselq
        localparam      AW=ADDRESS_WIDTH;
163 201 dgisselq
        localparam      [(AW-1):0]       RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2];
164 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
165
        // Debug interface -- inputs
166 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
167 2 dgisselq
        input           [4:0]    i_dbg_reg;
168
        input                   i_dbg_we;
169
        input           [31:0]   i_dbg_data;
170
        // Debug interface -- outputs
171 160 dgisselq
        output  wire            o_dbg_stall;
172 2 dgisselq
        output  reg     [31:0]   o_dbg_reg;
173 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
174 2 dgisselq
        output  wire            o_break;
175
        // Wishbone interface -- outputs
176 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
177
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
178 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
179
        output  wire    [31:0]   o_wb_data;
180 201 dgisselq
        output  wire    [3:0]    o_wb_sel;
181 2 dgisselq
        // Wishbone interface -- inputs
182
        input                   i_wb_ack, i_wb_stall;
183
        input           [31:0]   i_wb_data;
184 36 dgisselq
        input                   i_wb_err;
185 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
186 9 dgisselq
        output  wire            o_op_stall;
187 2 dgisselq
        output  wire            o_pf_stall;
188 9 dgisselq
        output  wire            o_i_count;
189 56 dgisselq
        //
190 65 dgisselq
`ifdef  DEBUG_SCOPE
191 56 dgisselq
        output  reg     [31:0]   o_debug;
192 65 dgisselq
`endif
193 2 dgisselq
 
194 25 dgisselq
 
195 2 dgisselq
        // Registers
196 56 dgisselq
        //
197
        //      The distributed RAM style comment is necessary on the
198
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
199
        // set and in the process ruining everything else.  It basically
200
        // optimizes logic away, to where it no longer works.  The logic
201
        // as described herein will work, this just makes sure XST implements
202
        // that logic.
203
        //
204
        (* ram_style = "distributed" *)
205 201 dgisselq
`ifdef  OPT_NO_USERMODE
206
        reg     [31:0]   regset [0:15];
207
`else
208 2 dgisselq
        reg     [31:0]   regset [0:31];
209 201 dgisselq
`endif
210 9 dgisselq
 
211
        // Condition codes
212 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
213
        reg     [3:0]    flags, iflags;
214 179 dgisselq
        wire    [14:0]   w_uflags, w_iflags;
215 201 dgisselq
        reg             break_en, step, sleep, r_halted;
216
        wire            break_pending, trap, gie, ubreak;
217
        wire            w_clear_icache, ill_err_u;
218
        reg             ill_err_i;
219
        reg             ibus_err_flag;
220
        wire            ubus_err_flag;
221 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
222
        wire            ifpu_err_flag, ufpu_err_flag;
223
        wire            ihalt_phase, uhalt_phase;
224 2 dgisselq
 
225 9 dgisselq
        // The master chip enable
226
        wire            master_ce;
227 2 dgisselq
 
228
        //
229
        //
230
        //      PIPELINE STAGE #1 :: Prefetch
231
        //              Variable declarations
232
        //
233 201 dgisselq
        reg     [(AW+1):0]       pf_pc;
234 69 dgisselq
        reg     new_pc;
235 18 dgisselq
        wire    clear_pipeline;
236 179 dgisselq
        assign  clear_pipeline = new_pc;
237 9 dgisselq
 
238
        wire            dcd_stalled;
239 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
240 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
241
        wire    [31:0]           pf_data;
242 201 dgisselq
        wire    [31:0]           pf_instruction;
243
        wire    [(AW-1):0]       pf_instruction_pc;
244
        wire    pf_valid, pf_gie, pf_illegal;
245 2 dgisselq
 
246
        //
247
        //
248
        //      PIPELINE STAGE #2 :: Instruction Decode
249
        //              Variable declarations
250
        //
251
        //
252 201 dgisselq
        reg             op_valid /* verilator public_flat */,
253
                        op_valid_mem, op_valid_alu;
254
        reg             op_valid_div, op_valid_fpu;
255 69 dgisselq
        wire            op_stall, dcd_ce, dcd_phase;
256 201 dgisselq
        wire    [3:0]    dcd_opn;
257
        wire    [4:0]    dcd_A, dcd_B, dcd_R;
258
        wire            dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc;
259
        wire    [3:0]    dcd_F;
260
        wire            dcd_wR, dcd_rA, dcd_rB,
261
                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
262
                                dcd_wF, dcd_gie, dcd_break, dcd_lock,
263 105 dgisselq
                                dcd_pipe, dcd_ljmp;
264 201 dgisselq
        wire            dcd_valid;
265
        wire    [AW:0]   dcd_pc /* verilator public_flat */;
266
        wire    [31:0]   dcd_I;
267
        wire            dcd_zI; // true if dcd_I == 0
268
        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;
269 2 dgisselq
 
270 69 dgisselq
        wire    dcd_illegal;
271
        wire                    dcd_early_branch;
272 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
273 2 dgisselq
 
274 201 dgisselq
        wire            dcd_sim;
275
        wire    [22:0]   dcd_sim_immv;
276 2 dgisselq
 
277 201 dgisselq
 
278 2 dgisselq
        //
279
        //
280
        //      PIPELINE STAGE #3 :: Read Operands
281
        //              Variable declarations
282
        //
283
        //
284
        //
285
        // Now, let's read our operands
286
        reg     [4:0]    alu_reg;
287 201 dgisselq
        wire    [3:0]    op_opn;
288
        wire    [4:0]    op_R;
289
        reg     [31:0]   r_op_Av, r_op_Bv;
290 48 dgisselq
        reg     [(AW-1):0]       op_pc;
291 201 dgisselq
        wire    [31:0]   w_op_Av, w_op_Bv;
292
        wire    [31:0]   op_A_nowait, op_B_nowait, op_Av, op_Bv;
293
        reg             op_wR, op_wF;
294
        wire            op_gie, op_Rcc;
295
        wire    [14:0]   op_Fl;
296
        reg     [6:0]    r_op_F;
297
        wire    [7:0]    op_F;
298 160 dgisselq
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
299 56 dgisselq
        // Some pipeline control wires
300 36 dgisselq
        reg     op_illegal;
301 179 dgisselq
        wire    op_break;
302 69 dgisselq
        wire    op_lock;
303 2 dgisselq
 
304 201 dgisselq
`ifdef  VERILATOR
305
        reg             op_sim          /* verilator public_flat */;
306
        reg     [22:0]   op_sim_immv     /* verilator public_flat */;
307
`endif
308 2 dgisselq
 
309 201 dgisselq
 
310 2 dgisselq
        //
311
        //
312
        //      PIPELINE STAGE #4 :: ALU / Memory
313
        //              Variable declarations
314
        //
315
        //
316 179 dgisselq
        wire    [(AW-1):0]       alu_pc;
317 145 dgisselq
        reg             r_alu_pc_valid, mem_pc_valid;
318
        wire            alu_pc_valid;
319 69 dgisselq
        wire            alu_phase;
320 201 dgisselq
        wire            alu_ce /* verilator public_flat */, alu_stall;
321 2 dgisselq
        wire    [31:0]   alu_result;
322
        wire    [3:0]    alu_flags;
323 71 dgisselq
        wire            alu_valid, alu_busy;
324 2 dgisselq
        wire            set_cond;
325 201 dgisselq
        reg             alu_wR, alu_wF;
326 193 dgisselq
        wire            alu_gie, alu_illegal;
327 2 dgisselq
 
328
 
329
 
330
        wire    mem_ce, mem_stalled;
331 38 dgisselq
        wire    mem_pipe_stalled;
332 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
333
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
334 48 dgisselq
        wire    [4:0]            mem_wreg;
335 9 dgisselq
 
336 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
337
        wire    [(AW-1):0]       mem_addr;
338
        wire    [31:0]           mem_data, mem_result;
339 201 dgisselq
        wire    [3:0]            mem_sel;
340 2 dgisselq
 
341 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
342
        wire    [31:0]   div_result;
343
        wire    [3:0]    div_flags;
344 2 dgisselq
 
345 205 dgisselq
        assign  div_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_div)
346
                                &&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy)
347 69 dgisselq
                                &&(set_cond);
348 2 dgisselq
 
349 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
350
        wire    [31:0]   fpu_result;
351
        wire    [3:0]    fpu_flags;
352
 
353 205 dgisselq
        assign  fpu_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_fpu)
354
                                &&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy)
355 69 dgisselq
                                &&(set_cond);
356
 
357 179 dgisselq
        wire    adf_ce_unconditional;
358 69 dgisselq
 
359 2 dgisselq
        //
360
        //
361
        //      PIPELINE STAGE #5 :: Write-back
362
        //              Variable declarations
363
        //
364 179 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
365
                        wr_write_scc, wr_write_ucc;
366 2 dgisselq
        wire    [4:0]    wr_reg_id;
367 160 dgisselq
        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;
368 2 dgisselq
        wire    w_switch_to_interrupt, w_release_from_interrupt;
369 201 dgisselq
        reg     [(AW+1):0]       ipc;
370
        wire    [(AW+1):0]       upc;
371 2 dgisselq
 
372
 
373
 
374
        //
375
        //      MASTER: clock enable.
376
        //
377 205 dgisselq
        assign  master_ce = ((!i_halt)||(alu_phase))&&(!o_break)&&(!sleep);
378 2 dgisselq
 
379
 
380
        //
381
        //      PIPELINE STAGE #1 :: Prefetch
382
        //              Calculate stall conditions
383 65 dgisselq
        //
384
        //      These are calculated externally, within the prefetch module.
385
        //
386 2 dgisselq
 
387
        //
388
        //      PIPELINE STAGE #2 :: Instruction Decode
389
        //              Calculate stall conditions
390 145 dgisselq
 
391 69 dgisselq
`ifdef  OPT_PIPELINED
392 201 dgisselq
        assign          dcd_stalled = (dcd_valid)&&(op_stall);
393 205 dgisselq
`else // Not pipelined -- either double or single fetch
394
        assign          dcd_stalled = (dcd_valid)&&(op_stall);
395 69 dgisselq
`endif
396 2 dgisselq
        //
397
        //      PIPELINE STAGE #3 :: Read Operands
398
        //              Calculate stall conditions
399 201 dgisselq
        wire    prelock_stall;
400 69 dgisselq
`ifdef  OPT_PIPELINED
401 179 dgisselq
        reg     cc_invalid_for_dcd;
402
        always @(posedge i_clk)
403
                cc_invalid_for_dcd <= (wr_flags_ce)
404
                        ||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
405 201 dgisselq
                        ||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG)))
406
                        ||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG)))
407 179 dgisselq
                        ||(mem_busy)||(div_busy)||(fpu_busy);
408
 
409 201 dgisselq
        assign  op_stall = (op_valid)&&( // Only stall if we're loaded w/validins
410 69 dgisselq
                        // Stall if we're stopped, and not allowed to execute
411
                        // an instruction
412 205 dgisselq
                        // (!master_ce)         // Already captured in alu_stall
413 69 dgisselq
                        //
414 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
415
                        //      i.e. if the memory is busy, or we are single
416 69 dgisselq
                        //      stepping.  This also includes our stalls for
417
                        //      op_break and op_lock, so we don't need to
418
                        //      include those as well here.
419 83 dgisselq
                        // This also includes whether or not the divide or
420
                        // floating point units are busy.
421
                        (alu_stall)
422 201 dgisselq
                        ||(((op_valid_div)||(op_valid_fpu))
423
                                &&(!adf_ce_unconditional))
424 56 dgisselq
                        //
425
                        // Stall if we are going into memory with an operation
426
                        //      that cannot be pipelined, and the memory is
427
                        //      already busy
428 201 dgisselq
                        ||(mem_stalled) // &&(op_valid_mem) part of mem_stalled
429
                        ||(op_Rcc)
430 69 dgisselq
                        )
431 201 dgisselq
                        ||(dcd_valid)&&(
432 71 dgisselq
                                // Stall if we need to wait for an operand A
433 69 dgisselq
                                // to be ready to read
434 201 dgisselq
                                (dcd_A_stall)
435 69 dgisselq
                                // Likewise for B, also includes logic
436
                                // regarding immediate offset (register must
437
                                // be in register file if we need to add to
438
                                // an immediate)
439 201 dgisselq
                                ||(dcd_B_stall)
440 69 dgisselq
                                // Or if we need to wait on flags to work on the
441
                                // CC register
442 201 dgisselq
                                ||(dcd_F_stall)
443 69 dgisselq
                        );
444 201 dgisselq
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
445 179 dgisselq
 
446 205 dgisselq
`else
447
        assign  op_stall = (alu_busy)||(div_busy)||(fpu_busy)||(wr_reg_ce)
448
                        ||(mem_busy)||(op_valid)||(!master_ce)||(wr_flags_ce);
449
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
450
`endif
451 179 dgisselq
 
452 160 dgisselq
        // BUT ... op_ce is too complex for many of the data operations.  So
453
        // let's make their circuit enable code simpler.  In particular, if
454
        // op_ doesn't need to be preserved, we can change it all we want
455
        // ... right?  The clear_pipeline code, for example, really only needs
456 201 dgisselq
        // to determine whether op_valid is true.
457 205 dgisselq
        assign  op_change_data_ce = (!op_stall);
458 2 dgisselq
 
459
        //
460
        //      PIPELINE STAGE #4 :: ALU / Memory
461
        //              Calculate stall conditions
462 36 dgisselq
        //
463
        // 1. Basic stall is if the previous stage is valid and the next is
464 201 dgisselq
        //      busy.
465 36 dgisselq
        // 2. Also stall if the prior stage is valid and the master clock enable
466
        //      is de-selected
467 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
468
        //      since we don't know if it'll put us to sleep or not.
469 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
470
        //      through the ALU.  Break instructions are not allowed through
471
        //      the ALU.
472 69 dgisselq
`ifdef  OPT_PIPELINED
473 205 dgisselq
        assign  alu_stall = (((!master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2
474 201 dgisselq
                        ||(prelock_stall)
475
                        ||((op_valid)&&(op_break))
476 179 dgisselq
                        ||(wr_reg_ce)&&(wr_write_cc)
477 69 dgisselq
                        ||(div_busy)||(fpu_busy);
478 205 dgisselq
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)
479
                                &&(!clear_pipeline);
480 69 dgisselq
`else
481 205 dgisselq
        assign  alu_stall = (op_valid_alu)&&((!master_ce)||(op_break));
482
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)&&(!clear_pipeline);
483 69 dgisselq
`endif
484 2 dgisselq
        //
485 65 dgisselq
 
486
        //
487
        // Note: if you change the conditions for mem_ce, you must also change
488
        // alu_pc_valid.
489
        //
490 205 dgisselq
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(!mem_stalled)
491
                        &&(!clear_pipeline);
492
 
493 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
494 205 dgisselq
        assign  mem_stalled = (!master_ce)||(alu_busy)||((op_valid_mem)&&(
495 38 dgisselq
                                (mem_pipe_stalled)
496 201 dgisselq
                                ||(prelock_stall)
497 205 dgisselq
                                ||((!op_pipe)&&(mem_busy))
498 69 dgisselq
                                ||(div_busy)
499
                                ||(fpu_busy)
500 38 dgisselq
                                // Stall waiting for flags to be valid
501
                                // Or waiting for a write to the PC register
502
                                // Or CC register, since that can change the
503
                                //  PC as well
504
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
505
                                        &&((wr_write_pc)||(wr_write_cc)))));
506
`else
507 69 dgisselq
`ifdef  OPT_PIPELINED
508 201 dgisselq
        assign  mem_stalled = (mem_busy)||((op_valid_mem)&&(
509 205 dgisselq
                                (!master_ce)
510 2 dgisselq
                                // Stall waiting for flags to be valid
511
                                // Or waiting for a write to the PC register
512 25 dgisselq
                                // Or CC register, since that can change the
513
                                //  PC as well
514
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
515 69 dgisselq
`else
516 205 dgisselq
        assign  mem_stalled = (op_valid_mem)&&(!master_ce);
517 38 dgisselq
`endif
518 69 dgisselq
`endif
519 2 dgisselq
 
520 179 dgisselq
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
521 205 dgisselq
        assign  adf_ce_unconditional = (master_ce)&&(!clear_pipeline)&&(op_valid)
522
                                &&(!op_valid_mem)&&(!mem_rdbusy)
523
                                &&((!op_valid_alu)||(!alu_stall))&&(!op_break)
524
                                &&(!div_busy)&&(!fpu_busy)&&(!clear_pipeline);
525 2 dgisselq
 
526
        //
527
        //
528
        //      PIPELINE STAGE #1 :: Prefetch
529
        //
530
        //
531 205 dgisselq
        wire    pf_stalled;
532
        assign  pf_stalled = (dcd_stalled)||(dcd_phase);
533
 
534
        wire    pf_new_pc;
535
        assign  pf_new_pc = (new_pc)||((dcd_early_branch)&&(!clear_pipeline));
536
 
537
        wire    [(AW-1):0]       pf_request_address;
538
        assign  pf_request_address = ((dcd_early_branch)&&(!clear_pipeline))
539
                                ? dcd_branch_pc:pf_pc[(AW+1):2];
540
        assign  pf_gie = gie;
541 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
542 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
543 205 dgisselq
                        pf(i_clk, (i_rst), pf_new_pc, w_clear_icache,
544
                                (!pf_stalled),
545
                                pf_request_address,
546
                                pf_instruction, pf_instruction_pc,
547 36 dgisselq
                                        pf_valid, pf_illegal,
548
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
549
                                pf_ack, pf_stall, pf_err, i_wb_data);
550 69 dgisselq
 
551 205 dgisselq
`else
552
`ifdef  OPT_DOUBLE_FETCH
553 69 dgisselq
 
554 205 dgisselq
        wire    [1:0]    pf_dbg;
555
        dblfetch #(ADDRESS_WIDTH)
556
                pf(i_clk, i_rst, pf_new_pc,
557
                                w_clear_icache,
558
                                (!pf_stalled),
559
                                pf_request_address,
560
                                pf_instruction, pf_instruction_pc,
561
                                        pf_valid,
562
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
563
                                        pf_ack, pf_stall, pf_err, i_wb_data,
564
                                pf_illegal);
565 69 dgisselq
 
566 205 dgisselq
`else // Not single fetch and not double fetch
567
 
568 69 dgisselq
`ifdef  OPT_TRADITIONAL_PFCACHE
569
        pfcache #(LGICACHE, ADDRESS_WIDTH)
570 205 dgisselq
                pf(i_clk, i_rst, pf_new_pc, w_clear_icache,
571 69 dgisselq
                                // dcd_pc,
572 201 dgisselq
                                (!pf_stalled),
573
                                pf_request_address,
574
                                pf_instruction, pf_instruction_pc, pf_valid,
575 69 dgisselq
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
576
                                        pf_ack, pf_stall, pf_err, i_wb_data,
577
                                pf_illegal);
578
`else
579 201 dgisselq
        pipefetch       #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)
580 205 dgisselq
                        pf(i_clk, i_rst, pf_new_pc,
581 201 dgisselq
                                        w_clear_icache, (!pf_stalled),
582
                                        (new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,
583
                                        pf_instruction, pf_instruction_pc, pf_valid,
584 2 dgisselq
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
585 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
586
                                (mem_cyc_lcl)||(mem_cyc_gbl),
587
                                pf_illegal);
588 205 dgisselq
`endif  // OPT_TRADITIONAL_CACHE
589
`endif  // OPT_DOUBLE_FETCH
590
`endif  // OPT_SINGLE_FETCH
591 2 dgisselq
 
592 205 dgisselq
        assign          dcd_ce = (!dcd_valid)||(!dcd_stalled);
593 69 dgisselq
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
594
                        IMPLEMENT_FPU)
595 205 dgisselq
                instruction_decoder(i_clk,
596
                        (clear_pipeline)||(w_clear_icache),
597
                        dcd_ce,
598
                        dcd_stalled, pf_instruction, pf_gie,
599
                        pf_instruction_pc, pf_valid, pf_illegal,
600
                        dcd_valid, dcd_phase,
601 201 dgisselq
                        dcd_illegal, dcd_pc, dcd_gie,
602
                        { dcd_Rcc, dcd_Rpc, dcd_R },
603
                        { dcd_Acc, dcd_Apc, dcd_A },
604
                        { dcd_Bcc, dcd_Bpc, dcd_B },
605
                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
606
                        dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock,
607
                        dcd_wR,dcd_rA, dcd_rB,
608 69 dgisselq
                        dcd_early_branch,
609 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
610 201 dgisselq
                        dcd_pipe,
611
                        dcd_sim, dcd_sim_immv);
612 2 dgisselq
 
613 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
614 132 dgisselq
        reg             r_op_pipe;
615 2 dgisselq
 
616 132 dgisselq
        initial r_op_pipe = 1'b0;
617 201 dgisselq
        // To be a pipeable operation, there must be
618 38 dgisselq
        //      two valid adjacent instructions
619
        //      Both must be memory instructions
620
        //      Both must be writes, or both must be reads
621
        //      Both operations must be to the same identical address,
622
        //              or at least a single (one) increment above that address
623 71 dgisselq
        //
624
        // However ... we need to know this before this clock, hence this is
625
        // calculated in the instruction decoder.
626 38 dgisselq
        always @(posedge i_clk)
627 201 dgisselq
                if (clear_pipeline)
628
                        r_op_pipe <= 1'b0;
629
                else if (op_ce)
630 132 dgisselq
                        r_op_pipe <= dcd_pipe;
631 145 dgisselq
                else if (mem_ce) // Clear us any time an op_ is clocked in
632
                        r_op_pipe <= 1'b0;
633 132 dgisselq
        assign  op_pipe = r_op_pipe;
634
`else
635
        assign  op_pipe = 1'b0;
636 38 dgisselq
`endif
637
 
638 2 dgisselq
        //
639
        //
640
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
641
        //
642
        //
643 201 dgisselq
`ifdef  OPT_NO_USERMODE
644
        assign  w_op_Av = regset[dcd_A[3:0]];
645
        assign  w_op_Bv = regset[dcd_B[3:0]];
646
`else
647
        assign  w_op_Av = regset[dcd_A];
648
        assign  w_op_Bv = regset[dcd_B];
649
`endif
650 56 dgisselq
 
651 132 dgisselq
        wire    [8:0]    w_cpu_info;
652
        assign  w_cpu_info = {
653
        1'b1,
654 201 dgisselq
        (IMPLEMENT_MPY    >0)? 1'b1:1'b0,
655
        (IMPLEMENT_DIVIDE >0)? 1'b1:1'b0,
656
        (IMPLEMENT_FPU    >0)? 1'b1:1'b0,
657 132 dgisselq
`ifdef  OPT_PIPELINED
658
        1'b1,
659
`else
660
        1'b0,
661
`endif
662
`ifdef  OPT_TRADITIONAL_CACHE
663
        1'b1,
664
`else
665
        1'b0,
666
`endif
667
`ifdef  OPT_EARLY_BRANCHING
668
        1'b1,
669
`else
670
        1'b0,
671
`endif
672
`ifdef  OPT_PIPELINED_BUS_ACCESS
673
        1'b1,
674
`else
675
        1'b0,
676
`endif
677 201 dgisselq
`ifdef  OPT_CIS
678 132 dgisselq
        1'b1
679
`else
680
        1'b0
681
`endif
682
        };
683
 
684 56 dgisselq
        wire    [31:0]   w_pcA_v;
685 201 dgisselq
        assign  w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie)
686
                                ? { dcd_pc[AW:1], 2'b00 }
687
                                : { upc[(AW+1):2], uhalt_phase, 1'b0 } };
688 56 dgisselq
        generate
689 201 dgisselq
        if (AW < 30)
690
                assign  w_pcA_v[31:(AW+2)] = 0;
691 56 dgisselq
        endgenerate
692 71 dgisselq
 
693
`ifdef  OPT_PIPELINED
694 201 dgisselq
        reg     [4:0]    op_Aid, op_Bid;
695
        reg             op_rA, op_rB;
696 2 dgisselq
        always @(posedge i_clk)
697 71 dgisselq
                if (op_ce)
698
                begin
699 201 dgisselq
                        op_Aid <= dcd_A;
700
                        op_Bid <= dcd_B;
701
                        op_rA <= dcd_rA;
702
                        op_rB <= dcd_rB;
703 71 dgisselq
                end
704
`endif
705
 
706
        always @(posedge i_clk)
707 201 dgisselq
                if (op_ce)
708 2 dgisselq
                begin
709 179 dgisselq
`ifdef  OPT_PIPELINED
710 201 dgisselq
                        if ((wr_reg_ce)&&(wr_reg_id == dcd_A))
711
                                r_op_Av <= wr_gpreg_vl;
712 179 dgisselq
                        else
713
`endif
714 201 dgisselq
                        if (dcd_Apc)
715
                                r_op_Av <= w_pcA_v;
716
                        else if (dcd_Acc)
717
                                r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
718 2 dgisselq
                        else
719 201 dgisselq
                                r_op_Av <= w_op_Av;
720 69 dgisselq
`ifdef  OPT_PIPELINED
721 71 dgisselq
                end else
722 205 dgisselq
                begin
723 201 dgisselq
                        if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
724
                                r_op_Av <= wr_gpreg_vl;
725 56 dgisselq
`endif
726 2 dgisselq
                end
727 56 dgisselq
 
728 201 dgisselq
        wire    [31:0]   w_op_BnI, w_pcB_v;
729
        assign  w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie)
730
                                        ? { dcd_pc[AW:1], 2'b00 }
731
                                        : { upc[(AW+1):2], uhalt_phase, 1'b0 } };
732 56 dgisselq
        generate
733 201 dgisselq
        if (AW < 30)
734
                assign  w_pcB_v[31:(AW+2)] = 0;
735 56 dgisselq
        endgenerate
736
 
737 201 dgisselq
        assign  w_op_BnI = (!dcd_rB) ? 32'h00
738 179 dgisselq
`ifdef  OPT_PIPELINED
739 201 dgisselq
                : ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl
740 179 dgisselq
`endif
741 201 dgisselq
                : ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14],
742
                        1'b0, (dcd_B[4])?w_uflags:w_iflags}
743
                : w_op_Bv);
744 56 dgisselq
 
745 2 dgisselq
        always @(posedge i_clk)
746 179 dgisselq
`ifdef  OPT_PIPELINED
747 201 dgisselq
                if ((op_ce)&&(dcd_Bpc)&&(dcd_rB))
748
                        r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
749
                else if (op_ce)
750
                        r_op_Bv <= w_op_BnI + dcd_I;
751
                else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB))
752
                        r_op_Bv <= wr_gpreg_vl;
753 179 dgisselq
`else
754 201 dgisselq
                if ((dcd_Bpc)&&(dcd_rB))
755
                        r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
756
                else
757
                        r_op_Bv <= w_op_BnI + dcd_I;
758 56 dgisselq
`endif
759 2 dgisselq
 
760
        // The logic here has become more complex than it should be, no thanks
761
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
762
        // be two sets of four bits: the top bits specify what bits matter, the
763
        // bottom specify what those top bits must equal.  However, two of
764
        // conditions check whether bits are on, and those are the only two
765
        // conditions checking those bits.  Therefore, Vivado complains that
766
        // these two bits are redundant.  Hence the convoluted expression
767
        // below, arriving at what we finally want in the (now wire net)
768 201 dgisselq
        // op_F.
769 2 dgisselq
        always @(posedge i_clk)
770 201 dgisselq
                if (op_ce) // Cannot do op_change_data_ce here since op_F depends
771 160 dgisselq
                        // upon being either correct for a valid op, or correct
772
                        // for the last valid op
773 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
774 201 dgisselq
                        case(dcd_F[2:0])
775
                        3'h0:   r_op_F <= 7'h00;        // Always
776
                        3'h1:   r_op_F <= 7'h11;        // Z
777
                        3'h2:   r_op_F <= 7'h44;        // LT
778
                        3'h3:   r_op_F <= 7'h22;        // C
779
                        3'h4:   r_op_F <= 7'h08;        // V
780
                        3'h5:   r_op_F <= 7'h10;        // NE
781
                        3'h6:   r_op_F <= 7'h40;        // GE (!N)
782
                        3'h7:   r_op_F <= 7'h20;        // NC
783 2 dgisselq
                        endcase
784 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
785 201 dgisselq
        assign  op_F = { r_op_F[3], r_op_F[6:0] };
786 2 dgisselq
 
787 201 dgisselq
        wire    w_op_valid;
788 205 dgisselq
        assign  w_op_valid = (!clear_pipeline)&&(dcd_valid)&&(!dcd_ljmp)&&(!dcd_early_branch);
789 201 dgisselq
        initial op_valid     = 1'b0;
790
        initial op_valid_alu = 1'b0;
791
        initial op_valid_mem = 1'b0;
792
        initial op_valid_div = 1'b0;
793
        initial op_valid_fpu = 1'b0;
794 2 dgisselq
        always @(posedge i_clk)
795 201 dgisselq
                if (clear_pipeline)
796 25 dgisselq
                begin
797 201 dgisselq
                        op_valid     <= 1'b0;
798
                        op_valid_alu <= 1'b0;
799
                        op_valid_mem <= 1'b0;
800
                        op_valid_div <= 1'b0;
801
                        op_valid_fpu <= 1'b0;
802 25 dgisselq
                end else if (op_ce)
803
                begin
804 2 dgisselq
                        // Do we have a valid instruction?
805
                        //   The decoder may vote to stall one of its
806
                        //   instructions based upon something we currently
807
                        //   have in our queue.  This instruction must then
808
                        //   move forward, and get a stall cycle inserted.
809
                        //   Hence, the test on dcd_stalled here.  If we must
810
                        //   wait until our operands are valid, then we aren't
811
                        //   valid yet until then.
812 201 dgisselq
                        op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);
813
                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)
814
                                        ||(dcd_early_branch));
815 205 dgisselq
                        op_valid_mem <= (dcd_M)&&(!dcd_illegal)&&(w_op_valid);
816
                        op_valid_div <= (dcd_DIV)&&(!dcd_illegal)&&(w_op_valid);
817
                        op_valid_fpu <= (dcd_FP)&&(!dcd_illegal)&&(w_op_valid);
818 193 dgisselq
                end else if ((adf_ce_unconditional)||(mem_ce))
819 25 dgisselq
                begin
820 201 dgisselq
                        op_valid     <= 1'b0;
821
                        op_valid_alu <= 1'b0;
822
                        op_valid_mem <= 1'b0;
823
                        op_valid_div <= 1'b0;
824
                        op_valid_fpu <= 1'b0;
825 25 dgisselq
                end
826 2 dgisselq
 
827
        // Here's part of our debug interface.  When we recognize a break
828
        // instruction, we set the op_break flag.  That'll prevent this
829
        // instruction from entering the ALU, and cause an interrupt before
830
        // this instruction.  Thus, returning to this code will cause the
831
        // break to repeat and continue upon return.  To get out of this
832
        // condition, replace the break instruction with what it is supposed
833
        // to be, step through it, and then replace it back.  In this fashion,
834
        // a debugger can step through code.
835 201 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
836 179 dgisselq
        reg     r_op_break;
837
 
838
        initial r_op_break = 1'b0;
839 2 dgisselq
        always @(posedge i_clk)
840 201 dgisselq
                if ((i_rst)||(clear_pipeline))  r_op_break <= 1'b0;
841
                else if (op_ce)
842
                        r_op_break <= (dcd_break);
843
                else if (!op_valid)
844
                        r_op_break <= 1'b0;
845 179 dgisselq
        assign  op_break = r_op_break;
846 2 dgisselq
 
847 69 dgisselq
`ifdef  OPT_PIPELINED
848
        generate
849
        if (IMPLEMENT_LOCK != 0)
850
        begin
851 201 dgisselq
                reg     r_op_lock;
852 69 dgisselq
 
853
                initial r_op_lock = 1'b0;
854
                always @(posedge i_clk)
855 201 dgisselq
                        if (clear_pipeline)
856 69 dgisselq
                                r_op_lock <= 1'b0;
857 132 dgisselq
                        else if (op_ce)
858 205 dgisselq
                                r_op_lock <= (dcd_valid)&&(dcd_lock)&&(!clear_pipeline);
859 69 dgisselq
                assign  op_lock = r_op_lock;
860
 
861
        end else begin
862
                assign  op_lock = 1'b0;
863
        end endgenerate
864
 
865
`else
866
        assign op_lock       = 1'b0;
867
`endif
868
 
869 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
870 71 dgisselq
        initial op_illegal = 1'b0;
871 2 dgisselq
        always @(posedge i_clk)
872 201 dgisselq
                if (clear_pipeline)
873 71 dgisselq
                        op_illegal <= 1'b0;
874
                else if(op_ce)
875 69 dgisselq
`ifdef  OPT_PIPELINED
876 201 dgisselq
                        op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
877 69 dgisselq
`else
878 201 dgisselq
                        op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock));
879 36 dgisselq
`endif
880 179 dgisselq
                else if(alu_ce)
881
                        op_illegal <= 1'b0;
882 69 dgisselq
`endif
883 36 dgisselq
 
884 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
885
        // set, dcd_early_branch will simply be a wire connected to zero and
886
        // this logic should just optimize.
887 179 dgisselq
`ifdef  OPT_PIPELINED
888 71 dgisselq
        always @(posedge i_clk)
889
                if (op_ce)
890
                begin
891 205 dgisselq
                        op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR))
892
                                &&(!dcd_early_branch)&&(!dcd_illegal);
893
                        op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal);
894 71 dgisselq
                end
895 179 dgisselq
`else
896
        always @(posedge i_clk)
897
        begin
898 205 dgisselq
                op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR))
899
                        &&(!dcd_early_branch)&&(!dcd_illegal);
900
                op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal);
901 179 dgisselq
        end
902
`endif
903 69 dgisselq
 
904 201 dgisselq
`ifdef  VERILATOR
905 205 dgisselq
`ifdef  SINGLE_FETCH
906
        always @(*)
907
        begin
908
                op_sim      = dcd_sim;
909
                op_sim_immv = dcd_sim_immv;
910
        end
911
`else
912 201 dgisselq
        always @(posedge i_clk)
913
                if (op_change_data_ce)
914
                begin
915
                        op_sim      <= dcd_sim;
916
                        op_sim_immv <= dcd_sim_immv;
917
                end
918
`endif
919
`endif
920
 
921
        reg     [3:0]    r_op_opn;
922
        reg     [4:0]    r_op_R;
923
        reg             r_op_Rcc;
924 179 dgisselq
        reg             r_op_gie;
925 205 dgisselq
 
926
        initial r_op_gie = 1'b0;
927 36 dgisselq
        always @(posedge i_clk)
928 160 dgisselq
                if (op_change_data_ce)
929 2 dgisselq
                begin
930 201 dgisselq
                        // Which ALU operation?  Early branches are
931
                        // unimplemented moves
932
                        r_op_opn    <= (dcd_early_branch) ? 4'hf : dcd_opn;
933
                        // opM  <= dcd_M;       // Is this a memory operation?
934 2 dgisselq
                        // What register will these results be written into?
935 201 dgisselq
                        r_op_R    <= dcd_R;
936
                        r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie);
937 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
938 179 dgisselq
                        r_op_gie <= dcd_gie;
939 2 dgisselq
 
940
                        //
941 201 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
942 2 dgisselq
                end
943 201 dgisselq
        assign  op_opn = r_op_opn;
944
        assign  op_R = r_op_R;
945 179 dgisselq
        assign  op_gie = r_op_gie;
946 201 dgisselq
        assign  op_Rcc = r_op_Rcc;
947 205 dgisselq
 
948 201 dgisselq
        assign  op_Fl = (op_gie)?(w_uflags):(w_iflags);
949 2 dgisselq
 
950 201 dgisselq
`ifdef  OPT_CIS
951 69 dgisselq
        reg     r_op_phase;
952
        initial r_op_phase = 1'b0;
953
        always @(posedge i_clk)
954 201 dgisselq
                if (clear_pipeline)
955 69 dgisselq
                        r_op_phase <= 1'b0;
956 160 dgisselq
                else if (op_change_data_ce)
957 201 dgisselq
                        r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc));
958 69 dgisselq
        assign  op_phase = r_op_phase;
959
`else
960
        assign  op_phase = 1'b0;
961
`endif
962
 
963 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
964
        // register set but in special registers of their own.  So step one
965
        // is to select the right register.  Step to is to replace that
966
        // register with the results of an ALU or memory operation, if such
967
        // results are now available.  Otherwise, we'd need to insert a wait
968
        // state of some type.
969
        //
970
        // The alternative approach would be to define some sort of
971
        // op_stall wire, which would stall any upstream stage.
972
        // We'll create a flag here to start our coordination.  Once we
973
        // define this flag to something other than just plain zero, then
974
        // the stalls will already be in place.
975 69 dgisselq
`ifdef  OPT_PIPELINED
976 201 dgisselq
        assign  op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA))
977
                        ?  wr_gpreg_vl : r_op_Av;
978 56 dgisselq
`else
979 201 dgisselq
        assign  op_Av = r_op_Av;
980 56 dgisselq
`endif
981 48 dgisselq
 
982 69 dgisselq
`ifdef  OPT_PIPELINED
983 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
984
        //      AND ... something that may write a register is running
985
        //      AND (series of conditions here ...)
986
        //              The operation might set flags, and we wish to read the
987
        //                      CC register
988
        //              OR ... (No other conditions)
989 201 dgisselq
        assign  dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere
990
                                &&((op_valid)||(mem_rdbusy)
991 83 dgisselq
                                        ||(div_busy)||(fpu_busy))
992 201 dgisselq
                                &&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc))
993
                        ||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd));
994 56 dgisselq
`else
995 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
996 201 dgisselq
        assign  dcd_A_stall = 1'b0;
997 56 dgisselq
`endif
998 36 dgisselq
 
999 69 dgisselq
`ifdef  OPT_PIPELINED
1000 201 dgisselq
        assign  op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB))
1001
                        ? wr_gpreg_vl: r_op_Bv;
1002 56 dgisselq
`else
1003 201 dgisselq
        assign  op_Bv = r_op_Bv;
1004 56 dgisselq
`endif
1005
 
1006 69 dgisselq
`ifdef  OPT_PIPELINED
1007 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
1008
        //      AND ... something that may write a (unknown) register is running
1009
        //      AND (series of conditions here ...)
1010
        //              The operation might set flags, and we wish to read the
1011
        //                      CC register
1012
        //              OR the operation might set register B, and we still need
1013
        //                      a clock to add the offset to it
1014 201 dgisselq
        assign  dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere
1015 83 dgisselq
                                // If the op stage isn't valid, yet something
1016
                                // is running, then it must have been valid.
1017
                                // We'll use the last values from that stage
1018 201 dgisselq
                                // (op_wR, op_wF, op_R) in our logic below.
1019
                                &&((op_valid)||(mem_rdbusy)
1020 132 dgisselq
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
1021 83 dgisselq
                                &&(
1022 145 dgisselq
                                // Okay, what happens if the result register
1023
                                // from instruction 1 becomes the input for
1024
                                // instruction two, *and* there's an immediate
1025
                                // offset in instruction two?  In that case, we
1026 201 dgisselq
                                // need an extra clock between the two
1027
                                // instructions to calculate the base plus
1028 145 dgisselq
                                // offset.
1029
                                //
1030
                                // What if instruction 1 (or before) is in a
1031
                                // memory pipeline?  We may no longer know what
1032 201 dgisselq
                                // the register was!  We will then need  to
1033 145 dgisselq
                                // blindly wait.  We'll temper this only waiting
1034
                                // if we're not piping this new instruction.
1035
                                // If we were piping, the pipe logic in the
1036
                                // decode circuit has told us that the hazard
1037
                                // is clear, so we're okay then.
1038
                                //
1039 205 dgisselq
                                ((!dcd_zI)&&(
1040 201 dgisselq
                                        ((op_R == dcd_B)&&(op_wR))
1041 205 dgisselq
                                        ||((mem_rdbusy)&&(!dcd_pipe))
1042 145 dgisselq
                                        ))
1043 83 dgisselq
                                // Stall following any instruction that will
1044
                                // set the flags, if we're going to need the
1045 201 dgisselq
                                // flags (CC) register for op_B.
1046
                                ||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
1047 38 dgisselq
                                // Stall on any ongoing memory operation that
1048 201 dgisselq
                                // will write to op_B -- captured above
1049 205 dgisselq
                                // ||((mem_busy)&&(!mem_we)&&(mem_last_reg==dcd_B)&&(!dcd_zI))
1050 179 dgisselq
                                )
1051 201 dgisselq
                        ||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
1052 205 dgisselq
        assign  dcd_F_stall = ((!dcd_F[3])
1053 201 dgisselq
                                        ||((dcd_rA)&&(dcd_Acc))
1054
                                        ||((dcd_rB)&&(dcd_Bcc)))
1055
                                        &&(op_valid)&&(op_Rcc);
1056
                                // &&(dcd_valid) is checked for elsewhere
1057 56 dgisselq
`else
1058 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
1059
        // hazard without the pipeline?
1060 201 dgisselq
        assign  dcd_B_stall = 1'b0;
1061
        assign  dcd_F_stall = 1'b0;
1062 56 dgisselq
`endif
1063 2 dgisselq
        //
1064
        //
1065
        //      PIPELINE STAGE #4 :: Apply Instruction
1066
        //
1067
        //
1068 201 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline),
1069
                        alu_ce, op_opn, op_Av, op_Bv,
1070 193 dgisselq
                        alu_result, alu_flags, alu_valid, alu_busy);
1071 2 dgisselq
 
1072 69 dgisselq
        generate
1073
        if (IMPLEMENT_DIVIDE != 0)
1074
        begin
1075 201 dgisselq
                div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0],
1076
                        op_Av, op_Bv, div_busy, div_valid, div_error, div_result,
1077 69 dgisselq
                        div_flags);
1078
        end else begin
1079 179 dgisselq
                assign  div_error = 1'b0; // Can't be high unless div_valid
1080 69 dgisselq
                assign  div_busy  = 1'b0;
1081
                assign  div_valid = 1'b0;
1082
                assign  div_result= 32'h00;
1083
                assign  div_flags = 4'h0;
1084
        end endgenerate
1085
 
1086
        generate
1087
        if (IMPLEMENT_FPU != 0)
1088
        begin
1089
                //
1090
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1091 201 dgisselq
                //      op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result,
1092 69 dgisselq
                //      fpu_flags);
1093
                //
1094 179 dgisselq
                assign  fpu_error = 1'b0; // Must only be true if fpu_valid
1095 69 dgisselq
                assign  fpu_busy  = 1'b0;
1096
                assign  fpu_valid = 1'b0;
1097
                assign  fpu_result= 32'h00;
1098
                assign  fpu_flags = 4'h0;
1099
        end else begin
1100 179 dgisselq
                assign  fpu_error = 1'b0;
1101 69 dgisselq
                assign  fpu_busy  = 1'b0;
1102
                assign  fpu_valid = 1'b0;
1103
                assign  fpu_result= 32'h00;
1104
                assign  fpu_flags = 4'h0;
1105
        end endgenerate
1106
 
1107
 
1108 201 dgisselq
        assign  set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]);
1109
        initial alu_wF   = 1'b0;
1110
        initial alu_wR   = 1'b0;
1111 2 dgisselq
        always @(posedge i_clk)
1112
                if (i_rst)
1113
                begin
1114 201 dgisselq
                        alu_wR   <= 1'b0;
1115
                        alu_wF   <= 1'b0;
1116 2 dgisselq
                end else if (alu_ce)
1117
                begin
1118 201 dgisselq
                        // alu_reg <= op_R;
1119
                        alu_wR  <= (op_wR)&&(set_cond);
1120
                        alu_wF  <= (op_wF)&&(set_cond);
1121 205 dgisselq
                end else if (!alu_busy) begin
1122 2 dgisselq
                        // These are strobe signals, so clear them if not
1123
                        // set for any particular clock
1124 201 dgisselq
                        alu_wR <= (i_halt)&&(i_dbg_we);
1125
                        alu_wF <= 1'b0;
1126 2 dgisselq
                end
1127 69 dgisselq
 
1128 201 dgisselq
`ifdef  OPT_CIS
1129 69 dgisselq
        reg     r_alu_phase;
1130
        initial r_alu_phase = 1'b0;
1131 2 dgisselq
        always @(posedge i_clk)
1132 69 dgisselq
                if (i_rst)
1133
                        r_alu_phase <= 1'b0;
1134 160 dgisselq
                else if ((adf_ce_unconditional)||(mem_ce))
1135 69 dgisselq
                        r_alu_phase <= op_phase;
1136
        assign  alu_phase = r_alu_phase;
1137
`else
1138
        assign  alu_phase = 1'b0;
1139
`endif
1140
 
1141 179 dgisselq
`ifdef  OPT_PIPELINED
1142 69 dgisselq
        always @(posedge i_clk)
1143 160 dgisselq
                if (adf_ce_unconditional)
1144 201 dgisselq
                        alu_reg <= op_R;
1145 65 dgisselq
                else if ((i_halt)&&(i_dbg_we))
1146
                        alu_reg <= i_dbg_reg;
1147 179 dgisselq
`else
1148
        always @(posedge i_clk)
1149
                if ((i_halt)&&(i_dbg_we))
1150
                        alu_reg <= i_dbg_reg;
1151
                else
1152 201 dgisselq
                        alu_reg <= op_R;
1153 179 dgisselq
`endif
1154 69 dgisselq
 
1155 132 dgisselq
        //
1156
        // DEBUG Register write access starts here
1157
        //
1158 65 dgisselq
        reg             dbgv;
1159
        initial dbgv = 1'b0;
1160
        always @(posedge i_clk)
1161 205 dgisselq
                dbgv <= (!i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
1162 132 dgisselq
        reg     [31:0]   dbg_val;
1163 65 dgisselq
        always @(posedge i_clk)
1164 132 dgisselq
                dbg_val <= i_dbg_data;
1165 201 dgisselq
`ifdef  OPT_NO_USERMODE
1166
        assign  alu_gie = 1'b0;
1167
`else
1168 179 dgisselq
`ifdef  OPT_PIPELINED
1169
        reg     r_alu_gie;
1170
 
1171 132 dgisselq
        always @(posedge i_clk)
1172 160 dgisselq
                if ((adf_ce_unconditional)||(mem_ce))
1173 179 dgisselq
                        r_alu_gie  <= op_gie;
1174
        assign  alu_gie = r_alu_gie;
1175 201 dgisselq
`else
1176
        assign  alu_gie = op_gie;
1177
`endif
1178
`endif
1179 179 dgisselq
 
1180 201 dgisselq
`ifdef  OPT_PIPELINED
1181 179 dgisselq
        reg     [(AW-1):0]       r_alu_pc;
1182 2 dgisselq
        always @(posedge i_clk)
1183 160 dgisselq
                if ((adf_ce_unconditional)
1184 205 dgisselq
                        ||((master_ce)&&(op_valid_mem)&&(!clear_pipeline)
1185
                                &&(!mem_stalled)))
1186 179 dgisselq
                        r_alu_pc  <= op_pc;
1187
        assign  alu_pc = r_alu_pc;
1188
`else
1189
        assign  alu_pc = op_pc;
1190
`endif
1191 65 dgisselq
 
1192 56 dgisselq
        reg     r_alu_illegal;
1193
        initial r_alu_illegal = 0;
1194 38 dgisselq
        always @(posedge i_clk)
1195 201 dgisselq
                if (clear_pipeline)
1196 71 dgisselq
                        r_alu_illegal <= 1'b0;
1197 179 dgisselq
                else if (alu_ce)
1198 56 dgisselq
                        r_alu_illegal <= op_illegal;
1199 179 dgisselq
                else
1200
                        r_alu_illegal <= 1'b0;
1201 193 dgisselq
        assign  alu_illegal = (r_alu_illegal);
1202 38 dgisselq
 
1203 145 dgisselq
        initial r_alu_pc_valid = 1'b0;
1204 132 dgisselq
        initial mem_pc_valid = 1'b0;
1205 2 dgisselq
        always @(posedge i_clk)
1206 201 dgisselq
                if (clear_pipeline)
1207 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1208 205 dgisselq
                else if ((adf_ce_unconditional)&&(!op_phase))
1209 145 dgisselq
                        r_alu_pc_valid <= 1'b1;
1210 205 dgisselq
                else if (((!alu_busy)&&(!div_busy)&&(!fpu_busy))||(clear_pipeline))
1211 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1212 205 dgisselq
        assign  alu_pc_valid = (r_alu_pc_valid)&&((!alu_busy)&&(!div_busy)&&(!fpu_busy));
1213 132 dgisselq
        always @(posedge i_clk)
1214
                if (i_rst)
1215
                        mem_pc_valid <= 1'b0;
1216
                else
1217
                        mem_pc_valid <= (mem_ce);
1218 2 dgisselq
 
1219 69 dgisselq
        wire    bus_lock;
1220
`ifdef  OPT_PIPELINED
1221
        generate
1222
        if (IMPLEMENT_LOCK != 0)
1223
        begin
1224 201 dgisselq
                reg     r_prelock_stall;
1225
 
1226
                initial r_prelock_stall = 1'b0;
1227
                always @(posedge i_clk)
1228
                        if (clear_pipeline)
1229
                                r_prelock_stall <= 1'b0;
1230
                        else if ((op_valid)&&(op_lock)&&(op_ce))
1231
                                r_prelock_stall <= 1'b1;
1232
                        else if ((op_valid)&&(dcd_valid)&&(pf_valid))
1233
                                r_prelock_stall <= 1'b0;
1234
 
1235
                assign  prelock_stall = r_prelock_stall;
1236
 
1237
                reg     r_prelock_primed;
1238
                always @(posedge i_clk)
1239
                        if (clear_pipeline)
1240
                                r_prelock_primed <= 1'b0;
1241
                        else if (r_prelock_stall)
1242
                                r_prelock_primed <= 1'b1;
1243
                        else if ((adf_ce_unconditional)||(mem_ce))
1244
                                r_prelock_primed <= 1'b0;
1245
 
1246 132 dgisselq
                reg     [1:0]    r_bus_lock;
1247
                initial r_bus_lock = 2'b00;
1248 69 dgisselq
                always @(posedge i_clk)
1249 201 dgisselq
                        if (clear_pipeline)
1250 132 dgisselq
                                r_bus_lock <= 2'b00;
1251 201 dgisselq
                        else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce)))
1252
                        begin
1253
                                if (r_prelock_primed)
1254
                                        r_bus_lock <= 2'b10;
1255
                                else if (r_bus_lock != 2'h0)
1256
                                        r_bus_lock <= r_bus_lock + 2'b11;
1257
                        end
1258 132 dgisselq
                assign  bus_lock = |r_bus_lock;
1259 69 dgisselq
        end else begin
1260 201 dgisselq
                assign  prelock_stall = 1'b0;
1261 69 dgisselq
                assign  bus_lock = 1'b0;
1262
        end endgenerate
1263
`else
1264
        assign  bus_lock = 1'b0;
1265
`endif
1266
 
1267 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1268 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1269 201 dgisselq
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1270 38 dgisselq
                                mem_busy, mem_pipe_stalled,
1271
                                mem_valid, bus_err, mem_wreg, mem_result,
1272
                        mem_cyc_gbl, mem_cyc_lcl,
1273
                                mem_stb_gbl, mem_stb_lcl,
1274 201 dgisselq
                                mem_we, mem_addr, mem_data, mem_sel,
1275 38 dgisselq
                                mem_ack, mem_stall, mem_err, i_wb_data);
1276 201 dgisselq
 
1277 38 dgisselq
`else // PIPELINED_BUS_ACCESS
1278 205 dgisselq
        memops  #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,
1279
                        (mem_ce)&&(set_cond), bus_lock,
1280 201 dgisselq
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1281 38 dgisselq
                                mem_busy,
1282
                                mem_valid, bus_err, mem_wreg, mem_result,
1283 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1284
                                mem_stb_gbl, mem_stb_lcl,
1285 201 dgisselq
                                mem_we, mem_addr, mem_data, mem_sel,
1286 36 dgisselq
                                mem_ack, mem_stall, mem_err, i_wb_data);
1287 201 dgisselq
        assign  mem_pipe_stalled = 1'b0;
1288 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1289 205 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(!mem_we));
1290 2 dgisselq
 
1291 201 dgisselq
        // Either the prefetch or the instruction gets the memory bus, but
1292 2 dgisselq
        // never both.
1293 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1294 36 dgisselq
                // Memory access to the arbiter, priority position
1295
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1296 201 dgisselq
                        mem_we, mem_addr, mem_data, mem_sel,
1297
                        mem_ack, mem_stall, mem_err,
1298 2 dgisselq
                // Prefetch access to the arbiter
1299 201 dgisselq
                //
1300
                // At a first glance, we might want something like:
1301
                //
1302
                // pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf,
1303
                //
1304
                // However, we know that the prefetch will not generate any
1305
                // writes.  Therefore, the write specific lines (mem_data and
1306
                // mem_sel) can be shared with the memory in order to ease
1307
                // timing and LUT usage.
1308
                pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel,
1309 36 dgisselq
                        pf_ack, pf_stall, pf_err,
1310 2 dgisselq
                // Common wires, in and out, of the arbiter
1311 201 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1312
                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
1313 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_err);
1314 2 dgisselq
 
1315 132 dgisselq
 
1316
 
1317 2 dgisselq
        //
1318
        //
1319 132 dgisselq
        //
1320
        //
1321
        //
1322
        //
1323
        //
1324
        //
1325 2 dgisselq
        //      PIPELINE STAGE #5 :: Write-back results
1326
        //
1327
        //
1328
        // This stage is not allowed to stall.  If results are ready to be
1329
        // written back, they are written back at all cost.  Sleepy CPU's
1330
        // won't prevent write back, nor debug modes, halting the CPU, nor
1331
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1332
        // as knowinig something is available for writeback.
1333
 
1334
        //
1335
        // Write back to our generic register set ...
1336
        // When shall we write back?  On one of two conditions
1337
        //      Note that the flags needed to be checked before issuing the
1338
        //      bus instruction, so they don't need to be checked here.
1339 201 dgisselq
        //      Further, alu_wR includes (set_cond), so we don't need to
1340 2 dgisselq
        //      check for that here either.
1341 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1342 205 dgisselq
                                ||((!clear_pipeline)&&(!alu_illegal)
1343 201 dgisselq
                                        &&(((alu_wR)&&(alu_valid))
1344 160 dgisselq
                                                ||(div_valid)||(fpu_valid)));
1345 2 dgisselq
        // Which register shall be written?
1346 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1347
        //              One or PC, one for CC, and one for GIE match
1348 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1349
        //      FPU operation.
1350 201 dgisselq
`ifdef  OPT_NO_USERMODE
1351
        assign  wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid)
1352
                                ? alu_reg[3:0]:mem_wreg[3:0];
1353
        assign  wr_reg_id[4] = 1'b0;
1354
`else
1355
        assign  wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg;
1356
`endif
1357
 
1358 25 dgisselq
        // Are we writing to the CC register?
1359
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1360 179 dgisselq
        assign  wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
1361
        assign  wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
1362 2 dgisselq
        // Are we writing to the PC?
1363
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1364 179 dgisselq
 
1365 2 dgisselq
        // What value to write?
1366 160 dgisselq
        assign  wr_gpreg_vl = ((mem_valid) ? mem_result
1367 71 dgisselq
                                :((div_valid|fpu_valid))
1368
                                        ? ((div_valid) ? div_result:fpu_result)
1369
                                :((dbgv) ? dbg_val : alu_result));
1370 160 dgisselq
        assign  wr_spreg_vl = ((mem_valid) ? mem_result
1371
                                :((dbgv) ? dbg_val : alu_result));
1372 2 dgisselq
        always @(posedge i_clk)
1373
                if (wr_reg_ce)
1374 201 dgisselq
`ifdef  OPT_NO_USERMODE
1375
                        regset[wr_reg_id[3:0]] <= wr_gpreg_vl;
1376
`else
1377
                        regset[wr_reg_id] <= wr_gpreg_vl;
1378
`endif
1379 2 dgisselq
 
1380
        //
1381
        // Write back to the condition codes/flags register ...
1382 201 dgisselq
        // When shall we write to our flags register?  alu_wF already
1383 2 dgisselq
        // includes the set condition ...
1384 205 dgisselq
        assign  wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(!clear_pipeline)&&(!alu_illegal);
1385 179 dgisselq
        assign  w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
1386 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1387 179 dgisselq
                        ubreak, step, 1'b1, sleep,
1388 71 dgisselq
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1389 179 dgisselq
        assign  w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
1390 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1391
                        break_en, 1'b0, 1'b0, sleep,
1392 205 dgisselq
                        ((wr_flags_ce)&&(!alu_gie))?alu_flags:iflags };
1393 69 dgisselq
 
1394
 
1395 2 dgisselq
        // What value to write?
1396
        always @(posedge i_clk)
1397
                // If explicitly writing the register itself
1398 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_ucc))
1399 160 dgisselq
                        flags <= wr_gpreg_vl[3:0];
1400 2 dgisselq
                // Otherwise if we're setting the flags from an ALU operation
1401
                else if ((wr_flags_ce)&&(alu_gie))
1402 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1403
                                : alu_flags);
1404 2 dgisselq
 
1405
        always @(posedge i_clk)
1406 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_scc))
1407 160 dgisselq
                        iflags <= wr_gpreg_vl[3:0];
1408 205 dgisselq
                else if ((wr_flags_ce)&&(!alu_gie))
1409 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1410
                                : alu_flags);
1411 2 dgisselq
 
1412
        // The 'break' enable  bit.  This bit can only be set from supervisor
1413
        // mode.  It control what the CPU does upon encountering a break
1414
        // instruction.
1415
        //
1416
        // The goal, upon encountering a break is that the CPU should stop and
1417
        // not execute the break instruction, choosing instead to enter into
1418 201 dgisselq
        // either interrupt mode or halt first.
1419 2 dgisselq
        //      if ((break_en) AND (break_instruction)) // user mode or not
1420
        //              HALT CPU
1421
        //      else if (break_instruction) // only in user mode
1422 179 dgisselq
        //              set an interrupt flag, set the user break bit,
1423
        //              go to supervisor mode, allow supervisor to step the CPU.
1424 2 dgisselq
        //      Upon a CPU halt, any break condition will be reset.  The
1425
        //      external debugger will then need to deal with whatever
1426
        //      condition has taken place.
1427
        initial break_en = 1'b0;
1428
        always @(posedge i_clk)
1429
                if ((i_rst)||(i_halt))
1430
                        break_en <= 1'b0;
1431 179 dgisselq
                else if ((wr_reg_ce)&&(wr_write_scc))
1432 160 dgisselq
                        break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
1433 179 dgisselq
 
1434
`ifdef  OPT_PIPELINED
1435
        reg     r_break_pending;
1436
 
1437
        initial r_break_pending = 1'b0;
1438
        always @(posedge i_clk)
1439 205 dgisselq
                if ((clear_pipeline)||(!op_valid))
1440 179 dgisselq
                        r_break_pending <= 1'b0;
1441
                else if (op_break)
1442 205 dgisselq
                        r_break_pending <= (!alu_busy)&&(!div_busy)&&(!fpu_busy)&&(!mem_busy)&&(!wr_reg_ce);
1443 179 dgisselq
                else
1444
                        r_break_pending <= 1'b0;
1445
        assign  break_pending = r_break_pending;
1446 36 dgisselq
`else
1447 179 dgisselq
        assign  break_pending = op_break;
1448 36 dgisselq
`endif
1449 2 dgisselq
 
1450
 
1451 205 dgisselq
        assign  o_break = ((break_en)||(!op_gie))&&(break_pending)
1452
                                &&(!clear_pipeline)
1453
                        ||((!alu_gie)&&(bus_err))
1454
                        ||((!alu_gie)&&(div_error))
1455
                        ||((!alu_gie)&&(fpu_error))
1456
                        ||((!alu_gie)&&(alu_illegal)&&(!clear_pipeline));
1457 179 dgisselq
 
1458 2 dgisselq
        // The sleep register.  Setting the sleep register causes the CPU to
1459
        // sleep until the next interrupt.  Setting the sleep register within
1460
        // interrupt mode causes the processor to halt until a reset.  This is
1461 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1462 201 dgisselq
        // set the sleep bit and switch to supervisor mode in the same
1463 25 dgisselq
        // instruction: users are not allowed to halt the CPU.
1464 201 dgisselq
        initial sleep = 1'b0;
1465
`ifdef  OPT_NO_USERMODE
1466
        reg     r_sleep_is_halt;
1467
        initial r_sleep_is_halt = 1'b0;
1468 2 dgisselq
        always @(posedge i_clk)
1469 201 dgisselq
                if (i_rst)
1470
                        r_sleep_is_halt <= 1'b0;
1471
                else if ((wr_reg_ce)&&(wr_write_cc)
1472
                                &&(wr_spreg_vl[`CPU_SLEEP_BIT])
1473 205 dgisselq
                                &&(!wr_spreg_vl[`CPU_GIE_BIT]))
1474 201 dgisselq
                        r_sleep_is_halt <= 1'b1;
1475
 
1476
        // Trying to switch to user mode, either via a WAIT or an RTU
1477
        // instruction will cause the CPU to sleep until an interrupt, in
1478
        // the NO-USERMODE build.
1479
        always @(posedge i_clk)
1480
                if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt)))
1481
                        sleep <= 1'b0;
1482
                else if ((wr_reg_ce)&&(wr_write_cc)
1483
                                &&(wr_spreg_vl[`CPU_GIE_BIT]))
1484
                        sleep <= 1'b1;
1485
`else
1486
        always @(posedge i_clk)
1487 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1488 2 dgisselq
                        sleep <= 1'b0;
1489 205 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(!alu_gie))
1490 25 dgisselq
                        // In supervisor mode, we have no protections.  The
1491
                        // supervisor can set the sleep bit however he wants.
1492 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1493
                        // sleep mode shouold only be possible if the interrupt
1494
                        // flag isn't set.
1495 160 dgisselq
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
1496 69 dgisselq
                        //              don't set the sleep bit
1497
                        //      otherwise however it would o.w. be set
1498 160 dgisselq
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
1499 205 dgisselq
                                &&((!i_interrupt)||(!wr_spreg_vl[`CPU_GIE_BIT]));
1500 160 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
1501 25 dgisselq
                        // In user mode, however, you can only set the sleep
1502
                        // mode while remaining in user mode.  You can't switch
1503
                        // to sleep mode *and* supervisor mode at the same
1504
                        // time, lest you halt the CPU.
1505 160 dgisselq
                        sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
1506 201 dgisselq
`endif
1507 2 dgisselq
 
1508
        always @(posedge i_clk)
1509 193 dgisselq
                if (i_rst)
1510 2 dgisselq
                        step <= 1'b0;
1511 205 dgisselq
                else if ((wr_reg_ce)&&(!alu_gie)&&(wr_write_ucc))
1512 160 dgisselq
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
1513 2 dgisselq
 
1514
        // The GIE register.  Only interrupts can disable the interrupt register
1515 201 dgisselq
`ifdef  OPT_NO_USERMODE
1516
        assign  w_switch_to_interrupt    = 1'b0;
1517
        assign  w_release_from_interrupt = 1'b0;
1518
`else
1519 2 dgisselq
        assign  w_switch_to_interrupt = (gie)&&(
1520
                        // On interrupt (obviously)
1521 205 dgisselq
                        ((i_interrupt)&&(!alu_phase)&&(!bus_lock))
1522 2 dgisselq
                        // If we are stepping the CPU
1523 205 dgisselq
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(!alu_phase)&&(!bus_lock))
1524 2 dgisselq
                        // If we encounter a break instruction, if the break
1525 36 dgisselq
                        //      enable isn't set.
1526 205 dgisselq
                        ||((master_ce)&&(break_pending)&&(!break_en))
1527 36 dgisselq
                        // On an illegal instruction
1528 193 dgisselq
                        ||((alu_illegal)&&(!clear_pipeline))
1529 71 dgisselq
                        // On division by zero.  If the divide isn't
1530
                        // implemented, div_valid and div_error will be short
1531
                        // circuited and that logic will be bypassed
1532 179 dgisselq
                        ||(div_error)
1533
                        // Same thing on a floating point error.  Note that
1534
                        // fpu_error must *never* be set unless fpu_valid is
1535
                        // also set as well, else this will fail.
1536
                        ||(fpu_error)
1537 201 dgisselq
                        //
1538 69 dgisselq
                        ||(bus_err)
1539 2 dgisselq
                        // If we write to the CC register
1540 205 dgisselq
                        ||((wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
1541 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1542 2 dgisselq
                        );
1543 205 dgisselq
        assign  w_release_from_interrupt = (!gie)&&(!i_interrupt)
1544 179 dgisselq
                        // Then if we write the sCC register
1545 160 dgisselq
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
1546 179 dgisselq
                                &&(wr_write_scc))
1547 2 dgisselq
                        );
1548 201 dgisselq
`endif
1549
 
1550
`ifdef  OPT_NO_USERMODE
1551
        assign  gie = 1'b0;
1552
`else
1553
        reg     r_gie;
1554
 
1555
        initial r_gie = 1'b0;
1556 2 dgisselq
        always @(posedge i_clk)
1557
                if (i_rst)
1558 201 dgisselq
                        r_gie <= 1'b0;
1559 2 dgisselq
                else if (w_switch_to_interrupt)
1560 201 dgisselq
                        r_gie <= 1'b0;
1561 2 dgisselq
                else if (w_release_from_interrupt)
1562 201 dgisselq
                        r_gie <= 1'b1;
1563
        assign  gie = r_gie;
1564
`endif
1565 2 dgisselq
 
1566 201 dgisselq
`ifdef  OPT_NO_USERMODE
1567
        assign  trap   = 1'b0;
1568
        assign  ubreak = 1'b0;
1569
`else
1570
        reg     r_trap;
1571
 
1572
        initial r_trap = 1'b0;
1573 25 dgisselq
        always @(posedge i_clk)
1574 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1575 201 dgisselq
                        r_trap <= 1'b0;
1576 205 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
1577 179 dgisselq
                                &&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
1578 201 dgisselq
                        r_trap <= 1'b1;
1579 205 dgisselq
                else if ((wr_reg_ce)&&(wr_write_ucc)&&(!alu_gie))
1580 201 dgisselq
                        r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
1581 25 dgisselq
 
1582 201 dgisselq
        reg     r_ubreak;
1583
 
1584
        initial r_ubreak = 1'b0;
1585 179 dgisselq
        always @(posedge i_clk)
1586
                if ((i_rst)||(w_release_from_interrupt))
1587 201 dgisselq
                        r_ubreak <= 1'b0;
1588 179 dgisselq
                else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
1589 201 dgisselq
                        r_ubreak <= 1'b1;
1590 205 dgisselq
                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1591 201 dgisselq
                        r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
1592 179 dgisselq
 
1593 201 dgisselq
        assign  trap = r_trap;
1594
        assign  ubreak = r_ubreak;
1595
`endif
1596 179 dgisselq
 
1597 201 dgisselq
 
1598 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1599 65 dgisselq
        initial ill_err_i = 1'b0;
1600 36 dgisselq
        always @(posedge i_clk)
1601
                if (i_rst)
1602 65 dgisselq
                        ill_err_i <= 1'b0;
1603 132 dgisselq
                // Only the debug interface can clear this bit
1604 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
1605
                        ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
1606 205 dgisselq
                else if ((alu_illegal)&&(!alu_gie)&&(!clear_pipeline))
1607 65 dgisselq
                        ill_err_i <= 1'b1;
1608 201 dgisselq
 
1609
`ifdef  OPT_NO_USERMODE
1610
        assign  ill_err_u = 1'b0;
1611
`else
1612
        reg     r_ill_err_u;
1613
 
1614
        initial r_ill_err_u = 1'b0;
1615 65 dgisselq
        always @(posedge i_clk)
1616
                // The bit is automatically cleared on release from interrupt
1617 179 dgisselq
                // or reset
1618
                if ((i_rst)||(w_release_from_interrupt))
1619 201 dgisselq
                        r_ill_err_u <= 1'b0;
1620 179 dgisselq
                // If the supervisor (or debugger) writes to this register,
1621
                // clearing the bit, then clear it
1622 205 dgisselq
                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1623 201 dgisselq
                        r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
1624 193 dgisselq
                else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
1625 201 dgisselq
                        r_ill_err_u <= 1'b1;
1626
 
1627
        assign  ill_err_u = r_ill_err_u;
1628
`endif
1629 38 dgisselq
`else
1630 65 dgisselq
        assign ill_err_u = 1'b0;
1631
        assign ill_err_i = 1'b0;
1632 36 dgisselq
`endif
1633 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1634
        // ever set.
1635
        initial ibus_err_flag = 1'b0;
1636 36 dgisselq
        always @(posedge i_clk)
1637
                if (i_rst)
1638 65 dgisselq
                        ibus_err_flag <= 1'b0;
1639 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
1640
                        ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
1641 205 dgisselq
                else if ((bus_err)&&(!alu_gie))
1642 65 dgisselq
                        ibus_err_flag <= 1'b1;
1643
        // User bus error flag -- if ever set, it will cause an interrupt to
1644 201 dgisselq
        // supervisor mode.
1645
`ifdef  OPT_NO_USERMODE
1646
        assign  ubus_err_flag = 1'b0;
1647
`else
1648
        reg     r_ubus_err_flag;
1649
 
1650
        initial r_ubus_err_flag = 1'b0;
1651 65 dgisselq
        always @(posedge i_clk)
1652 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1653 201 dgisselq
                        r_ubus_err_flag <= 1'b0;
1654 205 dgisselq
                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1655 201 dgisselq
                        r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
1656 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1657 201 dgisselq
                        r_ubus_err_flag <= 1'b1;
1658 36 dgisselq
 
1659 201 dgisselq
        assign  ubus_err_flag = r_ubus_err_flag;
1660
`endif
1661
 
1662 69 dgisselq
        generate
1663
        if (IMPLEMENT_DIVIDE != 0)
1664
        begin
1665
                reg     r_idiv_err_flag, r_udiv_err_flag;
1666
 
1667
                // Supervisor/interrupt divide (by zero) error flag -- this will
1668
                // crash the CPU if ever set.  This bit is thus available for us
1669
                // to be able to tell if/why the CPU crashed.
1670
                initial r_idiv_err_flag = 1'b0;
1671
                always @(posedge i_clk)
1672
                        if (i_rst)
1673
                                r_idiv_err_flag <= 1'b0;
1674 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
1675
                                r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
1676 205 dgisselq
                        else if ((div_error)&&(!alu_gie))
1677 69 dgisselq
                                r_idiv_err_flag <= 1'b1;
1678 201 dgisselq
 
1679
                assign  idiv_err_flag = r_idiv_err_flag;
1680
`ifdef  OPT_NO_USERMODE
1681
                assign  udiv_err_flag = 1'b0;
1682
`else
1683 69 dgisselq
                // User divide (by zero) error flag -- if ever set, it will
1684 201 dgisselq
                // cause a sudden switch interrupt to supervisor mode.
1685 69 dgisselq
                initial r_udiv_err_flag = 1'b0;
1686
                always @(posedge i_clk)
1687 179 dgisselq
                        if ((i_rst)||(w_release_from_interrupt))
1688 69 dgisselq
                                r_udiv_err_flag <= 1'b0;
1689 205 dgisselq
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
1690 179 dgisselq
                                        &&(wr_write_ucc))
1691
                                r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
1692
                        else if ((div_error)&&(alu_gie))
1693 69 dgisselq
                                r_udiv_err_flag <= 1'b1;
1694
 
1695
                assign  udiv_err_flag = r_udiv_err_flag;
1696 201 dgisselq
`endif
1697 69 dgisselq
        end else begin
1698
                assign  idiv_err_flag = 1'b0;
1699
                assign  udiv_err_flag = 1'b0;
1700
        end endgenerate
1701
 
1702
        generate
1703
        if (IMPLEMENT_FPU !=0)
1704
        begin
1705
                // Supervisor/interrupt floating point error flag -- this will
1706
                // crash the CPU if ever set.
1707
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1708
                initial r_ifpu_err_flag = 1'b0;
1709
                always @(posedge i_clk)
1710
                        if (i_rst)
1711
                                r_ifpu_err_flag <= 1'b0;
1712 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
1713
                                r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
1714 205 dgisselq
                        else if ((fpu_error)&&(fpu_valid)&&(!alu_gie))
1715 69 dgisselq
                                r_ifpu_err_flag <= 1'b1;
1716
                // User floating point error flag -- if ever set, it will cause
1717 201 dgisselq
                // a sudden switch interrupt to supervisor mode.
1718 69 dgisselq
                initial r_ufpu_err_flag = 1'b0;
1719
                always @(posedge i_clk)
1720 179 dgisselq
                        if ((i_rst)&&(w_release_from_interrupt))
1721 69 dgisselq
                                r_ufpu_err_flag <= 1'b0;
1722 205 dgisselq
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
1723 179 dgisselq
                                        &&(wr_write_ucc))
1724
                                r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
1725 69 dgisselq
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1726
                                r_ufpu_err_flag <= 1'b1;
1727
 
1728
                assign  ifpu_err_flag = r_ifpu_err_flag;
1729
                assign  ufpu_err_flag = r_ufpu_err_flag;
1730
        end else begin
1731
                assign  ifpu_err_flag = 1'b0;
1732
                assign  ufpu_err_flag = 1'b0;
1733
        end endgenerate
1734
 
1735 201 dgisselq
`ifdef  OPT_CIS
1736
        reg             r_ihalt_phase;
1737 69 dgisselq
 
1738
        initial r_ihalt_phase = 0;
1739
        always @(posedge i_clk)
1740 179 dgisselq
                if (i_rst)
1741
                        r_ihalt_phase <= 1'b0;
1742 205 dgisselq
                else if ((!alu_gie)&&(alu_pc_valid)&&(!clear_pipeline))
1743 69 dgisselq
                        r_ihalt_phase <= alu_phase;
1744 201 dgisselq
 
1745
        assign  ihalt_phase = r_ihalt_phase;
1746
 
1747
`ifdef  OPT_NO_USERMODE
1748
        assign  uhalt_phase = 1'b0;
1749
`else
1750
        reg             r_uhalt_phase;
1751
 
1752
        initial r_uhalt_phase = 0;
1753 69 dgisselq
        always @(posedge i_clk)
1754 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1755
                        r_uhalt_phase <= 1'b0;
1756
                else if ((alu_gie)&&(alu_pc_valid))
1757 69 dgisselq
                        r_uhalt_phase <= alu_phase;
1758 205 dgisselq
                else if ((!alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
1759 179 dgisselq
                        r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
1760 69 dgisselq
 
1761
        assign  uhalt_phase = r_uhalt_phase;
1762 201 dgisselq
`endif
1763 69 dgisselq
`else
1764
        assign  ihalt_phase = 1'b0;
1765
        assign  uhalt_phase = 1'b0;
1766
`endif
1767
 
1768 2 dgisselq
        //
1769
        // Write backs to the PC register, and general increments of it
1770
        //      We support two: upc and ipc.  If the instruction is normal,
1771
        // we increment upc, if interrupt level we increment ipc.  If
1772
        // the instruction writes the PC, we write whichever PC is appropriate.
1773
        //
1774
        // Do we need to all our partial results from the pipeline?
1775 205 dgisselq
        // What happens when the pipeline has gie and !gie instructions within
1776 2 dgisselq
        // it?  Do we clear both?  What if a gie instruction tries to clear
1777
        // a non-gie instruction?
1778 201 dgisselq
`ifdef  OPT_NO_USERMODE
1779
        assign  upc = {(AW+2){1'b0}};
1780
`else
1781
        reg     [(AW+1):0]       r_upc;
1782
 
1783 2 dgisselq
        always @(posedge i_clk)
1784 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1785 201 dgisselq
                        r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
1786 132 dgisselq
                else if ((alu_gie)&&
1787 205 dgisselq
                                (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
1788 132 dgisselq
                                ||(mem_pc_valid)))
1789 201 dgisselq
                        r_upc <= { alu_pc, 2'b00 };
1790
        assign  upc = r_upc;
1791
`endif
1792 2 dgisselq
 
1793
        always @(posedge i_clk)
1794
                if (i_rst)
1795 201 dgisselq
                        ipc <= { RESET_BUS_ADDRESS, 2'b00 };
1796 205 dgisselq
                else if ((wr_reg_ce)&&(!wr_reg_id[4])&&(wr_write_pc))
1797 201 dgisselq
                        ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
1798
                else if ((!alu_gie)&&(!alu_phase)&&
1799 205 dgisselq
                                (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
1800 132 dgisselq
                                ||(mem_pc_valid)))
1801 201 dgisselq
                        ipc <= { alu_pc, 2'b00 };
1802 2 dgisselq
 
1803
        always @(posedge i_clk)
1804
                if (i_rst)
1805 201 dgisselq
                        pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
1806 205 dgisselq
                else if ((w_switch_to_interrupt)||((!gie)&&(w_clear_icache)))
1807 201 dgisselq
                        pf_pc <= { ipc[(AW+1):2], 2'b00 };
1808 179 dgisselq
                else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
1809 201 dgisselq
                        pf_pc <= { upc[(AW+1):2], 2'b00 };
1810 2 dgisselq
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1811 201 dgisselq
                        pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
1812 205 dgisselq
                else if ((dcd_early_branch)&&(!clear_pipeline))
1813 201 dgisselq
                        pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 };
1814
                else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
1815
                        pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 };
1816 2 dgisselq
 
1817 205 dgisselq
        // If we aren't pipelined, or equivalently if we have no cache, these
1818
        // instructions will get quietly (or not so quietly) ignored by the
1819
        // optimizer.
1820 179 dgisselq
        reg     r_clear_icache;
1821
        initial r_clear_icache = 1'b1;
1822
        always @(posedge i_clk)
1823
                if ((i_rst)||(i_clear_pf_cache))
1824
                        r_clear_icache <= 1'b1;
1825
                else if ((wr_reg_ce)&&(wr_write_scc))
1826
                        r_clear_icache <=  wr_spreg_vl[`CPU_CLRCACHE_BIT];
1827
                else
1828
                        r_clear_icache <= 1'b0;
1829
        assign  w_clear_icache = r_clear_icache;
1830
 
1831 201 dgisselq
        initial new_pc = 1'b1;
1832
        always @(posedge i_clk)
1833
                if ((i_rst)||(w_clear_icache))
1834
                        new_pc <= 1'b1;
1835
                else if (w_switch_to_interrupt)
1836
                        new_pc <= 1'b1;
1837
                else if (w_release_from_interrupt)
1838
                        new_pc <= 1'b1;
1839
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1840
                        new_pc <= 1'b1;
1841
                else
1842
                        new_pc <= 1'b0;
1843
 
1844 2 dgisselq
        //
1845
        // The debug interface
1846 201 dgisselq
        wire    [31:0]   w_debug_pc;
1847
`ifdef  OPT_NO_USERMODE
1848
        assign  w_debug_pc[(AW+1):0] = { ipc, 2'b00 };
1849
`else
1850
        assign  w_debug_pc[(AW+1):0] = { (i_dbg_reg[4])
1851
                                ? { upc[(AW+1):2], uhalt_phase, 1'b0 }
1852
                                : { ipc[(AW+1):2], ihalt_phase, 1'b0 } };
1853
`endif
1854 56 dgisselq
        generate
1855 201 dgisselq
        if (AW<30)
1856
                assign  w_debug_pc[31:(AW+2)] = 0;
1857
        endgenerate
1858
 
1859
        always @(posedge i_clk)
1860 56 dgisselq
        begin
1861 201 dgisselq
`ifdef  OPT_NO_USERMODE
1862
                o_dbg_reg <= regset[i_dbg_reg[3:0]];
1863
                if (i_dbg_reg[3:0] == `CPU_PC_REG)
1864
                        o_dbg_reg <= w_debug_pc;
1865
                else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1866 2 dgisselq
                begin
1867 201 dgisselq
                        o_dbg_reg[14:0] <= w_iflags;
1868
                        o_dbg_reg[15] <= 1'b0;
1869
                        o_dbg_reg[31:23] <= w_cpu_info;
1870
                        o_dbg_reg[`CPU_GIE_BIT] <= gie;
1871 2 dgisselq
                end
1872 201 dgisselq
`else
1873
                o_dbg_reg <= regset[i_dbg_reg];
1874
                if (i_dbg_reg[3:0] == `CPU_PC_REG)
1875
                        o_dbg_reg <= w_debug_pc;
1876
                else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1877 56 dgisselq
                begin
1878 201 dgisselq
                        o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1879
                        o_dbg_reg[15] <= 1'b0;
1880
                        o_dbg_reg[31:23] <= w_cpu_info;
1881
                        o_dbg_reg[`CPU_GIE_BIT] <= gie;
1882 56 dgisselq
                end
1883 201 dgisselq
`endif
1884
        end
1885 56 dgisselq
 
1886 2 dgisselq
        always @(posedge i_clk)
1887 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1888 18 dgisselq
 
1889 179 dgisselq
`ifdef  OPT_PIPELINED
1890 18 dgisselq
        always @(posedge i_clk)
1891 160 dgisselq
                r_halted <= (i_halt)&&(
1892 179 dgisselq
                        // To be halted, any long lasting instruction must
1893
                        // be completed.
1894 205 dgisselq
                        (!pf_cyc)&&(!mem_busy)&&(!alu_busy)
1895
                                &&(!div_busy)&&(!fpu_busy)
1896 179 dgisselq
                        // Operations must either be valid, or illegal
1897 201 dgisselq
                        &&((op_valid)||(i_rst)||(dcd_illegal))
1898 179 dgisselq
                        // Decode stage must be either valid, in reset, or ill
1899 201 dgisselq
                        &&((dcd_valid)||(i_rst)||(pf_illegal)));
1900 179 dgisselq
`else
1901
        always @(posedge i_clk)
1902 201 dgisselq
                r_halted <= (i_halt)&&((op_valid)||(i_rst));
1903 179 dgisselq
`endif
1904 205 dgisselq
        assign  o_dbg_stall = !r_halted;
1905 2 dgisselq
 
1906
        //
1907
        //
1908
        // Produce accounting outputs: Account for any CPU stalls, so we can
1909
        // later evaluate how well we are doing.
1910
        //
1911
        //
1912 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1913 205 dgisselq
        assign  o_pf_stall = (master_ce)&&(!pf_valid);
1914
        assign  o_i_count  = (alu_pc_valid)&&(!clear_pipeline);
1915 56 dgisselq
 
1916 65 dgisselq
`ifdef  DEBUG_SCOPE
1917 56 dgisselq
        always @(posedge i_clk)
1918 65 dgisselq
                o_debug <= {
1919 179 dgisselq
                /*
1920 132 dgisselq
                        o_break, i_wb_err, pf_pc[1:0],
1921
                        flags,
1922 201 dgisselq
                        pf_valid, dcd_valid, op_valid, alu_valid, mem_valid,
1923 56 dgisselq
                        op_ce, alu_ce, mem_ce,
1924 65 dgisselq
                        //
1925 201 dgisselq
                        master_ce, op_valid_alu, op_valid_mem,
1926 65 dgisselq
                        //
1927
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1928
                        mem_we,
1929 201 dgisselq
                        // ((op_valid_alu)&&(alu_stall))
1930
                        // ||((op_valid_mem)&&(~op_pipe)&&(mem_busy))
1931
                        // ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1932
                        // op_Av[23:20], op_Av[3:0],
1933 160 dgisselq
                        gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
1934 179 dgisselq
                */
1935 71 dgisselq
                /*
1936 69 dgisselq
                        i_rst, master_ce, (new_pc),
1937 201 dgisselq
                        ((dcd_early_branch)&&(dcd_valid)),
1938 69 dgisselq
                        pf_valid, pf_illegal,
1939 201 dgisselq
                        op_ce, dcd_ce, dcd_valid, dcd_stalled,
1940 69 dgisselq
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1941
                        pf_pc[7:0], pf_addr[7:0]
1942 71 dgisselq
                */
1943 179 dgisselq
 
1944 132 dgisselq
                        i_wb_err, gie, alu_illegal,
1945
                              (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
1946
                        mem_busy,
1947
                                (mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
1948
                                        o_wb_addr[8:0] }
1949 201 dgisselq
                                        : { pf_instruction[31:21] },
1950 132 dgisselq
                        pf_valid, (pf_valid) ? alu_pc[14:0]
1951 201 dgisselq
                                :{ pf_cyc, pf_stb, pf_pc[14:2] }
1952 179 dgisselq
 
1953 132 dgisselq
                /*
1954
                        i_wb_err, gie, new_pc, dcd_early_branch,        // 4
1955 201 dgisselq
                        pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4
1956
                        pf_instruction[30:27],                          // 4
1957 132 dgisselq
                        dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb,  // 4
1958 201 dgisselq
                        dcd_valid,
1959 132 dgisselq
                        ((dcd_early_branch)&&(~clear_pipeline))         // 15
1960
                                        ? dcd_branch_pc[14:0]:pf_pc[14:0]
1961
                */
1962 56 dgisselq
                        };
1963 65 dgisselq
`endif
1964 201 dgisselq
 
1965 2 dgisselq
endmodule

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