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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9
//              The instruction set is about as RISC as you can get, there are
10
//              only 16 instruction types supported (of which one isn't yet
11
//              supported ...)  Please see the accompanying iset.html file
12
//              for a description of these instructions.
13
//
14
//              All instructions are 32-bits wide.  All bus accesses, both
15
//              address and data, are 32-bits over a wishbone bus.
16
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19
//              1. Prefetch, returns the instruction from memory.  On the
20
//              Basys board that I'm working on, one instruction may be
21
//              issued every 20 clocks or so, unless and until I implement a
22
//              cache or local memory.
23
//
24
//              2. Instruction Decode
25
//
26
//              3. Read Operands
27
//
28
//              4. Apply Instruction
29
//
30
//              4. Write-back Results
31
//
32
//      A lot of difficult work has been placed into the pipeline stall
33
//      handling.  My original proposal was not to allow pipeline stalls at all.
34
//      The idea would be that the CPU would just run every clock and whatever
35
//      stalled answer took place would just get fixed a clock or two later,
36
//      meaning that the compiler could just schedule everything out.
37
//      This idea died at the memory interface, which can take a variable
38
//      amount of time to read or write any value, thus the whole CPU needed
39
//      to stall on a stalled memory access.
40
//
41
//      My next idea was to just let things complete.  I.e., once an instrution
42
//      starts, it continues to completion no matter what and we go on.  This
43
//      failed at writing the PC.  If the PC gets written in something such as
44
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
45
//      later, if whether or not something happens in those clocks depends
46
//      upon the instruction fetch filling the pipeline, then the CPU has a
47
//      non-deterministic behavior.
48
//
49
//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
51
//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
53
//      read or a write, there is no undoing it--since peripherals on the
54
//      bus may act upon the answer with whatever side effects they might
55
//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
94
// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
99
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
104
//              http://www.gnu.org/licenses/gpl.html
105
//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109
`define CPU_PC_REG      4'hf
110
`define CPU_CC_REG      4'he
111
`define CPU_BREAK_BIT   7
112
`define CPU_STEP_BIT    6
113
`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
115
module  zipcpu(i_clk, i_rst, i_interrupt,
116
                // Debug interface
117
                i_halt, i_dbg_reg, i_dbg_we, i_dbg_data,
118
                        o_dbg_stall, o_dbg_reg,
119
                        o_break,
120
                // CPU interface to the wishbone bus
121
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
122
                        i_wb_ack, i_wb_stall, i_wb_data,
123
                // Accounting/CPU usage interface
124
                o_mem_stall, o_pf_stall, o_alu_stall);
125
        parameter       RESET_ADDRESS=32'h0100000;
126
        input                   i_clk, i_rst, i_interrupt;
127
        // Debug interface -- inputs
128
        input                   i_halt;
129
        input           [4:0]    i_dbg_reg;
130
        input                   i_dbg_we;
131
        input           [31:0]   i_dbg_data;
132
        // Debug interface -- outputs
133
        output  reg             o_dbg_stall;
134
        output  reg     [31:0]   o_dbg_reg;
135
        output  wire            o_break;
136
        // Wishbone interface -- outputs
137
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
138
        output  wire    [31:0]   o_wb_addr, o_wb_data;
139
        // Wishbone interface -- inputs
140
        input                   i_wb_ack, i_wb_stall;
141
        input           [31:0]   i_wb_data;
142
        // Accounting outputs ... to help us count stalls and usage
143
        output  wire            o_mem_stall;
144
        output  wire            o_pf_stall;
145
        output  wire            o_alu_stall;
146
 
147
 
148
        // Registers
149
        reg     [31:0]   regset [0:31];
150
        reg     [3:0]    flags, iflags;  // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
151
        wire            master_ce;
152
        wire    [7:0]    w_uflags, w_iflags;
153
        reg             step, gie, sleep, break_en;
154
 
155
        wire    [4:0]    mem_wreg;
156
        wire            mem_busy, mem_rdbusy;
157
 
158
        reg     [31:0]   pf_pc;
159
        reg             new_pc;
160
 
161
        //
162
        //
163
        //      PIPELINE STAGE #1 :: Prefetch
164
        //              Variable declarations
165
        //
166
        wire            pf_ce, dcd_stalled;
167
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
168
        wire    [31:0]   pf_addr, pf_data;
169
        wire    [31:0]   instruction, instruction_pc;
170
        wire    pf_valid, instruction_gie;
171
 
172
        //
173
        //
174
        //      PIPELINE STAGE #2 :: Instruction Decode
175
        //              Variable declarations
176
        //
177
        //
178
        reg             opvalid, op_wr_pc, op_break;
179
        wire            op_stall, dcd_ce;
180
        reg     [3:0]    dcdOp;
181
        reg     [4:0]    dcdA, dcdB;
182
        reg     [3:0]    dcdF;
183
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
184
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
185
        reg     [31:0]   dcd_pc;
186
        reg     [23:0]   r_dcdI;
187
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
188
 
189
 
190
 
191
        //
192
        //
193
        //      PIPELINE STAGE #3 :: Read Operands
194
        //              Variable declarations
195
        //
196
        //
197
        //
198
        // Now, let's read our operands
199
        reg     [4:0]    alu_reg;
200
        reg     [3:0]    opn;
201
        reg     [4:0]    opR;
202
        reg     [1:0]    opA_cc, opB_cc;
203
        reg     [31:0]   r_opA, r_opB, op_pc;
204
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
205
        reg             opR_wr, opM, opF_wr, op_gie,
206
                        opA_rd, opB_rd;
207 3 dgisselq
        wire    [7:0]    opFl;
208
        reg     [6:0]    r_opF;
209 2 dgisselq
        wire    [8:0]    opF;
210
        wire            op_ce;
211
 
212
 
213
 
214
        //
215
        //
216
        //      PIPELINE STAGE #4 :: ALU / Memory
217
        //              Variable declarations
218
        //
219
        //
220
        reg     [31:0]   alu_pc;
221
        reg             alu_pc_valid;;
222
        wire            alu_ce, alu_stall;
223
        wire    [31:0]   alu_result;
224
        wire    [3:0]    alu_flags;
225
        wire            alu_valid;
226
        wire            set_cond;
227
        reg             alu_wr, alF_wr, alu_gie;
228
 
229
 
230
 
231
        wire    mem_ce, mem_stalled;
232
        wire    mem_valid, mem_ack, mem_stall,
233
                mem_cyc, mem_stb, mem_we;
234
        wire    [31:0]   mem_addr, mem_data, mem_result;
235
 
236
 
237
 
238
        //
239
        //
240
        //      PIPELINE STAGE #5 :: Write-back
241
        //              Variable declarations
242
        //
243
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc;
244
        wire    [4:0]    wr_reg_id;
245
        wire    [31:0]   wr_reg_vl;
246
        wire    w_switch_to_interrupt, w_release_from_interrupt;
247
        reg     [31:0]   upc, ipc;
248
 
249
 
250
 
251
        //
252
        //      MASTER: clock enable.
253
        //
254
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep)&&(~mem_rdbusy);
255
 
256
 
257
        //
258
        //      PIPELINE STAGE #1 :: Prefetch
259
        //              Calculate stall conditions
260
        assign          pf_ce = (~dcd_stalled);
261
 
262
        //
263
        //      PIPELINE STAGE #2 :: Instruction Decode
264
        //              Calculate stall conditions
265
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
266
        assign          dcd_stalled = (dcdvalid)&&(
267
                                        (op_stall)
268
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
269
                                        ||((opvalid)&&(op_wr_pc)));
270
        //
271
        //      PIPELINE STAGE #3 :: Read Operands
272
        //              Calculate stall conditions
273
        assign  op_stall = (opvalid)&&(
274
                                ((mem_stalled)&&(opM))
275
                                ||((alu_stall)&&(~opM)));
276
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
277
 
278
        //
279
        //      PIPELINE STAGE #4 :: ALU / Memory
280
        //              Calculate stall conditions
281
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
282
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
283
        assign  alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~new_pc);
284
        //
285
        assign  mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~new_pc)&&(set_cond);
286
        assign  mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
287
                                (~master_ce)
288
                                // Stall waiting for flags to be valid
289
                                ||((~opF[8])&&(
290
                                        ((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))))
291
                                        // Do I need this last condition?
292
                                        //||((wr_flags_ce)&&(alu_gie==op_gie))))
293
                                // Or waiting for a write to the PC register
294
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&(wr_write_pc))));
295
 
296
 
297
        //
298
        //
299
        //      PIPELINE STAGE #1 :: Prefetch
300
        //
301
        //
302
`ifdef  SINGLE_FETCH
303
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
304
                                instruction, instruction_pc, instruction_gie,
305
                                        pf_valid,
306
                                pf_cyc, pf_stb, pf_we, pf_addr,
307
                                        pf_data,
308
                                pf_ack, pf_stall, i_wb_data);
309
`else // Pipe fetch
310 3 dgisselq
        pipefetch       #(RESET_ADDRESS)
311
                        pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
312 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
313
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
314 3 dgisselq
                                        pf_ack, pf_stall, i_wb_data,
315
                                mem_cyc);
316 2 dgisselq
        assign  instruction_gie = gie;
317
`endif
318
 
319
        always @(posedge i_clk)
320
                if (i_rst)
321
                        dcdvalid <= 1'b0;
322
                else if (dcd_ce)
323
                        dcdvalid <= (~new_pc);
324
                else if ((~dcd_stalled)||(new_pc))
325
                        dcdvalid <= 1'b0;
326
 
327
        always @(posedge i_clk)
328
                if (dcd_ce)
329
                begin
330
                        dcd_pc <= instruction_pc+1;
331
 
332
                        // Record what operation we are doing
333
                        dcdOp <= instruction[31:28];
334
 
335
                        // Default values
336
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
337
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
338
                        dcdM    <= 1'b0;
339
                        dcdF_wr <= 1'b1;
340
                        dcd_break <= 1'b0;
341
 
342
                        // Set the condition under which we do this operation
343
                        // The top four bits are a mask, the bottom four the
344
                        // value the flags must equal once anded with the mask
345
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
346
                        casez(instruction[31:28])
347
                        4'h2: begin // Move instruction
348
                                if (~instruction_gie)
349
                                begin
350
                                        dcdA[4] <= instruction[20];
351
                                        dcdB[4] <= instruction[15];
352
                                end
353
                                dcdA_wr <= 1'b1;
354
                                dcdA_rd <= 1'b0;
355
                                dcdB_rd <= 1'b1;
356
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
357
                                dcdF_wr <= 1'b0; // Don't write flags
358
                                end
359
                        4'h3: begin // Load immediate
360
                                dcdA_wr <= 1'b1;
361
                                dcdA_rd <= 1'b0;
362
                                dcdB_rd <= 1'b0;
363
                                r_dcdI <= { instruction[23:0] };
364
                                dcdF_wr <= 1'b0; // Don't write flags
365
                                dcdF    <= 4'h8; // This is unconditional
366
                                dcdOp <= 4'h2;
367
                                end
368
                        4'h4: begin // Load immediate special
369
                                dcdF_wr <= 1'b0; // Don't write flags
370
                                r_dcdI <= { 8'h00, instruction[15:0] };
371
                                if (instruction[27:24] == 4'he)
372
                                begin
373
                                        // NOOP instruction
374
                                        dcdA_wr <= 1'b0;
375
                                        dcdA_rd <= 1'b0;
376
                                        dcdB_rd <= 1'b0;
377
                                        dcdOp <= 4'h2;
378
                                        dcd_break <= 1'b1;//Could be a break ins
379
                                end else if (instruction[27:24] == 4'hf)
380
                                begin // Load partial immediate(s)
381
                                        dcdA_wr <= 1'b1;
382
                                        dcdA_rd <= 1'b1;
383
                                        dcdB_rd <= 1'b0;
384
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
385
                                        dcdOp <= { 3'h3, instruction[20] };
386
                                end else begin
387
                                        ; // Multiply instruction place holder
388
                                end end
389
                        4'b011?: begin // Load/Store
390
                                dcdF_wr <= 1'b0; // Don't write flags
391
                                dcdA_wr <= (~instruction[28]); // Write on loads
392
                                dcdA_rd <= (instruction[28]); // Read on stores
393
                                dcdB_rd <= instruction[20];
394
                                if (instruction[20])
395
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
396
                                else
397
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
398
                                dcdM <= 1'b1; // Memory operation
399
                                end
400
                        default: begin
401
                                dcdA <= { instruction_gie, instruction[27:24] };
402
                                dcdB <= { instruction_gie, instruction[19:16] };
403
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
404
                                dcdA_rd <= 1'b1;
405
                                dcdB_rd <= instruction[20];
406
                                if (instruction[20])
407
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
408
                                else
409
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
410
                                end
411
                        endcase
412
 
413
 
414
                        dcd_gie <= instruction_gie;
415
                end
416
 
417
 
418
        //
419
        //
420
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
421
        //
422
        //
423
 
424
        always @(posedge i_clk)
425
                if (op_ce) // &&(dcdvalid))
426
                begin
427
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
428
                                r_opA <= wr_reg_vl;
429
                        else if (dcdA == { dcd_gie, `CPU_PC_REG })
430
                                r_opA <= dcd_pc;
431
                        else if (dcdA[3:0] == `CPU_PC_REG)
432
                                r_opA <= (dcdA[4])?upc:ipc;
433
                        else
434
                                r_opA <= regset[dcdA];
435
                end
436
        wire    [31:0]   dcdI;
437
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
438
        always @(posedge i_clk)
439
                if (op_ce) // &&(dcdvalid))
440
                begin
441
                        if (~dcdB_rd)
442
                                r_opB <= dcdI;
443
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
444
                                r_opB <= wr_reg_vl + dcdI;
445
                        else if (dcdB == { dcd_gie, `CPU_PC_REG })
446
                                r_opB <= dcd_pc + dcdI;
447
                        else if (dcdB[3:0] == `CPU_PC_REG)
448
                                r_opB <= ((dcdB[4])?upc:ipc) + dcdI;
449
                        else
450
                                r_opB <= regset[dcdB] + dcdI;
451
                end
452
 
453
        // The logic here has become more complex than it should be, no thanks
454
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
455
        // be two sets of four bits: the top bits specify what bits matter, the
456
        // bottom specify what those top bits must equal.  However, two of
457
        // conditions check whether bits are on, and those are the only two
458
        // conditions checking those bits.  Therefore, Vivado complains that
459
        // these two bits are redundant.  Hence the convoluted expression
460
        // below, arriving at what we finally want in the (now wire net)
461
        // opF.
462 3 dgisselq
`define NEWCODE
463 2 dgisselq
`ifdef  NEWCODE
464
        always @(posedge i_clk)
465
                if (op_ce)
466
                begin // Set the flag condition codes
467
                        case(dcdF[2:0])
468
                        3'h0:   r_opF <= 7'h80; // Always
469
                        3'h1:   r_opF <= 7'h11; // Z
470
                        3'h2:   r_opF <= 7'h10; // NE
471
                        3'h3:   r_opF <= 7'h20; // GE (!N)
472
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
473
                        3'h5:   r_opF <= 7'h24; // LT
474
                        3'h6:   r_opF <= 7'h02; // C
475
                        3'h7:   r_opF <= 7'h08; // V
476
                        endcase
477
                end
478
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
479
`else
480
        always @(posedge i_clk)
481
                if (op_ce)
482
                begin // Set the flag condition codes
483
                        case(dcdF[2:0])
484
                        3'h0:   opF <= 9'h100;  // Always
485
                        3'h1:   opF <= 9'h011;  // Z
486
                        3'h2:   opF <= 9'h010;  // NE
487
                        3'h3:   opF <= 9'h040;  // GE (!N)
488
                        3'h4:   opF <= 9'h050;  // GT (!N&!Z)
489
                        3'h5:   opF <= 9'h044;  // LT
490
                        3'h6:   opF <= 9'h022;  // C
491
                        3'h7:   opF <= 9'h088;  // V
492
                        endcase
493
                end
494
`endif
495
 
496
        always @(posedge i_clk)
497
                if (i_rst)
498
                        opvalid <= 1'b0;
499
                else if (op_ce)
500
                        // Do we have a valid instruction?
501
                        //   The decoder may vote to stall one of its
502
                        //   instructions based upon something we currently
503
                        //   have in our queue.  This instruction must then
504
                        //   move forward, and get a stall cycle inserted.
505
                        //   Hence, the test on dcd_stalled here.  If we must
506
                        //   wait until our operands are valid, then we aren't
507
                        //   valid yet until then.
508
                        opvalid<= (~new_pc)&&(dcdvalid)&&(~dcd_stalled);
509
                else if ((~op_stall)||(new_pc))
510
                        opvalid <= 1'b0;
511
 
512
        // Here's part of our debug interface.  When we recognize a break
513
        // instruction, we set the op_break flag.  That'll prevent this
514
        // instruction from entering the ALU, and cause an interrupt before
515
        // this instruction.  Thus, returning to this code will cause the
516
        // break to repeat and continue upon return.  To get out of this
517
        // condition, replace the break instruction with what it is supposed
518
        // to be, step through it, and then replace it back.  In this fashion,
519
        // a debugger can step through code.
520
        always @(posedge i_clk)
521
                if (i_rst)
522
                        op_break <= 1'b0;
523
                else if (op_ce)
524
                        op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
525
                else if ((~op_stall)||(new_pc))
526
                        op_break <= 1'b0;
527
 
528
        always @(posedge i_clk)
529
                if (op_ce)
530
                begin
531
                        opn    <= dcdOp;        // Which ALU operation?
532
                        opM    <= dcdM;         // Is this a memory operation?
533
                        // Will we write the flags/CC Register with our result?
534
                        opF_wr <= dcdF_wr;
535
                        // Will we be writing our results into a register?
536
                        opR_wr <= dcdA_wr;
537
                        // What register will these results be written into?
538
                        opR    <= dcdA;
539
                        // User level (1), vs supervisor (0)/interrupts disabled
540
                        op_gie <= dcd_gie;
541
 
542
                        // We're not done with these yet--we still need them
543
                        // for the unclocked assign.  We need the unclocked
544
                        // assign so that there's no wait state between an
545
                        // ALU or memory result and the next register that may
546
                        // use that value.
547
                        opA_cc <= {dcdA[4], (dcdA[3:0] == `CPU_CC_REG) };
548
                        opA_rd <= dcdA_rd;
549
                        opB_cc <= {dcdB[4], (dcdB[3:0] == `CPU_CC_REG) };
550
                        opB_rd <= dcdB_rd;
551
                        op_pc  <= dcd_pc;
552
                        //
553
                        op_wr_pc <= ((dcdA_wr)&&(dcdA[3:0] == `CPU_PC_REG));
554
                end
555
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
556
 
557
        // This is tricky.  First, the PC and Flags registers aren't kept in
558
        // register set but in special registers of their own.  So step one
559
        // is to select the right register.  Step to is to replace that
560
        // register with the results of an ALU or memory operation, if such
561
        // results are now available.  Otherwise, we'd need to insert a wait
562
        // state of some type.
563
        //
564
        // The alternative approach would be to define some sort of
565
        // op_stall wire, which would stall any upstream stage.
566
        // We'll create a flag here to start our coordination.  Once we
567
        // define this flag to something other than just plain zero, then
568
        // the stalls will already be in place.
569
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&
570
                                (((opvalid)&&(opR_wr)&&(opR == dcdA))
571
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))
572
                                        ||((mem_valid)&&(mem_wreg == dcdA)));
573
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)
574
                                &&(((opvalid)&&(opR_wr)&&(opR == dcdB))
575
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))
576
                                        ||((mem_valid)&&(mem_wreg == dcdB)));
577
        assign  dcdF_stall = (dcdvalid)&&(((dcdF[3])
578
                                        ||(dcdA[3:0]==`CPU_CC_REG)
579
                                        ||(dcdB[3:0]==`CPU_CC_REG))
580
                                &&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
581
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
582
        assign  opA = { r_opA[31:8], ((opA_cc[0]) ?
583
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
584
        assign  opB = { r_opB[31:8], ((opB_cc[0]) ?
585 3 dgisselq
                        ((opB_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
586 2 dgisselq
 
587
        //
588
        //
589
        //      PIPELINE STAGE #4 :: Apply Instruction
590
        //
591
        //
592
        cpuops  doalu(i_clk, i_rst, alu_ce,
593
                        (opvalid)&&(~opM), opn, opA, opB,
594
                        alu_result, alu_flags, alu_valid);
595
 
596
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
597
        initial alF_wr   = 1'b0;
598
        initial alu_wr   = 1'b0;
599
        always @(posedge i_clk)
600
                if (i_rst)
601
                begin
602
                        alu_wr   <= 1'b0;
603
                        alF_wr   <= 1'b0;
604
                end else if (alu_ce)
605
                begin
606
                        alu_reg <= opR;
607
                        alu_wr  <= (opR_wr)&&(set_cond);
608
                        alF_wr  <= (opF_wr)&&(set_cond);
609
                end else begin
610
                        // These are strobe signals, so clear them if not
611
                        // set for any particular clock
612
                        alu_wr <= 1'b0;
613
                        alF_wr <= 1'b0;
614
                end
615
        always @(posedge i_clk)
616
                if ((alu_ce)||(mem_ce))
617
                        alu_gie  <= op_gie;
618
        always @(posedge i_clk)
619
                if ((alu_ce)||(mem_ce))
620
                        alu_pc  <= op_pc;
621
        initial alu_pc_valid = 1'b0;
622
        always @(posedge i_clk)
623
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~new_pc)
624
                                        &&((~opM)
625
                                                ||(~mem_stalled));
626
 
627
        memops  domem(i_clk, i_rst, mem_ce,
628
                                (opn[0]), opB, opA, opR,
629
                                mem_busy, mem_valid, mem_wreg, mem_result,
630
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
631
                                mem_ack, mem_stall, i_wb_data);
632
        assign  mem_rdbusy = ((mem_cyc)&&(~mem_we));
633
 
634
        // Either the prefetch or the instruction gets the memory bus, but 
635
        // never both.
636
        wbarbiter       #(32,32) pformem(i_clk, i_rst,
637
                // Prefetch access to the arbiter
638
                pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall,
639
                // Memory access to the arbiter
640
                mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall,
641
                // Common wires, in and out, of the arbiter
642
                o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack,
643
                        i_wb_stall);
644
 
645
        //
646
        //
647
        //      PIPELINE STAGE #5 :: Write-back results
648
        //
649
        //
650
        // This stage is not allowed to stall.  If results are ready to be
651
        // written back, they are written back at all cost.  Sleepy CPU's
652
        // won't prevent write back, nor debug modes, halting the CPU, nor
653
        // anything else.  Indeed, the (master_ce) bit is only as relevant
654
        // as knowinig something is available for writeback.
655
 
656
        //
657
        // Write back to our generic register set ...
658
        // When shall we write back?  On one of two conditions
659
        //      Note that the flags needed to be checked before issuing the
660
        //      bus instruction, so they don't need to be checked here.
661
        //      Further, alu_wr includes (set_cond), so we don't need to
662
        //      check for that here either.
663
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
664
        // Which register shall be written?
665
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
666
        // Are we writing to the PC?
667
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
668
        // What value to write?
669
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
670
        always @(posedge i_clk)
671
                if (wr_reg_ce)
672
                        regset[wr_reg_id] <= wr_reg_vl;
673
 
674
        //
675
        // Write back to the condition codes/flags register ...
676
        // When shall we write to our flags register?  alF_wr already
677
        // includes the set condition ...
678
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
679
        assign  w_uflags = { 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
680
        assign  w_iflags = { break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
681
        // What value to write?
682
        always @(posedge i_clk)
683
                // If explicitly writing the register itself
684
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
685
                        flags <= wr_reg_vl[3:0];
686
                // Otherwise if we're setting the flags from an ALU operation
687
                else if ((wr_flags_ce)&&(alu_gie))
688
                        flags <= alu_flags;
689
                else if ((i_halt)&&(i_dbg_we)
690
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
691
                        flags <= i_dbg_data[3:0];
692
 
693
        always @(posedge i_clk)
694
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
695
                        iflags <= wr_reg_vl[3:0];
696
                else if ((wr_flags_ce)&&(~alu_gie))
697
                        iflags <= alu_flags;
698
                else if ((i_halt)&&(i_dbg_we)
699
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
700
                        iflags <= i_dbg_data[3:0];
701
 
702
        // The 'break' enable  bit.  This bit can only be set from supervisor
703
        // mode.  It control what the CPU does upon encountering a break
704
        // instruction.
705
        //
706
        // The goal, upon encountering a break is that the CPU should stop and
707
        // not execute the break instruction, choosing instead to enter into
708
        // either interrupt mode or halt first.  
709
        //      if ((break_en) AND (break_instruction)) // user mode or not
710
        //              HALT CPU
711
        //      else if (break_instruction) // only in user mode
712
        //              set an interrupt flag, go to supervisor mode
713
        //              allow supervisor to step the CPU.
714
        //      Upon a CPU halt, any break condition will be reset.  The
715
        //      external debugger will then need to deal with whatever
716
        //      condition has taken place.
717
        initial break_en = 1'b0;
718
        always @(posedge i_clk)
719
                if ((i_rst)||(i_halt))
720
                        break_en <= 1'b0;
721
                else if ((wr_reg_ce)&&(wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}))
722
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
723
        assign  o_break = (break_en)&&(op_break);
724
 
725
 
726
        // The sleep register.  Setting the sleep register causes the CPU to
727
        // sleep until the next interrupt.  Setting the sleep register within
728
        // interrupt mode causes the processor to halt until a reset.  This is
729
        // a panic/fault halt.
730
        always @(posedge i_clk)
731
                if ((i_rst)||((i_interrupt)&&(gie)))
732
                        sleep <= 1'b0;
733
                else if ((wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG))
734
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
735
                else if ((i_halt)&&(i_dbg_we)
736
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
737
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
738
 
739
        always @(posedge i_clk)
740
                if ((i_rst)||(w_switch_to_interrupt))
741
                        step <= 1'b0;
742
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4:0] == {1'b1,`CPU_CC_REG}))
743
                        step <= wr_reg_vl[`CPU_STEP_BIT];
744
                else if ((i_halt)&&(i_dbg_we)
745
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
746
                        step <= i_dbg_data[`CPU_STEP_BIT];
747
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
748
                        step <= 1'b0;
749
 
750
        // The GIE register.  Only interrupts can disable the interrupt register
751
        assign  w_switch_to_interrupt = (gie)&&(
752
                        // On interrupt (obviously)
753
                        (i_interrupt)
754
                        // If we are stepping the CPU
755
                        ||((master_ce)&&(alu_pc_valid)&&(step))
756
                        // If we encounter a break instruction, if the break
757
                        //      enable isn't not set.
758
                        ||((master_ce)&&(op_break))
759
                        // If we write to the CC register
760
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
761
                                &&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
762
                        // Or if, in debug mode, we write to the CC register
763
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
764
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
765
                        );
766
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
767
                        // Then if we write the CC register
768
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
769
                                &&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
770
                        // Or if, in debug mode, we write the CC register
771
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
772
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
773
                        );
774
        always @(posedge i_clk)
775
                if (i_rst)
776
                        gie <= 1'b0;
777
                else if (w_switch_to_interrupt)
778
                        gie <= 1'b0;
779
                else if (w_release_from_interrupt)
780
                        gie <= 1'b1;
781
 
782
        //
783
        // Write backs to the PC register, and general increments of it
784
        //      We support two: upc and ipc.  If the instruction is normal,
785
        // we increment upc, if interrupt level we increment ipc.  If
786
        // the instruction writes the PC, we write whichever PC is appropriate.
787
        //
788
        // Do we need to all our partial results from the pipeline?
789
        // What happens when the pipeline has gie and ~gie instructions within
790
        // it?  Do we clear both?  What if a gie instruction tries to clear
791
        // a non-gie instruction?
792
        always @(posedge i_clk)
793
                if (i_rst)
794
                        upc <= RESET_ADDRESS;
795
                else if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
796
                        upc <= wr_reg_vl;
797
                else if ((alu_gie)&&(alu_pc_valid))
798
                        upc <= alu_pc;
799
                else if ((i_halt)&&(i_dbg_we)
800
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
801
                        upc <= i_dbg_data;
802
 
803
        always @(posedge i_clk)
804
                if (i_rst)
805
                        ipc <= RESET_ADDRESS;
806
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
807
                        ipc <= wr_reg_vl;
808
                else if ((~alu_gie)&&(alu_pc_valid))
809
                        ipc <= alu_pc;
810
                else if ((i_halt)&&(i_dbg_we)
811
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
812
                        ipc <= i_dbg_data;
813
 
814
        always @(posedge i_clk)
815
                if (i_rst)
816
                        pf_pc <= RESET_ADDRESS;
817
                else if (w_switch_to_interrupt)
818
                        pf_pc <= ipc;
819
                else if (w_release_from_interrupt)
820
                        pf_pc <= upc;
821
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
822
                        pf_pc <= wr_reg_vl;
823
                else if ((i_halt)&&(i_dbg_we)
824
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
825
                        pf_pc <= i_dbg_data;
826
                // else if (pf_ce)
827
                else if (dcd_ce)
828
                        pf_pc <= pf_pc + 1;
829
 
830
        initial new_pc = 1'b1;
831
        always @(posedge i_clk)
832
                if (i_rst)
833
                        new_pc <= 1'b1;
834
                else if (w_switch_to_interrupt)
835
                        new_pc <= 1'b1;
836
                else if (w_release_from_interrupt)
837
                        new_pc <= 1'b1;
838
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
839
                        new_pc <= 1'b1;
840
                else if ((i_halt)&&(i_dbg_we)
841
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
842
                        new_pc <= 1'b1;
843
                else
844
                        new_pc <= 1'b0;
845
 
846
        //
847
        // The debug interface
848
        always @(posedge i_clk)
849
                begin
850
                        o_dbg_reg <= regset[i_dbg_reg];
851
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
852
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
853
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
854
                                o_dbg_reg <= { 25'h00, step, gie, sleep,
855
                                        ((i_dbg_reg[4])?flags:iflags) };
856
                end
857
        always @(posedge i_clk)
858
                o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
859
                        ||((~opvalid)&&(~i_rst))
860
                        ||((~dcdvalid)&&(~i_rst));
861
 
862
        //
863
        //
864
        // Produce accounting outputs: Account for any CPU stalls, so we can
865
        // later evaluate how well we are doing.
866
        //
867
        //
868
        assign  o_mem_stall  = (~i_halt)&&(~sleep)&&(opvalid)&&(mem_busy)
869
                                        &&(~pf_cyc);
870
        assign  o_pf_stall   = (~i_halt)&&(~sleep)&&(((pf_ce)&&(~pf_valid))
871
                                        ||((opvalid)&&(mem_busy)&&(pf_cyc)));
872
        // assign       o_alu_stall  = (~i_halt)&&(~sleep)&&(~mem_busy)&&
873
                                        // ((alu_stall)||(~alu_valid));
874
        assign  o_alu_stall  = alu_pc_valid;
875
endmodule

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