OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9
//              The instruction set is about as RISC as you can get, there are
10
//              only 16 instruction types supported (of which one isn't yet
11
//              supported ...)  Please see the accompanying iset.html file
12
//              for a description of these instructions.
13
//
14
//              All instructions are 32-bits wide.  All bus accesses, both
15
//              address and data, are 32-bits over a wishbone bus.
16
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19
//              1. Prefetch, returns the instruction from memory.  On the
20
//              Basys board that I'm working on, one instruction may be
21
//              issued every 20 clocks or so, unless and until I implement a
22
//              cache or local memory.
23
//
24
//              2. Instruction Decode
25
//
26
//              3. Read Operands
27
//
28
//              4. Apply Instruction
29
//
30
//              4. Write-back Results
31
//
32
//      A lot of difficult work has been placed into the pipeline stall
33
//      handling.  My original proposal was not to allow pipeline stalls at all.
34
//      The idea would be that the CPU would just run every clock and whatever
35
//      stalled answer took place would just get fixed a clock or two later,
36
//      meaning that the compiler could just schedule everything out.
37
//      This idea died at the memory interface, which can take a variable
38
//      amount of time to read or write any value, thus the whole CPU needed
39
//      to stall on a stalled memory access.
40
//
41
//      My next idea was to just let things complete.  I.e., once an instrution
42
//      starts, it continues to completion no matter what and we go on.  This
43
//      failed at writing the PC.  If the PC gets written in something such as
44
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
45
//      later, if whether or not something happens in those clocks depends
46
//      upon the instruction fetch filling the pipeline, then the CPU has a
47
//      non-deterministic behavior.
48
//
49
//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
51
//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
53
//      read or a write, there is no undoing it--since peripherals on the
54
//      bus may act upon the answer with whatever side effects they might
55
//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
94
// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
99
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
104
//              http://www.gnu.org/licenses/gpl.html
105
//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109 25 dgisselq
`define CPU_CC_REG      4'he
110 2 dgisselq
`define CPU_PC_REG      4'hf
111 25 dgisselq
`define CPU_TRAP_BIT    9
112 2 dgisselq
`define CPU_BREAK_BIT   7
113
`define CPU_STEP_BIT    6
114
`define CPU_GIE_BIT     5
115
`define CPU_SLEEP_BIT   4
116
module  zipcpu(i_clk, i_rst, i_interrupt,
117
                // Debug interface
118 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
119
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
120 2 dgisselq
                        o_break,
121
                // CPU interface to the wishbone bus
122
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
123
                        i_wb_ack, i_wb_stall, i_wb_data,
124
                // Accounting/CPU usage interface
125 9 dgisselq
                o_op_stall, o_pf_stall, o_i_count);
126 2 dgisselq
        parameter       RESET_ADDRESS=32'h0100000;
127
        input                   i_clk, i_rst, i_interrupt;
128
        // Debug interface -- inputs
129 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
130 2 dgisselq
        input           [4:0]    i_dbg_reg;
131
        input                   i_dbg_we;
132
        input           [31:0]   i_dbg_data;
133
        // Debug interface -- outputs
134
        output  reg             o_dbg_stall;
135
        output  reg     [31:0]   o_dbg_reg;
136 25 dgisselq
        output  reg     [1:0]    o_dbg_cc;
137 2 dgisselq
        output  wire            o_break;
138
        // Wishbone interface -- outputs
139
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
140
        output  wire    [31:0]   o_wb_addr, o_wb_data;
141
        // Wishbone interface -- inputs
142
        input                   i_wb_ack, i_wb_stall;
143
        input           [31:0]   i_wb_data;
144
        // Accounting outputs ... to help us count stalls and usage
145 9 dgisselq
        output  wire            o_op_stall;
146 2 dgisselq
        output  wire            o_pf_stall;
147 9 dgisselq
        output  wire            o_i_count;
148 2 dgisselq
 
149 25 dgisselq
 
150 2 dgisselq
        // Registers
151
        reg     [31:0]   regset [0:31];
152 9 dgisselq
 
153
        // Condition codes
154 25 dgisselq
        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
155
        wire    [9:0]    w_uflags, w_iflags;
156
        reg             trap, break_en, step, gie, sleep;
157 2 dgisselq
 
158 9 dgisselq
        // The master chip enable
159
        wire            master_ce;
160 2 dgisselq
 
161
        //
162
        //
163
        //      PIPELINE STAGE #1 :: Prefetch
164
        //              Variable declarations
165
        //
166 9 dgisselq
        reg     [31:0]   pf_pc;
167 25 dgisselq
        reg             new_pc, op_break;
168 18 dgisselq
        wire    clear_pipeline;
169 25 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache || op_break;
170 9 dgisselq
 
171
        wire            dcd_stalled;
172 2 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
173
        wire    [31:0]   pf_addr, pf_data;
174
        wire    [31:0]   instruction, instruction_pc;
175
        wire    pf_valid, instruction_gie;
176
 
177
        //
178
        //
179
        //      PIPELINE STAGE #2 :: Instruction Decode
180
        //              Variable declarations
181
        //
182
        //
183 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
184 2 dgisselq
        wire            op_stall, dcd_ce;
185
        reg     [3:0]    dcdOp;
186
        reg     [4:0]    dcdA, dcdB;
187 25 dgisselq
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
188 2 dgisselq
        reg     [3:0]    dcdF;
189
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
190
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
191
        reg     [31:0]   dcd_pc;
192
        reg     [23:0]   r_dcdI;
193
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
194
 
195
 
196
 
197
        //
198
        //
199
        //      PIPELINE STAGE #3 :: Read Operands
200
        //              Variable declarations
201
        //
202
        //
203
        //
204
        // Now, let's read our operands
205
        reg     [4:0]    alu_reg;
206
        reg     [3:0]    opn;
207
        reg     [4:0]    opR;
208
        reg     [31:0]   r_opA, r_opB, op_pc;
209 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
210 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
211 25 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie,
212 2 dgisselq
                        opA_rd, opB_rd;
213 25 dgisselq
        wire    [9:0]    opFl;
214 3 dgisselq
        reg     [6:0]    r_opF;
215 2 dgisselq
        wire    [8:0]    opF;
216
        wire            op_ce;
217
 
218
 
219
 
220
        //
221
        //
222
        //      PIPELINE STAGE #4 :: ALU / Memory
223
        //              Variable declarations
224
        //
225
        //
226
        reg     [31:0]   alu_pc;
227
        reg             alu_pc_valid;;
228
        wire            alu_ce, alu_stall;
229
        wire    [31:0]   alu_result;
230
        wire    [3:0]    alu_flags;
231
        wire            alu_valid;
232
        wire            set_cond;
233
        reg             alu_wr, alF_wr, alu_gie;
234
 
235
 
236
 
237
        wire    mem_ce, mem_stalled;
238
        wire    mem_valid, mem_ack, mem_stall,
239
                mem_cyc, mem_stb, mem_we;
240 9 dgisselq
        wire    [4:0]    mem_wreg;
241
 
242
        wire            mem_busy, mem_rdbusy;
243 2 dgisselq
        wire    [31:0]   mem_addr, mem_data, mem_result;
244
 
245
 
246
 
247
        //
248
        //
249
        //      PIPELINE STAGE #5 :: Write-back
250
        //              Variable declarations
251
        //
252 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
253 2 dgisselq
        wire    [4:0]    wr_reg_id;
254
        wire    [31:0]   wr_reg_vl;
255
        wire    w_switch_to_interrupt, w_release_from_interrupt;
256
        reg     [31:0]   upc, ipc;
257
 
258
 
259
 
260
        //
261
        //      MASTER: clock enable.
262
        //
263
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep)&&(~mem_rdbusy);
264
 
265
 
266
        //
267
        //      PIPELINE STAGE #1 :: Prefetch
268
        //              Calculate stall conditions
269
 
270
        //
271
        //      PIPELINE STAGE #2 :: Instruction Decode
272
        //              Calculate stall conditions
273
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
274
        assign          dcd_stalled = (dcdvalid)&&(
275
                                        (op_stall)
276
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
277 25 dgisselq
                                        ||((opvalid)&&((op_wr_pc)||(opR_cc))));
278 2 dgisselq
        //
279
        //      PIPELINE STAGE #3 :: Read Operands
280
        //              Calculate stall conditions
281 25 dgisselq
        assign  op_stall = ((mem_stalled)&&(opvalid_mem))
282
                                ||((alu_stall)&&(opvalid_alu));
283 2 dgisselq
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
284
 
285
        //
286
        //      PIPELINE STAGE #4 :: ALU / Memory
287
        //              Calculate stall conditions
288 25 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu))
289
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
290
                                &&(wr_write_pc)||(wr_write_cc));
291
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
292 2 dgisselq
        //
293 25 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
294
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
295 2 dgisselq
                                (~master_ce)
296
                                // Stall waiting for flags to be valid
297
                                // Or waiting for a write to the PC register
298 25 dgisselq
                                // Or CC register, since that can change the
299
                                //  PC as well
300
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
301 2 dgisselq
 
302
 
303
        //
304
        //
305
        //      PIPELINE STAGE #1 :: Prefetch
306
        //
307
        //
308
`ifdef  SINGLE_FETCH
309 9 dgisselq
        wire            pf_ce;
310
 
311
        assign          pf_ce = (~dcd_stalled);
312 2 dgisselq
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
313
                                instruction, instruction_pc, instruction_gie,
314
                                        pf_valid,
315
                                pf_cyc, pf_stb, pf_we, pf_addr,
316
                                        pf_data,
317
                                pf_ack, pf_stall, i_wb_data);
318
`else // Pipe fetch
319 3 dgisselq
        pipefetch       #(RESET_ADDRESS)
320 18 dgisselq
                        pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc,
321 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
322
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
323 3 dgisselq
                                        pf_ack, pf_stall, i_wb_data,
324
                                mem_cyc);
325 2 dgisselq
        assign  instruction_gie = gie;
326
`endif
327
 
328
        always @(posedge i_clk)
329
                if (i_rst)
330
                        dcdvalid <= 1'b0;
331
                else if (dcd_ce)
332 18 dgisselq
                        dcdvalid <= (~clear_pipeline);
333
                else if ((~dcd_stalled)||(clear_pipeline))
334 2 dgisselq
                        dcdvalid <= 1'b0;
335
 
336
        always @(posedge i_clk)
337
                if (dcd_ce)
338
                begin
339
                        dcd_pc <= instruction_pc+1;
340
 
341
                        // Record what operation we are doing
342
                        dcdOp <= instruction[31:28];
343
 
344
                        // Default values
345
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
346
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
347 25 dgisselq
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
348
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
349
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
350
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
351 2 dgisselq
                        dcdM    <= 1'b0;
352
                        dcdF_wr <= 1'b1;
353
 
354
                        // Set the condition under which we do this operation
355
                        // The top four bits are a mask, the bottom four the
356
                        // value the flags must equal once anded with the mask
357
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
358
                        casez(instruction[31:28])
359
                        4'h2: begin // Move instruction
360
                                if (~instruction_gie)
361
                                begin
362
                                        dcdA[4] <= instruction[20];
363
                                        dcdB[4] <= instruction[15];
364
                                end
365
                                dcdA_wr <= 1'b1;
366
                                dcdA_rd <= 1'b0;
367
                                dcdB_rd <= 1'b1;
368
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
369
                                dcdF_wr <= 1'b0; // Don't write flags
370
                                end
371
                        4'h3: begin // Load immediate
372
                                dcdA_wr <= 1'b1;
373
                                dcdA_rd <= 1'b0;
374
                                dcdB_rd <= 1'b0;
375
                                r_dcdI <= { instruction[23:0] };
376
                                dcdF_wr <= 1'b0; // Don't write flags
377
                                dcdF    <= 4'h8; // This is unconditional
378
                                dcdOp <= 4'h2;
379
                                end
380 25 dgisselq
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
381
                                // Don't write flags except for multiplies
382
                                dcdF_wr <= (instruction[27:25] != 3'h7);
383 2 dgisselq
                                r_dcdI <= { 8'h00, instruction[15:0] };
384
                                if (instruction[27:24] == 4'he)
385
                                begin
386
                                        // NOOP instruction
387
                                        dcdA_wr <= 1'b0;
388
                                        dcdA_rd <= 1'b0;
389
                                        dcdB_rd <= 1'b0;
390
                                        dcdOp <= 4'h2;
391
                                end else if (instruction[27:24] == 4'hf)
392
                                begin // Load partial immediate(s)
393
                                        dcdA_wr <= 1'b1;
394
                                        dcdA_rd <= 1'b1;
395
                                        dcdB_rd <= 1'b0;
396
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
397 25 dgisselq
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
398
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
399 2 dgisselq
                                        dcdOp <= { 3'h3, instruction[20] };
400
                                end else begin
401 25 dgisselq
                                        // Actual multiply instruction
402
                                        r_dcdI <= { 8'h00, instruction[15:0] };
403
                                        dcdA_rd <= 1'b1;
404
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
405
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
406 2 dgisselq
                                end end
407
                        4'b011?: begin // Load/Store
408
                                dcdF_wr <= 1'b0; // Don't write flags
409
                                dcdA_wr <= (~instruction[28]); // Write on loads
410
                                dcdA_rd <= (instruction[28]); // Read on stores
411
                                dcdB_rd <= instruction[20];
412
                                if (instruction[20])
413
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
414
                                else
415
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
416
                                dcdM <= 1'b1; // Memory operation
417
                                end
418
                        default: begin
419
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
420
                                dcdA_rd <= 1'b1;
421
                                dcdB_rd <= instruction[20];
422
                                if (instruction[20])
423
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
424
                                else
425
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
426
                                end
427
                        endcase
428
 
429
 
430
                        dcd_gie <= instruction_gie;
431
                end
432 25 dgisselq
        always @(posedge i_clk)
433
                if (dcd_ce)
434
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
435
                else
436
                        dcd_break <= 1'b0;
437 2 dgisselq
 
438
 
439
        //
440
        //
441
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
442
        //
443
        //
444 25 dgisselq
        assign  w_opA = regset[dcdA];
445
        assign  w_opB = regset[dcdB];
446 2 dgisselq
        always @(posedge i_clk)
447
                if (op_ce) // &&(dcdvalid))
448
                begin
449
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
450
                                r_opA <= wr_reg_vl;
451 25 dgisselq
                        else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
452 2 dgisselq
                                r_opA <= dcd_pc;
453 25 dgisselq
                        else if (dcdA_pc)
454
                                r_opA <= upc;
455
                        else if (dcdA_cc)
456
                                r_opA <= { w_opA[31:10], (dcd_gie)?w_uflags:w_iflags };
457 2 dgisselq
                        else
458 25 dgisselq
                                r_opA <= w_opA;
459 2 dgisselq
                end
460
        wire    [31:0]   dcdI;
461
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
462
        always @(posedge i_clk)
463
                if (op_ce) // &&(dcdvalid))
464
                begin
465
                        if (~dcdB_rd)
466
                                r_opB <= dcdI;
467
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
468
                                r_opB <= wr_reg_vl + dcdI;
469 25 dgisselq
                        else if ((dcdB_pc)&&(dcdB[4] == dcd_gie))
470 2 dgisselq
                                r_opB <= dcd_pc + dcdI;
471 25 dgisselq
                        else if (dcdB_pc) // & dcdB[4] != dcd_gie thus is user
472
                                r_opB <= upc + dcdI;
473
                        else if (dcdB_cc)
474
                                r_opB <= { w_opB[31:10], (dcd_gie)?w_uflags:w_iflags} + dcdI;
475 2 dgisselq
                        else
476
                                r_opB <= regset[dcdB] + dcdI;
477
                end
478
 
479
        // The logic here has become more complex than it should be, no thanks
480
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
481
        // be two sets of four bits: the top bits specify what bits matter, the
482
        // bottom specify what those top bits must equal.  However, two of
483
        // conditions check whether bits are on, and those are the only two
484
        // conditions checking those bits.  Therefore, Vivado complains that
485
        // these two bits are redundant.  Hence the convoluted expression
486
        // below, arriving at what we finally want in the (now wire net)
487
        // opF.
488
        always @(posedge i_clk)
489
                if (op_ce)
490
                begin // Set the flag condition codes
491
                        case(dcdF[2:0])
492
                        3'h0:   r_opF <= 7'h80; // Always
493
                        3'h1:   r_opF <= 7'h11; // Z
494
                        3'h2:   r_opF <= 7'h10; // NE
495
                        3'h3:   r_opF <= 7'h20; // GE (!N)
496
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
497
                        3'h5:   r_opF <= 7'h24; // LT
498
                        3'h6:   r_opF <= 7'h02; // C
499
                        3'h7:   r_opF <= 7'h08; // V
500
                        endcase
501
                end
502
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
503
 
504
        always @(posedge i_clk)
505
                if (i_rst)
506 25 dgisselq
                begin
507
                        opvalid     <= 1'b0;
508
                        opvalid_alu <= 1'b0;
509
                        opvalid_mem <= 1'b0;
510
                end else if (op_ce)
511
                begin
512 2 dgisselq
                        // Do we have a valid instruction?
513
                        //   The decoder may vote to stall one of its
514
                        //   instructions based upon something we currently
515
                        //   have in our queue.  This instruction must then
516
                        //   move forward, and get a stall cycle inserted.
517
                        //   Hence, the test on dcd_stalled here.  If we must
518
                        //   wait until our operands are valid, then we aren't
519
                        //   valid yet until then.
520 18 dgisselq
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
521 25 dgisselq
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
522
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
523
                end else if ((~op_stall)||(clear_pipeline))
524
                begin
525
                        opvalid     <= 1'b0;
526
                        opvalid_alu <= 1'b0;
527
                        opvalid_mem <= 1'b0;
528
                end
529 2 dgisselq
 
530
        // Here's part of our debug interface.  When we recognize a break
531
        // instruction, we set the op_break flag.  That'll prevent this
532
        // instruction from entering the ALU, and cause an interrupt before
533
        // this instruction.  Thus, returning to this code will cause the
534
        // break to repeat and continue upon return.  To get out of this
535
        // condition, replace the break instruction with what it is supposed
536
        // to be, step through it, and then replace it back.  In this fashion,
537
        // a debugger can step through code.
538 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
539
        initial op_break = 1'b0;
540 2 dgisselq
        always @(posedge i_clk)
541 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
542
                else if (op_ce) op_break <= (dcd_break);
543
                else if ((clear_pipeline)||(~opvalid))
544
                                op_break <= 1'b0;
545 2 dgisselq
 
546
        always @(posedge i_clk)
547
                if (op_ce)
548
                begin
549
                        opn    <= dcdOp;        // Which ALU operation?
550 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
551 2 dgisselq
                        // Will we write the flags/CC Register with our result?
552 25 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
553 2 dgisselq
                        // Will we be writing our results into a register?
554
                        opR_wr <= dcdA_wr;
555
                        // What register will these results be written into?
556
                        opR    <= dcdA;
557 25 dgisselq
                        opR_cc <= (dcdA_wr)&&(dcdA_cc);
558 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
559
                        op_gie <= dcd_gie;
560
 
561
                        // We're not done with these yet--we still need them
562
                        // for the unclocked assign.  We need the unclocked
563
                        // assign so that there's no wait state between an
564
                        // ALU or memory result and the next register that may
565
                        // use that value.
566
                        opA_rd <= dcdA_rd;
567
                        opB_rd <= dcdB_rd;
568
                        op_pc  <= dcd_pc;
569
                        //
570 30 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
571 2 dgisselq
                end
572
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
573
 
574
        // This is tricky.  First, the PC and Flags registers aren't kept in
575
        // register set but in special registers of their own.  So step one
576
        // is to select the right register.  Step to is to replace that
577
        // register with the results of an ALU or memory operation, if such
578
        // results are now available.  Otherwise, we'd need to insert a wait
579
        // state of some type.
580
        //
581
        // The alternative approach would be to define some sort of
582
        // op_stall wire, which would stall any upstream stage.
583
        // We'll create a flag here to start our coordination.  Once we
584
        // define this flag to something other than just plain zero, then
585
        // the stalls will already be in place.
586 25 dgisselq
`define DONT_STALL_ON_OPA
587
`ifdef  DONT_STALL_ON_OPA
588
        reg     opA_alu;
589
        always @(posedge i_clk)
590
                if (op_ce)
591
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd);
592
        assign  opA = (opA_alu) ? alu_result : r_opA;
593
`else
594
        assign  opA = r_opA;
595
`endif
596
 
597
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
598 30 dgisselq
`define DONT_STALL_ON_OPA
599
`ifdef  DONT_STALL_ON_OPA
600 25 dgisselq
                // Skip the requirement on writing back opA
601
                // Stall on memory, since we'll always need to stall for a 
602
                // memory access anyway
603
                                ((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
604 30 dgisselq
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc))||
605 25 dgisselq
`else
606
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))||
607
`endif
608
                                        ((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
609 30 dgisselq
`define DONT_STALL_ON_OPB
610 25 dgisselq
`ifdef  DONT_STALL_ON_OPB
611
        reg     opB_alu;
612
        always @(posedge i_clk)
613
                if (op_ce)
614
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
615
        assign  opB = (opB_alu) ? alu_result : r_opB;
616
`else
617
        assign  opB = r_opB;
618
`endif
619
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
620
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
621 30 dgisselq
                                        &&((opvalid_mem)||(dcdI != 0)))
622
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
623 25 dgisselq
`ifdef  DONT_STALL_ON_OPB
624
`endif
625 30 dgisselq
                                ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
626
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
627
                                        &&(opvalid)&&(opR_cc);
628 2 dgisselq
        //
629
        //
630
        //      PIPELINE STAGE #4 :: Apply Instruction
631
        //
632
        //
633
        cpuops  doalu(i_clk, i_rst, alu_ce,
634 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
635 2 dgisselq
                        alu_result, alu_flags, alu_valid);
636
 
637
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
638
        initial alF_wr   = 1'b0;
639
        initial alu_wr   = 1'b0;
640
        always @(posedge i_clk)
641
                if (i_rst)
642
                begin
643
                        alu_wr   <= 1'b0;
644
                        alF_wr   <= 1'b0;
645
                end else if (alu_ce)
646
                begin
647
                        alu_reg <= opR;
648
                        alu_wr  <= (opR_wr)&&(set_cond);
649
                        alF_wr  <= (opF_wr)&&(set_cond);
650
                end else begin
651
                        // These are strobe signals, so clear them if not
652
                        // set for any particular clock
653
                        alu_wr <= 1'b0;
654
                        alF_wr <= 1'b0;
655
                end
656
        always @(posedge i_clk)
657
                if ((alu_ce)||(mem_ce))
658
                        alu_gie  <= op_gie;
659
        always @(posedge i_clk)
660
                if ((alu_ce)||(mem_ce))
661
                        alu_pc  <= op_pc;
662
        initial alu_pc_valid = 1'b0;
663
        always @(posedge i_clk)
664 18 dgisselq
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
665 25 dgisselq
                                        &&((opvalid_alu)||(~mem_stalled));
666 2 dgisselq
 
667
        memops  domem(i_clk, i_rst, mem_ce,
668
                                (opn[0]), opB, opA, opR,
669
                                mem_busy, mem_valid, mem_wreg, mem_result,
670
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
671
                                mem_ack, mem_stall, i_wb_data);
672
        assign  mem_rdbusy = ((mem_cyc)&&(~mem_we));
673
 
674
        // Either the prefetch or the instruction gets the memory bus, but 
675
        // never both.
676
        wbarbiter       #(32,32) pformem(i_clk, i_rst,
677
                // Prefetch access to the arbiter
678
                pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall,
679
                // Memory access to the arbiter
680
                mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall,
681
                // Common wires, in and out, of the arbiter
682
                o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack,
683
                        i_wb_stall);
684
 
685
        //
686
        //
687
        //      PIPELINE STAGE #5 :: Write-back results
688
        //
689
        //
690
        // This stage is not allowed to stall.  If results are ready to be
691
        // written back, they are written back at all cost.  Sleepy CPU's
692
        // won't prevent write back, nor debug modes, halting the CPU, nor
693
        // anything else.  Indeed, the (master_ce) bit is only as relevant
694
        // as knowinig something is available for writeback.
695
 
696
        //
697
        // Write back to our generic register set ...
698
        // When shall we write back?  On one of two conditions
699
        //      Note that the flags needed to be checked before issuing the
700
        //      bus instruction, so they don't need to be checked here.
701
        //      Further, alu_wr includes (set_cond), so we don't need to
702
        //      check for that here either.
703
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
704
        // Which register shall be written?
705
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
706 25 dgisselq
        // Are we writing to the CC register?
707
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
708 2 dgisselq
        // Are we writing to the PC?
709
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
710
        // What value to write?
711
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
712
        always @(posedge i_clk)
713
                if (wr_reg_ce)
714
                        regset[wr_reg_id] <= wr_reg_vl;
715 18 dgisselq
                else if ((i_halt)&&(i_dbg_we))
716
                        regset[i_dbg_reg] <= i_dbg_data[31:0];
717 2 dgisselq
 
718
        //
719
        // Write back to the condition codes/flags register ...
720
        // When shall we write to our flags register?  alF_wr already
721
        // includes the set condition ...
722
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
723 25 dgisselq
        assign  w_uflags = { trap, 1'b0, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
724
        assign  w_iflags = { trap, 1'b0, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
725 2 dgisselq
        // What value to write?
726
        always @(posedge i_clk)
727
                // If explicitly writing the register itself
728 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
729 2 dgisselq
                        flags <= wr_reg_vl[3:0];
730
                // Otherwise if we're setting the flags from an ALU operation
731
                else if ((wr_flags_ce)&&(alu_gie))
732
                        flags <= alu_flags;
733
                else if ((i_halt)&&(i_dbg_we)
734
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
735
                        flags <= i_dbg_data[3:0];
736
 
737
        always @(posedge i_clk)
738 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
739 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
740
                else if ((wr_flags_ce)&&(~alu_gie))
741
                        iflags <= alu_flags;
742
                else if ((i_halt)&&(i_dbg_we)
743
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
744
                        iflags <= i_dbg_data[3:0];
745
 
746
        // The 'break' enable  bit.  This bit can only be set from supervisor
747
        // mode.  It control what the CPU does upon encountering a break
748
        // instruction.
749
        //
750
        // The goal, upon encountering a break is that the CPU should stop and
751
        // not execute the break instruction, choosing instead to enter into
752
        // either interrupt mode or halt first.  
753
        //      if ((break_en) AND (break_instruction)) // user mode or not
754
        //              HALT CPU
755
        //      else if (break_instruction) // only in user mode
756
        //              set an interrupt flag, go to supervisor mode
757
        //              allow supervisor to step the CPU.
758
        //      Upon a CPU halt, any break condition will be reset.  The
759
        //      external debugger will then need to deal with whatever
760
        //      condition has taken place.
761
        initial break_en = 1'b0;
762
        always @(posedge i_clk)
763
                if ((i_rst)||(i_halt))
764
                        break_en <= 1'b0;
765 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
766 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
767 25 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy);
768 2 dgisselq
 
769
 
770
        // The sleep register.  Setting the sleep register causes the CPU to
771
        // sleep until the next interrupt.  Setting the sleep register within
772
        // interrupt mode causes the processor to halt until a reset.  This is
773 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
774
        // set the sleep bit and switch to supervisor mode in the same 
775
        // instruction: users are not allowed to halt the CPU.
776 2 dgisselq
        always @(posedge i_clk)
777
                if ((i_rst)||((i_interrupt)&&(gie)))
778
                        sleep <= 1'b0;
779 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
780
                        // In supervisor mode, we have no protections.  The
781
                        // supervisor can set the sleep bit however he wants.
782 2 dgisselq
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
783 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
784
                        // In user mode, however, you can only set the sleep
785
                        // mode while remaining in user mode.  You can't switch
786
                        // to sleep mode *and* supervisor mode at the same
787
                        // time, lest you halt the CPU.
788
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
789 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
790
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
791
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
792
 
793
        always @(posedge i_clk)
794
                if ((i_rst)||(w_switch_to_interrupt))
795
                        step <= 1'b0;
796 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
797 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
798
                else if ((i_halt)&&(i_dbg_we)
799
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
800
                        step <= i_dbg_data[`CPU_STEP_BIT];
801
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
802
                        step <= 1'b0;
803
 
804
        // The GIE register.  Only interrupts can disable the interrupt register
805
        assign  w_switch_to_interrupt = (gie)&&(
806
                        // On interrupt (obviously)
807
                        (i_interrupt)
808
                        // If we are stepping the CPU
809
                        ||((master_ce)&&(alu_pc_valid)&&(step))
810
                        // If we encounter a break instruction, if the break
811
                        //      enable isn't not set.
812 25 dgisselq
                        ||((master_ce)&&(op_break)&&(~break_en))
813 2 dgisselq
                        // If we write to the CC register
814
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
815 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
816 2 dgisselq
                        // Or if, in debug mode, we write to the CC register
817
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
818
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
819
                        );
820
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
821
                        // Then if we write the CC register
822
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
823 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
824 2 dgisselq
                        // Or if, in debug mode, we write the CC register
825
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
826
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
827
                        );
828
        always @(posedge i_clk)
829
                if (i_rst)
830
                        gie <= 1'b0;
831
                else if (w_switch_to_interrupt)
832
                        gie <= 1'b0;
833
                else if (w_release_from_interrupt)
834
                        gie <= 1'b1;
835
 
836 25 dgisselq
        initial trap = 1'b0;
837
        always @(posedge i_clk)
838
                if (i_rst)
839
                        trap <= 1'b0;
840
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
841
                                &&(wr_reg_id[4])&&(wr_write_cc))
842
                        trap <= 1'b1;
843
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
844
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
845
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
846
                else if (w_release_from_interrupt)
847
                        trap <= 1'b0;
848
 
849 2 dgisselq
        //
850
        // Write backs to the PC register, and general increments of it
851
        //      We support two: upc and ipc.  If the instruction is normal,
852
        // we increment upc, if interrupt level we increment ipc.  If
853
        // the instruction writes the PC, we write whichever PC is appropriate.
854
        //
855
        // Do we need to all our partial results from the pipeline?
856
        // What happens when the pipeline has gie and ~gie instructions within
857
        // it?  Do we clear both?  What if a gie instruction tries to clear
858
        // a non-gie instruction?
859
        always @(posedge i_clk)
860 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
861 2 dgisselq
                        upc <= wr_reg_vl;
862
                else if ((alu_gie)&&(alu_pc_valid))
863
                        upc <= alu_pc;
864
                else if ((i_halt)&&(i_dbg_we)
865
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
866
                        upc <= i_dbg_data;
867
 
868
        always @(posedge i_clk)
869
                if (i_rst)
870
                        ipc <= RESET_ADDRESS;
871
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
872
                        ipc <= wr_reg_vl;
873
                else if ((~alu_gie)&&(alu_pc_valid))
874
                        ipc <= alu_pc;
875
                else if ((i_halt)&&(i_dbg_we)
876
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
877
                        ipc <= i_dbg_data;
878
 
879
        always @(posedge i_clk)
880
                if (i_rst)
881
                        pf_pc <= RESET_ADDRESS;
882
                else if (w_switch_to_interrupt)
883
                        pf_pc <= ipc;
884
                else if (w_release_from_interrupt)
885
                        pf_pc <= upc;
886
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
887
                        pf_pc <= wr_reg_vl;
888
                else if ((i_halt)&&(i_dbg_we)
889
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
890
                        pf_pc <= i_dbg_data;
891
                else if (dcd_ce)
892
                        pf_pc <= pf_pc + 1;
893
 
894
        initial new_pc = 1'b1;
895
        always @(posedge i_clk)
896 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
897 2 dgisselq
                        new_pc <= 1'b1;
898
                else if (w_switch_to_interrupt)
899
                        new_pc <= 1'b1;
900
                else if (w_release_from_interrupt)
901
                        new_pc <= 1'b1;
902
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
903
                        new_pc <= 1'b1;
904
                else if ((i_halt)&&(i_dbg_we)
905
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
906
                        new_pc <= 1'b1;
907
                else
908
                        new_pc <= 1'b0;
909
 
910
        //
911
        // The debug interface
912
        always @(posedge i_clk)
913
                begin
914
                        o_dbg_reg <= regset[i_dbg_reg];
915
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
916
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
917
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
918 25 dgisselq
                                o_dbg_reg[9:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
919 2 dgisselq
                end
920
        always @(posedge i_clk)
921 25 dgisselq
                o_dbg_cc <= { gie, sleep };
922 18 dgisselq
 
923
        always @(posedge i_clk)
924 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
925
                        (pf_cyc)||(mem_cyc)||(mem_busy)
926 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
927 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
928 2 dgisselq
 
929
        //
930
        //
931
        // Produce accounting outputs: Account for any CPU stalls, so we can
932
        // later evaluate how well we are doing.
933
        //
934
        //
935 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
936
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
937
        assign  o_i_count  = alu_pc_valid;
938 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.