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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
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// Filename:    zipcpu.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//              The instruction set is about as RISC as you can get, there are
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//              only 16 instruction types supported (of which one isn't yet
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//              supported ...)  Please see the accompanying iset.html file
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//              for a description of these instructions.
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//
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//              All instructions are 32-bits wide.  All bus accesses, both
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//              address and data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory.  On the
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//              Basys board that I'm working on, one instruction may be
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//              issued every 20 clocks or so, unless and until I implement a
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//              cache or local memory.
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//
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//              2. Instruction Decode
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//
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//              3. Read Operands
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//
28
//              4. Apply Instruction
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//
30
//              4. Write-back Results
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//
32
//      A lot of difficult work has been placed into the pipeline stall
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//      handling.  My original proposal was not to allow pipeline stalls at all.
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//      The idea would be that the CPU would just run every clock and whatever
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//      stalled answer took place would just get fixed a clock or two later,
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//      meaning that the compiler could just schedule everything out.
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//      This idea died at the memory interface, which can take a variable
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//      amount of time to read or write any value, thus the whole CPU needed
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//      to stall on a stalled memory access.
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//
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//      My next idea was to just let things complete.  I.e., once an instrution
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//      starts, it continues to completion no matter what and we go on.  This
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//      failed at writing the PC.  If the PC gets written in something such as
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//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
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//      later, if whether or not something happens in those clocks depends
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//      upon the instruction fetch filling the pipeline, then the CPU has a
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//      non-deterministic behavior.
48
//
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//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
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//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
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//      read or a write, there is no undoing it--since peripherals on the
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//      bus may act upon the answer with whatever side effects they might
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//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
110
// fetches are more complicated and therefore use more FPGA resources, while
111
// single fetches will cause the CPU to stall for about 5 stalls each 
112
// instruction cycle, effectively reducing the instruction count per clock to
113
// about 0.2.  However, the area cost may be worth it.  Consider:
114
//
115
//      Slice LUTs              ZipSystem       ZipCPU
116
//      Single Fetching         2521            1734
117
//      Pipelined fetching      2796            2046
118
//
119 38 dgisselq
// `define      OPT_SINGLE_FETCH
120 36 dgisselq
//
121
//
122
//
123 25 dgisselq
`define CPU_CC_REG      4'he
124 2 dgisselq
`define CPU_PC_REG      4'hf
125 25 dgisselq
`define CPU_TRAP_BIT    9
126 2 dgisselq
`define CPU_BREAK_BIT   7
127
`define CPU_STEP_BIT    6
128
`define CPU_GIE_BIT     5
129
`define CPU_SLEEP_BIT   4
130 36 dgisselq
// Compile time defines
131 38 dgisselq
// (Currently unused)
132
// `define      OPT_SINGLE_FETCH
133
// (Best path--define these!)
134
`define OPT_CONDITIONAL_FLAGS
135 48 dgisselq
`define OPT_ILLEGAL_INSTRUCTION
136
`ifndef OPT_SINGLE_FETCH
137
        // The following are pipeline optimization options.
138
        // They make no sense in a single instruction fetch mode.
139 38 dgisselq
`define OPT_PRECLEAR_BUS
140
`define OPT_EARLY_BRANCHING
141
`define OPT_PIPELINED_BUS_ACCESS
142 48 dgisselq
`endif
143 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
144
                // Debug interface
145 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
146
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
147 2 dgisselq
                        o_break,
148
                // CPU interface to the wishbone bus
149 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
150
                        o_wb_lcl_cyc, o_wb_lcl_stb,
151
                        o_wb_we, o_wb_addr, o_wb_data,
152 2 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data,
153 36 dgisselq
                        i_wb_err,
154 2 dgisselq
                // Accounting/CPU usage interface
155 9 dgisselq
                o_op_stall, o_pf_stall, o_i_count);
156 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
157
                        LGICACHE=6, AW=ADDRESS_WIDTH;
158 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
159
        // Debug interface -- inputs
160 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
161 2 dgisselq
        input           [4:0]    i_dbg_reg;
162
        input                   i_dbg_we;
163
        input           [31:0]   i_dbg_data;
164
        // Debug interface -- outputs
165
        output  reg             o_dbg_stall;
166
        output  reg     [31:0]   o_dbg_reg;
167 25 dgisselq
        output  reg     [1:0]    o_dbg_cc;
168 2 dgisselq
        output  wire            o_break;
169
        // Wishbone interface -- outputs
170 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
171
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
172 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
173
        output  wire    [31:0]   o_wb_data;
174 2 dgisselq
        // Wishbone interface -- inputs
175
        input                   i_wb_ack, i_wb_stall;
176
        input           [31:0]   i_wb_data;
177 36 dgisselq
        input                   i_wb_err;
178 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
179 9 dgisselq
        output  wire            o_op_stall;
180 2 dgisselq
        output  wire            o_pf_stall;
181 9 dgisselq
        output  wire            o_i_count;
182 2 dgisselq
 
183 25 dgisselq
 
184 2 dgisselq
        // Registers
185
        reg     [31:0]   regset [0:31];
186 9 dgisselq
 
187
        // Condition codes
188 25 dgisselq
        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
189 36 dgisselq
        wire    [10:0]   w_uflags, w_iflags;
190 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
191 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
192 36 dgisselq
        reg             ill_err;
193 38 dgisselq
`else
194
        wire            ill_err;
195 36 dgisselq
`endif
196
        reg             bus_err_flag;
197 2 dgisselq
 
198 9 dgisselq
        // The master chip enable
199
        wire            master_ce;
200 2 dgisselq
 
201
        //
202
        //
203
        //      PIPELINE STAGE #1 :: Prefetch
204
        //              Variable declarations
205
        //
206 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
207 25 dgisselq
        reg             new_pc, op_break;
208 18 dgisselq
        wire    clear_pipeline;
209 36 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
210 9 dgisselq
 
211
        wire            dcd_stalled;
212 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
213 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
214
        wire    [31:0]           pf_data;
215
        wire    [31:0]           instruction;
216
        wire    [(AW-1):0]       instruction_pc;
217 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
218 2 dgisselq
 
219
        //
220
        //
221
        //      PIPELINE STAGE #2 :: Instruction Decode
222
        //              Variable declarations
223
        //
224
        //
225 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
226 2 dgisselq
        wire            op_stall, dcd_ce;
227
        reg     [3:0]    dcdOp;
228
        reg     [4:0]    dcdA, dcdB;
229 25 dgisselq
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
230 2 dgisselq
        reg     [3:0]    dcdF;
231
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
232
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
233 48 dgisselq
        reg     [(AW-1):0]       dcd_pc;
234 2 dgisselq
        reg     [23:0]   r_dcdI;
235 48 dgisselq
        reg             dcd_zI; // true if dcdI == 0
236 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
237
 
238 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
239 36 dgisselq
        reg     dcd_clear_bus;
240
`endif
241 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
242 36 dgisselq
        reg     dcd_illegal;
243
`endif
244 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
245 48 dgisselq
        reg                     dcd_early_branch_stb, dcd_early_branch;
246
        reg     [(AW-1):0]       dcd_branch_pc;
247 36 dgisselq
`else
248 48 dgisselq
        wire                    dcd_early_branch_stb, dcd_early_branch;
249
        wire    [(AW-1):0]       dcd_branch_pc;
250 36 dgisselq
`endif
251 2 dgisselq
 
252
 
253
        //
254
        //
255
        //      PIPELINE STAGE #3 :: Read Operands
256
        //              Variable declarations
257
        //
258
        //
259
        //
260
        // Now, let's read our operands
261
        reg     [4:0]    alu_reg;
262
        reg     [3:0]    opn;
263
        reg     [4:0]    opR;
264 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
265
        reg     [(AW-1):0]       op_pc;
266 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
267 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
268 25 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie,
269 2 dgisselq
                        opA_rd, opB_rd;
270 36 dgisselq
        wire    [10:0]   opFl;
271 3 dgisselq
        reg     [6:0]    r_opF;
272 2 dgisselq
        wire    [8:0]    opF;
273
        wire            op_ce;
274 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
275 36 dgisselq
        reg     op_clear_bus;
276
`endif
277 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
278 36 dgisselq
        reg     op_illegal;
279
`endif
280 2 dgisselq
 
281
 
282
        //
283
        //
284
        //      PIPELINE STAGE #4 :: ALU / Memory
285
        //              Variable declarations
286
        //
287
        //
288 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
289 2 dgisselq
        reg             alu_pc_valid;;
290
        wire            alu_ce, alu_stall;
291
        wire    [31:0]   alu_result;
292
        wire    [3:0]    alu_flags;
293
        wire            alu_valid;
294
        wire            set_cond;
295
        reg             alu_wr, alF_wr, alu_gie;
296 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
297 36 dgisselq
        reg             alu_illegal;
298 38 dgisselq
`else
299
        wire            alu_illegal;
300 36 dgisselq
`endif
301 2 dgisselq
 
302
 
303
 
304
        wire    mem_ce, mem_stalled;
305 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
306
        wire    mem_pipe_stalled;
307
`endif
308 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
309
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
310 48 dgisselq
        wire    [4:0]            mem_wreg;
311 9 dgisselq
 
312 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
313
        wire    [(AW-1):0]       mem_addr;
314
        wire    [31:0]           mem_data, mem_result;
315
        reg     [4:0]            mem_last_reg; // Last register result to go in
316 2 dgisselq
 
317
 
318
 
319
        //
320
        //
321
        //      PIPELINE STAGE #5 :: Write-back
322
        //              Variable declarations
323
        //
324 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
325 2 dgisselq
        wire    [4:0]    wr_reg_id;
326
        wire    [31:0]   wr_reg_vl;
327
        wire    w_switch_to_interrupt, w_release_from_interrupt;
328 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
329 2 dgisselq
 
330
 
331
 
332
        //
333
        //      MASTER: clock enable.
334
        //
335 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
336 2 dgisselq
 
337
 
338
        //
339
        //      PIPELINE STAGE #1 :: Prefetch
340
        //              Calculate stall conditions
341
 
342
        //
343
        //      PIPELINE STAGE #2 :: Instruction Decode
344
        //              Calculate stall conditions
345 34 dgisselq
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
346 2 dgisselq
        assign          dcd_stalled = (dcdvalid)&&(
347
                                        (op_stall)
348
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
349 36 dgisselq
                                        ||((opvalid_mem)&&(op_wr_pc))
350
                                        ||((opvalid_mem)&&(opR_cc)));
351 2 dgisselq
        //
352
        //      PIPELINE STAGE #3 :: Read Operands
353
        //              Calculate stall conditions
354 25 dgisselq
        assign  op_stall = ((mem_stalled)&&(opvalid_mem))
355
                                ||((alu_stall)&&(opvalid_alu));
356 2 dgisselq
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
357
 
358
        //
359
        //      PIPELINE STAGE #4 :: ALU / Memory
360
        //              Calculate stall conditions
361 36 dgisselq
        //
362
        // 1. Basic stall is if the previous stage is valid and the next is
363
        //      busy.  
364
        // 2. Also stall if the prior stage is valid and the master clock enable
365
        //      is de-selected
366
        // 3. Next case: Stall if we want to start a memory operation and the
367
        //      prior operation will write either the PC or CC registers.
368
        // 4. Last case: Stall if we would otherwise move a break instruction
369
        //      through the ALU.  Break instructions are not allowed through
370
        //      the ALU.
371
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
372
                        ||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
373
                                &&((wr_write_pc)||(wr_write_cc))) // Case 3
374
                        ||((opvalid)&&(op_break)); // Case 4
375 38 dgisselq
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
376 2 dgisselq
        //
377 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
378
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
379
                        &&(set_cond)&&(~mem_stalled);
380
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
381
                                (mem_pipe_stalled)
382
                                ||((~op_pipe)&&(mem_busy))
383
                                // Stall waiting for flags to be valid
384
                                // Or waiting for a write to the PC register
385
                                // Or CC register, since that can change the
386
                                //  PC as well
387
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
388
                                        &&((wr_write_pc)||(wr_write_cc)))));
389
`else
390 25 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
391 38 dgisselq
 
392 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
393 2 dgisselq
                                (~master_ce)
394
                                // Stall waiting for flags to be valid
395
                                // Or waiting for a write to the PC register
396 25 dgisselq
                                // Or CC register, since that can change the
397
                                //  PC as well
398
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
399 38 dgisselq
`endif
400 2 dgisselq
 
401
 
402
        //
403
        //
404
        //      PIPELINE STAGE #1 :: Prefetch
405
        //
406
        //
407 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
408 9 dgisselq
        wire            pf_ce;
409
 
410
        assign          pf_ce = (~dcd_stalled);
411 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
412
                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
413 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
414 36 dgisselq
                                        pf_valid, pf_illegal,
415
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
416
                                pf_ack, pf_stall, pf_err, i_wb_data);
417 2 dgisselq
`else // Pipe fetch
418 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
419 36 dgisselq
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
420
                                        i_clear_pf_cache, ~dcd_stalled,
421
                                        (new_pc)?pf_pc:dcd_branch_pc,
422 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
423
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
424 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
425 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
426 36 dgisselq
                                ((dcd_clear_bus)&&(dcdvalid))
427
                                ||((op_clear_bus)&&(opvalid))
428
                                ||
429
`endif
430
                                (mem_cyc_lcl)||(mem_cyc_gbl),
431
                                pf_illegal);
432 2 dgisselq
        assign  instruction_gie = gie;
433
`endif
434
 
435 36 dgisselq
        initial dcdvalid = 1'b0;
436 2 dgisselq
        always @(posedge i_clk)
437
                if (i_rst)
438
                        dcdvalid <= 1'b0;
439
                else if (dcd_ce)
440 36 dgisselq
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
441
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
442 2 dgisselq
                        dcdvalid <= 1'b0;
443
 
444 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
445 2 dgisselq
        always @(posedge i_clk)
446 38 dgisselq
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(~sleep))
447 36 dgisselq
                begin
448
                        dcd_early_branch <= 1'b0;
449
                        // First case, a move to PC instruction
450
                        if ((instruction[31:28] == 4'h2)
451
                                &&((instruction_gie)
452
                                        ||((~instruction[20])&&(~instruction[15])))
453
                                &&(instruction[23:21]==3'h0))
454
                        begin
455
                                dcd_early_branch_stb <= 1'b1;
456
                                dcd_early_branch <= 1'b1;
457
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
458
 
459
                        end else // Next case, an Add Imm -> PC instruction
460
                        if ((instruction[31:28] == 4'ha) // Add
461
                                &&(~instruction[20]) // Immediate
462
                                &&(instruction[23:21]==3'h0)) // Always
463
                        begin
464
                                dcd_early_branch_stb <= 1'b1;
465
                                dcd_early_branch <= 1'b1;
466
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
467
                        end else // Next case: load Immediate to PC
468
                        if (instruction[31:28] == 4'h3)
469
                        begin
470
                                dcd_early_branch_stb <= 1'b1;
471
                                dcd_early_branch <= 1'b1;
472
                                // r_dcdI <= { instruction[23:0] };
473
                        end
474
                end else
475
                begin
476
                        if (dcd_ce) dcd_early_branch <= 1'b0;
477
                        dcd_early_branch_stb <= 1'b0;
478
                end
479
        always @(posedge i_clk)
480 2 dgisselq
                if (dcd_ce)
481
                begin
482 36 dgisselq
                        if (instruction[31]) // Add
483 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-20){instruction[19]}}, instruction[19:0] } + {{(AW-1){1'b0}},1'b1};
484 36 dgisselq
                        else if (~instruction[28]) // 4'h2 = MOV
485 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
486 36 dgisselq
                        else // if (instruction[28]) // 4'h3 = LDI
487 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
488 36 dgisselq
                end
489 38 dgisselq
`else   //      OPT_EARLY_BRANCHING
490 36 dgisselq
        assign  dcd_early_branch_stb = 1'b0;
491
        assign  dcd_early_branch     = 1'b0;
492 48 dgisselq
        assign  dcd_branch_pc        = {(AW){1'b0}};
493 38 dgisselq
`endif  //      OPT_EARLY_BRANCHING
494 36 dgisselq
 
495
        always @(posedge i_clk)
496
                if (dcd_ce)
497
                begin
498 2 dgisselq
                        dcd_pc <= instruction_pc+1;
499
 
500
                        // Record what operation we are doing
501
                        dcdOp <= instruction[31:28];
502
 
503
                        // Default values
504
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
505
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
506 25 dgisselq
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
507
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
508
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
509
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
510 2 dgisselq
                        dcdM    <= 1'b0;
511 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
512 36 dgisselq
                        dcdF_wr <= (instruction[23:21]==3'h0);
513
`else
514 2 dgisselq
                        dcdF_wr <= 1'b1;
515 36 dgisselq
`endif
516 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
517 36 dgisselq
                        dcd_clear_bus <= 1'b0;
518
`endif
519 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
520 36 dgisselq
                        dcd_illegal <= pf_illegal;
521
`endif
522 2 dgisselq
 
523
                        // Set the condition under which we do this operation
524
                        // The top four bits are a mask, the bottom four the
525
                        // value the flags must equal once anded with the mask
526
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
527
                        casez(instruction[31:28])
528
                        4'h2: begin // Move instruction
529
                                if (~instruction_gie)
530
                                begin
531
                                        dcdA[4] <= instruction[20];
532
                                        dcdB[4] <= instruction[15];
533
                                end
534
                                dcdA_wr <= 1'b1;
535
                                dcdA_rd <= 1'b0;
536
                                dcdB_rd <= 1'b1;
537
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
538 48 dgisselq
                                dcd_zI <= (instruction[14:0] == 0);
539 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
540
                                end
541
                        4'h3: begin // Load immediate
542
                                dcdA_wr <= 1'b1;
543
                                dcdA_rd <= 1'b0;
544
                                dcdB_rd <= 1'b0;
545
                                r_dcdI <= { instruction[23:0] };
546 48 dgisselq
                                dcd_zI <= (instruction[23:0] == 0);
547 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
548
                                dcdF    <= 4'h8; // This is unconditional
549
                                dcdOp <= 4'h2;
550
                                end
551 25 dgisselq
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
552 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
553 25 dgisselq
                                // Don't write flags except for multiplies
554 36 dgisselq
                                //   and then only if they are unconditional
555
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
556
                                        &&(instruction[23:21]==3'h0));
557
`else
558
                                // Don't write flags except for multiplies
559 25 dgisselq
                                dcdF_wr <= (instruction[27:25] != 3'h7);
560 36 dgisselq
`endif
561 2 dgisselq
                                r_dcdI <= { 8'h00, instruction[15:0] };
562 48 dgisselq
                                dcd_zI <= (instruction[15:0] == 0);
563 2 dgisselq
                                if (instruction[27:24] == 4'he)
564
                                begin
565
                                        // NOOP instruction
566
                                        dcdA_wr <= 1'b0;
567
                                        dcdA_rd <= 1'b0;
568
                                        dcdB_rd <= 1'b0;
569
                                        dcdOp <= 4'h2;
570 36 dgisselq
                                        // Might also be a break.  Big
571
                                        // instruction set hole here.
572 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
573 36 dgisselq
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
574
`endif
575 2 dgisselq
                                end else if (instruction[27:24] == 4'hf)
576
                                begin // Load partial immediate(s)
577
                                        dcdA_wr <= 1'b1;
578
                                        dcdA_rd <= 1'b1;
579
                                        dcdB_rd <= 1'b0;
580
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
581 25 dgisselq
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
582
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
583 2 dgisselq
                                        dcdOp <= { 3'h3, instruction[20] };
584
                                end else begin
585 25 dgisselq
                                        // Actual multiply instruction
586
                                        r_dcdI <= { 8'h00, instruction[15:0] };
587 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
588 25 dgisselq
                                        dcdA_rd <= 1'b1;
589
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
590
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
591 2 dgisselq
                                end end
592
                        4'b011?: begin // Load/Store
593
                                dcdF_wr <= 1'b0; // Don't write flags
594
                                dcdA_wr <= (~instruction[28]); // Write on loads
595
                                dcdA_rd <= (instruction[28]); // Read on stores
596
                                dcdB_rd <= instruction[20];
597
                                if (instruction[20])
598 48 dgisselq
                                begin
599 2 dgisselq
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
600 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
601
                                end else begin
602 2 dgisselq
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
603 48 dgisselq
                                        dcd_zI <= (instruction[19:0] == 0);
604
                                end
605 2 dgisselq
                                dcdM <= 1'b1; // Memory operation
606 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
607 36 dgisselq
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
608
`endif
609 2 dgisselq
                                end
610
                        default: begin
611
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
612
                                dcdA_rd <= 1'b1;
613
                                dcdB_rd <= instruction[20];
614
                                if (instruction[20])
615 48 dgisselq
                                begin
616 2 dgisselq
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
617 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
618
                                end else begin
619 2 dgisselq
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
620 48 dgisselq
                                        dcd_zI <= (instruction[19:0] == 0);
621
                                end end
622 2 dgisselq
                        endcase
623
 
624
 
625
                        dcd_gie <= instruction_gie;
626
                end
627 25 dgisselq
        always @(posedge i_clk)
628
                if (dcd_ce)
629
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
630 38 dgisselq
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
631 25 dgisselq
                        dcd_break <= 1'b0;
632 2 dgisselq
 
633 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
634
        reg     [23:0]   r_opI;
635
        reg     [4:0]    op_B;
636
        reg             op_pipe;
637 2 dgisselq
 
638 38 dgisselq
        initial op_pipe = 1'b0;
639
        // To be a pipeable operation, there must be 
640
        //      two valid adjacent instructions
641
        //      Both must be memory instructions
642
        //      Both must be writes, or both must be reads
643
        //      Both operations must be to the same identical address,
644
        //              or at least a single (one) increment above that address
645
        always @(posedge i_clk)
646
                if (op_ce)
647
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
648
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
649
                                &&(dcdB == op_B) // Same address register
650
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
651
        always @(posedge i_clk)
652
                if (op_ce) // &&(dcdvalid))
653
                        r_opI <= r_dcdI;
654
        always @(posedge i_clk)
655
                if (op_ce) // &&(dcdvalid))
656
                        op_B <= dcdB;
657
`endif
658
 
659 2 dgisselq
        //
660
        //
661
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
662
        //
663
        //
664 25 dgisselq
        assign  w_opA = regset[dcdA];
665
        assign  w_opB = regset[dcdB];
666 2 dgisselq
        always @(posedge i_clk)
667
                if (op_ce) // &&(dcdvalid))
668
                begin
669
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
670
                                r_opA <= wr_reg_vl;
671 25 dgisselq
                        else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
672 48 dgisselq
                                r_opA <= { {(32-AW){1'b0}}, dcd_pc };
673 25 dgisselq
                        else if (dcdA_pc)
674 48 dgisselq
                                r_opA <= { {(32-AW){1'b0}}, upc };
675 25 dgisselq
                        else if (dcdA_cc)
676 36 dgisselq
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
677 2 dgisselq
                        else
678 25 dgisselq
                                r_opA <= w_opA;
679 48 dgisselq
                end else if (opvalid)
680
                begin // We were going to pick these up when they became valid,
681
                        // but for some reason we're stuck here as they became
682
                        // valid.  Pick them up now anyway
683
                        if ((opA_alu)||((opA_mem)&&(mem_valid)))
684
                                r_opA <= wr_reg_vl;
685 2 dgisselq
                end
686 36 dgisselq
        wire    [31:0]   dcdI, w_opBnI;
687 2 dgisselq
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
688 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
689
                        : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
690 48 dgisselq
                        : (((dcdB_pc)&&(dcdB[4] == dcd_gie)) ? {{(32-AW){1'b0}},dcd_pc }
691
                        : ((dcdB_pc) ? {{(32-AW){1'b0}},upc}
692 36 dgisselq
                        : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
693
                        : regset[dcdB]))));
694 2 dgisselq
        always @(posedge i_clk)
695
                if (op_ce) // &&(dcdvalid))
696 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
697 48 dgisselq
                else if ((opvalid)&&((opB_alu)||((opB_mem)&&(mem_valid))))
698
                        r_opB <= wr_reg_vl;
699 2 dgisselq
 
700
        // The logic here has become more complex than it should be, no thanks
701
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
702
        // be two sets of four bits: the top bits specify what bits matter, the
703
        // bottom specify what those top bits must equal.  However, two of
704
        // conditions check whether bits are on, and those are the only two
705
        // conditions checking those bits.  Therefore, Vivado complains that
706
        // these two bits are redundant.  Hence the convoluted expression
707
        // below, arriving at what we finally want in the (now wire net)
708
        // opF.
709
        always @(posedge i_clk)
710
                if (op_ce)
711 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
712 2 dgisselq
                        case(dcdF[2:0])
713
                        3'h0:   r_opF <= 7'h80; // Always
714
                        3'h1:   r_opF <= 7'h11; // Z
715
                        3'h2:   r_opF <= 7'h10; // NE
716
                        3'h3:   r_opF <= 7'h20; // GE (!N)
717
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
718
                        3'h5:   r_opF <= 7'h24; // LT
719
                        3'h6:   r_opF <= 7'h02; // C
720
                        3'h7:   r_opF <= 7'h08; // V
721
                        endcase
722 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
723 2 dgisselq
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
724
 
725 36 dgisselq
        initial opvalid     = 1'b0;
726
        initial opvalid_alu = 1'b0;
727
        initial opvalid_mem = 1'b0;
728 2 dgisselq
        always @(posedge i_clk)
729
                if (i_rst)
730 25 dgisselq
                begin
731
                        opvalid     <= 1'b0;
732
                        opvalid_alu <= 1'b0;
733
                        opvalid_mem <= 1'b0;
734
                end else if (op_ce)
735
                begin
736 2 dgisselq
                        // Do we have a valid instruction?
737
                        //   The decoder may vote to stall one of its
738
                        //   instructions based upon something we currently
739
                        //   have in our queue.  This instruction must then
740
                        //   move forward, and get a stall cycle inserted.
741
                        //   Hence, the test on dcd_stalled here.  If we must
742
                        //   wait until our operands are valid, then we aren't
743
                        //   valid yet until then.
744 18 dgisselq
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
745 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
746 36 dgisselq
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
747
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
748
`else
749 25 dgisselq
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
750
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
751 36 dgisselq
`endif
752 25 dgisselq
                end else if ((~op_stall)||(clear_pipeline))
753
                begin
754
                        opvalid     <= 1'b0;
755
                        opvalid_alu <= 1'b0;
756
                        opvalid_mem <= 1'b0;
757
                end
758 2 dgisselq
 
759
        // Here's part of our debug interface.  When we recognize a break
760
        // instruction, we set the op_break flag.  That'll prevent this
761
        // instruction from entering the ALU, and cause an interrupt before
762
        // this instruction.  Thus, returning to this code will cause the
763
        // break to repeat and continue upon return.  To get out of this
764
        // condition, replace the break instruction with what it is supposed
765
        // to be, step through it, and then replace it back.  In this fashion,
766
        // a debugger can step through code.
767 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
768
        initial op_break = 1'b0;
769 2 dgisselq
        always @(posedge i_clk)
770 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
771
                else if (op_ce) op_break <= (dcd_break);
772
                else if ((clear_pipeline)||(~opvalid))
773
                                op_break <= 1'b0;
774 2 dgisselq
 
775 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
776 2 dgisselq
        always @(posedge i_clk)
777 36 dgisselq
                if(op_ce)
778
                        op_illegal <= dcd_illegal;
779
`endif
780
 
781
        always @(posedge i_clk)
782 2 dgisselq
                if (op_ce)
783
                begin
784
                        opn    <= dcdOp;        // Which ALU operation?
785 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
786 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
787 36 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
788
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
789
`else
790 2 dgisselq
                        // Will we write the flags/CC Register with our result?
791 25 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
792 2 dgisselq
                        // Will we be writing our results into a register?
793
                        opR_wr <= dcdA_wr;
794 36 dgisselq
`endif
795 2 dgisselq
                        // What register will these results be written into?
796
                        opR    <= dcdA;
797 38 dgisselq
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
798 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
799
                        op_gie <= dcd_gie;
800
 
801
                        // We're not done with these yet--we still need them
802
                        // for the unclocked assign.  We need the unclocked
803
                        // assign so that there's no wait state between an
804
                        // ALU or memory result and the next register that may
805
                        // use that value.
806
                        opA_rd <= dcdA_rd;
807
                        opB_rd <= dcdB_rd;
808
                        //
809 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
810 36 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
811
`else
812 30 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
813 36 dgisselq
`endif
814 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
815
                        // op_pc  <= dcd_pc;
816 36 dgisselq
 
817 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
818 36 dgisselq
                        op_clear_bus <= dcd_clear_bus;
819
`endif
820 2 dgisselq
                end
821
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
822
 
823
        // This is tricky.  First, the PC and Flags registers aren't kept in
824
        // register set but in special registers of their own.  So step one
825
        // is to select the right register.  Step to is to replace that
826
        // register with the results of an ALU or memory operation, if such
827
        // results are now available.  Otherwise, we'd need to insert a wait
828
        // state of some type.
829
        //
830
        // The alternative approach would be to define some sort of
831
        // op_stall wire, which would stall any upstream stage.
832
        // We'll create a flag here to start our coordination.  Once we
833
        // define this flag to something other than just plain zero, then
834
        // the stalls will already be in place.
835 48 dgisselq
        reg     opA_alu, opA_mem;
836 25 dgisselq
        always @(posedge i_clk)
837
                if (op_ce)
838 48 dgisselq
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
839
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
840
                        opA_alu <= 1'b0;
841
        always @(posedge i_clk)
842
                if (op_ce)
843
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd))
844
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
845
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
846
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
847
                        opA_mem <= 1'b0;
848 25 dgisselq
 
849 48 dgisselq
        always @(posedge i_clk)
850
                if (mem_ce)
851
                        mem_last_reg <= opR;
852
        assign  opA = (opA_alu) ? alu_result
853
                        : ( ((opA_mem)&&(mem_valid))?mem_result
854
                        : r_opA );
855
 
856 25 dgisselq
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
857
                // Skip the requirement on writing back opA
858
                // Stall on memory, since we'll always need to stall for a 
859
                // memory access anyway
860 48 dgisselq
                                // ((opvalid_mem)&&(opR_wr)&&(opR == dcdA))
861
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
862
                // Place stalls for this latter case into the ops stage
863
                //              ||((mem_busy)&&(~mem_we));
864 36 dgisselq
 
865 48 dgisselq
        reg     opB_alu, opB_mem;
866 25 dgisselq
        always @(posedge i_clk)
867
                if (op_ce)
868 48 dgisselq
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
869
        always @(posedge i_clk)
870
                if (op_ce)
871
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
872
                                ((opvalid_mem)&&(opR == dcdB))
873
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
874
                                        &&(mem_last_reg == dcdB)));
875
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
876
                        opB_mem <= 1'b0;
877
        assign  opB = (opB_alu) ? alu_result
878
                        : ( ((opB_mem)&&(mem_valid))?mem_result
879
                        : r_opB );
880 25 dgisselq
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
881 38 dgisselq
                                // Stall on memory ops writing to my register
882
                                //      (i.e. loads), or on any write to my
883
                                //      register if I have an immediate offset
884
                                // Note the exception for writing to the PC:
885
                                //      if I write to the PC, the whole next
886
                                //      instruction is invalid, not just the
887
                                //      operand.  That'll get wiped in the
888
                                //      next operation anyway, so don't stall
889
                                //      here.
890 25 dgisselq
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
891 38 dgisselq
                                        &&(opR != { op_gie, `CPU_PC_REG} )
892 48 dgisselq
                                        &&(~dcd_zI))
893 38 dgisselq
                                // Stall on any write to the flags register,
894
                                // if we're going to need the flags value for
895
                                // opB.
896 30 dgisselq
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
897 38 dgisselq
                                // Stall on any ongoing memory operation that
898
                                // will write to opB
899 48 dgisselq
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
900 30 dgisselq
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
901
                                        &&(opvalid)&&(opR_cc);
902 2 dgisselq
        //
903
        //
904
        //      PIPELINE STAGE #4 :: Apply Instruction
905
        //
906
        //
907
        cpuops  doalu(i_clk, i_rst, alu_ce,
908 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
909 2 dgisselq
                        alu_result, alu_flags, alu_valid);
910
 
911
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
912
        initial alF_wr   = 1'b0;
913
        initial alu_wr   = 1'b0;
914
        always @(posedge i_clk)
915
                if (i_rst)
916
                begin
917
                        alu_wr   <= 1'b0;
918
                        alF_wr   <= 1'b0;
919
                end else if (alu_ce)
920
                begin
921
                        alu_reg <= opR;
922
                        alu_wr  <= (opR_wr)&&(set_cond);
923
                        alF_wr  <= (opF_wr)&&(set_cond);
924
                end else begin
925
                        // These are strobe signals, so clear them if not
926
                        // set for any particular clock
927
                        alu_wr <= 1'b0;
928
                        alF_wr <= 1'b0;
929
                end
930
        always @(posedge i_clk)
931
                if ((alu_ce)||(mem_ce))
932
                        alu_gie  <= op_gie;
933
        always @(posedge i_clk)
934
                if ((alu_ce)||(mem_ce))
935
                        alu_pc  <= op_pc;
936 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
937
        always @(posedge i_clk)
938
                if ((alu_ce)||(mem_ce))
939
                        alu_illegal <= op_illegal;
940
`endif
941
 
942 2 dgisselq
        initial alu_pc_valid = 1'b0;
943
        always @(posedge i_clk)
944 38 dgisselq
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
945 25 dgisselq
                                        &&((opvalid_alu)||(~mem_stalled));
946 2 dgisselq
 
947 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
948 48 dgisselq
        pipemem #(AW) domem(i_clk, i_rst, mem_ce,
949 38 dgisselq
                                (opn[0]), opB, opA, opR,
950
                                mem_busy, mem_pipe_stalled,
951
                                mem_valid, bus_err, mem_wreg, mem_result,
952
                        mem_cyc_gbl, mem_cyc_lcl,
953
                                mem_stb_gbl, mem_stb_lcl,
954
                                mem_we, mem_addr, mem_data,
955
                                mem_ack, mem_stall, mem_err, i_wb_data);
956
 
957
`else // PIPELINED_BUS_ACCESS
958 48 dgisselq
        memops  #(AW) domem(i_clk, i_rst, mem_ce,
959 2 dgisselq
                                (opn[0]), opB, opA, opR,
960 38 dgisselq
                                mem_busy,
961
                                mem_valid, bus_err, mem_wreg, mem_result,
962 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
963
                                mem_stb_gbl, mem_stb_lcl,
964
                                mem_we, mem_addr, mem_data,
965
                                mem_ack, mem_stall, mem_err, i_wb_data);
966 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
967 36 dgisselq
        assign  mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
968 2 dgisselq
 
969
        // Either the prefetch or the instruction gets the memory bus, but 
970
        // never both.
971 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
972 36 dgisselq
                // Memory access to the arbiter, priority position
973
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
974
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
975 2 dgisselq
                // Prefetch access to the arbiter
976 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
977
                        pf_ack, pf_stall, pf_err,
978 2 dgisselq
                // Common wires, in and out, of the arbiter
979 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
980
                        o_wb_we, o_wb_addr, o_wb_data,
981
                        i_wb_ack, i_wb_stall, i_wb_err);
982 2 dgisselq
 
983
        //
984
        //
985
        //      PIPELINE STAGE #5 :: Write-back results
986
        //
987
        //
988
        // This stage is not allowed to stall.  If results are ready to be
989
        // written back, they are written back at all cost.  Sleepy CPU's
990
        // won't prevent write back, nor debug modes, halting the CPU, nor
991
        // anything else.  Indeed, the (master_ce) bit is only as relevant
992
        // as knowinig something is available for writeback.
993
 
994
        //
995
        // Write back to our generic register set ...
996
        // When shall we write back?  On one of two conditions
997
        //      Note that the flags needed to be checked before issuing the
998
        //      bus instruction, so they don't need to be checked here.
999
        //      Further, alu_wr includes (set_cond), so we don't need to
1000
        //      check for that here either.
1001 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1002 36 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
1003
`else
1004
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
1005
`endif
1006 2 dgisselq
        // Which register shall be written?
1007 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1008
        //              One or PC, one for CC, and one for GIE match
1009 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1010 25 dgisselq
        // Are we writing to the CC register?
1011
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1012 2 dgisselq
        // Are we writing to the PC?
1013
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1014
        // What value to write?
1015
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
1016
        always @(posedge i_clk)
1017
                if (wr_reg_ce)
1018
                        regset[wr_reg_id] <= wr_reg_vl;
1019 18 dgisselq
                else if ((i_halt)&&(i_dbg_we))
1020
                        regset[i_dbg_reg] <= i_dbg_data[31:0];
1021 2 dgisselq
 
1022
        //
1023
        // Write back to the condition codes/flags register ...
1024
        // When shall we write to our flags register?  alF_wr already
1025
        // includes the set condition ...
1026 36 dgisselq
        assign  wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
1027 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1028 36 dgisselq
        assign  w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1029
        assign  w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1030
`else
1031
        assign  w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1032
        assign  w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1033
`endif
1034 2 dgisselq
        // What value to write?
1035
        always @(posedge i_clk)
1036
                // If explicitly writing the register itself
1037 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1038 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1039
                // Otherwise if we're setting the flags from an ALU operation
1040
                else if ((wr_flags_ce)&&(alu_gie))
1041
                        flags <= alu_flags;
1042
                else if ((i_halt)&&(i_dbg_we)
1043
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1044
                        flags <= i_dbg_data[3:0];
1045
 
1046
        always @(posedge i_clk)
1047 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1048 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1049
                else if ((wr_flags_ce)&&(~alu_gie))
1050
                        iflags <= alu_flags;
1051
                else if ((i_halt)&&(i_dbg_we)
1052
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
1053
                        iflags <= i_dbg_data[3:0];
1054
 
1055
        // The 'break' enable  bit.  This bit can only be set from supervisor
1056
        // mode.  It control what the CPU does upon encountering a break
1057
        // instruction.
1058
        //
1059
        // The goal, upon encountering a break is that the CPU should stop and
1060
        // not execute the break instruction, choosing instead to enter into
1061
        // either interrupt mode or halt first.  
1062
        //      if ((break_en) AND (break_instruction)) // user mode or not
1063
        //              HALT CPU
1064
        //      else if (break_instruction) // only in user mode
1065
        //              set an interrupt flag, go to supervisor mode
1066
        //              allow supervisor to step the CPU.
1067
        //      Upon a CPU halt, any break condition will be reset.  The
1068
        //      external debugger will then need to deal with whatever
1069
        //      condition has taken place.
1070
        initial break_en = 1'b0;
1071
        always @(posedge i_clk)
1072
                if ((i_rst)||(i_halt))
1073
                        break_en <= 1'b0;
1074 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1075 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1076 34 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1077
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
1078
                        break_en <= i_dbg_data[`CPU_BREAK_BIT];
1079 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1080 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1081
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1082
                                &&(~clear_pipeline)
1083
                        ||((~alu_gie)&&(bus_err))
1084
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
1085
`else
1086
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1087
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1088
                                &&(~clear_pipeline))
1089 38 dgisselq
                        ||((~alu_gie)&&(bus_err));
1090 36 dgisselq
`endif
1091 2 dgisselq
 
1092
 
1093
        // The sleep register.  Setting the sleep register causes the CPU to
1094
        // sleep until the next interrupt.  Setting the sleep register within
1095
        // interrupt mode causes the processor to halt until a reset.  This is
1096 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1097
        // set the sleep bit and switch to supervisor mode in the same 
1098
        // instruction: users are not allowed to halt the CPU.
1099 2 dgisselq
        always @(posedge i_clk)
1100
                if ((i_rst)||((i_interrupt)&&(gie)))
1101
                        sleep <= 1'b0;
1102 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1103
                        // In supervisor mode, we have no protections.  The
1104
                        // supervisor can set the sleep bit however he wants.
1105 2 dgisselq
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1106 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1107
                        // In user mode, however, you can only set the sleep
1108
                        // mode while remaining in user mode.  You can't switch
1109
                        // to sleep mode *and* supervisor mode at the same
1110
                        // time, lest you halt the CPU.
1111
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1112 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1113
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1114
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
1115
 
1116
        always @(posedge i_clk)
1117
                if ((i_rst)||(w_switch_to_interrupt))
1118
                        step <= 1'b0;
1119 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1120 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1121
                else if ((i_halt)&&(i_dbg_we)
1122
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1123
                        step <= i_dbg_data[`CPU_STEP_BIT];
1124 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1125 2 dgisselq
                        step <= 1'b0;
1126
 
1127
        // The GIE register.  Only interrupts can disable the interrupt register
1128
        assign  w_switch_to_interrupt = (gie)&&(
1129
                        // On interrupt (obviously)
1130
                        (i_interrupt)
1131
                        // If we are stepping the CPU
1132 38 dgisselq
                        ||((alu_pc_valid)&&(step))
1133 2 dgisselq
                        // If we encounter a break instruction, if the break
1134 36 dgisselq
                        //      enable isn't set.
1135 38 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
1136
`ifdef  OPT_ILLEGAL_INSTRUCTION
1137 36 dgisselq
                        // On an illegal instruction
1138
                        ||((alu_valid)&&(alu_illegal))
1139
`endif
1140 2 dgisselq
                        // If we write to the CC register
1141
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1142 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1143 2 dgisselq
                        // Or if, in debug mode, we write to the CC register
1144
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
1145
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
1146
                        );
1147
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1148
                        // Then if we write the CC register
1149
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1150 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1151 2 dgisselq
                        // Or if, in debug mode, we write the CC register
1152
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
1153
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
1154
                        );
1155
        always @(posedge i_clk)
1156
                if (i_rst)
1157
                        gie <= 1'b0;
1158
                else if (w_switch_to_interrupt)
1159
                        gie <= 1'b0;
1160
                else if (w_release_from_interrupt)
1161
                        gie <= 1'b1;
1162
 
1163 25 dgisselq
        initial trap = 1'b0;
1164
        always @(posedge i_clk)
1165
                if (i_rst)
1166
                        trap <= 1'b0;
1167
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1168
                                &&(wr_reg_id[4])&&(wr_write_cc))
1169
                        trap <= 1'b1;
1170
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
1171
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
1172
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
1173
                else if (w_release_from_interrupt)
1174
                        trap <= 1'b0;
1175
 
1176 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1177 36 dgisselq
        initial ill_err = 1'b0;
1178
        always @(posedge i_clk)
1179
                if (i_rst)
1180
                        ill_err <= 1'b0;
1181
                else if (w_release_from_interrupt)
1182
                        ill_err <= 1'b0;
1183
                else if ((alu_valid)&&(alu_illegal)&&(gie))
1184
                        ill_err <= 1'b1;
1185 38 dgisselq
`else
1186
        assign ill_err = 1'b0;
1187 36 dgisselq
`endif
1188
        initial bus_err_flag = 1'b0;
1189
        always @(posedge i_clk)
1190
                if (i_rst)
1191
                        bus_err_flag <= 1'b0;
1192
                else if (w_release_from_interrupt)
1193
                        bus_err_flag <= 1'b0;
1194
                else if ((bus_err)&&(alu_gie))
1195
                        bus_err_flag <= 1'b1;
1196
 
1197 2 dgisselq
        //
1198
        // Write backs to the PC register, and general increments of it
1199
        //      We support two: upc and ipc.  If the instruction is normal,
1200
        // we increment upc, if interrupt level we increment ipc.  If
1201
        // the instruction writes the PC, we write whichever PC is appropriate.
1202
        //
1203
        // Do we need to all our partial results from the pipeline?
1204
        // What happens when the pipeline has gie and ~gie instructions within
1205
        // it?  Do we clear both?  What if a gie instruction tries to clear
1206
        // a non-gie instruction?
1207
        always @(posedge i_clk)
1208 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1209 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1210 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1211 2 dgisselq
                        upc <= alu_pc;
1212
                else if ((i_halt)&&(i_dbg_we)
1213
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
1214 48 dgisselq
                        upc <= i_dbg_data[(AW-1):0];
1215 2 dgisselq
 
1216
        always @(posedge i_clk)
1217
                if (i_rst)
1218
                        ipc <= RESET_ADDRESS;
1219
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1220 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1221 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1222 2 dgisselq
                        ipc <= alu_pc;
1223
                else if ((i_halt)&&(i_dbg_we)
1224
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
1225 48 dgisselq
                        ipc <= i_dbg_data[(AW-1):0];
1226 2 dgisselq
 
1227
        always @(posedge i_clk)
1228
                if (i_rst)
1229
                        pf_pc <= RESET_ADDRESS;
1230
                else if (w_switch_to_interrupt)
1231
                        pf_pc <= ipc;
1232
                else if (w_release_from_interrupt)
1233
                        pf_pc <= upc;
1234
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1235 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1236 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1237 34 dgisselq
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
1238 48 dgisselq
                        pf_pc <= i_dbg_data[(AW-1):0];
1239 2 dgisselq
                else if (dcd_ce)
1240
                        pf_pc <= pf_pc + 1;
1241
 
1242
        initial new_pc = 1'b1;
1243
        always @(posedge i_clk)
1244 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1245 2 dgisselq
                        new_pc <= 1'b1;
1246
                else if (w_switch_to_interrupt)
1247
                        new_pc <= 1'b1;
1248
                else if (w_release_from_interrupt)
1249
                        new_pc <= 1'b1;
1250
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1251
                        new_pc <= 1'b1;
1252
                else if ((i_halt)&&(i_dbg_we)
1253 34 dgisselq
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
1254 2 dgisselq
                        new_pc <= 1'b1;
1255
                else
1256
                        new_pc <= 1'b0;
1257
 
1258
        //
1259
        // The debug interface
1260
        always @(posedge i_clk)
1261
                begin
1262
                        o_dbg_reg <= regset[i_dbg_reg];
1263
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1264 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1265 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1266 36 dgisselq
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1267 2 dgisselq
                end
1268
        always @(posedge i_clk)
1269 25 dgisselq
                o_dbg_cc <= { gie, sleep };
1270 18 dgisselq
 
1271
        always @(posedge i_clk)
1272 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1273 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1274 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1275 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1276 2 dgisselq
 
1277
        //
1278
        //
1279
        // Produce accounting outputs: Account for any CPU stalls, so we can
1280
        // later evaluate how well we are doing.
1281
        //
1282
        //
1283 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
1284
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1285 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1286 2 dgisselq
endmodule

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