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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Blame information for rev 56

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///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9 56 dgisselq
//      (actual implementation aside ...)  The instruction set is about as
10
//      RISC as you can get, there are only 16 instruction types supported.
11
//      Please see the accompanying spec.pdf file for a description of these
12
//      instructions.
13 2 dgisselq
//
14 56 dgisselq
//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
16 2 dgisselq
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19 56 dgisselq
//              1. Prefetch, returns the instruction from memory. 
20 2 dgisselq
//
21
//              2. Instruction Decode
22
//
23
//              3. Read Operands
24
//
25
//              4. Apply Instruction
26
//
27
//              4. Write-back Results
28
//
29 56 dgisselq
//      Further information about the inner workings of this CPU may be
30
//      found in the spec.pdf file.  (The documentation within this file
31
//      had become out of date and out of sync with the spec.pdf, so look
32
//      to the spec.pdf for accurate and up to date information.)
33 2 dgisselq
//
34
//
35
// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
// Copyright (C) 2015, Gisselquist Technology, LLC
41
//
42
// This program is free software (firmware): you can redistribute it and/or
43
// modify it under the terms of  the GNU General Public License as published
44
// by the Free Software Foundation, either version 3 of the License, or (at
45
// your option) any later version.
46
//
47
// This program is distributed in the hope that it will be useful, but WITHOUT
48
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
49
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
50
// for more details.
51
//
52
// License:     GPL, v3, as defined and found on www.gnu.org,
53
//              http://www.gnu.org/licenses/gpl.html
54
//
55
//
56
///////////////////////////////////////////////////////////////////////////////
57
//
58 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
59
// fetches are more complicated and therefore use more FPGA resources, while
60
// single fetches will cause the CPU to stall for about 5 stalls each 
61
// instruction cycle, effectively reducing the instruction count per clock to
62
// about 0.2.  However, the area cost may be worth it.  Consider:
63
//
64
//      Slice LUTs              ZipSystem       ZipCPU
65
//      Single Fetching         2521            1734
66
//      Pipelined fetching      2796            2046
67
//
68 38 dgisselq
// `define      OPT_SINGLE_FETCH
69 36 dgisselq
//
70
//
71
//
72 25 dgisselq
`define CPU_CC_REG      4'he
73 2 dgisselq
`define CPU_PC_REG      4'hf
74 25 dgisselq
`define CPU_TRAP_BIT    9
75 2 dgisselq
`define CPU_BREAK_BIT   7
76
`define CPU_STEP_BIT    6
77
`define CPU_GIE_BIT     5
78
`define CPU_SLEEP_BIT   4
79 36 dgisselq
// Compile time defines
80 56 dgisselq
//
81
`include "cpudefs.v"
82
//
83 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
84
                // Debug interface
85 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
86
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
87 2 dgisselq
                        o_break,
88
                // CPU interface to the wishbone bus
89 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
90
                        o_wb_lcl_cyc, o_wb_lcl_stb,
91
                        o_wb_we, o_wb_addr, o_wb_data,
92 2 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data,
93 36 dgisselq
                        i_wb_err,
94 2 dgisselq
                // Accounting/CPU usage interface
95 56 dgisselq
                o_op_stall, o_pf_stall, o_i_count,
96
                //
97
                o_debug);
98 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
99
                        LGICACHE=6, AW=ADDRESS_WIDTH;
100 56 dgisselq
`ifdef  OPT_MULTIPLY
101
        parameter       IMPLEMENT_MPY = 1;
102
`else
103
        parameter       IMPLEMENT_MPY = 0;
104
`endif
105 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
106
        // Debug interface -- inputs
107 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
108 2 dgisselq
        input           [4:0]    i_dbg_reg;
109
        input                   i_dbg_we;
110
        input           [31:0]   i_dbg_data;
111
        // Debug interface -- outputs
112
        output  reg             o_dbg_stall;
113
        output  reg     [31:0]   o_dbg_reg;
114 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
115 2 dgisselq
        output  wire            o_break;
116
        // Wishbone interface -- outputs
117 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
118
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
119 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
120
        output  wire    [31:0]   o_wb_data;
121 2 dgisselq
        // Wishbone interface -- inputs
122
        input                   i_wb_ack, i_wb_stall;
123
        input           [31:0]   i_wb_data;
124 36 dgisselq
        input                   i_wb_err;
125 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
126 9 dgisselq
        output  wire            o_op_stall;
127 2 dgisselq
        output  wire            o_pf_stall;
128 9 dgisselq
        output  wire            o_i_count;
129 56 dgisselq
        //
130
        output  reg     [31:0]   o_debug;
131 2 dgisselq
 
132 25 dgisselq
 
133 2 dgisselq
        // Registers
134 56 dgisselq
        //
135
        //      The distributed RAM style comment is necessary on the
136
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
137
        // set and in the process ruining everything else.  It basically
138
        // optimizes logic away, to where it no longer works.  The logic
139
        // as described herein will work, this just makes sure XST implements
140
        // that logic.
141
        //
142
        (* ram_style = "distributed" *)
143 2 dgisselq
        reg     [31:0]   regset [0:31];
144 9 dgisselq
 
145
        // Condition codes
146 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
147
        reg     [3:0]    flags, iflags;
148 36 dgisselq
        wire    [10:0]   w_uflags, w_iflags;
149 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
150 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
151 36 dgisselq
        reg             ill_err;
152 38 dgisselq
`else
153
        wire            ill_err;
154 36 dgisselq
`endif
155
        reg             bus_err_flag;
156 2 dgisselq
 
157 9 dgisselq
        // The master chip enable
158
        wire            master_ce;
159 2 dgisselq
 
160
        //
161
        //
162
        //      PIPELINE STAGE #1 :: Prefetch
163
        //              Variable declarations
164
        //
165 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
166 25 dgisselq
        reg             new_pc, op_break;
167 18 dgisselq
        wire    clear_pipeline;
168 36 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
169 9 dgisselq
 
170
        wire            dcd_stalled;
171 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
172 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
173
        wire    [31:0]           pf_data;
174
        wire    [31:0]           instruction;
175
        wire    [(AW-1):0]       instruction_pc;
176 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
177 2 dgisselq
 
178
        //
179
        //
180
        //      PIPELINE STAGE #2 :: Instruction Decode
181
        //              Variable declarations
182
        //
183
        //
184 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
185 2 dgisselq
        wire            op_stall, dcd_ce;
186
        reg     [3:0]    dcdOp;
187
        reg     [4:0]    dcdA, dcdB;
188 25 dgisselq
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
189 2 dgisselq
        reg     [3:0]    dcdF;
190
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
191
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
192 48 dgisselq
        reg     [(AW-1):0]       dcd_pc;
193 2 dgisselq
        reg     [23:0]   r_dcdI;
194 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
195 48 dgisselq
        reg             dcd_zI; // true if dcdI == 0
196 56 dgisselq
`endif
197 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
198
 
199 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
200 36 dgisselq
        reg     dcd_clear_bus;
201
`endif
202 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
203 36 dgisselq
        reg     dcd_illegal;
204
`endif
205 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
206 48 dgisselq
        reg                     dcd_early_branch_stb, dcd_early_branch;
207
        reg     [(AW-1):0]       dcd_branch_pc;
208 36 dgisselq
`else
209 48 dgisselq
        wire                    dcd_early_branch_stb, dcd_early_branch;
210
        wire    [(AW-1):0]       dcd_branch_pc;
211 36 dgisselq
`endif
212 2 dgisselq
 
213
 
214
        //
215
        //
216
        //      PIPELINE STAGE #3 :: Read Operands
217
        //              Variable declarations
218
        //
219
        //
220
        //
221
        // Now, let's read our operands
222
        reg     [4:0]    alu_reg;
223
        reg     [3:0]    opn;
224
        reg     [4:0]    opR;
225 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
226
        reg     [(AW-1):0]       op_pc;
227 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
228 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
229 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
230 36 dgisselq
        wire    [10:0]   opFl;
231 56 dgisselq
        reg     [5:0]    r_opF;
232
        wire    [7:0]    opF;
233
        reg     [2:0]    opF_cp;
234 2 dgisselq
        wire            op_ce;
235 56 dgisselq
        // Some pipeline control wires
236
`ifdef  OPT_SINGLE_CYCLE
237
        reg     opA_alu, opA_mem;
238
        reg     opB_alu, opB_mem;
239
`endif
240 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
241 36 dgisselq
        reg     op_clear_bus;
242
`endif
243 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
244 36 dgisselq
        reg     op_illegal;
245
`endif
246 2 dgisselq
 
247
 
248
        //
249
        //
250
        //      PIPELINE STAGE #4 :: ALU / Memory
251
        //              Variable declarations
252
        //
253
        //
254 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
255 2 dgisselq
        reg             alu_pc_valid;;
256
        wire            alu_ce, alu_stall;
257
        wire    [31:0]   alu_result;
258
        wire    [3:0]    alu_flags;
259
        wire            alu_valid;
260
        wire            set_cond;
261
        reg             alu_wr, alF_wr, alu_gie;
262 56 dgisselq
        wire            alu_illegal_op;
263 38 dgisselq
        wire            alu_illegal;
264 2 dgisselq
 
265
 
266
 
267
        wire    mem_ce, mem_stalled;
268 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
269
        wire    mem_pipe_stalled;
270
`endif
271 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
272
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
273 48 dgisselq
        wire    [4:0]            mem_wreg;
274 9 dgisselq
 
275 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
276
        wire    [(AW-1):0]       mem_addr;
277
        wire    [31:0]           mem_data, mem_result;
278
        reg     [4:0]            mem_last_reg; // Last register result to go in
279 2 dgisselq
 
280
 
281
 
282
        //
283
        //
284
        //      PIPELINE STAGE #5 :: Write-back
285
        //              Variable declarations
286
        //
287 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
288 2 dgisselq
        wire    [4:0]    wr_reg_id;
289
        wire    [31:0]   wr_reg_vl;
290
        wire    w_switch_to_interrupt, w_release_from_interrupt;
291 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
292 2 dgisselq
 
293
 
294
 
295
        //
296
        //      MASTER: clock enable.
297
        //
298 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
299 2 dgisselq
 
300
 
301
        //
302
        //      PIPELINE STAGE #1 :: Prefetch
303
        //              Calculate stall conditions
304
 
305
        //
306
        //      PIPELINE STAGE #2 :: Instruction Decode
307
        //              Calculate stall conditions
308 34 dgisselq
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
309 2 dgisselq
        assign          dcd_stalled = (dcdvalid)&&(
310
                                        (op_stall)
311
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
312 36 dgisselq
                                        ||((opvalid_mem)&&(op_wr_pc))
313
                                        ||((opvalid_mem)&&(opR_cc)));
314 2 dgisselq
        //
315
        //      PIPELINE STAGE #3 :: Read Operands
316
        //              Calculate stall conditions
317 56 dgisselq
        assign  op_stall = ((opvalid)&&(~master_ce))||(
318
                        // Stall if going into the ALU and the ALU is stalled
319
                        //      i.e. if the memory is busy, or we are single
320
                        //      stepping
321
                        ((opvalid_alu)&&(alu_stall))
322
                        //
323
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
324
                        // Stall if we are going into memory with an operation
325
                        //      that cannot be pipelined, and the memory is
326
                        //      already busy
327
                        ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
328
                        //
329
                        // Stall if we are going into memory with a pipeable
330
                        //      operation, but the memory unit declares it is
331
                        //      not going to accept any more pipeline operations
332
                        ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
333 2 dgisselq
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
334
 
335
        //
336
        //      PIPELINE STAGE #4 :: ALU / Memory
337
        //              Calculate stall conditions
338 36 dgisselq
        //
339
        // 1. Basic stall is if the previous stage is valid and the next is
340
        //      busy.  
341
        // 2. Also stall if the prior stage is valid and the master clock enable
342
        //      is de-selected
343 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
344
        //      since we don't know if it'll put us to sleep or not.
345 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
346
        //      through the ALU.  Break instructions are not allowed through
347
        //      the ALU.
348
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
349 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
350
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
351
                                &&(wr_write_cc)) // Case 3
352
                        ||((opvalid_alu)&&(op_break)); // Case 3
353 38 dgisselq
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
354 2 dgisselq
        //
355 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
356
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
357
                        &&(set_cond)&&(~mem_stalled);
358
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
359
                                (mem_pipe_stalled)
360
                                ||((~op_pipe)&&(mem_busy))
361
                                // Stall waiting for flags to be valid
362
                                // Or waiting for a write to the PC register
363
                                // Or CC register, since that can change the
364
                                //  PC as well
365
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
366
                                        &&((wr_write_pc)||(wr_write_cc)))));
367
`else
368 25 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
369 38 dgisselq
 
370 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
371 2 dgisselq
                                (~master_ce)
372
                                // Stall waiting for flags to be valid
373
                                // Or waiting for a write to the PC register
374 25 dgisselq
                                // Or CC register, since that can change the
375
                                //  PC as well
376
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
377 38 dgisselq
`endif
378 2 dgisselq
 
379
 
380
        //
381
        //
382
        //      PIPELINE STAGE #1 :: Prefetch
383
        //
384
        //
385 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
386 9 dgisselq
        wire            pf_ce;
387
 
388
        assign          pf_ce = (~dcd_stalled);
389 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
390
                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
391 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
392 36 dgisselq
                                        pf_valid, pf_illegal,
393
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
394
                                pf_ack, pf_stall, pf_err, i_wb_data);
395 2 dgisselq
`else // Pipe fetch
396 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
397 36 dgisselq
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
398
                                        i_clear_pf_cache, ~dcd_stalled,
399
                                        (new_pc)?pf_pc:dcd_branch_pc,
400 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
401
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
402 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
403 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
404 36 dgisselq
                                ((dcd_clear_bus)&&(dcdvalid))
405
                                ||((op_clear_bus)&&(opvalid))
406
                                ||
407
`endif
408
                                (mem_cyc_lcl)||(mem_cyc_gbl),
409
                                pf_illegal);
410 2 dgisselq
        assign  instruction_gie = gie;
411
`endif
412
 
413 36 dgisselq
        initial dcdvalid = 1'b0;
414 2 dgisselq
        always @(posedge i_clk)
415
                if (i_rst)
416
                        dcdvalid <= 1'b0;
417
                else if (dcd_ce)
418 36 dgisselq
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
419
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
420 2 dgisselq
                        dcdvalid <= 1'b0;
421
 
422 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
423 2 dgisselq
        always @(posedge i_clk)
424 56 dgisselq
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
425 36 dgisselq
                begin
426
                        dcd_early_branch <= 1'b0;
427
                        // First case, a move to PC instruction
428
                        if ((instruction[31:28] == 4'h2)
429
                                &&((instruction_gie)
430
                                        ||((~instruction[20])&&(~instruction[15])))
431
                                &&(instruction[23:21]==3'h0))
432
                        begin
433
                                dcd_early_branch_stb <= 1'b1;
434
                                dcd_early_branch <= 1'b1;
435
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
436
 
437
                        end else // Next case, an Add Imm -> PC instruction
438
                        if ((instruction[31:28] == 4'ha) // Add
439
                                &&(~instruction[20]) // Immediate
440
                                &&(instruction[23:21]==3'h0)) // Always
441
                        begin
442
                                dcd_early_branch_stb <= 1'b1;
443
                                dcd_early_branch <= 1'b1;
444
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
445
                        end else // Next case: load Immediate to PC
446
                        if (instruction[31:28] == 4'h3)
447
                        begin
448
                                dcd_early_branch_stb <= 1'b1;
449
                                dcd_early_branch <= 1'b1;
450
                                // r_dcdI <= { instruction[23:0] };
451
                        end
452
                end else
453
                begin
454
                        if (dcd_ce) dcd_early_branch <= 1'b0;
455
                        dcd_early_branch_stb <= 1'b0;
456
                end
457 56 dgisselq
        generate
458
        if (AW == 24)
459
        begin
460
                always @(posedge i_clk)
461 2 dgisselq
                if (dcd_ce)
462
                begin
463 36 dgisselq
                        if (instruction[31]) // Add
464 56 dgisselq
                        begin
465
                                dcd_branch_pc <= instruction_pc
466
                                                + { {(AW-20){instruction[19]}}, instruction[19:0] }
467
                                                + {{(AW-1){1'b0}},1'b1};
468
                        end else if (~instruction[28]) // 4'h2 = MOV
469 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
470 36 dgisselq
                        else // if (instruction[28]) // 4'h3 = LDI
471 56 dgisselq
                                dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
472
                end
473
        end else begin
474
                always @(posedge i_clk)
475
                if (dcd_ce)
476
                begin
477
                        if (instruction[31]) // Add
478
                        begin
479
                                dcd_branch_pc <= instruction_pc
480
                                                        + { {(AW-20){instruction[19]}}, instruction[19:0] }
481
                                                        + {{(AW-1){1'b0}},1'b1};
482
                        end else if (~instruction[28]) // 4'h2 = MOV
483
                        begin
484
                                        dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
485
                        end else // if (instruction[28]) // 4'h3 = LDI
486
                        begin
487 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
488 56 dgisselq
                        end
489 36 dgisselq
                end
490 56 dgisselq
        end endgenerate
491 38 dgisselq
`else   //      OPT_EARLY_BRANCHING
492 36 dgisselq
        assign  dcd_early_branch_stb = 1'b0;
493
        assign  dcd_early_branch     = 1'b0;
494 48 dgisselq
        assign  dcd_branch_pc        = {(AW){1'b0}};
495 38 dgisselq
`endif  //      OPT_EARLY_BRANCHING
496 36 dgisselq
 
497
        always @(posedge i_clk)
498
                if (dcd_ce)
499
                begin
500 56 dgisselq
                        dcd_pc <= instruction_pc
501
                                +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
502 2 dgisselq
 
503
                        // Record what operation we are doing
504
                        dcdOp <= instruction[31:28];
505
 
506
                        // Default values
507
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
508
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
509 25 dgisselq
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
510
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
511
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
512
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
513 2 dgisselq
                        dcdM    <= 1'b0;
514 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
515 36 dgisselq
                        dcdF_wr <= (instruction[23:21]==3'h0);
516
`else
517 2 dgisselq
                        dcdF_wr <= 1'b1;
518 36 dgisselq
`endif
519 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
520 36 dgisselq
                        dcd_clear_bus <= 1'b0;
521
`endif
522 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
523 36 dgisselq
                        dcd_illegal <= pf_illegal;
524
`endif
525 2 dgisselq
 
526
                        // Set the condition under which we do this operation
527
                        // The top four bits are a mask, the bottom four the
528
                        // value the flags must equal once anded with the mask
529
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
530
                        casez(instruction[31:28])
531
                        4'h2: begin // Move instruction
532
                                if (~instruction_gie)
533
                                begin
534
                                        dcdA[4] <= instruction[20];
535
                                        dcdB[4] <= instruction[15];
536
                                end
537
                                dcdA_wr <= 1'b1;
538
                                dcdA_rd <= 1'b0;
539
                                dcdB_rd <= 1'b1;
540
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
541 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
542 48 dgisselq
                                dcd_zI <= (instruction[14:0] == 0);
543 56 dgisselq
`endif
544 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
545
                                end
546
                        4'h3: begin // Load immediate
547
                                dcdA_wr <= 1'b1;
548
                                dcdA_rd <= 1'b0;
549
                                dcdB_rd <= 1'b0;
550
                                r_dcdI <= { instruction[23:0] };
551 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
552 48 dgisselq
                                dcd_zI <= (instruction[23:0] == 0);
553 56 dgisselq
`endif
554 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
555
                                dcdF    <= 4'h8; // This is unconditional
556
                                dcdOp <= 4'h2;
557
                                end
558 25 dgisselq
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
559 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
560 25 dgisselq
                                // Don't write flags except for multiplies
561 36 dgisselq
                                //   and then only if they are unconditional
562
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
563
                                        &&(instruction[23:21]==3'h0));
564
`else
565
                                // Don't write flags except for multiplies
566 25 dgisselq
                                dcdF_wr <= (instruction[27:25] != 3'h7);
567 36 dgisselq
`endif
568 2 dgisselq
                                r_dcdI <= { 8'h00, instruction[15:0] };
569 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
570 48 dgisselq
                                dcd_zI <= (instruction[15:0] == 0);
571 56 dgisselq
`endif
572 2 dgisselq
                                if (instruction[27:24] == 4'he)
573
                                begin
574
                                        // NOOP instruction
575
                                        dcdA_wr <= 1'b0;
576
                                        dcdA_rd <= 1'b0;
577
                                        dcdB_rd <= 1'b0;
578
                                        dcdOp <= 4'h2;
579 36 dgisselq
                                        // Might also be a break.  Big
580
                                        // instruction set hole here.
581 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
582 36 dgisselq
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
583
`endif
584 2 dgisselq
                                end else if (instruction[27:24] == 4'hf)
585
                                begin // Load partial immediate(s)
586
                                        dcdA_wr <= 1'b1;
587
                                        dcdA_rd <= 1'b1;
588
                                        dcdB_rd <= 1'b0;
589
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
590 25 dgisselq
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
591
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
592 2 dgisselq
                                        dcdOp <= { 3'h3, instruction[20] };
593
                                end else begin
594 25 dgisselq
                                        // Actual multiply instruction
595
                                        r_dcdI <= { 8'h00, instruction[15:0] };
596 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
597 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
598 56 dgisselq
`endif
599 25 dgisselq
                                        dcdA_rd <= 1'b1;
600
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
601
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
602 2 dgisselq
                                end end
603 56 dgisselq
                        4'b011?: begin // LOD/STO or Load/Store
604 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
605
                                dcdA_wr <= (~instruction[28]); // Write on loads
606
                                dcdA_rd <= (instruction[28]); // Read on stores
607
                                dcdB_rd <= instruction[20];
608
                                if (instruction[20])
609 48 dgisselq
                                begin
610 2 dgisselq
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
611 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
612 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
613 56 dgisselq
`endif
614 48 dgisselq
                                end else begin
615 2 dgisselq
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
616 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
617 48 dgisselq
                                        dcd_zI <= (instruction[19:0] == 0);
618 56 dgisselq
`endif
619 48 dgisselq
                                end
620 2 dgisselq
                                dcdM <= 1'b1; // Memory operation
621 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
622 36 dgisselq
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
623
`endif
624 2 dgisselq
                                end
625
                        default: begin
626
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
627
                                dcdA_rd <= 1'b1;
628
                                dcdB_rd <= instruction[20];
629
                                if (instruction[20])
630 48 dgisselq
                                begin
631 2 dgisselq
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
632 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
633 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
634 56 dgisselq
`endif
635 48 dgisselq
                                end else begin
636 2 dgisselq
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
637 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
638 48 dgisselq
                                        dcd_zI <= (instruction[19:0] == 0);
639 56 dgisselq
`endif
640 48 dgisselq
                                end end
641 2 dgisselq
                        endcase
642
 
643
 
644
                        dcd_gie <= instruction_gie;
645
                end
646 25 dgisselq
        always @(posedge i_clk)
647
                if (dcd_ce)
648
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
649 38 dgisselq
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
650 25 dgisselq
                        dcd_break <= 1'b0;
651 2 dgisselq
 
652 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
653
        reg     [23:0]   r_opI;
654
        reg     [4:0]    op_B;
655
        reg             op_pipe;
656 2 dgisselq
 
657 38 dgisselq
        initial op_pipe = 1'b0;
658
        // To be a pipeable operation, there must be 
659
        //      two valid adjacent instructions
660
        //      Both must be memory instructions
661
        //      Both must be writes, or both must be reads
662
        //      Both operations must be to the same identical address,
663
        //              or at least a single (one) increment above that address
664
        always @(posedge i_clk)
665
                if (op_ce)
666
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
667
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
668
                                &&(dcdB == op_B) // Same address register
669 56 dgisselq
                                &&(dcdF[2:0] == opF_cp) // Same condition
670 38 dgisselq
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
671
        always @(posedge i_clk)
672
                if (op_ce) // &&(dcdvalid))
673
                        r_opI <= r_dcdI;
674
        always @(posedge i_clk)
675
                if (op_ce) // &&(dcdvalid))
676
                        op_B <= dcdB;
677
`endif
678
 
679 2 dgisselq
        //
680
        //
681
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
682
        //
683
        //
684 25 dgisselq
        assign  w_opA = regset[dcdA];
685
        assign  w_opB = regset[dcdB];
686 56 dgisselq
 
687
        wire    [31:0]   w_pcA_v;
688
        generate
689
        if (AW < 32)
690
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
691
        else
692
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
693
        endgenerate
694 2 dgisselq
        always @(posedge i_clk)
695
                if (op_ce) // &&(dcdvalid))
696
                begin
697
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
698
                                r_opA <= wr_reg_vl;
699 25 dgisselq
                        else if (dcdA_pc)
700 56 dgisselq
                                r_opA <= w_pcA_v;
701 25 dgisselq
                        else if (dcdA_cc)
702 36 dgisselq
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
703 2 dgisselq
                        else
704 25 dgisselq
                                r_opA <= w_opA;
705 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
706 48 dgisselq
                end else if (opvalid)
707
                begin // We were going to pick these up when they became valid,
708
                        // but for some reason we're stuck here as they became
709
                        // valid.  Pick them up now anyway
710 56 dgisselq
                        if (((opA_alu)&&(alu_valid)&&(alu_wr))||((opA_mem)&&(mem_valid)))
711 48 dgisselq
                                r_opA <= wr_reg_vl;
712 56 dgisselq
`endif
713 2 dgisselq
                end
714 56 dgisselq
 
715
        wire    [31:0]   dcdI, w_opBnI, w_pcB_v;
716 2 dgisselq
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
717 56 dgisselq
        generate
718
        if (AW < 32)
719
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
720
        else
721
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
722
        endgenerate
723
 
724 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
725 56 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
726
                : ((dcdB_pc) ? w_pcB_v
727
                : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
728
                : w_opB)));
729
 
730 2 dgisselq
        always @(posedge i_clk)
731
                if (op_ce) // &&(dcdvalid))
732 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
733 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
734
                else if ((opvalid)&&(
735
                                ((opB_alu)&&(alu_valid)&&(alu_wr))
736
                                ||((opB_mem)&&(mem_valid))))
737 48 dgisselq
                        r_opB <= wr_reg_vl;
738 56 dgisselq
`endif
739 2 dgisselq
 
740
        // The logic here has become more complex than it should be, no thanks
741
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
742
        // be two sets of four bits: the top bits specify what bits matter, the
743
        // bottom specify what those top bits must equal.  However, two of
744
        // conditions check whether bits are on, and those are the only two
745
        // conditions checking those bits.  Therefore, Vivado complains that
746
        // these two bits are redundant.  Hence the convoluted expression
747
        // below, arriving at what we finally want in the (now wire net)
748
        // opF.
749
        always @(posedge i_clk)
750
                if (op_ce)
751 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
752 2 dgisselq
                        case(dcdF[2:0])
753 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
754
                        3'h1:   r_opF <= 6'h11; // Z
755
                        3'h2:   r_opF <= 6'h10; // NE
756
                        3'h3:   r_opF <= 6'h20; // GE (!N)
757
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
758
                        3'h5:   r_opF <= 6'h24; // LT
759
                        3'h6:   r_opF <= 6'h02; // C
760
                        3'h7:   r_opF <= 6'h08; // V
761 2 dgisselq
                        endcase
762 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
763 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
764
        always @(posedge i_clk)
765
                if (op_ce)
766
                        opF_cp[2:0] <= dcdF[2:0];
767 2 dgisselq
 
768 36 dgisselq
        initial opvalid     = 1'b0;
769
        initial opvalid_alu = 1'b0;
770
        initial opvalid_mem = 1'b0;
771 2 dgisselq
        always @(posedge i_clk)
772
                if (i_rst)
773 25 dgisselq
                begin
774
                        opvalid     <= 1'b0;
775
                        opvalid_alu <= 1'b0;
776
                        opvalid_mem <= 1'b0;
777
                end else if (op_ce)
778
                begin
779 2 dgisselq
                        // Do we have a valid instruction?
780
                        //   The decoder may vote to stall one of its
781
                        //   instructions based upon something we currently
782
                        //   have in our queue.  This instruction must then
783
                        //   move forward, and get a stall cycle inserted.
784
                        //   Hence, the test on dcd_stalled here.  If we must
785
                        //   wait until our operands are valid, then we aren't
786
                        //   valid yet until then.
787 18 dgisselq
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
788 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
789 36 dgisselq
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
790
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
791
`else
792 25 dgisselq
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
793
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
794 36 dgisselq
`endif
795 25 dgisselq
                end else if ((~op_stall)||(clear_pipeline))
796
                begin
797
                        opvalid     <= 1'b0;
798
                        opvalid_alu <= 1'b0;
799
                        opvalid_mem <= 1'b0;
800
                end
801 2 dgisselq
 
802
        // Here's part of our debug interface.  When we recognize a break
803
        // instruction, we set the op_break flag.  That'll prevent this
804
        // instruction from entering the ALU, and cause an interrupt before
805
        // this instruction.  Thus, returning to this code will cause the
806
        // break to repeat and continue upon return.  To get out of this
807
        // condition, replace the break instruction with what it is supposed
808
        // to be, step through it, and then replace it back.  In this fashion,
809
        // a debugger can step through code.
810 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
811
        initial op_break = 1'b0;
812 2 dgisselq
        always @(posedge i_clk)
813 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
814
                else if (op_ce) op_break <= (dcd_break);
815
                else if ((clear_pipeline)||(~opvalid))
816
                                op_break <= 1'b0;
817 2 dgisselq
 
818 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
819 2 dgisselq
        always @(posedge i_clk)
820 36 dgisselq
                if(op_ce)
821
                        op_illegal <= dcd_illegal;
822
`endif
823
 
824
        always @(posedge i_clk)
825 2 dgisselq
                if (op_ce)
826
                begin
827
                        opn    <= dcdOp;        // Which ALU operation?
828 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
829 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
830 36 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
831
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
832
`else
833 2 dgisselq
                        // Will we write the flags/CC Register with our result?
834 25 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
835 2 dgisselq
                        // Will we be writing our results into a register?
836
                        opR_wr <= dcdA_wr;
837 36 dgisselq
`endif
838 2 dgisselq
                        // What register will these results be written into?
839
                        opR    <= dcdA;
840 38 dgisselq
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
841 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
842
                        op_gie <= dcd_gie;
843
 
844
                        //
845 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
846 36 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
847
`else
848 30 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
849 36 dgisselq
`endif
850 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
851
                        // op_pc  <= dcd_pc;
852 36 dgisselq
 
853 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
854 36 dgisselq
                        op_clear_bus <= dcd_clear_bus;
855
`endif
856 2 dgisselq
                end
857
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
858
 
859
        // This is tricky.  First, the PC and Flags registers aren't kept in
860
        // register set but in special registers of their own.  So step one
861
        // is to select the right register.  Step to is to replace that
862
        // register with the results of an ALU or memory operation, if such
863
        // results are now available.  Otherwise, we'd need to insert a wait
864
        // state of some type.
865
        //
866
        // The alternative approach would be to define some sort of
867
        // op_stall wire, which would stall any upstream stage.
868
        // We'll create a flag here to start our coordination.  Once we
869
        // define this flag to something other than just plain zero, then
870
        // the stalls will already be in place.
871 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
872
        initial opA_alu = 1'b0;
873 25 dgisselq
        always @(posedge i_clk)
874
                if (op_ce)
875 48 dgisselq
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
876
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
877
                        opA_alu <= 1'b0;
878 56 dgisselq
        initial opA_mem = 1'b0;
879 48 dgisselq
        always @(posedge i_clk)
880
                if (op_ce)
881 56 dgisselq
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd)&&(~opn[0]))
882 48 dgisselq
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
883
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
884
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
885
                        opA_mem <= 1'b0;
886 56 dgisselq
`endif
887 25 dgisselq
 
888 48 dgisselq
        always @(posedge i_clk)
889
                if (mem_ce)
890
                        mem_last_reg <= opR;
891 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
892
        assign  opA = ((opA_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
893 48 dgisselq
                        : ( ((opA_mem)&&(mem_valid))?mem_result
894
                        : r_opA );
895 56 dgisselq
`else
896
        assign  opA = r_opA;
897
`endif
898 48 dgisselq
 
899 25 dgisselq
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
900 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
901 25 dgisselq
                // Skip the requirement on writing back opA
902
                // Stall on memory, since we'll always need to stall for a 
903
                // memory access anyway
904 48 dgisselq
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
905 56 dgisselq
`else
906
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))
907
                                ||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
908
                                ||((mem_rdbusy)&&(mem_last_reg == dcdA))
909
                                );
910
`endif
911 36 dgisselq
 
912 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
913 25 dgisselq
        always @(posedge i_clk)
914
                if (op_ce)
915 48 dgisselq
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
916
        always @(posedge i_clk)
917
                if (op_ce)
918
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
919 56 dgisselq
                                ((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
920 48 dgisselq
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
921
                                        &&(mem_last_reg == dcdB)));
922
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
923
                        opB_mem <= 1'b0;
924 56 dgisselq
        assign  opB = ((opB_alu)&&(alu_valid)&&(alu_wr)) ? alu_result
925 48 dgisselq
                        : ( ((opB_mem)&&(mem_valid))?mem_result
926
                        : r_opB );
927 56 dgisselq
`else
928
        assign  opB = r_opB;
929
`endif
930
 
931 25 dgisselq
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
932 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
933 38 dgisselq
                                // Stall on memory ops writing to my register
934
                                //      (i.e. loads), or on any write to my
935
                                //      register if I have an immediate offset
936
                                // Note the exception for writing to the PC:
937
                                //      if I write to the PC, the whole next
938
                                //      instruction is invalid, not just the
939
                                //      operand.  That'll get wiped in the
940
                                //      next operation anyway, so don't stall
941
                                //      here.
942 25 dgisselq
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
943 38 dgisselq
                                        &&(opR != { op_gie, `CPU_PC_REG} )
944 48 dgisselq
                                        &&(~dcd_zI))
945 38 dgisselq
                                // Stall on any write to the flags register,
946
                                // if we're going to need the flags value for
947
                                // opB.
948 30 dgisselq
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
949 38 dgisselq
                                // Stall on any ongoing memory operation that
950
                                // will write to opB
951 48 dgisselq
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
952 56 dgisselq
`else
953
                                ((opvalid)&&(opR_wr)&&(opR == dcdB))
954
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
955
                                ||((mem_rdbusy)&&(mem_last_reg == dcdB))
956
                                );
957
`endif
958 30 dgisselq
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
959
                                        &&(opvalid)&&(opR_cc);
960 2 dgisselq
        //
961
        //
962
        //      PIPELINE STAGE #4 :: Apply Instruction
963
        //
964
        //
965 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
966 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
967 56 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
968 2 dgisselq
 
969
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
970
        initial alF_wr   = 1'b0;
971
        initial alu_wr   = 1'b0;
972
        always @(posedge i_clk)
973
                if (i_rst)
974
                begin
975
                        alu_wr   <= 1'b0;
976
                        alF_wr   <= 1'b0;
977
                end else if (alu_ce)
978
                begin
979
                        alu_reg <= opR;
980
                        alu_wr  <= (opR_wr)&&(set_cond);
981
                        alF_wr  <= (opF_wr)&&(set_cond);
982
                end else begin
983
                        // These are strobe signals, so clear them if not
984
                        // set for any particular clock
985
                        alu_wr <= 1'b0;
986
                        alF_wr <= 1'b0;
987
                end
988
        always @(posedge i_clk)
989
                if ((alu_ce)||(mem_ce))
990
                        alu_gie  <= op_gie;
991
        always @(posedge i_clk)
992
                if ((alu_ce)||(mem_ce))
993
                        alu_pc  <= op_pc;
994 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
995 56 dgisselq
        reg     r_alu_illegal;
996
        initial r_alu_illegal = 0;
997 38 dgisselq
        always @(posedge i_clk)
998
                if ((alu_ce)||(mem_ce))
999 56 dgisselq
                        r_alu_illegal <= op_illegal;
1000
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1001 38 dgisselq
`endif
1002
 
1003 2 dgisselq
        initial alu_pc_valid = 1'b0;
1004
        always @(posedge i_clk)
1005 38 dgisselq
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
1006 25 dgisselq
                                        &&((opvalid_alu)||(~mem_stalled));
1007 2 dgisselq
 
1008 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1009 48 dgisselq
        pipemem #(AW) domem(i_clk, i_rst, mem_ce,
1010 38 dgisselq
                                (opn[0]), opB, opA, opR,
1011
                                mem_busy, mem_pipe_stalled,
1012
                                mem_valid, bus_err, mem_wreg, mem_result,
1013
                        mem_cyc_gbl, mem_cyc_lcl,
1014
                                mem_stb_gbl, mem_stb_lcl,
1015
                                mem_we, mem_addr, mem_data,
1016
                                mem_ack, mem_stall, mem_err, i_wb_data);
1017
 
1018
`else // PIPELINED_BUS_ACCESS
1019 48 dgisselq
        memops  #(AW) domem(i_clk, i_rst, mem_ce,
1020 2 dgisselq
                                (opn[0]), opB, opA, opR,
1021 38 dgisselq
                                mem_busy,
1022
                                mem_valid, bus_err, mem_wreg, mem_result,
1023 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1024
                                mem_stb_gbl, mem_stb_lcl,
1025
                                mem_we, mem_addr, mem_data,
1026
                                mem_ack, mem_stall, mem_err, i_wb_data);
1027 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1028 36 dgisselq
        assign  mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
1029 2 dgisselq
 
1030
        // Either the prefetch or the instruction gets the memory bus, but 
1031
        // never both.
1032 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1033 36 dgisselq
                // Memory access to the arbiter, priority position
1034
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1035
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1036 2 dgisselq
                // Prefetch access to the arbiter
1037 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1038
                        pf_ack, pf_stall, pf_err,
1039 2 dgisselq
                // Common wires, in and out, of the arbiter
1040 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1041
                        o_wb_we, o_wb_addr, o_wb_data,
1042
                        i_wb_ack, i_wb_stall, i_wb_err);
1043 2 dgisselq
 
1044
        //
1045
        //
1046
        //      PIPELINE STAGE #5 :: Write-back results
1047
        //
1048
        //
1049
        // This stage is not allowed to stall.  If results are ready to be
1050
        // written back, they are written back at all cost.  Sleepy CPU's
1051
        // won't prevent write back, nor debug modes, halting the CPU, nor
1052
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1053
        // as knowinig something is available for writeback.
1054
 
1055
        //
1056
        // Write back to our generic register set ...
1057
        // When shall we write back?  On one of two conditions
1058
        //      Note that the flags needed to be checked before issuing the
1059
        //      bus instruction, so they don't need to be checked here.
1060
        //      Further, alu_wr includes (set_cond), so we don't need to
1061
        //      check for that here either.
1062 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1063 36 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
1064
`else
1065
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
1066
`endif
1067 2 dgisselq
        // Which register shall be written?
1068 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1069
        //              One or PC, one for CC, and one for GIE match
1070 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1071 25 dgisselq
        // Are we writing to the CC register?
1072
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1073 2 dgisselq
        // Are we writing to the PC?
1074
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1075
        // What value to write?
1076
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
1077
        always @(posedge i_clk)
1078
                if (wr_reg_ce)
1079
                        regset[wr_reg_id] <= wr_reg_vl;
1080 18 dgisselq
                else if ((i_halt)&&(i_dbg_we))
1081
                        regset[i_dbg_reg] <= i_dbg_data[31:0];
1082 2 dgisselq
 
1083
        //
1084
        // Write back to the condition codes/flags register ...
1085
        // When shall we write to our flags register?  alF_wr already
1086
        // includes the set condition ...
1087 36 dgisselq
        assign  wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
1088 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1089 56 dgisselq
        assign  w_uflags = { bus_err_flag, trap, ill_err,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1090
        assign  w_iflags = { bus_err_flag, trap, ill_err,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1091 36 dgisselq
`else
1092
        assign  w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1093
        assign  w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1094
`endif
1095 2 dgisselq
        // What value to write?
1096
        always @(posedge i_clk)
1097
                // If explicitly writing the register itself
1098 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1099 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1100
                // Otherwise if we're setting the flags from an ALU operation
1101
                else if ((wr_flags_ce)&&(alu_gie))
1102
                        flags <= alu_flags;
1103
                else if ((i_halt)&&(i_dbg_we)
1104
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1105
                        flags <= i_dbg_data[3:0];
1106
 
1107
        always @(posedge i_clk)
1108 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1109 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1110
                else if ((wr_flags_ce)&&(~alu_gie))
1111
                        iflags <= alu_flags;
1112
                else if ((i_halt)&&(i_dbg_we)
1113
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
1114
                        iflags <= i_dbg_data[3:0];
1115
 
1116
        // The 'break' enable  bit.  This bit can only be set from supervisor
1117
        // mode.  It control what the CPU does upon encountering a break
1118
        // instruction.
1119
        //
1120
        // The goal, upon encountering a break is that the CPU should stop and
1121
        // not execute the break instruction, choosing instead to enter into
1122
        // either interrupt mode or halt first.  
1123
        //      if ((break_en) AND (break_instruction)) // user mode or not
1124
        //              HALT CPU
1125
        //      else if (break_instruction) // only in user mode
1126
        //              set an interrupt flag, go to supervisor mode
1127
        //              allow supervisor to step the CPU.
1128
        //      Upon a CPU halt, any break condition will be reset.  The
1129
        //      external debugger will then need to deal with whatever
1130
        //      condition has taken place.
1131
        initial break_en = 1'b0;
1132
        always @(posedge i_clk)
1133
                if ((i_rst)||(i_halt))
1134
                        break_en <= 1'b0;
1135 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1136 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1137 34 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1138
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
1139
                        break_en <= i_dbg_data[`CPU_BREAK_BIT];
1140 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1141 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1142
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1143
                                &&(~clear_pipeline)
1144
                        ||((~alu_gie)&&(bus_err))
1145
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
1146
`else
1147
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1148
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1149
                                &&(~clear_pipeline))
1150 38 dgisselq
                        ||((~alu_gie)&&(bus_err));
1151 36 dgisselq
`endif
1152 2 dgisselq
 
1153
 
1154
        // The sleep register.  Setting the sleep register causes the CPU to
1155
        // sleep until the next interrupt.  Setting the sleep register within
1156
        // interrupt mode causes the processor to halt until a reset.  This is
1157 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1158
        // set the sleep bit and switch to supervisor mode in the same 
1159
        // instruction: users are not allowed to halt the CPU.
1160 2 dgisselq
        always @(posedge i_clk)
1161
                if ((i_rst)||((i_interrupt)&&(gie)))
1162
                        sleep <= 1'b0;
1163 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1164
                        // In supervisor mode, we have no protections.  The
1165
                        // supervisor can set the sleep bit however he wants.
1166 2 dgisselq
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1167 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1168
                        // In user mode, however, you can only set the sleep
1169
                        // mode while remaining in user mode.  You can't switch
1170
                        // to sleep mode *and* supervisor mode at the same
1171
                        // time, lest you halt the CPU.
1172
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1173 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1174
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1175
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
1176
 
1177
        always @(posedge i_clk)
1178
                if ((i_rst)||(w_switch_to_interrupt))
1179
                        step <= 1'b0;
1180 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1181 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1182
                else if ((i_halt)&&(i_dbg_we)
1183
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1184
                        step <= i_dbg_data[`CPU_STEP_BIT];
1185 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1186 2 dgisselq
                        step <= 1'b0;
1187
 
1188
        // The GIE register.  Only interrupts can disable the interrupt register
1189
        assign  w_switch_to_interrupt = (gie)&&(
1190
                        // On interrupt (obviously)
1191
                        (i_interrupt)
1192
                        // If we are stepping the CPU
1193 38 dgisselq
                        ||((alu_pc_valid)&&(step))
1194 2 dgisselq
                        // If we encounter a break instruction, if the break
1195 36 dgisselq
                        //      enable isn't set.
1196 38 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
1197
`ifdef  OPT_ILLEGAL_INSTRUCTION
1198 36 dgisselq
                        // On an illegal instruction
1199
                        ||((alu_valid)&&(alu_illegal))
1200
`endif
1201 2 dgisselq
                        // If we write to the CC register
1202
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1203 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1204 2 dgisselq
                        // Or if, in debug mode, we write to the CC register
1205
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
1206
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
1207
                        );
1208
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1209
                        // Then if we write the CC register
1210
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1211 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1212 2 dgisselq
                        // Or if, in debug mode, we write the CC register
1213
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
1214
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
1215
                        );
1216
        always @(posedge i_clk)
1217
                if (i_rst)
1218
                        gie <= 1'b0;
1219
                else if (w_switch_to_interrupt)
1220
                        gie <= 1'b0;
1221
                else if (w_release_from_interrupt)
1222
                        gie <= 1'b1;
1223
 
1224 25 dgisselq
        initial trap = 1'b0;
1225
        always @(posedge i_clk)
1226
                if (i_rst)
1227
                        trap <= 1'b0;
1228
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1229
                                &&(wr_reg_id[4])&&(wr_write_cc))
1230
                        trap <= 1'b1;
1231
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
1232
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
1233
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
1234
                else if (w_release_from_interrupt)
1235
                        trap <= 1'b0;
1236
 
1237 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1238 36 dgisselq
        initial ill_err = 1'b0;
1239
        always @(posedge i_clk)
1240
                if (i_rst)
1241
                        ill_err <= 1'b0;
1242
                else if (w_release_from_interrupt)
1243
                        ill_err <= 1'b0;
1244
                else if ((alu_valid)&&(alu_illegal)&&(gie))
1245
                        ill_err <= 1'b1;
1246 38 dgisselq
`else
1247
        assign ill_err = 1'b0;
1248 36 dgisselq
`endif
1249
        initial bus_err_flag = 1'b0;
1250
        always @(posedge i_clk)
1251
                if (i_rst)
1252
                        bus_err_flag <= 1'b0;
1253
                else if (w_release_from_interrupt)
1254
                        bus_err_flag <= 1'b0;
1255
                else if ((bus_err)&&(alu_gie))
1256
                        bus_err_flag <= 1'b1;
1257
 
1258 2 dgisselq
        //
1259
        // Write backs to the PC register, and general increments of it
1260
        //      We support two: upc and ipc.  If the instruction is normal,
1261
        // we increment upc, if interrupt level we increment ipc.  If
1262
        // the instruction writes the PC, we write whichever PC is appropriate.
1263
        //
1264
        // Do we need to all our partial results from the pipeline?
1265
        // What happens when the pipeline has gie and ~gie instructions within
1266
        // it?  Do we clear both?  What if a gie instruction tries to clear
1267
        // a non-gie instruction?
1268
        always @(posedge i_clk)
1269 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1270 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1271 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1272 2 dgisselq
                        upc <= alu_pc;
1273
                else if ((i_halt)&&(i_dbg_we)
1274
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
1275 48 dgisselq
                        upc <= i_dbg_data[(AW-1):0];
1276 2 dgisselq
 
1277
        always @(posedge i_clk)
1278
                if (i_rst)
1279
                        ipc <= RESET_ADDRESS;
1280
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1281 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1282 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1283 2 dgisselq
                        ipc <= alu_pc;
1284
                else if ((i_halt)&&(i_dbg_we)
1285
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
1286 48 dgisselq
                        ipc <= i_dbg_data[(AW-1):0];
1287 2 dgisselq
 
1288
        always @(posedge i_clk)
1289
                if (i_rst)
1290
                        pf_pc <= RESET_ADDRESS;
1291
                else if (w_switch_to_interrupt)
1292
                        pf_pc <= ipc;
1293
                else if (w_release_from_interrupt)
1294
                        pf_pc <= upc;
1295
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1296 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1297 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1298 34 dgisselq
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
1299 48 dgisselq
                        pf_pc <= i_dbg_data[(AW-1):0];
1300 2 dgisselq
                else if (dcd_ce)
1301 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1302 2 dgisselq
 
1303
        initial new_pc = 1'b1;
1304
        always @(posedge i_clk)
1305 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1306 2 dgisselq
                        new_pc <= 1'b1;
1307
                else if (w_switch_to_interrupt)
1308
                        new_pc <= 1'b1;
1309
                else if (w_release_from_interrupt)
1310
                        new_pc <= 1'b1;
1311
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1312
                        new_pc <= 1'b1;
1313
                else if ((i_halt)&&(i_dbg_we)
1314 34 dgisselq
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
1315 2 dgisselq
                        new_pc <= 1'b1;
1316
                else
1317
                        new_pc <= 1'b0;
1318
 
1319
        //
1320
        // The debug interface
1321 56 dgisselq
        generate
1322
        if (AW<32)
1323
        begin
1324
                always @(posedge i_clk)
1325 2 dgisselq
                begin
1326
                        o_dbg_reg <= regset[i_dbg_reg];
1327
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1328 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1329 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1330 56 dgisselq
                        begin
1331 36 dgisselq
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1332 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1333
                        end
1334 2 dgisselq
                end
1335 56 dgisselq
        end else begin
1336
                always @(posedge i_clk)
1337
                begin
1338
                        o_dbg_reg <= regset[i_dbg_reg];
1339
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1340
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1341
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1342
                        begin
1343
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1344
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1345
                        end
1346
                end
1347
        end endgenerate
1348
 
1349 2 dgisselq
        always @(posedge i_clk)
1350 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1351 18 dgisselq
 
1352
        always @(posedge i_clk)
1353 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1354 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1355 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1356 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1357 2 dgisselq
 
1358
        //
1359
        //
1360
        // Produce accounting outputs: Account for any CPU stalls, so we can
1361
        // later evaluate how well we are doing.
1362
        //
1363
        //
1364 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
1365
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1366 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1367 56 dgisselq
 
1368
        always @(posedge i_clk)
1369
                o_debug <= {
1370
                        pf_pc[7:0],
1371
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1372
                        op_ce, alu_ce, mem_ce,
1373
                        opA[23:20], opA[3:0],
1374
                        wr_reg_vl[7:0]
1375
                        };
1376
 
1377 2 dgisselq
endmodule

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