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///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9 56 dgisselq
//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, there are only 16 instruction types supported.
11
//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
13 2 dgisselq
//
14 56 dgisselq
//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
16 2 dgisselq
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
19 56 dgisselq
//              1. Prefetch, returns the instruction from memory. 
20 2 dgisselq
//
21
//              2. Instruction Decode
22
//
23
//              3. Read Operands
24
//
25
//              4. Apply Instruction
26
//
27
//              4. Write-back Results
28
//
29 56 dgisselq
//      Further information about the inner workings of this CPU may be
30
//      found in the spec.pdf file.  (The documentation within this file
31
//      had become out of date and out of sync with the spec.pdf, so look
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//      to the spec.pdf for accurate and up to date information.)
33 2 dgisselq
//
34
//
35
// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
// Copyright (C) 2015, Gisselquist Technology, LLC
41
//
42
// This program is free software (firmware): you can redistribute it and/or
43
// modify it under the terms of  the GNU General Public License as published
44
// by the Free Software Foundation, either version 3 of the License, or (at
45
// your option) any later version.
46
//
47
// This program is distributed in the hope that it will be useful, but WITHOUT
48
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
49
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
50
// for more details.
51
//
52
// License:     GPL, v3, as defined and found on www.gnu.org,
53
//              http://www.gnu.org/licenses/gpl.html
54
//
55
//
56
///////////////////////////////////////////////////////////////////////////////
57
//
58 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
59
// fetches are more complicated and therefore use more FPGA resources, while
60
// single fetches will cause the CPU to stall for about 5 stalls each 
61
// instruction cycle, effectively reducing the instruction count per clock to
62
// about 0.2.  However, the area cost may be worth it.  Consider:
63
//
64
//      Slice LUTs              ZipSystem       ZipCPU
65
//      Single Fetching         2521            1734
66
//      Pipelined fetching      2796            2046
67
//
68
//
69
//
70 25 dgisselq
`define CPU_CC_REG      4'he
71 2 dgisselq
`define CPU_PC_REG      4'hf
72 65 dgisselq
`define CPU_BUSERR_BIT  10
73 25 dgisselq
`define CPU_TRAP_BIT    9
74 65 dgisselq
`define CPU_ILL_BIT     8
75 2 dgisselq
`define CPU_BREAK_BIT   7
76
`define CPU_STEP_BIT    6
77
`define CPU_GIE_BIT     5
78
`define CPU_SLEEP_BIT   4
79 36 dgisselq
// Compile time defines
80 56 dgisselq
//
81
`include "cpudefs.v"
82
//
83 65 dgisselq
//
84
//
85
// `define      DEBUG_SCOPE
86
//
87
//
88
//
89 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
90
                // Debug interface
91 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
92
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
94
                // CPU interface to the wishbone bus
95 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
96
                        o_wb_lcl_cyc, o_wb_lcl_stb,
97
                        o_wb_we, o_wb_addr, o_wb_data,
98 2 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data,
99 36 dgisselq
                        i_wb_err,
100 2 dgisselq
                // Accounting/CPU usage interface
101 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
102
`ifdef  DEBUG_SCOPE
103
                , o_debug
104
`endif
105
                );
106 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
107
                        LGICACHE=6, AW=ADDRESS_WIDTH;
108 56 dgisselq
`ifdef  OPT_MULTIPLY
109
        parameter       IMPLEMENT_MPY = 1;
110
`else
111
        parameter       IMPLEMENT_MPY = 0;
112
`endif
113 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
114
        // Debug interface -- inputs
115 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
116 2 dgisselq
        input           [4:0]    i_dbg_reg;
117
        input                   i_dbg_we;
118
        input           [31:0]   i_dbg_data;
119
        // Debug interface -- outputs
120
        output  reg             o_dbg_stall;
121
        output  reg     [31:0]   o_dbg_reg;
122 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
123 2 dgisselq
        output  wire            o_break;
124
        // Wishbone interface -- outputs
125 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
126
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
127 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
128
        output  wire    [31:0]   o_wb_data;
129 2 dgisselq
        // Wishbone interface -- inputs
130
        input                   i_wb_ack, i_wb_stall;
131
        input           [31:0]   i_wb_data;
132 36 dgisselq
        input                   i_wb_err;
133 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
134 9 dgisselq
        output  wire            o_op_stall;
135 2 dgisselq
        output  wire            o_pf_stall;
136 9 dgisselq
        output  wire            o_i_count;
137 56 dgisselq
        //
138 65 dgisselq
`ifdef  DEBUG_SCOPE
139 56 dgisselq
        output  reg     [31:0]   o_debug;
140 65 dgisselq
`endif
141 2 dgisselq
 
142 25 dgisselq
 
143 2 dgisselq
        // Registers
144 56 dgisselq
        //
145
        //      The distributed RAM style comment is necessary on the
146
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
147
        // set and in the process ruining everything else.  It basically
148
        // optimizes logic away, to where it no longer works.  The logic
149
        // as described herein will work, this just makes sure XST implements
150
        // that logic.
151
        //
152
        (* ram_style = "distributed" *)
153 2 dgisselq
        reg     [31:0]   regset [0:31];
154 9 dgisselq
 
155
        // Condition codes
156 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
157
        reg     [3:0]    flags, iflags;
158 36 dgisselq
        wire    [10:0]   w_uflags, w_iflags;
159 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
160 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
161 65 dgisselq
        reg             ill_err_u, ill_err_i;
162 38 dgisselq
`else
163 65 dgisselq
        wire            ill_err_u, ill_err_i;
164 36 dgisselq
`endif
165 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
166 2 dgisselq
 
167 9 dgisselq
        // The master chip enable
168
        wire            master_ce;
169 2 dgisselq
 
170
        //
171
        //
172
        //      PIPELINE STAGE #1 :: Prefetch
173
        //              Variable declarations
174
        //
175 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
176 25 dgisselq
        reg             new_pc, op_break;
177 18 dgisselq
        wire    clear_pipeline;
178 36 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
179 9 dgisselq
 
180
        wire            dcd_stalled;
181 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
182 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
183
        wire    [31:0]           pf_data;
184
        wire    [31:0]           instruction;
185
        wire    [(AW-1):0]       instruction_pc;
186 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
187 2 dgisselq
 
188
        //
189
        //
190
        //      PIPELINE STAGE #2 :: Instruction Decode
191
        //              Variable declarations
192
        //
193
        //
194 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
195 2 dgisselq
        wire            op_stall, dcd_ce;
196
        reg     [3:0]    dcdOp;
197
        reg     [4:0]    dcdA, dcdB;
198 25 dgisselq
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
199 2 dgisselq
        reg     [3:0]    dcdF;
200
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
201
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
202 48 dgisselq
        reg     [(AW-1):0]       dcd_pc;
203 2 dgisselq
        reg     [23:0]   r_dcdI;
204 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
205 48 dgisselq
        reg             dcd_zI; // true if dcdI == 0
206 56 dgisselq
`endif
207 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
208
 
209 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
210 36 dgisselq
        reg     dcd_clear_bus;
211
`endif
212 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
213 36 dgisselq
        reg     dcd_illegal;
214
`endif
215 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
216 48 dgisselq
        reg                     dcd_early_branch_stb, dcd_early_branch;
217
        reg     [(AW-1):0]       dcd_branch_pc;
218 36 dgisselq
`else
219 48 dgisselq
        wire                    dcd_early_branch_stb, dcd_early_branch;
220
        wire    [(AW-1):0]       dcd_branch_pc;
221 36 dgisselq
`endif
222 2 dgisselq
 
223
 
224
        //
225
        //
226
        //      PIPELINE STAGE #3 :: Read Operands
227
        //              Variable declarations
228
        //
229
        //
230
        //
231
        // Now, let's read our operands
232
        reg     [4:0]    alu_reg;
233
        reg     [3:0]    opn;
234
        reg     [4:0]    opR;
235 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
236
        reg     [(AW-1):0]       op_pc;
237 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
238 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
239 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
240 36 dgisselq
        wire    [10:0]   opFl;
241 56 dgisselq
        reg     [5:0]    r_opF;
242
        wire    [7:0]    opF;
243
        reg     [2:0]    opF_cp;
244 2 dgisselq
        wire            op_ce;
245 56 dgisselq
        // Some pipeline control wires
246
`ifdef  OPT_SINGLE_CYCLE
247
        reg     opA_alu, opA_mem;
248
        reg     opB_alu, opB_mem;
249
`endif
250 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
251 36 dgisselq
        reg     op_clear_bus;
252
`endif
253 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
254 36 dgisselq
        reg     op_illegal;
255
`endif
256 2 dgisselq
 
257
 
258
        //
259
        //
260
        //      PIPELINE STAGE #4 :: ALU / Memory
261
        //              Variable declarations
262
        //
263
        //
264 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
265 2 dgisselq
        reg             alu_pc_valid;;
266
        wire            alu_ce, alu_stall;
267
        wire    [31:0]   alu_result;
268
        wire    [3:0]    alu_flags;
269
        wire            alu_valid;
270
        wire            set_cond;
271
        reg             alu_wr, alF_wr, alu_gie;
272 56 dgisselq
        wire            alu_illegal_op;
273 38 dgisselq
        wire            alu_illegal;
274 2 dgisselq
 
275
 
276
 
277
        wire    mem_ce, mem_stalled;
278 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
279
        wire    mem_pipe_stalled;
280
`endif
281 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
282
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
283 48 dgisselq
        wire    [4:0]            mem_wreg;
284 9 dgisselq
 
285 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
286
        wire    [(AW-1):0]       mem_addr;
287
        wire    [31:0]           mem_data, mem_result;
288
        reg     [4:0]            mem_last_reg; // Last register result to go in
289 2 dgisselq
 
290
 
291
 
292
        //
293
        //
294
        //      PIPELINE STAGE #5 :: Write-back
295
        //              Variable declarations
296
        //
297 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
298 2 dgisselq
        wire    [4:0]    wr_reg_id;
299
        wire    [31:0]   wr_reg_vl;
300
        wire    w_switch_to_interrupt, w_release_from_interrupt;
301 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
302 2 dgisselq
 
303
 
304
 
305
        //
306
        //      MASTER: clock enable.
307
        //
308 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
309 2 dgisselq
 
310
 
311
        //
312
        //      PIPELINE STAGE #1 :: Prefetch
313
        //              Calculate stall conditions
314 65 dgisselq
        //
315
        //      These are calculated externally, within the prefetch module.
316
        //
317 2 dgisselq
 
318
        //
319
        //      PIPELINE STAGE #2 :: Instruction Decode
320
        //              Calculate stall conditions
321 34 dgisselq
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
322 2 dgisselq
        assign          dcd_stalled = (dcdvalid)&&(
323
                                        (op_stall)
324
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
325 36 dgisselq
                                        ||((opvalid_mem)&&(op_wr_pc))
326
                                        ||((opvalid_mem)&&(opR_cc)));
327 2 dgisselq
        //
328
        //      PIPELINE STAGE #3 :: Read Operands
329
        //              Calculate stall conditions
330 56 dgisselq
        assign  op_stall = ((opvalid)&&(~master_ce))||(
331
                        // Stall if going into the ALU and the ALU is stalled
332
                        //      i.e. if the memory is busy, or we are single
333
                        //      stepping
334
                        ((opvalid_alu)&&(alu_stall))
335
                        //
336
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
337
                        // Stall if we are going into memory with an operation
338
                        //      that cannot be pipelined, and the memory is
339
                        //      already busy
340 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
341 56 dgisselq
                        ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
342
                        //
343
                        // Stall if we are going into memory with a pipeable
344
                        //      operation, but the memory unit declares it is
345
                        //      not going to accept any more pipeline operations
346 65 dgisselq
                        ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))
347
`else
348
                        ||((opvalid_mem)&&(mem_busy))
349
`endif
350
                        );
351 2 dgisselq
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
352
 
353
        //
354
        //      PIPELINE STAGE #4 :: ALU / Memory
355
        //              Calculate stall conditions
356 36 dgisselq
        //
357
        // 1. Basic stall is if the previous stage is valid and the next is
358
        //      busy.  
359
        // 2. Also stall if the prior stage is valid and the master clock enable
360
        //      is de-selected
361 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
362
        //      since we don't know if it'll put us to sleep or not.
363 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
364
        //      through the ALU.  Break instructions are not allowed through
365
        //      the ALU.
366
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
367 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
368
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
369
                                &&(wr_write_cc)) // Case 3
370
                        ||((opvalid_alu)&&(op_break)); // Case 3
371 38 dgisselq
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
372 2 dgisselq
        //
373 65 dgisselq
 
374
        //
375
        // Note: if you change the conditions for mem_ce, you must also change
376
        // alu_pc_valid.
377
        //
378 38 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
379
                        &&(set_cond)&&(~mem_stalled);
380 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
381 38 dgisselq
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
382
                                (mem_pipe_stalled)
383
                                ||((~op_pipe)&&(mem_busy))
384
                                // Stall waiting for flags to be valid
385
                                // Or waiting for a write to the PC register
386
                                // Or CC register, since that can change the
387
                                //  PC as well
388
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
389
                                        &&((wr_write_pc)||(wr_write_cc)))));
390
`else
391 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
392 2 dgisselq
                                (~master_ce)
393
                                // Stall waiting for flags to be valid
394
                                // Or waiting for a write to the PC register
395 25 dgisselq
                                // Or CC register, since that can change the
396
                                //  PC as well
397
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
398 38 dgisselq
`endif
399 2 dgisselq
 
400
 
401
        //
402
        //
403
        //      PIPELINE STAGE #1 :: Prefetch
404
        //
405
        //
406 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
407 9 dgisselq
        wire            pf_ce;
408
 
409
        assign          pf_ce = (~dcd_stalled);
410 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
411
                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
412 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
413 36 dgisselq
                                        pf_valid, pf_illegal,
414
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
415
                                pf_ack, pf_stall, pf_err, i_wb_data);
416 2 dgisselq
`else // Pipe fetch
417 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
418 36 dgisselq
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
419
                                        i_clear_pf_cache, ~dcd_stalled,
420
                                        (new_pc)?pf_pc:dcd_branch_pc,
421 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
422
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
423 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
424 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
425 36 dgisselq
                                ((dcd_clear_bus)&&(dcdvalid))
426
                                ||((op_clear_bus)&&(opvalid))
427
                                ||
428
`endif
429
                                (mem_cyc_lcl)||(mem_cyc_gbl),
430
                                pf_illegal);
431 2 dgisselq
        assign  instruction_gie = gie;
432
`endif
433
 
434 36 dgisselq
        initial dcdvalid = 1'b0;
435 2 dgisselq
        always @(posedge i_clk)
436
                if (i_rst)
437
                        dcdvalid <= 1'b0;
438
                else if (dcd_ce)
439 36 dgisselq
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
440
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
441 2 dgisselq
                        dcdvalid <= 1'b0;
442
 
443 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
444 2 dgisselq
        always @(posedge i_clk)
445 56 dgisselq
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
446 36 dgisselq
                begin
447
                        dcd_early_branch <= 1'b0;
448
                        // First case, a move to PC instruction
449
                        if ((instruction[31:28] == 4'h2)
450 65 dgisselq
                                // Offsets of the PC register *only*
451
                                &&(instruction[19:16] == `CPU_PC_REG)
452 36 dgisselq
                                &&((instruction_gie)
453
                                        ||((~instruction[20])&&(~instruction[15])))
454 65 dgisselq
                                &&(instruction[23:21]==3'h0)) // Unconditional
455 36 dgisselq
                        begin
456
                                dcd_early_branch_stb <= 1'b1;
457
                                dcd_early_branch <= 1'b1;
458
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
459
 
460
                        end else // Next case, an Add Imm -> PC instruction
461
                        if ((instruction[31:28] == 4'ha) // Add
462
                                &&(~instruction[20]) // Immediate
463
                                &&(instruction[23:21]==3'h0)) // Always
464
                        begin
465
                                dcd_early_branch_stb <= 1'b1;
466
                                dcd_early_branch <= 1'b1;
467
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
468
                        end else // Next case: load Immediate to PC
469
                        if (instruction[31:28] == 4'h3)
470
                        begin
471
                                dcd_early_branch_stb <= 1'b1;
472
                                dcd_early_branch <= 1'b1;
473
                                // r_dcdI <= { instruction[23:0] };
474
                        end
475
                end else
476
                begin
477
                        if (dcd_ce) dcd_early_branch <= 1'b0;
478
                        dcd_early_branch_stb <= 1'b0;
479
                end
480 56 dgisselq
        generate
481
        if (AW == 24)
482
        begin
483
                always @(posedge i_clk)
484 2 dgisselq
                if (dcd_ce)
485
                begin
486 36 dgisselq
                        if (instruction[31]) // Add
487 56 dgisselq
                        begin
488
                                dcd_branch_pc <= instruction_pc
489
                                                + { {(AW-20){instruction[19]}}, instruction[19:0] }
490
                                                + {{(AW-1){1'b0}},1'b1};
491
                        end else if (~instruction[28]) // 4'h2 = MOV
492 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
493 36 dgisselq
                        else // if (instruction[28]) // 4'h3 = LDI
494 56 dgisselq
                                dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
495
                end
496
        end else begin
497
                always @(posedge i_clk)
498
                if (dcd_ce)
499
                begin
500
                        if (instruction[31]) // Add
501
                        begin
502
                                dcd_branch_pc <= instruction_pc
503
                                                        + { {(AW-20){instruction[19]}}, instruction[19:0] }
504
                                                        + {{(AW-1){1'b0}},1'b1};
505
                        end else if (~instruction[28]) // 4'h2 = MOV
506
                        begin
507
                                        dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
508
                        end else // if (instruction[28]) // 4'h3 = LDI
509
                        begin
510 48 dgisselq
                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
511 56 dgisselq
                        end
512 36 dgisselq
                end
513 56 dgisselq
        end endgenerate
514 38 dgisselq
`else   //      OPT_EARLY_BRANCHING
515 36 dgisselq
        assign  dcd_early_branch_stb = 1'b0;
516
        assign  dcd_early_branch     = 1'b0;
517 48 dgisselq
        assign  dcd_branch_pc        = {(AW){1'b0}};
518 38 dgisselq
`endif  //      OPT_EARLY_BRANCHING
519 36 dgisselq
 
520
        always @(posedge i_clk)
521
                if (dcd_ce)
522
                begin
523 56 dgisselq
                        dcd_pc <= instruction_pc
524
                                +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
525 2 dgisselq
 
526
                        // Record what operation we are doing
527
                        dcdOp <= instruction[31:28];
528
 
529
                        // Default values
530
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
531
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
532 25 dgisselq
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
533
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
534
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
535
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
536 2 dgisselq
                        dcdM    <= 1'b0;
537 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
538 65 dgisselq
                        // Don't change the flags on conditional instructions,
539
                        // UNLESS: the conditional instruction was a CMP
540
                        // or TST instruction.
541
                        dcdF_wr <= ((instruction[23:21]==3'h0)
542
                                        ||(instruction[31:29] == 3'h0));
543 36 dgisselq
`else
544 2 dgisselq
                        dcdF_wr <= 1'b1;
545 36 dgisselq
`endif
546 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
547 36 dgisselq
                        dcd_clear_bus <= 1'b0;
548
`endif
549 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
550 36 dgisselq
                        dcd_illegal <= pf_illegal;
551
`endif
552 2 dgisselq
 
553
                        // Set the condition under which we do this operation
554
                        // The top four bits are a mask, the bottom four the
555
                        // value the flags must equal once anded with the mask
556
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
557
                        casez(instruction[31:28])
558
                        4'h2: begin // Move instruction
559
                                if (~instruction_gie)
560
                                begin
561
                                        dcdA[4] <= instruction[20];
562
                                        dcdB[4] <= instruction[15];
563
                                end
564
                                dcdA_wr <= 1'b1;
565
                                dcdA_rd <= 1'b0;
566
                                dcdB_rd <= 1'b1;
567
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
568 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
569 48 dgisselq
                                dcd_zI <= (instruction[14:0] == 0);
570 56 dgisselq
`endif
571 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
572
                                end
573
                        4'h3: begin // Load immediate
574
                                dcdA_wr <= 1'b1;
575
                                dcdA_rd <= 1'b0;
576
                                dcdB_rd <= 1'b0;
577
                                r_dcdI <= { instruction[23:0] };
578 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
579 48 dgisselq
                                dcd_zI <= (instruction[23:0] == 0);
580 56 dgisselq
`endif
581 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
582
                                dcdF    <= 4'h8; // This is unconditional
583
                                dcdOp <= 4'h2;
584
                                end
585 25 dgisselq
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
586 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
587 25 dgisselq
                                // Don't write flags except for multiplies
588 36 dgisselq
                                //   and then only if they are unconditional
589
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
590
                                        &&(instruction[23:21]==3'h0));
591
`else
592
                                // Don't write flags except for multiplies
593 25 dgisselq
                                dcdF_wr <= (instruction[27:25] != 3'h7);
594 36 dgisselq
`endif
595 2 dgisselq
                                r_dcdI <= { 8'h00, instruction[15:0] };
596 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
597 48 dgisselq
                                dcd_zI <= (instruction[15:0] == 0);
598 56 dgisselq
`endif
599 2 dgisselq
                                if (instruction[27:24] == 4'he)
600
                                begin
601
                                        // NOOP instruction
602
                                        dcdA_wr <= 1'b0;
603
                                        dcdA_rd <= 1'b0;
604
                                        dcdB_rd <= 1'b0;
605
                                        dcdOp <= 4'h2;
606 36 dgisselq
                                        // Might also be a break.  Big
607
                                        // instruction set hole here.
608 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
609 36 dgisselq
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
610
`endif
611 2 dgisselq
                                end else if (instruction[27:24] == 4'hf)
612
                                begin // Load partial immediate(s)
613
                                        dcdA_wr <= 1'b1;
614
                                        dcdA_rd <= 1'b1;
615
                                        dcdB_rd <= 1'b0;
616
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
617 25 dgisselq
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
618
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
619 2 dgisselq
                                        dcdOp <= { 3'h3, instruction[20] };
620
                                end else begin
621 25 dgisselq
                                        // Actual multiply instruction
622
                                        r_dcdI <= { 8'h00, instruction[15:0] };
623 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
624 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
625 56 dgisselq
`endif
626 25 dgisselq
                                        dcdA_rd <= 1'b1;
627
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
628
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
629 2 dgisselq
                                end end
630 56 dgisselq
                        4'b011?: begin // LOD/STO or Load/Store
631 2 dgisselq
                                dcdF_wr <= 1'b0; // Don't write flags
632
                                dcdA_wr <= (~instruction[28]); // Write on loads
633
                                dcdA_rd <= (instruction[28]); // Read on stores
634
                                dcdB_rd <= instruction[20];
635
                                if (instruction[20])
636 48 dgisselq
                                begin
637 2 dgisselq
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
638 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
639 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
640 56 dgisselq
`endif
641 48 dgisselq
                                end else begin
642 2 dgisselq
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
643 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
644 48 dgisselq
                                        dcd_zI <= (instruction[19:0] == 0);
645 56 dgisselq
`endif
646 48 dgisselq
                                end
647 2 dgisselq
                                dcdM <= 1'b1; // Memory operation
648 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
649 36 dgisselq
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
650
`endif
651 2 dgisselq
                                end
652
                        default: begin
653
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
654
                                dcdA_rd <= 1'b1;
655
                                dcdB_rd <= instruction[20];
656
                                if (instruction[20])
657 48 dgisselq
                                begin
658 2 dgisselq
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
659 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
660 48 dgisselq
                                        dcd_zI <= (instruction[15:0] == 0);
661 56 dgisselq
`endif
662 48 dgisselq
                                end else begin
663 2 dgisselq
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
664 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
665 48 dgisselq
                                        dcd_zI <= (instruction[19:0] == 0);
666 56 dgisselq
`endif
667 48 dgisselq
                                end end
668 2 dgisselq
                        endcase
669
 
670
 
671
                        dcd_gie <= instruction_gie;
672
                end
673 25 dgisselq
        always @(posedge i_clk)
674
                if (dcd_ce)
675
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
676 38 dgisselq
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
677 25 dgisselq
                        dcd_break <= 1'b0;
678 2 dgisselq
 
679 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
680
        reg     [23:0]   r_opI;
681
        reg     [4:0]    op_B;
682
        reg             op_pipe;
683 2 dgisselq
 
684 38 dgisselq
        initial op_pipe = 1'b0;
685
        // To be a pipeable operation, there must be 
686
        //      two valid adjacent instructions
687
        //      Both must be memory instructions
688
        //      Both must be writes, or both must be reads
689
        //      Both operations must be to the same identical address,
690
        //              or at least a single (one) increment above that address
691
        always @(posedge i_clk)
692
                if (op_ce)
693
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
694
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
695
                                &&(dcdB == op_B) // Same address register
696 65 dgisselq
                                &&((dcdF[2:0] == opF_cp) // Same condition
697
                                        ||(opF_cp == 3'h0)) // or no prev condition
698 38 dgisselq
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
699
        always @(posedge i_clk)
700
                if (op_ce) // &&(dcdvalid))
701
                        r_opI <= r_dcdI;
702
        always @(posedge i_clk)
703
                if (op_ce) // &&(dcdvalid))
704
                        op_B <= dcdB;
705
`endif
706
 
707 2 dgisselq
        //
708
        //
709
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
710
        //
711
        //
712 25 dgisselq
        assign  w_opA = regset[dcdA];
713
        assign  w_opB = regset[dcdB];
714 56 dgisselq
 
715
        wire    [31:0]   w_pcA_v;
716
        generate
717
        if (AW < 32)
718
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
719
        else
720
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
721
        endgenerate
722 2 dgisselq
        always @(posedge i_clk)
723
                if (op_ce) // &&(dcdvalid))
724
                begin
725
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
726
                                r_opA <= wr_reg_vl;
727 25 dgisselq
                        else if (dcdA_pc)
728 56 dgisselq
                                r_opA <= w_pcA_v;
729 25 dgisselq
                        else if (dcdA_cc)
730 36 dgisselq
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
731 2 dgisselq
                        else
732 25 dgisselq
                                r_opA <= w_opA;
733 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
734 48 dgisselq
                end else if (opvalid)
735
                begin // We were going to pick these up when they became valid,
736
                        // but for some reason we're stuck here as they became
737
                        // valid.  Pick them up now anyway
738 65 dgisselq
                        if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
739 48 dgisselq
                                r_opA <= wr_reg_vl;
740 56 dgisselq
`endif
741 2 dgisselq
                end
742 56 dgisselq
 
743
        wire    [31:0]   dcdI, w_opBnI, w_pcB_v;
744 2 dgisselq
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
745 56 dgisselq
        generate
746
        if (AW < 32)
747
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
748
        else
749
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
750
        endgenerate
751
 
752 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
753 56 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
754
                : ((dcdB_pc) ? w_pcB_v
755
                : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
756
                : w_opB)));
757
 
758 2 dgisselq
        always @(posedge i_clk)
759
                if (op_ce) // &&(dcdvalid))
760 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
761 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
762
                else if ((opvalid)&&(
763 65 dgisselq
                                ((opB_alu)&&(alu_wr))
764 56 dgisselq
                                ||((opB_mem)&&(mem_valid))))
765 48 dgisselq
                        r_opB <= wr_reg_vl;
766 56 dgisselq
`endif
767 2 dgisselq
 
768
        // The logic here has become more complex than it should be, no thanks
769
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
770
        // be two sets of four bits: the top bits specify what bits matter, the
771
        // bottom specify what those top bits must equal.  However, two of
772
        // conditions check whether bits are on, and those are the only two
773
        // conditions checking those bits.  Therefore, Vivado complains that
774
        // these two bits are redundant.  Hence the convoluted expression
775
        // below, arriving at what we finally want in the (now wire net)
776
        // opF.
777
        always @(posedge i_clk)
778
                if (op_ce)
779 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
780 2 dgisselq
                        case(dcdF[2:0])
781 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
782
                        3'h1:   r_opF <= 6'h11; // Z
783
                        3'h2:   r_opF <= 6'h10; // NE
784
                        3'h3:   r_opF <= 6'h20; // GE (!N)
785
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
786
                        3'h5:   r_opF <= 6'h24; // LT
787
                        3'h6:   r_opF <= 6'h02; // C
788
                        3'h7:   r_opF <= 6'h08; // V
789 2 dgisselq
                        endcase
790 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
791 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
792
        always @(posedge i_clk)
793
                if (op_ce)
794
                        opF_cp[2:0] <= dcdF[2:0];
795 2 dgisselq
 
796 36 dgisselq
        initial opvalid     = 1'b0;
797
        initial opvalid_alu = 1'b0;
798
        initial opvalid_mem = 1'b0;
799 2 dgisselq
        always @(posedge i_clk)
800
                if (i_rst)
801 25 dgisselq
                begin
802
                        opvalid     <= 1'b0;
803
                        opvalid_alu <= 1'b0;
804
                        opvalid_mem <= 1'b0;
805
                end else if (op_ce)
806
                begin
807 2 dgisselq
                        // Do we have a valid instruction?
808
                        //   The decoder may vote to stall one of its
809
                        //   instructions based upon something we currently
810
                        //   have in our queue.  This instruction must then
811
                        //   move forward, and get a stall cycle inserted.
812
                        //   Hence, the test on dcd_stalled here.  If we must
813
                        //   wait until our operands are valid, then we aren't
814
                        //   valid yet until then.
815 18 dgisselq
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
816 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
817 36 dgisselq
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
818
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
819
`else
820 25 dgisselq
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
821
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
822 36 dgisselq
`endif
823 25 dgisselq
                end else if ((~op_stall)||(clear_pipeline))
824
                begin
825
                        opvalid     <= 1'b0;
826
                        opvalid_alu <= 1'b0;
827
                        opvalid_mem <= 1'b0;
828
                end
829 2 dgisselq
 
830
        // Here's part of our debug interface.  When we recognize a break
831
        // instruction, we set the op_break flag.  That'll prevent this
832
        // instruction from entering the ALU, and cause an interrupt before
833
        // this instruction.  Thus, returning to this code will cause the
834
        // break to repeat and continue upon return.  To get out of this
835
        // condition, replace the break instruction with what it is supposed
836
        // to be, step through it, and then replace it back.  In this fashion,
837
        // a debugger can step through code.
838 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
839
        initial op_break = 1'b0;
840 2 dgisselq
        always @(posedge i_clk)
841 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
842
                else if (op_ce) op_break <= (dcd_break);
843
                else if ((clear_pipeline)||(~opvalid))
844
                                op_break <= 1'b0;
845 2 dgisselq
 
846 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
847 2 dgisselq
        always @(posedge i_clk)
848 36 dgisselq
                if(op_ce)
849
                        op_illegal <= dcd_illegal;
850
`endif
851
 
852
        always @(posedge i_clk)
853 2 dgisselq
                if (op_ce)
854
                begin
855
                        opn    <= dcdOp;        // Which ALU operation?
856 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
857 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
858 36 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
859
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
860
`else
861 2 dgisselq
                        // Will we write the flags/CC Register with our result?
862 25 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
863 2 dgisselq
                        // Will we be writing our results into a register?
864
                        opR_wr <= dcdA_wr;
865 36 dgisselq
`endif
866 2 dgisselq
                        // What register will these results be written into?
867
                        opR    <= dcdA;
868 38 dgisselq
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
869 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
870
                        op_gie <= dcd_gie;
871
 
872
                        //
873 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
874 36 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
875
`else
876 30 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
877 36 dgisselq
`endif
878 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
879
                        // op_pc  <= dcd_pc;
880 36 dgisselq
 
881 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
882 36 dgisselq
                        op_clear_bus <= dcd_clear_bus;
883
`endif
884 2 dgisselq
                end
885
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
886
 
887
        // This is tricky.  First, the PC and Flags registers aren't kept in
888
        // register set but in special registers of their own.  So step one
889
        // is to select the right register.  Step to is to replace that
890
        // register with the results of an ALU or memory operation, if such
891
        // results are now available.  Otherwise, we'd need to insert a wait
892
        // state of some type.
893
        //
894
        // The alternative approach would be to define some sort of
895
        // op_stall wire, which would stall any upstream stage.
896
        // We'll create a flag here to start our coordination.  Once we
897
        // define this flag to something other than just plain zero, then
898
        // the stalls will already be in place.
899 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
900
        initial opA_alu = 1'b0;
901 25 dgisselq
        always @(posedge i_clk)
902
                if (op_ce)
903 48 dgisselq
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
904
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
905
                        opA_alu <= 1'b0;
906 56 dgisselq
        initial opA_mem = 1'b0;
907 48 dgisselq
        always @(posedge i_clk)
908
                if (op_ce)
909 56 dgisselq
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd)&&(~opn[0]))
910 48 dgisselq
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
911
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
912
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
913
                        opA_mem <= 1'b0;
914 56 dgisselq
`endif
915 25 dgisselq
 
916 48 dgisselq
        always @(posedge i_clk)
917
                if (mem_ce)
918
                        mem_last_reg <= opR;
919 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
920 65 dgisselq
        assign  opA = ((opA_alu)&&(alu_wr)) ? alu_result
921 48 dgisselq
                        : ( ((opA_mem)&&(mem_valid))?mem_result
922
                        : r_opA );
923 56 dgisselq
`else
924
        assign  opA = r_opA;
925
`endif
926 48 dgisselq
 
927 25 dgisselq
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
928 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
929 25 dgisselq
                // Skip the requirement on writing back opA
930
                // Stall on memory, since we'll always need to stall for a 
931
                // memory access anyway
932 48 dgisselq
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
933 56 dgisselq
`else
934
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))
935
                                ||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
936
                                ||((mem_rdbusy)&&(mem_last_reg == dcdA))
937
                                );
938
`endif
939 36 dgisselq
 
940 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
941 25 dgisselq
        always @(posedge i_clk)
942
                if (op_ce)
943 48 dgisselq
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
944
        always @(posedge i_clk)
945
                if (op_ce)
946
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
947 56 dgisselq
                                ((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
948 48 dgisselq
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
949
                                        &&(mem_last_reg == dcdB)));
950
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
951
                        opB_mem <= 1'b0;
952 65 dgisselq
        assign  opB = ((opB_alu)&&(alu_wr)) ? alu_result
953 48 dgisselq
                        : ( ((opB_mem)&&(mem_valid))?mem_result
954
                        : r_opB );
955 56 dgisselq
`else
956
        assign  opB = r_opB;
957
`endif
958
 
959 25 dgisselq
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
960 56 dgisselq
`ifdef  OPT_SINGLE_CYCLE
961 38 dgisselq
                                // Stall on memory ops writing to my register
962
                                //      (i.e. loads), or on any write to my
963
                                //      register if I have an immediate offset
964
                                // Note the exception for writing to the PC:
965
                                //      if I write to the PC, the whole next
966
                                //      instruction is invalid, not just the
967
                                //      operand.  That'll get wiped in the
968
                                //      next operation anyway, so don't stall
969
                                //      here.
970 25 dgisselq
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
971 38 dgisselq
                                        &&(opR != { op_gie, `CPU_PC_REG} )
972 48 dgisselq
                                        &&(~dcd_zI))
973 38 dgisselq
                                // Stall on any write to the flags register,
974
                                // if we're going to need the flags value for
975
                                // opB.
976 30 dgisselq
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
977 38 dgisselq
                                // Stall on any ongoing memory operation that
978
                                // will write to opB
979 48 dgisselq
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
980 56 dgisselq
`else
981
                                ((opvalid)&&(opR_wr)&&(opR == dcdB))
982
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
983
                                ||((mem_rdbusy)&&(mem_last_reg == dcdB))
984
                                );
985
`endif
986 30 dgisselq
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
987
                                        &&(opvalid)&&(opR_cc);
988 2 dgisselq
        //
989
        //
990
        //      PIPELINE STAGE #4 :: Apply Instruction
991
        //
992
        //
993 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
994 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
995 56 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
996 2 dgisselq
 
997
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
998
        initial alF_wr   = 1'b0;
999
        initial alu_wr   = 1'b0;
1000
        always @(posedge i_clk)
1001
                if (i_rst)
1002
                begin
1003
                        alu_wr   <= 1'b0;
1004
                        alF_wr   <= 1'b0;
1005
                end else if (alu_ce)
1006
                begin
1007 65 dgisselq
                        // alu_reg <= opR;
1008 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1009
                        alF_wr  <= (opF_wr)&&(set_cond);
1010
                end else begin
1011
                        // These are strobe signals, so clear them if not
1012
                        // set for any particular clock
1013 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1014 2 dgisselq
                        alF_wr <= 1'b0;
1015
                end
1016
        always @(posedge i_clk)
1017 65 dgisselq
                if (alu_ce)
1018
                        alu_reg <= opR;
1019
                else if ((i_halt)&&(i_dbg_we))
1020
                        alu_reg <= i_dbg_reg;
1021
        reg     [31:0]   dbg_val;
1022
        reg             dbgv;
1023
        always @(posedge i_clk)
1024
                dbg_val <= i_dbg_data;
1025
        initial dbgv = 1'b0;
1026
        always @(posedge i_clk)
1027
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
1028
        always @(posedge i_clk)
1029 2 dgisselq
                if ((alu_ce)||(mem_ce))
1030
                        alu_gie  <= op_gie;
1031
        always @(posedge i_clk)
1032 65 dgisselq
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1033
                                &&(~mem_stalled)))
1034 2 dgisselq
                        alu_pc  <= op_pc;
1035 65 dgisselq
 
1036 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1037 56 dgisselq
        reg     r_alu_illegal;
1038
        initial r_alu_illegal = 0;
1039 38 dgisselq
        always @(posedge i_clk)
1040
                if ((alu_ce)||(mem_ce))
1041 56 dgisselq
                        r_alu_illegal <= op_illegal;
1042
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1043 38 dgisselq
`endif
1044
 
1045 65 dgisselq
        // This _almost_ is equal to (alu_ce)||(mem_ce).  The only
1046
        // problem is that mem_ce is gated by the set_cond, and
1047
        // the PC will be valid independent of the set condition.  Hence, this
1048
        // equals (alu_ce)||(everything in mem_ce but the set condition)
1049 2 dgisselq
        initial alu_pc_valid = 1'b0;
1050
        always @(posedge i_clk)
1051 65 dgisselq
                alu_pc_valid <= ((alu_ce)
1052
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
1053 2 dgisselq
 
1054 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1055 48 dgisselq
        pipemem #(AW) domem(i_clk, i_rst, mem_ce,
1056 38 dgisselq
                                (opn[0]), opB, opA, opR,
1057
                                mem_busy, mem_pipe_stalled,
1058
                                mem_valid, bus_err, mem_wreg, mem_result,
1059
                        mem_cyc_gbl, mem_cyc_lcl,
1060
                                mem_stb_gbl, mem_stb_lcl,
1061
                                mem_we, mem_addr, mem_data,
1062
                                mem_ack, mem_stall, mem_err, i_wb_data);
1063
 
1064
`else // PIPELINED_BUS_ACCESS
1065 48 dgisselq
        memops  #(AW) domem(i_clk, i_rst, mem_ce,
1066 2 dgisselq
                                (opn[0]), opB, opA, opR,
1067 38 dgisselq
                                mem_busy,
1068
                                mem_valid, bus_err, mem_wreg, mem_result,
1069 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1070
                                mem_stb_gbl, mem_stb_lcl,
1071
                                mem_we, mem_addr, mem_data,
1072
                                mem_ack, mem_stall, mem_err, i_wb_data);
1073 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1074 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1075 2 dgisselq
 
1076
        // Either the prefetch or the instruction gets the memory bus, but 
1077
        // never both.
1078 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1079 36 dgisselq
                // Memory access to the arbiter, priority position
1080
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1081
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1082 2 dgisselq
                // Prefetch access to the arbiter
1083 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1084
                        pf_ack, pf_stall, pf_err,
1085 2 dgisselq
                // Common wires, in and out, of the arbiter
1086 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1087
                        o_wb_we, o_wb_addr, o_wb_data,
1088
                        i_wb_ack, i_wb_stall, i_wb_err);
1089 2 dgisselq
 
1090
        //
1091
        //
1092
        //      PIPELINE STAGE #5 :: Write-back results
1093
        //
1094
        //
1095
        // This stage is not allowed to stall.  If results are ready to be
1096
        // written back, they are written back at all cost.  Sleepy CPU's
1097
        // won't prevent write back, nor debug modes, halting the CPU, nor
1098
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1099
        // as knowinig something is available for writeback.
1100
 
1101
        //
1102
        // Write back to our generic register set ...
1103
        // When shall we write back?  On one of two conditions
1104
        //      Note that the flags needed to be checked before issuing the
1105
        //      bus instruction, so they don't need to be checked here.
1106
        //      Further, alu_wr includes (set_cond), so we don't need to
1107
        //      check for that here either.
1108 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1109 65 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid);
1110 36 dgisselq
`else
1111 65 dgisselq
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid);
1112 36 dgisselq
`endif
1113 2 dgisselq
        // Which register shall be written?
1114 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1115
        //              One or PC, one for CC, and one for GIE match
1116 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1117 25 dgisselq
        // Are we writing to the CC register?
1118
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1119 2 dgisselq
        // Are we writing to the PC?
1120
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1121
        // What value to write?
1122 65 dgisselq
        assign  wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result) :mem_result;
1123 2 dgisselq
        always @(posedge i_clk)
1124
                if (wr_reg_ce)
1125
                        regset[wr_reg_id] <= wr_reg_vl;
1126
 
1127
        //
1128
        // Write back to the condition codes/flags register ...
1129
        // When shall we write to our flags register?  alF_wr already
1130
        // includes the set condition ...
1131 65 dgisselq
        assign  wr_flags_ce = (alF_wr)&&(~clear_pipeline)&&(~alu_illegal);
1132 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1133 65 dgisselq
        assign  w_uflags = { ubus_err_flag, trap, ill_err_u,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1134
        assign  w_iflags = { ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1135 36 dgisselq
`else
1136 65 dgisselq
        assign  w_uflags = { ubus_err_flag, trap, ill_err_u,     1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1137
        assign  w_iflags = { ibus_err_flag, trap, ill_err_i, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1138 36 dgisselq
`endif
1139 2 dgisselq
        // What value to write?
1140
        always @(posedge i_clk)
1141
                // If explicitly writing the register itself
1142 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1143 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1144
                // Otherwise if we're setting the flags from an ALU operation
1145
                else if ((wr_flags_ce)&&(alu_gie))
1146
                        flags <= alu_flags;
1147
 
1148
        always @(posedge i_clk)
1149 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1150 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1151
                else if ((wr_flags_ce)&&(~alu_gie))
1152
                        iflags <= alu_flags;
1153
 
1154
        // The 'break' enable  bit.  This bit can only be set from supervisor
1155
        // mode.  It control what the CPU does upon encountering a break
1156
        // instruction.
1157
        //
1158
        // The goal, upon encountering a break is that the CPU should stop and
1159
        // not execute the break instruction, choosing instead to enter into
1160
        // either interrupt mode or halt first.  
1161
        //      if ((break_en) AND (break_instruction)) // user mode or not
1162
        //              HALT CPU
1163
        //      else if (break_instruction) // only in user mode
1164
        //              set an interrupt flag, go to supervisor mode
1165
        //              allow supervisor to step the CPU.
1166
        //      Upon a CPU halt, any break condition will be reset.  The
1167
        //      external debugger will then need to deal with whatever
1168
        //      condition has taken place.
1169
        initial break_en = 1'b0;
1170
        always @(posedge i_clk)
1171
                if ((i_rst)||(i_halt))
1172
                        break_en <= 1'b0;
1173 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1174 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1175 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1176 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1177
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1178
                                &&(~clear_pipeline)
1179
                        ||((~alu_gie)&&(bus_err))
1180
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
1181
`else
1182
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1183
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1184
                                &&(~clear_pipeline))
1185 38 dgisselq
                        ||((~alu_gie)&&(bus_err));
1186 36 dgisselq
`endif
1187 2 dgisselq
 
1188
 
1189
        // The sleep register.  Setting the sleep register causes the CPU to
1190
        // sleep until the next interrupt.  Setting the sleep register within
1191
        // interrupt mode causes the processor to halt until a reset.  This is
1192 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1193
        // set the sleep bit and switch to supervisor mode in the same 
1194
        // instruction: users are not allowed to halt the CPU.
1195 2 dgisselq
        always @(posedge i_clk)
1196
                if ((i_rst)||((i_interrupt)&&(gie)))
1197
                        sleep <= 1'b0;
1198 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1199
                        // In supervisor mode, we have no protections.  The
1200
                        // supervisor can set the sleep bit however he wants.
1201 2 dgisselq
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1202 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1203
                        // In user mode, however, you can only set the sleep
1204
                        // mode while remaining in user mode.  You can't switch
1205
                        // to sleep mode *and* supervisor mode at the same
1206
                        // time, lest you halt the CPU.
1207
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1208 2 dgisselq
 
1209
        always @(posedge i_clk)
1210
                if ((i_rst)||(w_switch_to_interrupt))
1211
                        step <= 1'b0;
1212 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1213 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1214 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1215 2 dgisselq
                        step <= 1'b0;
1216
 
1217
        // The GIE register.  Only interrupts can disable the interrupt register
1218
        assign  w_switch_to_interrupt = (gie)&&(
1219
                        // On interrupt (obviously)
1220
                        (i_interrupt)
1221
                        // If we are stepping the CPU
1222 38 dgisselq
                        ||((alu_pc_valid)&&(step))
1223 2 dgisselq
                        // If we encounter a break instruction, if the break
1224 36 dgisselq
                        //      enable isn't set.
1225 38 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
1226
`ifdef  OPT_ILLEGAL_INSTRUCTION
1227 36 dgisselq
                        // On an illegal instruction
1228
                        ||((alu_valid)&&(alu_illegal))
1229
`endif
1230 2 dgisselq
                        // If we write to the CC register
1231
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1232 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1233 2 dgisselq
                        );
1234
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1235
                        // Then if we write the CC register
1236
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1237 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1238 2 dgisselq
                        );
1239
        always @(posedge i_clk)
1240
                if (i_rst)
1241
                        gie <= 1'b0;
1242
                else if (w_switch_to_interrupt)
1243
                        gie <= 1'b0;
1244
                else if (w_release_from_interrupt)
1245
                        gie <= 1'b1;
1246
 
1247 25 dgisselq
        initial trap = 1'b0;
1248
        always @(posedge i_clk)
1249
                if (i_rst)
1250
                        trap <= 1'b0;
1251
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1252
                                &&(wr_reg_id[4])&&(wr_write_cc))
1253
                        trap <= 1'b1;
1254 65 dgisselq
                // else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
1255
                                // &&(~i_dbg_data[`CPU_GIE_BIT]))
1256
                        // trap <= i_dbg_data[`CPU_TRAP_BIT];
1257 25 dgisselq
                else if (w_release_from_interrupt)
1258
                        trap <= 1'b0;
1259
 
1260 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1261 65 dgisselq
        initial ill_err_i = 1'b0;
1262 36 dgisselq
        always @(posedge i_clk)
1263
                if (i_rst)
1264 65 dgisselq
                        ill_err_i <= 1'b0;
1265
                // The debug interface can clear this bit
1266
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1267
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
1268
                        ill_err_i <= 1'b0;
1269
                else if ((alu_valid)&&(alu_illegal)&&(~alu_gie))
1270
                        ill_err_i <= 1'b1;
1271
        initial ill_err_u = 1'b0;
1272
        always @(posedge i_clk)
1273
                if (i_rst)
1274
                        ill_err_u <= 1'b0;
1275
                // The bit is automatically cleared on release from interrupt
1276 36 dgisselq
                else if (w_release_from_interrupt)
1277 65 dgisselq
                        ill_err_u <= 1'b0;
1278
                // If the supervisor writes to this register, clearing the
1279
                // bit, then clear it
1280
                else if (((~alu_gie)||(dbgv))
1281
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
1282
                                &&(wr_reg_id[4])&&(wr_write_cc))
1283
                        ill_err_u <= 1'b0;
1284 36 dgisselq
                else if ((alu_valid)&&(alu_illegal)&&(gie))
1285 65 dgisselq
                        ill_err_u <= 1'b1;
1286 38 dgisselq
`else
1287 65 dgisselq
        assign ill_err_u = 1'b0;
1288
        assign ill_err_i = 1'b0;
1289 36 dgisselq
`endif
1290 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1291
        // ever set.
1292
        initial ibus_err_flag = 1'b0;
1293 36 dgisselq
        always @(posedge i_clk)
1294
                if (i_rst)
1295 65 dgisselq
                        ibus_err_flag <= 1'b0;
1296
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1297
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
1298
                        ibus_err_flag <= 1'b0;
1299
                else if ((bus_err)&&(~alu_gie))
1300
                        ibus_err_flag <= 1'b1;
1301
        // User bus error flag -- if ever set, it will cause an interrupt to
1302
        // supervisor mode.  
1303
        initial ubus_err_flag = 1'b0;
1304
        always @(posedge i_clk)
1305
                if (i_rst)
1306
                        ubus_err_flag <= 1'b0;
1307 36 dgisselq
                else if (w_release_from_interrupt)
1308 65 dgisselq
                        ubus_err_flag <= 1'b0;
1309
                // else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4])
1310
                                // &&(i_dbg_reg == {1'b1, `CPU_CC_REG})
1311
                                // &&(~i_dbg_data[`CPU_BUSERR_BIT]))
1312
                        // ubus_err_flag <= 1'b0;
1313
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1314
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
1315
                                &&(wr_reg_id[4])&&(wr_write_cc))
1316
                        ubus_err_flag <= 1'b0;
1317 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1318 65 dgisselq
                        ubus_err_flag <= 1'b1;
1319 36 dgisselq
 
1320 2 dgisselq
        //
1321
        // Write backs to the PC register, and general increments of it
1322
        //      We support two: upc and ipc.  If the instruction is normal,
1323
        // we increment upc, if interrupt level we increment ipc.  If
1324
        // the instruction writes the PC, we write whichever PC is appropriate.
1325
        //
1326
        // Do we need to all our partial results from the pipeline?
1327
        // What happens when the pipeline has gie and ~gie instructions within
1328
        // it?  Do we clear both?  What if a gie instruction tries to clear
1329
        // a non-gie instruction?
1330
        always @(posedge i_clk)
1331 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1332 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1333 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1334 2 dgisselq
                        upc <= alu_pc;
1335
 
1336
        always @(posedge i_clk)
1337
                if (i_rst)
1338
                        ipc <= RESET_ADDRESS;
1339
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1340 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1341 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1342 2 dgisselq
                        ipc <= alu_pc;
1343
 
1344
        always @(posedge i_clk)
1345
                if (i_rst)
1346
                        pf_pc <= RESET_ADDRESS;
1347
                else if (w_switch_to_interrupt)
1348
                        pf_pc <= ipc;
1349
                else if (w_release_from_interrupt)
1350
                        pf_pc <= upc;
1351
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1352 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1353 2 dgisselq
                else if (dcd_ce)
1354 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1355 2 dgisselq
 
1356
        initial new_pc = 1'b1;
1357
        always @(posedge i_clk)
1358 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1359 2 dgisselq
                        new_pc <= 1'b1;
1360
                else if (w_switch_to_interrupt)
1361
                        new_pc <= 1'b1;
1362
                else if (w_release_from_interrupt)
1363
                        new_pc <= 1'b1;
1364
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1365
                        new_pc <= 1'b1;
1366
                else
1367
                        new_pc <= 1'b0;
1368
 
1369
        //
1370
        // The debug interface
1371 56 dgisselq
        generate
1372
        if (AW<32)
1373
        begin
1374
                always @(posedge i_clk)
1375 2 dgisselq
                begin
1376
                        o_dbg_reg <= regset[i_dbg_reg];
1377
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1378 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1379 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1380 56 dgisselq
                        begin
1381 36 dgisselq
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1382 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1383
                        end
1384 2 dgisselq
                end
1385 56 dgisselq
        end else begin
1386
                always @(posedge i_clk)
1387
                begin
1388
                        o_dbg_reg <= regset[i_dbg_reg];
1389
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1390
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1391
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1392
                        begin
1393
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1394
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1395
                        end
1396
                end
1397
        end endgenerate
1398
 
1399 2 dgisselq
        always @(posedge i_clk)
1400 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1401 18 dgisselq
 
1402
        always @(posedge i_clk)
1403 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1404 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1405 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1406 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1407 2 dgisselq
 
1408
        //
1409
        //
1410
        // Produce accounting outputs: Account for any CPU stalls, so we can
1411
        // later evaluate how well we are doing.
1412
        //
1413
        //
1414 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
1415
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1416 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1417 56 dgisselq
 
1418 65 dgisselq
`ifdef  DEBUG_SCOPE
1419 56 dgisselq
        always @(posedge i_clk)
1420 65 dgisselq
                o_debug <= {
1421 56 dgisselq
                        pf_pc[7:0],
1422
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1423
                        op_ce, alu_ce, mem_ce,
1424 65 dgisselq
                        //
1425
                        master_ce, opvalid_alu, opvalid_mem,
1426
                        //
1427
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1428
                        mem_we,
1429
                        // ((opvalid_alu)&&(alu_stall))
1430
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1431
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1432
                        // opA[23:20], opA[3:0],
1433
                        gie, sleep,
1434
                        wr_reg_vl[5:0]
1435 56 dgisselq
                        };
1436 65 dgisselq
`endif
1437 56 dgisselq
 
1438 2 dgisselq
endmodule

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