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///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, there are only 16 instruction types supported.
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory. 
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//
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//              2. Instruction Decode
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//
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//              3. Read Operands
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//
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//              4. Apply Instruction
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//
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//              4. Write-back Results
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//
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//      Further information about the inner workings of this CPU may be
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//      found in the spec.pdf file.  (The documentation within this file
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//      had become out of date and out of sync with the spec.pdf, so look
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//      to the spec.pdf for accurate and up to date information.)
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//
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//
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//      In general, the pipelining is controlled by three pieces of logic
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//      per stage: _ce, _stall, and _valid.  _valid means that the stage
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//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
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//      The difference between these control signals allows individual stages
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//      to propagate instructions independently.  In general, the logic works
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//      as:
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//
44
//
45
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
46
//
47
//
48
//      always @(posedge i_clk)
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//              if ((i_rst)||(clear_pipeline))
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//                      (n)_valid = 0
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//              else if (n)_ce
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//                      (n)_valid = 1
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//              else if (n+1)_ce
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//                      (n)_valid = 0
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//
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//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
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//                      || (  (n)_valid && (n+1)_stall );
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//
59
//      and ...
60
//
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//      always @(posedge i_clk)
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//              if (n)_ce
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//                      (n)_variable = ... whatever logic for this stage
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//
65
//      Note that a stage can stall even if no instruction is loaded into
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//      it.
67
//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
89
//
90
///////////////////////////////////////////////////////////////////////////////
91
//
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// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
93
// fetches are more complicated and therefore use more FPGA resources, while
94
// single fetches will cause the CPU to stall for about 5 stalls each 
95
// instruction cycle, effectively reducing the instruction count per clock to
96
// about 0.2.  However, the area cost may be worth it.  Consider:
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//
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//      Slice LUTs              ZipSystem       ZipCPU
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//      Single Fetching         2521            1734
100
//      Pipelined fetching      2796            2046
101
//
102
//
103
//
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`define CPU_CC_REG      4'he
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`define CPU_PC_REG      4'hf
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`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
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`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
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// Compile time defines
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//
117
`include "cpudefs.v"
118
//
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//
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module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
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                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
125
                // CPU interface to the wishbone bus
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                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
128
                        o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_data,
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                        i_wb_err,
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                // Accounting/CPU usage interface
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                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
137 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
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                        LGICACHE=6;
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`ifdef  OPT_MULTIPLY
140
        parameter       IMPLEMENT_MPY = 1;
141
`else
142
        parameter       IMPLEMENT_MPY = 0;
143
`endif
144 69 dgisselq
        parameter       IMPLEMENT_DIVIDE = 1, IMPLEMENT_FPU = 0,
145
                        IMPLEMENT_LOCK=1;
146
`ifdef  OPT_EARLY_BRANCHING
147
        parameter       EARLY_BRANCHING = 1;
148
`else
149
        parameter       EARLY_BRANCHING = 0;
150
`endif
151
        parameter       AW=ADDRESS_WIDTH;
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        input                   i_clk, i_rst, i_interrupt;
153
        // Debug interface -- inputs
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        input                   i_halt, i_clear_pf_cache;
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        input           [4:0]    i_dbg_reg;
156
        input                   i_dbg_we;
157
        input           [31:0]   i_dbg_data;
158
        // Debug interface -- outputs
159
        output  reg             o_dbg_stall;
160
        output  reg     [31:0]   o_dbg_reg;
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        output  reg     [3:0]    o_dbg_cc;
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        output  wire            o_break;
163
        // Wishbone interface -- outputs
164 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
165
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
166 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
167
        output  wire    [31:0]   o_wb_data;
168 2 dgisselq
        // Wishbone interface -- inputs
169
        input                   i_wb_ack, i_wb_stall;
170
        input           [31:0]   i_wb_data;
171 36 dgisselq
        input                   i_wb_err;
172 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
173 9 dgisselq
        output  wire            o_op_stall;
174 2 dgisselq
        output  wire            o_pf_stall;
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        output  wire            o_i_count;
176 56 dgisselq
        //
177 65 dgisselq
`ifdef  DEBUG_SCOPE
178 56 dgisselq
        output  reg     [31:0]   o_debug;
179 65 dgisselq
`endif
180 2 dgisselq
 
181 25 dgisselq
 
182 2 dgisselq
        // Registers
183 56 dgisselq
        //
184
        //      The distributed RAM style comment is necessary on the
185
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
186
        // set and in the process ruining everything else.  It basically
187
        // optimizes logic away, to where it no longer works.  The logic
188
        // as described herein will work, this just makes sure XST implements
189
        // that logic.
190
        //
191
        (* ram_style = "distributed" *)
192 2 dgisselq
        reg     [31:0]   regset [0:31];
193 9 dgisselq
 
194
        // Condition codes
195 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
196
        reg     [3:0]    flags, iflags;
197 69 dgisselq
        wire    [12:0]   w_uflags, w_iflags;
198 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
199 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
200 65 dgisselq
        reg             ill_err_u, ill_err_i;
201 38 dgisselq
`else
202 65 dgisselq
        wire            ill_err_u, ill_err_i;
203 36 dgisselq
`endif
204 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
205 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
206
        wire            ifpu_err_flag, ufpu_err_flag;
207
        wire            ihalt_phase, uhalt_phase;
208 2 dgisselq
 
209 9 dgisselq
        // The master chip enable
210
        wire            master_ce;
211 2 dgisselq
 
212
        //
213
        //
214
        //      PIPELINE STAGE #1 :: Prefetch
215
        //              Variable declarations
216
        //
217 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
218 69 dgisselq
        reg     new_pc;
219 18 dgisselq
        wire    clear_pipeline;
220 69 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
221 9 dgisselq
 
222
        wire            dcd_stalled;
223 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
224 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
225
        wire    [31:0]           pf_data;
226
        wire    [31:0]           instruction;
227
        wire    [(AW-1):0]       instruction_pc;
228 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
229 2 dgisselq
 
230
        //
231
        //
232
        //      PIPELINE STAGE #2 :: Instruction Decode
233
        //              Variable declarations
234
        //
235
        //
236 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
237 69 dgisselq
        reg             opvalid_div, opvalid_fpu;
238
        wire            op_stall, dcd_ce, dcd_phase;
239
        wire    [3:0]    dcdOp;
240
        wire    [4:0]    dcdA, dcdB, dcdR;
241
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
242
        wire    [3:0]    dcdF;
243
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
244
                                dcdALU, dcdM, dcdDV, dcdFP,
245
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock;
246
        reg             r_dcdvalid;
247
        wire            dcdvalid;
248
        wire    [(AW-1):0]       dcd_pc;
249
        wire    [31:0]   dcdI;
250
        wire            dcd_zI; // true if dcdI == 0
251 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
252
 
253 69 dgisselq
        wire    dcd_illegal;
254
        wire                    dcd_early_branch;
255 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
256 2 dgisselq
 
257
 
258
        //
259
        //
260
        //      PIPELINE STAGE #3 :: Read Operands
261
        //              Variable declarations
262
        //
263
        //
264
        //
265
        // Now, let's read our operands
266
        reg     [4:0]    alu_reg;
267
        reg     [3:0]    opn;
268
        reg     [4:0]    opR;
269 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
270
        reg     [(AW-1):0]       op_pc;
271 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
272 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
273 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
274 69 dgisselq
        wire    [12:0]   opFl;
275 56 dgisselq
        reg     [5:0]    r_opF;
276
        wire    [7:0]    opF;
277
        reg     [2:0]    opF_cp;
278 69 dgisselq
        wire            op_ce, op_phase;
279 56 dgisselq
        // Some pipeline control wires
280 69 dgisselq
`ifdef  OPT_PIPELINED
281 56 dgisselq
        reg     opA_alu, opA_mem;
282
        reg     opB_alu, opB_mem;
283
`endif
284 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
285 36 dgisselq
        reg     op_illegal;
286
`endif
287 69 dgisselq
        reg     op_break;
288
        wire    op_lock;
289 2 dgisselq
 
290
 
291
        //
292
        //
293
        //      PIPELINE STAGE #4 :: ALU / Memory
294
        //              Variable declarations
295
        //
296
        //
297 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
298 69 dgisselq
        reg             alu_pc_valid;
299
        wire            alu_phase;
300 2 dgisselq
        wire            alu_ce, alu_stall;
301
        wire    [31:0]   alu_result;
302
        wire    [3:0]    alu_flags;
303
        wire            alu_valid;
304
        wire            set_cond;
305
        reg             alu_wr, alF_wr, alu_gie;
306 56 dgisselq
        wire            alu_illegal_op;
307 38 dgisselq
        wire            alu_illegal;
308 2 dgisselq
 
309
 
310
 
311
        wire    mem_ce, mem_stalled;
312 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
313
        wire    mem_pipe_stalled;
314
`endif
315 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
316
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
317 48 dgisselq
        wire    [4:0]            mem_wreg;
318 9 dgisselq
 
319 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
320
        wire    [(AW-1):0]       mem_addr;
321
        wire    [31:0]           mem_data, mem_result;
322
        reg     [4:0]            mem_last_reg; // Last register result to go in
323 2 dgisselq
 
324 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
325
        wire    [31:0]   div_result;
326
        wire    [3:0]    div_flags;
327 2 dgisselq
 
328 69 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
329
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
330
                                &&(set_cond);
331 2 dgisselq
 
332 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
333
        wire    [31:0]   fpu_result;
334
        wire    [3:0]    fpu_flags;
335
 
336
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
337
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
338
                                &&(set_cond);
339
 
340
 
341 2 dgisselq
        //
342
        //
343
        //      PIPELINE STAGE #5 :: Write-back
344
        //              Variable declarations
345
        //
346 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
347 2 dgisselq
        wire    [4:0]    wr_reg_id;
348
        wire    [31:0]   wr_reg_vl;
349
        wire    w_switch_to_interrupt, w_release_from_interrupt;
350 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
351 2 dgisselq
 
352
 
353
 
354
        //
355
        //      MASTER: clock enable.
356
        //
357 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
358 2 dgisselq
 
359
 
360
        //
361
        //      PIPELINE STAGE #1 :: Prefetch
362
        //              Calculate stall conditions
363 65 dgisselq
        //
364
        //      These are calculated externally, within the prefetch module.
365
        //
366 2 dgisselq
 
367
        //
368
        //      PIPELINE STAGE #2 :: Instruction Decode
369
        //              Calculate stall conditions
370 69 dgisselq
`ifdef  OPT_PIPELINED
371
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
372
`else
373
        assign          dcd_ce = 1'b1;
374
`endif
375
`ifdef  OPT_PIPELINED
376
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
377
`else
378
        // If not pipelined, there will be no opvalid_ anything, and the
379
        // op_stall will be false, dcdX_stall will be false, thus we can simply
380
        // do a ...
381
        assign          dcd_stalled = 1'b0;
382
`endif
383 2 dgisselq
        //
384
        //      PIPELINE STAGE #3 :: Read Operands
385
        //              Calculate stall conditions
386 69 dgisselq
        wire    op_lock_stall;
387
`ifdef  OPT_PIPELINED
388
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
389
                        // Stall if we're stopped, and not allowed to execute
390
                        // an instruction
391
                        // (~master_ce)         // Already captured in alu_stall
392
                        //
393 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
394
                        //      i.e. if the memory is busy, or we are single
395 69 dgisselq
                        //      stepping.  This also includes our stalls for
396
                        //      op_break and op_lock, so we don't need to
397
                        //      include those as well here.
398
                        ((opvalid)&&(alu_stall))
399
                        // Stall if the divide is busy, since we can't have
400
                        // two parallel stages writing back at the same time
401
                        ||(div_busy)
402
                        // Same for the floating point unit
403
                        ||(fpu_busy)
404 56 dgisselq
                        //
405
                        // ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
406
                        // Stall if we are going into memory with an operation
407
                        //      that cannot be pipelined, and the memory is
408
                        //      already busy
409 69 dgisselq
                        ||((opvalid_mem)&&(mem_stalled))
410
                        )
411
                        ||(dcdvalid)&&(
412
                                // Stall if we've got a read going with an
413
                                // unknown output (known w/in the memory module)
414
                                (mem_rdbusy)
415
                                // Or if we need to wait for an operand A
416
                                // to be ready to read
417
                                ||(dcdA_stall)
418
                                // Likewise for B, also includes logic
419
                                // regarding immediate offset (register must
420
                                // be in register file if we need to add to
421
                                // an immediate)
422
                                ||(dcdB_stall)
423
                                // Or if we need to wait on flags to work on the
424
                                // CC register
425
                                ||(dcdF_stall)
426
                        );
427
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall))&&(~clear_pipeline);
428 65 dgisselq
`else
429 69 dgisselq
        assign  op_stall = (opvalid)&&(~master_ce);
430
        assign  op_ce = (dcdvalid);
431 65 dgisselq
`endif
432 2 dgisselq
 
433
        //
434
        //      PIPELINE STAGE #4 :: ALU / Memory
435
        //              Calculate stall conditions
436 36 dgisselq
        //
437
        // 1. Basic stall is if the previous stage is valid and the next is
438
        //      busy.  
439
        // 2. Also stall if the prior stage is valid and the master clock enable
440
        //      is de-selected
441 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
442
        //      since we don't know if it'll put us to sleep or not.
443 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
444
        //      through the ALU.  Break instructions are not allowed through
445
        //      the ALU.
446 69 dgisselq
`ifdef  OPT_PIPELINED
447 36 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
448 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
449
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
450
                                &&(wr_write_cc)) // Case 3
451 69 dgisselq
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
452
                        ||((opvalid)&&(op_break))
453
                        ||(div_busy)||(fpu_busy);
454
        assign  alu_ce = (master_ce)&&(opvalid_alu)
455
                                &&(~alu_stall)
456
                                &&(~clear_pipeline);
457
`else
458
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
459
                                ||((opvalid_alu)&&(op_break));
460
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall);
461
`endif
462 2 dgisselq
        //
463 65 dgisselq
 
464
        //
465
        // Note: if you change the conditions for mem_ce, you must also change
466
        // alu_pc_valid.
467
        //
468 69 dgisselq
`ifdef  OPT_PIPELINED
469
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
470
                        &&(~clear_pipeline)&&(set_cond);
471
`else
472
        // If we aren't pipelined, then no one will be changing what's in the
473
        // pipeline (i.e. clear_pipeline), while our only instruction goes
474
        // through the ... pipeline.
475
        assign  mem_ce = (master_ce)&&(opvalid_mem)
476 38 dgisselq
                        &&(set_cond)&&(~mem_stalled);
477 69 dgisselq
`endif
478 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
479 38 dgisselq
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
480
                                (mem_pipe_stalled)
481
                                ||((~op_pipe)&&(mem_busy))
482 69 dgisselq
                                ||(div_busy)
483
                                ||(fpu_busy)
484 38 dgisselq
                                // Stall waiting for flags to be valid
485
                                // Or waiting for a write to the PC register
486
                                // Or CC register, since that can change the
487
                                //  PC as well
488
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
489
                                        &&((wr_write_pc)||(wr_write_cc)))));
490
`else
491 69 dgisselq
`ifdef  OPT_PIPELINED
492 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
493 2 dgisselq
                                (~master_ce)
494
                                // Stall waiting for flags to be valid
495
                                // Or waiting for a write to the PC register
496 25 dgisselq
                                // Or CC register, since that can change the
497
                                //  PC as well
498
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
499 69 dgisselq
`else
500
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
501 38 dgisselq
`endif
502 69 dgisselq
`endif
503 2 dgisselq
 
504
 
505
        //
506
        //
507
        //      PIPELINE STAGE #1 :: Prefetch
508
        //
509
        //
510 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
511 9 dgisselq
        wire            pf_ce;
512
 
513 69 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
514 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
515 69 dgisselq
                        pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
516 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
517 36 dgisselq
                                        pf_valid, pf_illegal,
518
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
519
                                pf_ack, pf_stall, pf_err, i_wb_data);
520 69 dgisselq
 
521
        initial r_dcdvalid = 1'b0;
522
        always @(posedge i_clk)
523
                if (i_rst)
524
                        r_dcdvalid <= 1'b0;
525
                else if (dcd_ce)
526
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
527
                else if ((op_ce)||(clear_pipeline))
528
                        r_dcdvalid <= 1'b0;
529
        assign  dcdvalid = r_dcdvalid;
530
 
531 2 dgisselq
`else // Pipe fetch
532 69 dgisselq
 
533
`ifdef  OPT_TRADITIONAL_PFCACHE
534
        pfcache #(LGICACHE, ADDRESS_WIDTH)
535
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
536
                                        i_clear_pf_cache,
537
                                // dcd_pc,
538
                                ~dcd_stalled,
539
                                ((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
540
                                        ? dcd_branch_pc:pf_pc,
541
                                instruction, instruction_pc, pf_valid,
542
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
543
                                        pf_ack, pf_stall, pf_err, i_wb_data,
544
                                pf_illegal);
545
`else
546 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
547 69 dgisselq
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
548 36 dgisselq
                                        i_clear_pf_cache, ~dcd_stalled,
549
                                        (new_pc)?pf_pc:dcd_branch_pc,
550 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
551
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
552 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
553 69 dgisselq
//`ifdef        OPT_PRECLEAR_BUS
554
                                //((dcd_clear_bus)&&(dcdvalid))
555
                                //||((op_clear_bus)&&(opvalid))
556
                                //||
557
//`endif
558 36 dgisselq
                                (mem_cyc_lcl)||(mem_cyc_gbl),
559
                                pf_illegal);
560 69 dgisselq
`endif
561 2 dgisselq
        assign  instruction_gie = gie;
562
 
563 69 dgisselq
        initial r_dcdvalid = 1'b0;
564 2 dgisselq
        always @(posedge i_clk)
565 69 dgisselq
                if ((i_rst)||(clear_pipeline))
566
                        r_dcdvalid <= 1'b0;
567 2 dgisselq
                else if (dcd_ce)
568 69 dgisselq
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
569
                else if (op_ce)
570
                        r_dcdvalid <= 1'b0;
571
        assign  dcdvalid = r_dcdvalid;
572 36 dgisselq
`endif
573 2 dgisselq
 
574 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
575
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
576
                        IMPLEMENT_FPU)
577
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
578
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
579
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
580
                        dcd_illegal, dcd_pc, dcd_gie,
581
                        { dcdR_cc, dcdR_pc, dcdR },
582
                        { dcdA_cc, dcdA_pc, dcdA },
583
                        { dcdB_cc, dcdB_pc, dcdB },
584
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
585
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
586
                        dcdR_wr,dcdA_rd, dcdB_rd,
587
                        dcd_early_branch,
588
                        dcd_branch_pc);
589 36 dgisselq
`else
590 69 dgisselq
        idecode_deprecated
591
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
592
                        IMPLEMENT_FPU)
593
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
594
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
595
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
596
                        dcd_illegal, dcd_pc, dcd_gie,
597
                        { dcdR_cc, dcdR_pc, dcdR },
598
                        { dcdA_cc, dcdA_pc, dcdA },
599
                        { dcdB_cc, dcdB_pc, dcdB },
600
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
601
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
602
                        dcdR_wr,dcdA_rd, dcdB_rd,
603
                        dcd_early_branch,
604
                        dcd_branch_pc);
605 36 dgisselq
`endif
606 2 dgisselq
 
607 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
608
        reg     [23:0]   r_opI;
609
        reg     [4:0]    op_B;
610
        reg             op_pipe;
611 2 dgisselq
 
612 38 dgisselq
        initial op_pipe = 1'b0;
613
        // To be a pipeable operation, there must be 
614
        //      two valid adjacent instructions
615
        //      Both must be memory instructions
616
        //      Both must be writes, or both must be reads
617
        //      Both operations must be to the same identical address,
618
        //              or at least a single (one) increment above that address
619
        always @(posedge i_clk)
620
                if (op_ce)
621
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
622
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
623
                                &&(dcdB == op_B) // Same address register
624 65 dgisselq
                                &&((dcdF[2:0] == opF_cp) // Same condition
625
                                        ||(opF_cp == 3'h0)) // or no prev condition
626 69 dgisselq
                                &&((dcdI[23:0] == r_opI)||(dcdI[23:0]==r_opI+24'h1));
627 38 dgisselq
        always @(posedge i_clk)
628
                if (op_ce) // &&(dcdvalid))
629 69 dgisselq
                        r_opI <= dcdI[23:0];
630 38 dgisselq
        always @(posedge i_clk)
631
                if (op_ce) // &&(dcdvalid))
632
                        op_B <= dcdB;
633
`endif
634
 
635 2 dgisselq
        //
636
        //
637
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
638
        //
639
        //
640 25 dgisselq
        assign  w_opA = regset[dcdA];
641
        assign  w_opB = regset[dcdB];
642 56 dgisselq
 
643
        wire    [31:0]   w_pcA_v;
644
        generate
645
        if (AW < 32)
646
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
647
        else
648
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
649
        endgenerate
650 2 dgisselq
        always @(posedge i_clk)
651
                if (op_ce) // &&(dcdvalid))
652
                begin
653
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
654
                                r_opA <= wr_reg_vl;
655 25 dgisselq
                        else if (dcdA_pc)
656 56 dgisselq
                                r_opA <= w_pcA_v;
657 25 dgisselq
                        else if (dcdA_cc)
658 69 dgisselq
                                r_opA <= { w_opA[31:13], (dcdA[4])?w_uflags:w_iflags };
659 2 dgisselq
                        else
660 25 dgisselq
                                r_opA <= w_opA;
661 69 dgisselq
`ifdef  OPT_PIPELINED
662 48 dgisselq
                end else if (opvalid)
663
                begin // We were going to pick these up when they became valid,
664
                        // but for some reason we're stuck here as they became
665
                        // valid.  Pick them up now anyway
666 65 dgisselq
                        if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
667 48 dgisselq
                                r_opA <= wr_reg_vl;
668 56 dgisselq
`endif
669 2 dgisselq
                end
670 56 dgisselq
 
671 69 dgisselq
        wire    [31:0]   w_opBnI, w_pcB_v;
672 56 dgisselq
        generate
673
        if (AW < 32)
674
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
675
        else
676
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
677
        endgenerate
678
 
679 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
680 56 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
681
                : ((dcdB_pc) ? w_pcB_v
682 69 dgisselq
                : ((dcdB_cc) ? { w_opB[31:13], (dcdB[4])?w_uflags:w_iflags}
683 56 dgisselq
                : w_opB)));
684
 
685 2 dgisselq
        always @(posedge i_clk)
686
                if (op_ce) // &&(dcdvalid))
687 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
688 69 dgisselq
`ifdef  OPT_PIPELINED
689 56 dgisselq
                else if ((opvalid)&&(
690 65 dgisselq
                                ((opB_alu)&&(alu_wr))
691 56 dgisselq
                                ||((opB_mem)&&(mem_valid))))
692 48 dgisselq
                        r_opB <= wr_reg_vl;
693 56 dgisselq
`endif
694 2 dgisselq
 
695
        // The logic here has become more complex than it should be, no thanks
696
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
697
        // be two sets of four bits: the top bits specify what bits matter, the
698
        // bottom specify what those top bits must equal.  However, two of
699
        // conditions check whether bits are on, and those are the only two
700
        // conditions checking those bits.  Therefore, Vivado complains that
701
        // these two bits are redundant.  Hence the convoluted expression
702
        // below, arriving at what we finally want in the (now wire net)
703
        // opF.
704
        always @(posedge i_clk)
705
                if (op_ce)
706 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
707 2 dgisselq
                        case(dcdF[2:0])
708 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
709 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
710
                        // These were remapped as part of the new instruction
711
                        // set in order to make certain that the low order
712
                        // two bits contained the most commonly used 
713
                        // conditions: Always, LT, Z, and NZ.
714
                        3'h1:   r_opF <= 6'h24; // LT
715
                        3'h2:   r_opF <= 6'h11; // Z
716
                        3'h3:   r_opF <= 6'h10; // NE
717
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
718
                        3'h5:   r_opF <= 6'h20; // GE (!N)
719
`else
720 56 dgisselq
                        3'h1:   r_opF <= 6'h11; // Z
721
                        3'h2:   r_opF <= 6'h10; // NE
722
                        3'h3:   r_opF <= 6'h20; // GE (!N)
723
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
724
                        3'h5:   r_opF <= 6'h24; // LT
725 69 dgisselq
`endif
726 56 dgisselq
                        3'h6:   r_opF <= 6'h02; // C
727
                        3'h7:   r_opF <= 6'h08; // V
728 2 dgisselq
                        endcase
729 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
730 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
731
        always @(posedge i_clk)
732
                if (op_ce)
733
                        opF_cp[2:0] <= dcdF[2:0];
734 2 dgisselq
 
735 69 dgisselq
        wire    w_opvalid;
736
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid);
737 36 dgisselq
        initial opvalid     = 1'b0;
738
        initial opvalid_alu = 1'b0;
739
        initial opvalid_mem = 1'b0;
740 2 dgisselq
        always @(posedge i_clk)
741
                if (i_rst)
742 25 dgisselq
                begin
743
                        opvalid     <= 1'b0;
744
                        opvalid_alu <= 1'b0;
745
                        opvalid_mem <= 1'b0;
746
                end else if (op_ce)
747
                begin
748 2 dgisselq
                        // Do we have a valid instruction?
749
                        //   The decoder may vote to stall one of its
750
                        //   instructions based upon something we currently
751
                        //   have in our queue.  This instruction must then
752
                        //   move forward, and get a stall cycle inserted.
753
                        //   Hence, the test on dcd_stalled here.  If we must
754
                        //   wait until our operands are valid, then we aren't
755
                        //   valid yet until then.
756 69 dgisselq
                        opvalid<= w_opvalid;
757 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
758 69 dgisselq
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
759
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
760
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
761
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
762 36 dgisselq
`else
763 69 dgisselq
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
764
                        opvalid_mem <= (dcdM)&&(w_opvalid);
765
                        opvalid_div <= (dcdDV)&&(w_opvalid);
766
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
767 36 dgisselq
`endif
768 69 dgisselq
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
769 25 dgisselq
                begin
770
                        opvalid     <= 1'b0;
771
                        opvalid_alu <= 1'b0;
772
                        opvalid_mem <= 1'b0;
773 69 dgisselq
                        opvalid_div <= 1'b0;
774
                        opvalid_fpu <= 1'b0;
775 25 dgisselq
                end
776 2 dgisselq
 
777
        // Here's part of our debug interface.  When we recognize a break
778
        // instruction, we set the op_break flag.  That'll prevent this
779
        // instruction from entering the ALU, and cause an interrupt before
780
        // this instruction.  Thus, returning to this code will cause the
781
        // break to repeat and continue upon return.  To get out of this
782
        // condition, replace the break instruction with what it is supposed
783
        // to be, step through it, and then replace it back.  In this fashion,
784
        // a debugger can step through code.
785 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
786
        initial op_break = 1'b0;
787 2 dgisselq
        always @(posedge i_clk)
788 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
789
                else if (op_ce) op_break <= (dcd_break);
790
                else if ((clear_pipeline)||(~opvalid))
791
                                op_break <= 1'b0;
792 2 dgisselq
 
793 69 dgisselq
`ifdef  OPT_PIPELINED
794
        generate
795
        if (IMPLEMENT_LOCK != 0)
796
        begin
797
                reg     r_op_lock, r_op_lock_stall;
798
 
799
                initial r_op_lock_stall = 1'b0;
800
                always @(posedge i_clk)
801
                        if (i_rst)
802
                                r_op_lock_stall <= 1'b0;
803
                        else
804
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
805
                                                ||(~dcdvalid)||(~pf_valid);
806
 
807
                assign  op_lock_stall = r_op_lock_stall;
808
 
809
                initial r_op_lock = 1'b0;
810
                always @(posedge i_clk)
811
                        if (i_rst)
812
                                r_op_lock <= 1'b0;
813
                        else if ((op_ce)&&(dcd_lock))
814
                                r_op_lock <= 1'b1;
815
                        else if ((op_ce)||(clear_pipeline))
816
                                r_op_lock <= 1'b0;
817
                assign  op_lock = r_op_lock;
818
 
819
        end else begin
820
                assign  op_lock_stall = 1'b0;
821
                assign  op_lock = 1'b0;
822
        end endgenerate
823
 
824
`else
825
        assign op_lock_stall = 1'b0;
826
        assign op_lock       = 1'b0;
827
`endif
828
 
829 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
830 2 dgisselq
        always @(posedge i_clk)
831 36 dgisselq
                if(op_ce)
832 69 dgisselq
`ifdef  OPT_PIPELINED
833
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
834
`else
835
                        op_illegal <= (dcd_illegal)||(dcd_lock);
836 36 dgisselq
`endif
837 69 dgisselq
`endif
838 36 dgisselq
 
839 69 dgisselq
        generate
840
        if (EARLY_BRANCHING > 0)
841
        begin
842
                always @(posedge i_clk)
843
                        if (op_ce)
844
                        begin
845
                                opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))&&(~dcd_early_branch);
846
                                opR_wr <= (dcdR_wr)&&(~dcd_early_branch);
847
                                op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
848
                                                &&(dcdR[4] == dcd_gie))
849
                                                &&(~dcd_early_branch);
850
                        end
851
        end else begin
852
                always @(posedge i_clk)
853
                        if (op_ce)
854
                        begin
855
                                // Will we write the flags/CC Register with
856
                                // our result?
857
                                opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr));
858
                                // Will we be writing our results into a
859
                                // register?
860
                                opR_wr <= dcdR_wr;
861
                                op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
862
                                                &&(dcdR[4] == dcd_gie));
863
                        end
864
        end endgenerate
865
 
866 36 dgisselq
        always @(posedge i_clk)
867 2 dgisselq
                if (op_ce)
868
                begin
869
                        opn    <= dcdOp;        // Which ALU operation?
870 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
871 2 dgisselq
                        // What register will these results be written into?
872 69 dgisselq
                        opR    <= dcdR;
873
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
874 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
875
                        op_gie <= dcd_gie;
876
 
877 69 dgisselq
 
878 2 dgisselq
                        //
879 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
880 2 dgisselq
                end
881
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
882
 
883 69 dgisselq
`ifdef  OPT_VLIW
884
        reg     r_op_phase;
885
        initial r_op_phase = 1'b0;
886
        always @(posedge i_clk)
887
                if ((i_rst)||(clear_pipeline))
888
                        r_op_phase <= 1'b0;
889
                else if (op_ce)
890
                        r_op_phase <= dcd_phase;
891
        assign  op_phase = r_op_phase;
892
`else
893
        assign  op_phase = 1'b0;
894
`endif
895
 
896 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
897
        // register set but in special registers of their own.  So step one
898
        // is to select the right register.  Step to is to replace that
899
        // register with the results of an ALU or memory operation, if such
900
        // results are now available.  Otherwise, we'd need to insert a wait
901
        // state of some type.
902
        //
903
        // The alternative approach would be to define some sort of
904
        // op_stall wire, which would stall any upstream stage.
905
        // We'll create a flag here to start our coordination.  Once we
906
        // define this flag to something other than just plain zero, then
907
        // the stalls will already be in place.
908 69 dgisselq
`ifdef  OPT_PIPELINED
909 56 dgisselq
        initial opA_alu = 1'b0;
910 25 dgisselq
        always @(posedge i_clk)
911
                if (op_ce)
912 48 dgisselq
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(opR_wr)&&(dcdA_rd);
913
                else if ((opvalid)&&(opA_alu)&&(alu_valid))
914
                        opA_alu <= 1'b0;
915 56 dgisselq
        initial opA_mem = 1'b0;
916 48 dgisselq
        always @(posedge i_clk)
917
                if (op_ce)
918 56 dgisselq
                        opA_mem <= ((opvalid_mem)&&(opR == dcdA)&&(dcdA_rd)&&(~opn[0]))
919 48 dgisselq
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
920
                                        &&(mem_last_reg == dcdA)&&(dcdA_rd));
921
                else if ((opvalid)&&(opA_mem)&&(mem_valid))
922
                        opA_mem <= 1'b0;
923 56 dgisselq
`endif
924 25 dgisselq
 
925 48 dgisselq
        always @(posedge i_clk)
926
                if (mem_ce)
927
                        mem_last_reg <= opR;
928 69 dgisselq
`ifdef  OPT_PIPELINED
929 65 dgisselq
        assign  opA = ((opA_alu)&&(alu_wr)) ? alu_result
930 48 dgisselq
                        : ( ((opA_mem)&&(mem_valid))?mem_result
931
                        : r_opA );
932 56 dgisselq
`else
933
        assign  opA = r_opA;
934
`endif
935 48 dgisselq
 
936 69 dgisselq
`ifdef  OPT_PIPELINED
937 25 dgisselq
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
938 48 dgisselq
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
939 56 dgisselq
`else
940 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
941
        assign  dcdA_stall = 1'b0;
942 56 dgisselq
`endif
943 36 dgisselq
 
944 69 dgisselq
`ifdef  OPT_PIPELINED
945 25 dgisselq
        always @(posedge i_clk)
946
                if (op_ce)
947 48 dgisselq
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
948
        always @(posedge i_clk)
949
                if (op_ce)
950
                        opB_mem <= (dcd_zI)&&(dcdB_rd)&&(
951 56 dgisselq
                                ((opvalid_mem)&&(opR == dcdB)&&(~opn[0]))
952 48 dgisselq
                                ||((~opvalid)&&(mem_busy)&&(~mem_we)
953
                                        &&(mem_last_reg == dcdB)));
954
                else if ((opvalid)&&(opB_mem)&&(mem_valid))
955
                        opB_mem <= 1'b0;
956 65 dgisselq
        assign  opB = ((opB_alu)&&(alu_wr)) ? alu_result
957 48 dgisselq
                        : ( ((opB_mem)&&(mem_valid))?mem_result
958
                        : r_opB );
959 56 dgisselq
`else
960
        assign  opB = r_opB;
961
`endif
962
 
963 69 dgisselq
`ifdef  OPT_PIPELINED
964 25 dgisselq
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
965 38 dgisselq
                                // Stall on memory ops writing to my register
966
                                //      (i.e. loads), or on any write to my
967
                                //      register if I have an immediate offset
968
                                // Note the exception for writing to the PC:
969
                                //      if I write to the PC, the whole next
970
                                //      instruction is invalid, not just the
971
                                //      operand.  That'll get wiped in the
972
                                //      next operation anyway, so don't stall
973
                                //      here.
974 25 dgisselq
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
975 38 dgisselq
                                        &&(opR != { op_gie, `CPU_PC_REG} )
976 48 dgisselq
                                        &&(~dcd_zI))
977 38 dgisselq
                                // Stall on any write to the flags register,
978
                                // if we're going to need the flags value for
979
                                // opB.
980 30 dgisselq
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
981 38 dgisselq
                                // Stall on any ongoing memory operation that
982
                                // will write to opB
983 48 dgisselq
                                ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
984 56 dgisselq
`else
985 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
986
        // hazard without the pipeline?
987
        assign  dcdB_stall = 1'b0;
988 56 dgisselq
`endif
989 69 dgisselq
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])
990
                                        ||((dcdA_rd)&&(dcdA_cc))
991
                                        ||((dcdB_rd)&&(dcdB_cc)))
992 30 dgisselq
                                        &&(opvalid)&&(opR_cc);
993 2 dgisselq
        //
994
        //
995
        //      PIPELINE STAGE #4 :: Apply Instruction
996
        //
997
        //
998 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
999 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1000 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
1001 56 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
1002 69 dgisselq
`else
1003
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
1004
                        (opvalid_alu), opn, opA, opB,
1005
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
1006
`endif
1007 2 dgisselq
 
1008 69 dgisselq
        generate
1009
        if (IMPLEMENT_DIVIDE != 0)
1010
        begin
1011
                div thedivide(i_clk, i_rst, div_ce, opn[0],
1012
                        opA, opB, div_busy, div_valid, div_error, div_result,
1013
                        div_flags);
1014
        end else begin
1015
                assign  div_error = 1'b1;
1016
                assign  div_busy  = 1'b0;
1017
                assign  div_valid = 1'b0;
1018
                assign  div_result= 32'h00;
1019
                assign  div_flags = 4'h0;
1020
        end endgenerate
1021
 
1022
        generate
1023
        if (IMPLEMENT_FPU != 0)
1024
        begin
1025
                //
1026
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1027
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1028
                //      fpu_flags);
1029
                //
1030
                assign  fpu_error = 1'b1;
1031
                assign  fpu_busy  = 1'b0;
1032
                assign  fpu_valid = 1'b0;
1033
                assign  fpu_result= 32'h00;
1034
                assign  fpu_flags = 4'h0;
1035
        end else begin
1036
                assign  fpu_error = 1'b1;
1037
                assign  fpu_busy  = 1'b0;
1038
                assign  fpu_valid = 1'b0;
1039
                assign  fpu_result= 32'h00;
1040
                assign  fpu_flags = 4'h0;
1041
        end endgenerate
1042
 
1043
 
1044 2 dgisselq
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1045
        initial alF_wr   = 1'b0;
1046
        initial alu_wr   = 1'b0;
1047
        always @(posedge i_clk)
1048
                if (i_rst)
1049
                begin
1050
                        alu_wr   <= 1'b0;
1051
                        alF_wr   <= 1'b0;
1052
                end else if (alu_ce)
1053
                begin
1054 65 dgisselq
                        // alu_reg <= opR;
1055 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1056
                        alF_wr  <= (opF_wr)&&(set_cond);
1057
                end else begin
1058
                        // These are strobe signals, so clear them if not
1059
                        // set for any particular clock
1060 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1061 2 dgisselq
                        alF_wr <= 1'b0;
1062
                end
1063 69 dgisselq
 
1064
`ifdef  OPT_VLIW
1065
        reg     r_alu_phase;
1066
        initial r_alu_phase = 1'b0;
1067 2 dgisselq
        always @(posedge i_clk)
1068 69 dgisselq
                if (i_rst)
1069
                        r_alu_phase <= 1'b0;
1070
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
1071
                        r_alu_phase <= op_phase;
1072
        assign  alu_phase = r_alu_phase;
1073
`else
1074
        assign  alu_phase = 1'b0;
1075
`endif
1076
 
1077
        always @(posedge i_clk)
1078
                if ((alu_ce)||(div_ce)||(fpu_ce))
1079 65 dgisselq
                        alu_reg <= opR;
1080
                else if ((i_halt)&&(i_dbg_we))
1081
                        alu_reg <= i_dbg_reg;
1082 69 dgisselq
 
1083 65 dgisselq
        reg     [31:0]   dbg_val;
1084
        reg             dbgv;
1085
        always @(posedge i_clk)
1086
                dbg_val <= i_dbg_data;
1087
        initial dbgv = 1'b0;
1088
        always @(posedge i_clk)
1089
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
1090
        always @(posedge i_clk)
1091 2 dgisselq
                if ((alu_ce)||(mem_ce))
1092
                        alu_gie  <= op_gie;
1093
        always @(posedge i_clk)
1094 65 dgisselq
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1095
                                &&(~mem_stalled)))
1096 2 dgisselq
                        alu_pc  <= op_pc;
1097 65 dgisselq
 
1098 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1099 56 dgisselq
        reg     r_alu_illegal;
1100
        initial r_alu_illegal = 0;
1101 38 dgisselq
        always @(posedge i_clk)
1102
                if ((alu_ce)||(mem_ce))
1103 56 dgisselq
                        r_alu_illegal <= op_illegal;
1104
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1105 38 dgisselq
`endif
1106
 
1107 65 dgisselq
        // This _almost_ is equal to (alu_ce)||(mem_ce).  The only
1108
        // problem is that mem_ce is gated by the set_cond, and
1109
        // the PC will be valid independent of the set condition.  Hence, this
1110
        // equals (alu_ce)||(everything in mem_ce but the set condition)
1111 2 dgisselq
        initial alu_pc_valid = 1'b0;
1112
        always @(posedge i_clk)
1113 65 dgisselq
                alu_pc_valid <= ((alu_ce)
1114
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
1115 2 dgisselq
 
1116 69 dgisselq
        wire    bus_lock;
1117
`ifdef  OPT_PIPELINED
1118
        generate
1119
        if (IMPLEMENT_LOCK != 0)
1120
        begin
1121
                reg     r_bus_lock;
1122
                initial r_bus_lock = 1'b0;
1123
                always @(posedge i_clk)
1124
                        if (i_rst)
1125
                                r_bus_lock <= 1'b0;
1126
                        else if ((op_ce)&&(op_lock))
1127
                                r_bus_lock <= 1'b1;
1128
                        else if (~opvalid_mem)
1129
                                r_bus_lock <= 1'b0;
1130
                assign  bus_lock = r_bus_lock;
1131
        end else begin
1132
                assign  bus_lock = 1'b0;
1133
        end endgenerate
1134
`else
1135
        assign  bus_lock = 1'b0;
1136
`endif
1137
 
1138 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1139 69 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
1140 38 dgisselq
                                (opn[0]), opB, opA, opR,
1141
                                mem_busy, mem_pipe_stalled,
1142
                                mem_valid, bus_err, mem_wreg, mem_result,
1143
                        mem_cyc_gbl, mem_cyc_lcl,
1144
                                mem_stb_gbl, mem_stb_lcl,
1145
                                mem_we, mem_addr, mem_data,
1146
                                mem_ack, mem_stall, mem_err, i_wb_data);
1147
 
1148
`else // PIPELINED_BUS_ACCESS
1149 69 dgisselq
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
1150 2 dgisselq
                                (opn[0]), opB, opA, opR,
1151 38 dgisselq
                                mem_busy,
1152
                                mem_valid, bus_err, mem_wreg, mem_result,
1153 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1154
                                mem_stb_gbl, mem_stb_lcl,
1155
                                mem_we, mem_addr, mem_data,
1156
                                mem_ack, mem_stall, mem_err, i_wb_data);
1157 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1158 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1159 2 dgisselq
 
1160
        // Either the prefetch or the instruction gets the memory bus, but 
1161
        // never both.
1162 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1163 36 dgisselq
                // Memory access to the arbiter, priority position
1164
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1165
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1166 2 dgisselq
                // Prefetch access to the arbiter
1167 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1168
                        pf_ack, pf_stall, pf_err,
1169 2 dgisselq
                // Common wires, in and out, of the arbiter
1170 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1171
                        o_wb_we, o_wb_addr, o_wb_data,
1172
                        i_wb_ack, i_wb_stall, i_wb_err);
1173 2 dgisselq
 
1174
        //
1175
        //
1176
        //      PIPELINE STAGE #5 :: Write-back results
1177
        //
1178
        //
1179
        // This stage is not allowed to stall.  If results are ready to be
1180
        // written back, they are written back at all cost.  Sleepy CPU's
1181
        // won't prevent write back, nor debug modes, halting the CPU, nor
1182
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1183
        // as knowinig something is available for writeback.
1184
 
1185
        //
1186
        // Write back to our generic register set ...
1187
        // When shall we write back?  On one of two conditions
1188
        //      Note that the flags needed to be checked before issuing the
1189
        //      bus instruction, so they don't need to be checked here.
1190
        //      Further, alu_wr includes (set_cond), so we don't need to
1191
        //      check for that here either.
1192 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1193 69 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
1194 36 dgisselq
`else
1195 69 dgisselq
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
1196 36 dgisselq
`endif
1197 2 dgisselq
        // Which register shall be written?
1198 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1199
        //              One or PC, one for CC, and one for GIE match
1200 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1201
        //      FPU operation.
1202 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1203 25 dgisselq
        // Are we writing to the CC register?
1204
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1205 2 dgisselq
        // Are we writing to the PC?
1206
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1207
        // What value to write?
1208 69 dgisselq
        assign  wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result)
1209
                                :((mem_valid) ? mem_result
1210
                                :((div_valid) ? div_result
1211
                                :fpu_result));
1212 2 dgisselq
        always @(posedge i_clk)
1213
                if (wr_reg_ce)
1214
                        regset[wr_reg_id] <= wr_reg_vl;
1215
 
1216
        //
1217
        // Write back to the condition codes/flags register ...
1218
        // When shall we write to our flags register?  alF_wr already
1219
        // includes the set condition ...
1220 69 dgisselq
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1221
        assign  w_uflags = { ufpu_err_flag, udiv_err_flag, ubus_err_flag, trap, ill_err_u,    1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1222
        assign  w_iflags = { ifpu_err_flag, idiv_err_flag, ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1223
 
1224
 
1225 2 dgisselq
        // What value to write?
1226
        always @(posedge i_clk)
1227
                // If explicitly writing the register itself
1228 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1229 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1230
                // Otherwise if we're setting the flags from an ALU operation
1231
                else if ((wr_flags_ce)&&(alu_gie))
1232 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1233
                                : alu_flags);
1234 2 dgisselq
 
1235
        always @(posedge i_clk)
1236 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1237 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1238
                else if ((wr_flags_ce)&&(~alu_gie))
1239 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1240
                                : alu_flags);
1241 2 dgisselq
 
1242
        // The 'break' enable  bit.  This bit can only be set from supervisor
1243
        // mode.  It control what the CPU does upon encountering a break
1244
        // instruction.
1245
        //
1246
        // The goal, upon encountering a break is that the CPU should stop and
1247
        // not execute the break instruction, choosing instead to enter into
1248
        // either interrupt mode or halt first.  
1249
        //      if ((break_en) AND (break_instruction)) // user mode or not
1250
        //              HALT CPU
1251
        //      else if (break_instruction) // only in user mode
1252
        //              set an interrupt flag, go to supervisor mode
1253
        //              allow supervisor to step the CPU.
1254
        //      Upon a CPU halt, any break condition will be reset.  The
1255
        //      external debugger will then need to deal with whatever
1256
        //      condition has taken place.
1257
        initial break_en = 1'b0;
1258
        always @(posedge i_clk)
1259
                if ((i_rst)||(i_halt))
1260
                        break_en <= 1'b0;
1261 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1262 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1263 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1264 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1265
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1266 69 dgisselq
                                &&(~div_busy)&&(~fpu_busy)
1267 36 dgisselq
                                &&(~clear_pipeline)
1268
                        ||((~alu_gie)&&(bus_err))
1269 69 dgisselq
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1270
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
1271 36 dgisselq
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
1272
`else
1273
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1274
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1275
                                &&(~clear_pipeline))
1276 38 dgisselq
                        ||((~alu_gie)&&(bus_err));
1277 36 dgisselq
`endif
1278 2 dgisselq
 
1279
 
1280
        // The sleep register.  Setting the sleep register causes the CPU to
1281
        // sleep until the next interrupt.  Setting the sleep register within
1282
        // interrupt mode causes the processor to halt until a reset.  This is
1283 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1284
        // set the sleep bit and switch to supervisor mode in the same 
1285
        // instruction: users are not allowed to halt the CPU.
1286 2 dgisselq
        always @(posedge i_clk)
1287 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1288 2 dgisselq
                        sleep <= 1'b0;
1289 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1290
                        // In supervisor mode, we have no protections.  The
1291
                        // supervisor can set the sleep bit however he wants.
1292 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1293
                        // sleep mode shouold only be possible if the interrupt
1294
                        // flag isn't set.
1295
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
1296
                        //              don't set the sleep bit
1297
                        //      otherwise however it would o.w. be set
1298
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
1299
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
1300 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1301
                        // In user mode, however, you can only set the sleep
1302
                        // mode while remaining in user mode.  You can't switch
1303
                        // to sleep mode *and* supervisor mode at the same
1304
                        // time, lest you halt the CPU.
1305
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1306 2 dgisselq
 
1307
        always @(posedge i_clk)
1308
                if ((i_rst)||(w_switch_to_interrupt))
1309
                        step <= 1'b0;
1310 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1311 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1312 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1313 2 dgisselq
                        step <= 1'b0;
1314
 
1315
        // The GIE register.  Only interrupts can disable the interrupt register
1316
        assign  w_switch_to_interrupt = (gie)&&(
1317
                        // On interrupt (obviously)
1318 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1319 2 dgisselq
                        // If we are stepping the CPU
1320 69 dgisselq
                        ||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
1321 2 dgisselq
                        // If we encounter a break instruction, if the break
1322 36 dgisselq
                        //      enable isn't set.
1323 69 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
1324
                                &&(op_break)&&(~break_en))
1325 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1326 36 dgisselq
                        // On an illegal instruction
1327
                        ||((alu_valid)&&(alu_illegal))
1328
`endif
1329 69 dgisselq
                        ||((div_valid)&&(div_error))
1330
                        ||((fpu_valid)&&(fpu_error))
1331
                        ||(bus_err)
1332 2 dgisselq
                        // If we write to the CC register
1333
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1334 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1335 2 dgisselq
                        );
1336
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1337
                        // Then if we write the CC register
1338
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1339 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1340 2 dgisselq
                        );
1341
        always @(posedge i_clk)
1342
                if (i_rst)
1343
                        gie <= 1'b0;
1344
                else if (w_switch_to_interrupt)
1345
                        gie <= 1'b0;
1346
                else if (w_release_from_interrupt)
1347
                        gie <= 1'b1;
1348
 
1349 25 dgisselq
        initial trap = 1'b0;
1350
        always @(posedge i_clk)
1351
                if (i_rst)
1352
                        trap <= 1'b0;
1353 69 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1354
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
1355 25 dgisselq
                        trap <= 1'b1;
1356
                else if (w_release_from_interrupt)
1357
                        trap <= 1'b0;
1358
 
1359 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1360 65 dgisselq
        initial ill_err_i = 1'b0;
1361 36 dgisselq
        always @(posedge i_clk)
1362
                if (i_rst)
1363 65 dgisselq
                        ill_err_i <= 1'b0;
1364
                // The debug interface can clear this bit
1365
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1366
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
1367
                        ill_err_i <= 1'b0;
1368
                else if ((alu_valid)&&(alu_illegal)&&(~alu_gie))
1369
                        ill_err_i <= 1'b1;
1370
        initial ill_err_u = 1'b0;
1371
        always @(posedge i_clk)
1372
                if (i_rst)
1373
                        ill_err_u <= 1'b0;
1374
                // The bit is automatically cleared on release from interrupt
1375 36 dgisselq
                else if (w_release_from_interrupt)
1376 65 dgisselq
                        ill_err_u <= 1'b0;
1377
                // If the supervisor writes to this register, clearing the
1378
                // bit, then clear it
1379
                else if (((~alu_gie)||(dbgv))
1380
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
1381
                                &&(wr_reg_id[4])&&(wr_write_cc))
1382
                        ill_err_u <= 1'b0;
1383 36 dgisselq
                else if ((alu_valid)&&(alu_illegal)&&(gie))
1384 65 dgisselq
                        ill_err_u <= 1'b1;
1385 38 dgisselq
`else
1386 65 dgisselq
        assign ill_err_u = 1'b0;
1387
        assign ill_err_i = 1'b0;
1388 36 dgisselq
`endif
1389 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1390
        // ever set.
1391
        initial ibus_err_flag = 1'b0;
1392 36 dgisselq
        always @(posedge i_clk)
1393
                if (i_rst)
1394 65 dgisselq
                        ibus_err_flag <= 1'b0;
1395
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1396
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
1397
                        ibus_err_flag <= 1'b0;
1398
                else if ((bus_err)&&(~alu_gie))
1399
                        ibus_err_flag <= 1'b1;
1400
        // User bus error flag -- if ever set, it will cause an interrupt to
1401
        // supervisor mode.  
1402
        initial ubus_err_flag = 1'b0;
1403
        always @(posedge i_clk)
1404
                if (i_rst)
1405
                        ubus_err_flag <= 1'b0;
1406 36 dgisselq
                else if (w_release_from_interrupt)
1407 65 dgisselq
                        ubus_err_flag <= 1'b0;
1408
                // else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4])
1409
                                // &&(i_dbg_reg == {1'b1, `CPU_CC_REG})
1410
                                // &&(~i_dbg_data[`CPU_BUSERR_BIT]))
1411
                        // ubus_err_flag <= 1'b0;
1412
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1413
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
1414
                                &&(wr_reg_id[4])&&(wr_write_cc))
1415
                        ubus_err_flag <= 1'b0;
1416 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1417 65 dgisselq
                        ubus_err_flag <= 1'b1;
1418 36 dgisselq
 
1419 69 dgisselq
        generate
1420
        if (IMPLEMENT_DIVIDE != 0)
1421
        begin
1422
                reg     r_idiv_err_flag, r_udiv_err_flag;
1423
 
1424
                // Supervisor/interrupt divide (by zero) error flag -- this will
1425
                // crash the CPU if ever set.  This bit is thus available for us
1426
                // to be able to tell if/why the CPU crashed.
1427
                initial r_idiv_err_flag = 1'b0;
1428
                always @(posedge i_clk)
1429
                        if (i_rst)
1430
                                r_idiv_err_flag <= 1'b0;
1431
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1432
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
1433
                                r_idiv_err_flag <= 1'b0;
1434
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
1435
                                r_idiv_err_flag <= 1'b1;
1436
                // User divide (by zero) error flag -- if ever set, it will
1437
                // cause a sudden switch interrupt to supervisor mode.  
1438
                initial r_udiv_err_flag = 1'b0;
1439
                always @(posedge i_clk)
1440
                        if (i_rst)
1441
                                r_udiv_err_flag <= 1'b0;
1442
                        else if (w_release_from_interrupt)
1443
                                r_udiv_err_flag <= 1'b0;
1444
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1445
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
1446
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1447
                                r_udiv_err_flag <= 1'b0;
1448
                        else if ((div_error)&&(alu_gie)&&(div_valid))
1449
                                r_udiv_err_flag <= 1'b1;
1450
 
1451
                assign  idiv_err_flag = r_idiv_err_flag;
1452
                assign  udiv_err_flag = r_udiv_err_flag;
1453
        end else begin
1454
                assign  idiv_err_flag = 1'b0;
1455
                assign  udiv_err_flag = 1'b0;
1456
        end endgenerate
1457
 
1458
        generate
1459
        if (IMPLEMENT_FPU !=0)
1460
        begin
1461
                // Supervisor/interrupt floating point error flag -- this will
1462
                // crash the CPU if ever set.
1463
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1464
                initial r_ifpu_err_flag = 1'b0;
1465
                always @(posedge i_clk)
1466
                        if (i_rst)
1467
                                r_ifpu_err_flag <= 1'b0;
1468
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1469
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
1470
                                r_ifpu_err_flag <= 1'b0;
1471
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1472
                                r_ifpu_err_flag <= 1'b1;
1473
                // User floating point error flag -- if ever set, it will cause
1474
                // a sudden switch interrupt to supervisor mode.  
1475
                initial r_ufpu_err_flag = 1'b0;
1476
                always @(posedge i_clk)
1477
                        if (i_rst)
1478
                                r_ufpu_err_flag <= 1'b0;
1479
                        else if (w_release_from_interrupt)
1480
                                r_ufpu_err_flag <= 1'b0;
1481
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1482
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
1483
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1484
                                r_ufpu_err_flag <= 1'b0;
1485
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1486
                                r_ufpu_err_flag <= 1'b1;
1487
 
1488
                assign  ifpu_err_flag = r_ifpu_err_flag;
1489
                assign  ufpu_err_flag = r_ufpu_err_flag;
1490
        end else begin
1491
                assign  ifpu_err_flag = 1'b0;
1492
                assign  ufpu_err_flag = 1'b0;
1493
        end endgenerate
1494
 
1495
`ifdef  OPT_VLIW
1496
        reg             r_ihalt_phase, r_uhalt_phase;
1497
 
1498
        initial r_ihalt_phase = 0;
1499
        initial r_uhalt_phase = 0;
1500
        always @(posedge i_clk)
1501
                if (~alu_gie)
1502
                        r_ihalt_phase <= alu_phase;
1503
        always @(posedge i_clk)
1504
                if (alu_gie)
1505
                        r_uhalt_phase <= alu_phase;
1506
                else if (w_release_from_interrupt)
1507
                        r_uhalt_phase <= 1'b0;
1508
 
1509
        assign  ihalt_phase = r_ihalt_phase;
1510
        assign  uhalt_phase = r_uhalt_phase;
1511
`else
1512
        assign  ihalt_phase = 1'b0;
1513
        assign  uhalt_phase = 1'b0;
1514
`endif
1515
 
1516 2 dgisselq
        //
1517
        // Write backs to the PC register, and general increments of it
1518
        //      We support two: upc and ipc.  If the instruction is normal,
1519
        // we increment upc, if interrupt level we increment ipc.  If
1520
        // the instruction writes the PC, we write whichever PC is appropriate.
1521
        //
1522
        // Do we need to all our partial results from the pipeline?
1523
        // What happens when the pipeline has gie and ~gie instructions within
1524
        // it?  Do we clear both?  What if a gie instruction tries to clear
1525
        // a non-gie instruction?
1526
        always @(posedge i_clk)
1527 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1528 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1529 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1530 2 dgisselq
                        upc <= alu_pc;
1531
 
1532
        always @(posedge i_clk)
1533
                if (i_rst)
1534
                        ipc <= RESET_ADDRESS;
1535
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1536 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1537 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1538 2 dgisselq
                        ipc <= alu_pc;
1539
 
1540
        always @(posedge i_clk)
1541
                if (i_rst)
1542
                        pf_pc <= RESET_ADDRESS;
1543
                else if (w_switch_to_interrupt)
1544
                        pf_pc <= ipc;
1545
                else if (w_release_from_interrupt)
1546
                        pf_pc <= upc;
1547
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1548 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1549 69 dgisselq
`ifdef  OPT_PIPELINED
1550
                else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
1551
                        pf_pc <= dcd_branch_pc + 1;
1552
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1553 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1554 69 dgisselq
`else
1555
                else if ((alu_pc_valid)&&(~clear_pipeline))
1556
                        pf_pc <= alu_pc;
1557
`endif
1558 2 dgisselq
 
1559
        initial new_pc = 1'b1;
1560
        always @(posedge i_clk)
1561 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1562 2 dgisselq
                        new_pc <= 1'b1;
1563
                else if (w_switch_to_interrupt)
1564
                        new_pc <= 1'b1;
1565
                else if (w_release_from_interrupt)
1566
                        new_pc <= 1'b1;
1567
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1568
                        new_pc <= 1'b1;
1569
                else
1570
                        new_pc <= 1'b0;
1571
 
1572
        //
1573
        // The debug interface
1574 56 dgisselq
        generate
1575
        if (AW<32)
1576
        begin
1577
                always @(posedge i_clk)
1578 2 dgisselq
                begin
1579
                        o_dbg_reg <= regset[i_dbg_reg];
1580
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1581 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1582 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1583 56 dgisselq
                        begin
1584 69 dgisselq
                                o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1585 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1586
                        end
1587 2 dgisselq
                end
1588 56 dgisselq
        end else begin
1589
                always @(posedge i_clk)
1590
                begin
1591
                        o_dbg_reg <= regset[i_dbg_reg];
1592
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1593
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1594
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1595
                        begin
1596 69 dgisselq
                                o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1597 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1598
                        end
1599
                end
1600
        end endgenerate
1601
 
1602 2 dgisselq
        always @(posedge i_clk)
1603 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1604 18 dgisselq
 
1605
        always @(posedge i_clk)
1606 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1607 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1608 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1609 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1610 2 dgisselq
 
1611
        //
1612
        //
1613
        // Produce accounting outputs: Account for any CPU stalls, so we can
1614
        // later evaluate how well we are doing.
1615
        //
1616
        //
1617 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
1618
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1619 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1620 56 dgisselq
 
1621 65 dgisselq
`ifdef  DEBUG_SCOPE
1622 56 dgisselq
        always @(posedge i_clk)
1623 65 dgisselq
                o_debug <= {
1624 69 dgisselq
                /*
1625
                        pf_pc[3:0], flags,
1626 56 dgisselq
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1627
                        op_ce, alu_ce, mem_ce,
1628 65 dgisselq
                        //
1629
                        master_ce, opvalid_alu, opvalid_mem,
1630
                        //
1631
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1632
                        mem_we,
1633
                        // ((opvalid_alu)&&(alu_stall))
1634
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1635
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1636
                        // opA[23:20], opA[3:0],
1637
                        gie, sleep,
1638
                        wr_reg_vl[5:0]
1639 69 dgisselq
                */
1640
                        i_rst, master_ce, (new_pc),
1641
                        ((dcd_early_branch)&&(dcdvalid)),
1642
                        pf_valid, pf_illegal,
1643
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1644
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1645
                        pf_pc[7:0], pf_addr[7:0]
1646 56 dgisselq
                        };
1647 65 dgisselq
`endif
1648 56 dgisselq
 
1649 2 dgisselq
endmodule

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