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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9
//              The instruction set is about as RISC as you can get, there are
10
//              only 16 instruction types supported (of which one isn't yet
11
//              supported ...)  Please see the accompanying iset.html file
12
//              for a description of these instructions.
13
//
14
//              All instructions are 32-bits wide.  All bus accesses, both
15
//              address and data, are 32-bits over a wishbone bus.
16
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19
//              1. Prefetch, returns the instruction from memory.  On the
20
//              Basys board that I'm working on, one instruction may be
21
//              issued every 20 clocks or so, unless and until I implement a
22
//              cache or local memory.
23
//
24
//              2. Instruction Decode
25
//
26
//              3. Read Operands
27
//
28
//              4. Apply Instruction
29
//
30
//              4. Write-back Results
31
//
32
//      A lot of difficult work has been placed into the pipeline stall
33
//      handling.  My original proposal was not to allow pipeline stalls at all.
34
//      The idea would be that the CPU would just run every clock and whatever
35
//      stalled answer took place would just get fixed a clock or two later,
36
//      meaning that the compiler could just schedule everything out.
37
//      This idea died at the memory interface, which can take a variable
38
//      amount of time to read or write any value, thus the whole CPU needed
39
//      to stall on a stalled memory access.
40
//
41
//      My next idea was to just let things complete.  I.e., once an instrution
42
//      starts, it continues to completion no matter what and we go on.  This
43
//      failed at writing the PC.  If the PC gets written in something such as
44
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
45
//      later, if whether or not something happens in those clocks depends
46
//      upon the instruction fetch filling the pipeline, then the CPU has a
47
//      non-deterministic behavior.
48
//
49
//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
51
//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
53
//      read or a write, there is no undoing it--since peripherals on the
54
//      bus may act upon the answer with whatever side effects they might
55
//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
94
// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
99
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
104
//              http://www.gnu.org/licenses/gpl.html
105
//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109
`define CPU_PC_REG      4'hf
110
`define CPU_CC_REG      4'he
111
`define CPU_BREAK_BIT   7
112
`define CPU_STEP_BIT    6
113
`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
115
module  zipcpu(i_clk, i_rst, i_interrupt,
116
                // Debug interface
117
                i_halt, i_dbg_reg, i_dbg_we, i_dbg_data,
118
                        o_dbg_stall, o_dbg_reg,
119
                        o_break,
120
                // CPU interface to the wishbone bus
121
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
122
                        i_wb_ack, i_wb_stall, i_wb_data,
123
                // Accounting/CPU usage interface
124 9 dgisselq
                o_op_stall, o_pf_stall, o_i_count);
125 2 dgisselq
        parameter       RESET_ADDRESS=32'h0100000;
126
        input                   i_clk, i_rst, i_interrupt;
127
        // Debug interface -- inputs
128
        input                   i_halt;
129
        input           [4:0]    i_dbg_reg;
130
        input                   i_dbg_we;
131
        input           [31:0]   i_dbg_data;
132
        // Debug interface -- outputs
133
        output  reg             o_dbg_stall;
134
        output  reg     [31:0]   o_dbg_reg;
135
        output  wire            o_break;
136
        // Wishbone interface -- outputs
137
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
138
        output  wire    [31:0]   o_wb_addr, o_wb_data;
139
        // Wishbone interface -- inputs
140
        input                   i_wb_ack, i_wb_stall;
141
        input           [31:0]   i_wb_data;
142
        // Accounting outputs ... to help us count stalls and usage
143 9 dgisselq
        output  wire            o_op_stall;
144 2 dgisselq
        output  wire            o_pf_stall;
145 9 dgisselq
        output  wire            o_i_count;
146 2 dgisselq
 
147
 
148
        // Registers
149
        reg     [31:0]   regset [0:31];
150 9 dgisselq
 
151
        // Condition codes
152 2 dgisselq
        reg     [3:0]    flags, iflags;  // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
153
        wire    [7:0]    w_uflags, w_iflags;
154 9 dgisselq
        reg             break_en, step, gie, sleep;
155 2 dgisselq
 
156 9 dgisselq
        // The master chip enable
157
        wire            master_ce;
158 2 dgisselq
 
159
        //
160
        //
161
        //      PIPELINE STAGE #1 :: Prefetch
162
        //              Variable declarations
163
        //
164 9 dgisselq
        reg     [31:0]   pf_pc;
165
        reg             new_pc;
166
 
167
        wire            dcd_stalled;
168 2 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
169
        wire    [31:0]   pf_addr, pf_data;
170
        wire    [31:0]   instruction, instruction_pc;
171
        wire    pf_valid, instruction_gie;
172
 
173
        //
174
        //
175
        //      PIPELINE STAGE #2 :: Instruction Decode
176
        //              Variable declarations
177
        //
178
        //
179
        reg             opvalid, op_wr_pc, op_break;
180
        wire            op_stall, dcd_ce;
181
        reg     [3:0]    dcdOp;
182
        reg     [4:0]    dcdA, dcdB;
183
        reg     [3:0]    dcdF;
184
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
185
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
186
        reg     [31:0]   dcd_pc;
187
        reg     [23:0]   r_dcdI;
188
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
189
 
190
 
191
 
192
        //
193
        //
194
        //      PIPELINE STAGE #3 :: Read Operands
195
        //              Variable declarations
196
        //
197
        //
198
        //
199
        // Now, let's read our operands
200
        reg     [4:0]    alu_reg;
201
        reg     [3:0]    opn;
202
        reg     [4:0]    opR;
203
        reg     [1:0]    opA_cc, opB_cc;
204
        reg     [31:0]   r_opA, r_opB, op_pc;
205
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
206
        reg             opR_wr, opM, opF_wr, op_gie,
207
                        opA_rd, opB_rd;
208 3 dgisselq
        wire    [7:0]    opFl;
209
        reg     [6:0]    r_opF;
210 2 dgisselq
        wire    [8:0]    opF;
211
        wire            op_ce;
212
 
213
 
214
 
215
        //
216
        //
217
        //      PIPELINE STAGE #4 :: ALU / Memory
218
        //              Variable declarations
219
        //
220
        //
221
        reg     [31:0]   alu_pc;
222
        reg             alu_pc_valid;;
223
        wire            alu_ce, alu_stall;
224
        wire    [31:0]   alu_result;
225
        wire    [3:0]    alu_flags;
226
        wire            alu_valid;
227
        wire            set_cond;
228
        reg             alu_wr, alF_wr, alu_gie;
229
 
230
 
231
 
232
        wire    mem_ce, mem_stalled;
233
        wire    mem_valid, mem_ack, mem_stall,
234
                mem_cyc, mem_stb, mem_we;
235 9 dgisselq
        wire    [4:0]    mem_wreg;
236
 
237
        wire            mem_busy, mem_rdbusy;
238 2 dgisselq
        wire    [31:0]   mem_addr, mem_data, mem_result;
239
 
240
 
241
 
242
        //
243
        //
244
        //      PIPELINE STAGE #5 :: Write-back
245
        //              Variable declarations
246
        //
247
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc;
248
        wire    [4:0]    wr_reg_id;
249
        wire    [31:0]   wr_reg_vl;
250
        wire    w_switch_to_interrupt, w_release_from_interrupt;
251
        reg     [31:0]   upc, ipc;
252
 
253
 
254
 
255
        //
256
        //      MASTER: clock enable.
257
        //
258
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep)&&(~mem_rdbusy);
259
 
260
 
261
        //
262
        //      PIPELINE STAGE #1 :: Prefetch
263
        //              Calculate stall conditions
264
 
265
        //
266
        //      PIPELINE STAGE #2 :: Instruction Decode
267
        //              Calculate stall conditions
268
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
269
        assign          dcd_stalled = (dcdvalid)&&(
270
                                        (op_stall)
271
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
272
                                        ||((opvalid)&&(op_wr_pc)));
273
        //
274
        //      PIPELINE STAGE #3 :: Read Operands
275
        //              Calculate stall conditions
276
        assign  op_stall = (opvalid)&&(
277
                                ((mem_stalled)&&(opM))
278
                                ||((alu_stall)&&(~opM)));
279
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
280
 
281
        //
282
        //      PIPELINE STAGE #4 :: ALU / Memory
283
        //              Calculate stall conditions
284
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM))
285
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG }));
286
        assign  alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~new_pc);
287
        //
288
        assign  mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~new_pc)&&(set_cond);
289
        assign  mem_stalled = (mem_busy)||((opvalid)&&(opM)&&(
290
                                (~master_ce)
291
                                // Stall waiting for flags to be valid
292
                                ||((~opF[8])&&(
293
                                        ((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))))
294
                                        // Do I need this last condition?
295
                                        //||((wr_flags_ce)&&(alu_gie==op_gie))))
296
                                // Or waiting for a write to the PC register
297
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&(wr_write_pc))));
298
 
299
 
300
        //
301
        //
302
        //      PIPELINE STAGE #1 :: Prefetch
303
        //
304
        //
305
`ifdef  SINGLE_FETCH
306 9 dgisselq
        wire            pf_ce;
307
 
308
        assign          pf_ce = (~dcd_stalled);
309 2 dgisselq
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
310
                                instruction, instruction_pc, instruction_gie,
311
                                        pf_valid,
312
                                pf_cyc, pf_stb, pf_we, pf_addr,
313
                                        pf_data,
314
                                pf_ack, pf_stall, i_wb_data);
315
`else // Pipe fetch
316 3 dgisselq
        pipefetch       #(RESET_ADDRESS)
317
                        pf(i_clk, i_rst, new_pc, ~dcd_stalled, pf_pc,
318 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
319
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
320 3 dgisselq
                                        pf_ack, pf_stall, i_wb_data,
321
                                mem_cyc);
322 2 dgisselq
        assign  instruction_gie = gie;
323
`endif
324
 
325
        always @(posedge i_clk)
326
                if (i_rst)
327
                        dcdvalid <= 1'b0;
328
                else if (dcd_ce)
329
                        dcdvalid <= (~new_pc);
330
                else if ((~dcd_stalled)||(new_pc))
331
                        dcdvalid <= 1'b0;
332
 
333
        always @(posedge i_clk)
334
                if (dcd_ce)
335
                begin
336
                        dcd_pc <= instruction_pc+1;
337
 
338
                        // Record what operation we are doing
339
                        dcdOp <= instruction[31:28];
340
 
341
                        // Default values
342
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
343
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
344
                        dcdM    <= 1'b0;
345
                        dcdF_wr <= 1'b1;
346
                        dcd_break <= 1'b0;
347
 
348
                        // Set the condition under which we do this operation
349
                        // The top four bits are a mask, the bottom four the
350
                        // value the flags must equal once anded with the mask
351
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
352
                        casez(instruction[31:28])
353
                        4'h2: begin // Move instruction
354
                                if (~instruction_gie)
355
                                begin
356
                                        dcdA[4] <= instruction[20];
357
                                        dcdB[4] <= instruction[15];
358
                                end
359
                                dcdA_wr <= 1'b1;
360
                                dcdA_rd <= 1'b0;
361
                                dcdB_rd <= 1'b1;
362
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
363
                                dcdF_wr <= 1'b0; // Don't write flags
364
                                end
365
                        4'h3: begin // Load immediate
366
                                dcdA_wr <= 1'b1;
367
                                dcdA_rd <= 1'b0;
368
                                dcdB_rd <= 1'b0;
369
                                r_dcdI <= { instruction[23:0] };
370
                                dcdF_wr <= 1'b0; // Don't write flags
371
                                dcdF    <= 4'h8; // This is unconditional
372
                                dcdOp <= 4'h2;
373
                                end
374
                        4'h4: begin // Load immediate special
375
                                dcdF_wr <= 1'b0; // Don't write flags
376
                                r_dcdI <= { 8'h00, instruction[15:0] };
377
                                if (instruction[27:24] == 4'he)
378
                                begin
379
                                        // NOOP instruction
380
                                        dcdA_wr <= 1'b0;
381
                                        dcdA_rd <= 1'b0;
382
                                        dcdB_rd <= 1'b0;
383
                                        dcdOp <= 4'h2;
384
                                        dcd_break <= 1'b1;//Could be a break ins
385
                                end else if (instruction[27:24] == 4'hf)
386
                                begin // Load partial immediate(s)
387
                                        dcdA_wr <= 1'b1;
388
                                        dcdA_rd <= 1'b1;
389
                                        dcdB_rd <= 1'b0;
390
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
391
                                        dcdOp <= { 3'h3, instruction[20] };
392
                                end else begin
393
                                        ; // Multiply instruction place holder
394
                                end end
395
                        4'b011?: begin // Load/Store
396
                                dcdF_wr <= 1'b0; // Don't write flags
397
                                dcdA_wr <= (~instruction[28]); // Write on loads
398
                                dcdA_rd <= (instruction[28]); // Read on stores
399
                                dcdB_rd <= instruction[20];
400
                                if (instruction[20])
401
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
402
                                else
403
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
404
                                dcdM <= 1'b1; // Memory operation
405
                                end
406
                        default: begin
407
                                dcdA <= { instruction_gie, instruction[27:24] };
408
                                dcdB <= { instruction_gie, instruction[19:16] };
409
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
410
                                dcdA_rd <= 1'b1;
411
                                dcdB_rd <= instruction[20];
412
                                if (instruction[20])
413
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
414
                                else
415
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
416
                                end
417
                        endcase
418
 
419
 
420
                        dcd_gie <= instruction_gie;
421
                end
422
 
423
 
424
        //
425
        //
426
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
427
        //
428
        //
429
 
430
        always @(posedge i_clk)
431
                if (op_ce) // &&(dcdvalid))
432
                begin
433
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
434
                                r_opA <= wr_reg_vl;
435
                        else if (dcdA == { dcd_gie, `CPU_PC_REG })
436
                                r_opA <= dcd_pc;
437
                        else if (dcdA[3:0] == `CPU_PC_REG)
438
                                r_opA <= (dcdA[4])?upc:ipc;
439
                        else
440
                                r_opA <= regset[dcdA];
441
                end
442
        wire    [31:0]   dcdI;
443
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
444
        always @(posedge i_clk)
445
                if (op_ce) // &&(dcdvalid))
446
                begin
447
                        if (~dcdB_rd)
448
                                r_opB <= dcdI;
449
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
450
                                r_opB <= wr_reg_vl + dcdI;
451
                        else if (dcdB == { dcd_gie, `CPU_PC_REG })
452
                                r_opB <= dcd_pc + dcdI;
453
                        else if (dcdB[3:0] == `CPU_PC_REG)
454
                                r_opB <= ((dcdB[4])?upc:ipc) + dcdI;
455
                        else
456
                                r_opB <= regset[dcdB] + dcdI;
457
                end
458
 
459
        // The logic here has become more complex than it should be, no thanks
460
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
461
        // be two sets of four bits: the top bits specify what bits matter, the
462
        // bottom specify what those top bits must equal.  However, two of
463
        // conditions check whether bits are on, and those are the only two
464
        // conditions checking those bits.  Therefore, Vivado complains that
465
        // these two bits are redundant.  Hence the convoluted expression
466
        // below, arriving at what we finally want in the (now wire net)
467
        // opF.
468 3 dgisselq
`define NEWCODE
469 2 dgisselq
`ifdef  NEWCODE
470
        always @(posedge i_clk)
471
                if (op_ce)
472
                begin // Set the flag condition codes
473
                        case(dcdF[2:0])
474
                        3'h0:   r_opF <= 7'h80; // Always
475
                        3'h1:   r_opF <= 7'h11; // Z
476
                        3'h2:   r_opF <= 7'h10; // NE
477
                        3'h3:   r_opF <= 7'h20; // GE (!N)
478
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
479
                        3'h5:   r_opF <= 7'h24; // LT
480
                        3'h6:   r_opF <= 7'h02; // C
481
                        3'h7:   r_opF <= 7'h08; // V
482
                        endcase
483
                end
484
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
485
`else
486
        always @(posedge i_clk)
487
                if (op_ce)
488
                begin // Set the flag condition codes
489
                        case(dcdF[2:0])
490
                        3'h0:   opF <= 9'h100;  // Always
491
                        3'h1:   opF <= 9'h011;  // Z
492
                        3'h2:   opF <= 9'h010;  // NE
493
                        3'h3:   opF <= 9'h040;  // GE (!N)
494
                        3'h4:   opF <= 9'h050;  // GT (!N&!Z)
495
                        3'h5:   opF <= 9'h044;  // LT
496
                        3'h6:   opF <= 9'h022;  // C
497
                        3'h7:   opF <= 9'h088;  // V
498
                        endcase
499
                end
500
`endif
501
 
502
        always @(posedge i_clk)
503
                if (i_rst)
504
                        opvalid <= 1'b0;
505
                else if (op_ce)
506
                        // Do we have a valid instruction?
507
                        //   The decoder may vote to stall one of its
508
                        //   instructions based upon something we currently
509
                        //   have in our queue.  This instruction must then
510
                        //   move forward, and get a stall cycle inserted.
511
                        //   Hence, the test on dcd_stalled here.  If we must
512
                        //   wait until our operands are valid, then we aren't
513
                        //   valid yet until then.
514
                        opvalid<= (~new_pc)&&(dcdvalid)&&(~dcd_stalled);
515
                else if ((~op_stall)||(new_pc))
516
                        opvalid <= 1'b0;
517
 
518
        // Here's part of our debug interface.  When we recognize a break
519
        // instruction, we set the op_break flag.  That'll prevent this
520
        // instruction from entering the ALU, and cause an interrupt before
521
        // this instruction.  Thus, returning to this code will cause the
522
        // break to repeat and continue upon return.  To get out of this
523
        // condition, replace the break instruction with what it is supposed
524
        // to be, step through it, and then replace it back.  In this fashion,
525
        // a debugger can step through code.
526
        always @(posedge i_clk)
527
                if (i_rst)
528
                        op_break <= 1'b0;
529
                else if (op_ce)
530
                        op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
531
                else if ((~op_stall)||(new_pc))
532
                        op_break <= 1'b0;
533
 
534
        always @(posedge i_clk)
535
                if (op_ce)
536
                begin
537
                        opn    <= dcdOp;        // Which ALU operation?
538
                        opM    <= dcdM;         // Is this a memory operation?
539
                        // Will we write the flags/CC Register with our result?
540
                        opF_wr <= dcdF_wr;
541
                        // Will we be writing our results into a register?
542
                        opR_wr <= dcdA_wr;
543
                        // What register will these results be written into?
544
                        opR    <= dcdA;
545
                        // User level (1), vs supervisor (0)/interrupts disabled
546
                        op_gie <= dcd_gie;
547
 
548
                        // We're not done with these yet--we still need them
549
                        // for the unclocked assign.  We need the unclocked
550
                        // assign so that there's no wait state between an
551
                        // ALU or memory result and the next register that may
552
                        // use that value.
553
                        opA_cc <= {dcdA[4], (dcdA[3:0] == `CPU_CC_REG) };
554
                        opA_rd <= dcdA_rd;
555
                        opB_cc <= {dcdB[4], (dcdB[3:0] == `CPU_CC_REG) };
556
                        opB_rd <= dcdB_rd;
557
                        op_pc  <= dcd_pc;
558
                        //
559
                        op_wr_pc <= ((dcdA_wr)&&(dcdA[3:0] == `CPU_PC_REG));
560
                end
561
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
562
 
563
        // This is tricky.  First, the PC and Flags registers aren't kept in
564
        // register set but in special registers of their own.  So step one
565
        // is to select the right register.  Step to is to replace that
566
        // register with the results of an ALU or memory operation, if such
567
        // results are now available.  Otherwise, we'd need to insert a wait
568
        // state of some type.
569
        //
570
        // The alternative approach would be to define some sort of
571
        // op_stall wire, which would stall any upstream stage.
572
        // We'll create a flag here to start our coordination.  Once we
573
        // define this flag to something other than just plain zero, then
574
        // the stalls will already be in place.
575
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&
576
                                (((opvalid)&&(opR_wr)&&(opR == dcdA))
577
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))
578
                                        ||((mem_valid)&&(mem_wreg == dcdA)));
579
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)
580
                                &&(((opvalid)&&(opR_wr)&&(opR == dcdB))
581
                                        ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))
582
                                        ||((mem_valid)&&(mem_wreg == dcdB)));
583
        assign  dcdF_stall = (dcdvalid)&&(((dcdF[3])
584
                                        ||(dcdA[3:0]==`CPU_CC_REG)
585
                                        ||(dcdB[3:0]==`CPU_CC_REG))
586
                                &&((opvalid)&&(opR[3:0] == `CPU_CC_REG))
587
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
588
        assign  opA = { r_opA[31:8], ((opA_cc[0]) ?
589
                        ((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) };
590
        assign  opB = { r_opB[31:8], ((opB_cc[0]) ?
591 3 dgisselq
                        ((opB_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) };
592 2 dgisselq
 
593
        //
594
        //
595
        //      PIPELINE STAGE #4 :: Apply Instruction
596
        //
597
        //
598
        cpuops  doalu(i_clk, i_rst, alu_ce,
599
                        (opvalid)&&(~opM), opn, opA, opB,
600
                        alu_result, alu_flags, alu_valid);
601
 
602
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
603
        initial alF_wr   = 1'b0;
604
        initial alu_wr   = 1'b0;
605
        always @(posedge i_clk)
606
                if (i_rst)
607
                begin
608
                        alu_wr   <= 1'b0;
609
                        alF_wr   <= 1'b0;
610
                end else if (alu_ce)
611
                begin
612
                        alu_reg <= opR;
613
                        alu_wr  <= (opR_wr)&&(set_cond);
614
                        alF_wr  <= (opF_wr)&&(set_cond);
615
                end else begin
616
                        // These are strobe signals, so clear them if not
617
                        // set for any particular clock
618
                        alu_wr <= 1'b0;
619
                        alF_wr <= 1'b0;
620
                end
621
        always @(posedge i_clk)
622
                if ((alu_ce)||(mem_ce))
623
                        alu_gie  <= op_gie;
624
        always @(posedge i_clk)
625
                if ((alu_ce)||(mem_ce))
626
                        alu_pc  <= op_pc;
627
        initial alu_pc_valid = 1'b0;
628
        always @(posedge i_clk)
629
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~new_pc)
630
                                        &&((~opM)
631
                                                ||(~mem_stalled));
632
 
633
        memops  domem(i_clk, i_rst, mem_ce,
634
                                (opn[0]), opB, opA, opR,
635
                                mem_busy, mem_valid, mem_wreg, mem_result,
636
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
637
                                mem_ack, mem_stall, i_wb_data);
638
        assign  mem_rdbusy = ((mem_cyc)&&(~mem_we));
639
 
640
        // Either the prefetch or the instruction gets the memory bus, but 
641
        // never both.
642
        wbarbiter       #(32,32) pformem(i_clk, i_rst,
643
                // Prefetch access to the arbiter
644
                pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall,
645
                // Memory access to the arbiter
646
                mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall,
647
                // Common wires, in and out, of the arbiter
648
                o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack,
649
                        i_wb_stall);
650
 
651
        //
652
        //
653
        //      PIPELINE STAGE #5 :: Write-back results
654
        //
655
        //
656
        // This stage is not allowed to stall.  If results are ready to be
657
        // written back, they are written back at all cost.  Sleepy CPU's
658
        // won't prevent write back, nor debug modes, halting the CPU, nor
659
        // anything else.  Indeed, the (master_ce) bit is only as relevant
660
        // as knowinig something is available for writeback.
661
 
662
        //
663
        // Write back to our generic register set ...
664
        // When shall we write back?  On one of two conditions
665
        //      Note that the flags needed to be checked before issuing the
666
        //      bus instruction, so they don't need to be checked here.
667
        //      Further, alu_wr includes (set_cond), so we don't need to
668
        //      check for that here either.
669
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
670
        // Which register shall be written?
671
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
672
        // Are we writing to the PC?
673
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
674
        // What value to write?
675
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
676
        always @(posedge i_clk)
677
                if (wr_reg_ce)
678
                        regset[wr_reg_id] <= wr_reg_vl;
679
 
680
        //
681
        // Write back to the condition codes/flags register ...
682
        // When shall we write to our flags register?  alF_wr already
683
        // includes the set condition ...
684
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
685
        assign  w_uflags = { 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
686
        assign  w_iflags = { break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
687
        // What value to write?
688
        always @(posedge i_clk)
689
                // If explicitly writing the register itself
690
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
691
                        flags <= wr_reg_vl[3:0];
692
                // Otherwise if we're setting the flags from an ALU operation
693
                else if ((wr_flags_ce)&&(alu_gie))
694
                        flags <= alu_flags;
695
                else if ((i_halt)&&(i_dbg_we)
696
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
697
                        flags <= i_dbg_data[3:0];
698
 
699
        always @(posedge i_clk)
700
                if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
701
                        iflags <= wr_reg_vl[3:0];
702
                else if ((wr_flags_ce)&&(~alu_gie))
703
                        iflags <= alu_flags;
704
                else if ((i_halt)&&(i_dbg_we)
705
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
706
                        iflags <= i_dbg_data[3:0];
707
 
708
        // The 'break' enable  bit.  This bit can only be set from supervisor
709
        // mode.  It control what the CPU does upon encountering a break
710
        // instruction.
711
        //
712
        // The goal, upon encountering a break is that the CPU should stop and
713
        // not execute the break instruction, choosing instead to enter into
714
        // either interrupt mode or halt first.  
715
        //      if ((break_en) AND (break_instruction)) // user mode or not
716
        //              HALT CPU
717
        //      else if (break_instruction) // only in user mode
718
        //              set an interrupt flag, go to supervisor mode
719
        //              allow supervisor to step the CPU.
720
        //      Upon a CPU halt, any break condition will be reset.  The
721
        //      external debugger will then need to deal with whatever
722
        //      condition has taken place.
723
        initial break_en = 1'b0;
724
        always @(posedge i_clk)
725
                if ((i_rst)||(i_halt))
726
                        break_en <= 1'b0;
727
                else if ((wr_reg_ce)&&(wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}))
728
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
729
        assign  o_break = (break_en)&&(op_break);
730
 
731
 
732
        // The sleep register.  Setting the sleep register causes the CPU to
733
        // sleep until the next interrupt.  Setting the sleep register within
734
        // interrupt mode causes the processor to halt until a reset.  This is
735
        // a panic/fault halt.
736
        always @(posedge i_clk)
737
                if ((i_rst)||((i_interrupt)&&(gie)))
738
                        sleep <= 1'b0;
739
                else if ((wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG))
740
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
741
                else if ((i_halt)&&(i_dbg_we)
742
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
743
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
744
 
745
        always @(posedge i_clk)
746
                if ((i_rst)||(w_switch_to_interrupt))
747
                        step <= 1'b0;
748
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4:0] == {1'b1,`CPU_CC_REG}))
749
                        step <= wr_reg_vl[`CPU_STEP_BIT];
750
                else if ((i_halt)&&(i_dbg_we)
751
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
752
                        step <= i_dbg_data[`CPU_STEP_BIT];
753
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
754
                        step <= 1'b0;
755
 
756
        // The GIE register.  Only interrupts can disable the interrupt register
757
        assign  w_switch_to_interrupt = (gie)&&(
758
                        // On interrupt (obviously)
759
                        (i_interrupt)
760
                        // If we are stepping the CPU
761
                        ||((master_ce)&&(alu_pc_valid)&&(step))
762
                        // If we encounter a break instruction, if the break
763
                        //      enable isn't not set.
764
                        ||((master_ce)&&(op_break))
765
                        // If we write to the CC register
766
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
767
                                &&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG }))
768
                        // Or if, in debug mode, we write to the CC register
769
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
770
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
771
                        );
772
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
773
                        // Then if we write the CC register
774
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
775
                                &&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG }))
776
                        // Or if, in debug mode, we write the CC register
777
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
778
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
779
                        );
780
        always @(posedge i_clk)
781
                if (i_rst)
782
                        gie <= 1'b0;
783
                else if (w_switch_to_interrupt)
784
                        gie <= 1'b0;
785
                else if (w_release_from_interrupt)
786
                        gie <= 1'b1;
787
 
788
        //
789
        // Write backs to the PC register, and general increments of it
790
        //      We support two: upc and ipc.  If the instruction is normal,
791
        // we increment upc, if interrupt level we increment ipc.  If
792
        // the instruction writes the PC, we write whichever PC is appropriate.
793
        //
794
        // Do we need to all our partial results from the pipeline?
795
        // What happens when the pipeline has gie and ~gie instructions within
796
        // it?  Do we clear both?  What if a gie instruction tries to clear
797
        // a non-gie instruction?
798
        always @(posedge i_clk)
799 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
800 2 dgisselq
                        upc <= wr_reg_vl;
801
                else if ((alu_gie)&&(alu_pc_valid))
802
                        upc <= alu_pc;
803
                else if ((i_halt)&&(i_dbg_we)
804
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
805
                        upc <= i_dbg_data;
806
 
807
        always @(posedge i_clk)
808
                if (i_rst)
809
                        ipc <= RESET_ADDRESS;
810
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
811
                        ipc <= wr_reg_vl;
812
                else if ((~alu_gie)&&(alu_pc_valid))
813
                        ipc <= alu_pc;
814
                else if ((i_halt)&&(i_dbg_we)
815
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
816
                        ipc <= i_dbg_data;
817
 
818
        always @(posedge i_clk)
819
                if (i_rst)
820
                        pf_pc <= RESET_ADDRESS;
821
                else if (w_switch_to_interrupt)
822
                        pf_pc <= ipc;
823
                else if (w_release_from_interrupt)
824
                        pf_pc <= upc;
825
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
826
                        pf_pc <= wr_reg_vl;
827
                else if ((i_halt)&&(i_dbg_we)
828
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
829
                        pf_pc <= i_dbg_data;
830
                else if (dcd_ce)
831
                        pf_pc <= pf_pc + 1;
832
 
833
        initial new_pc = 1'b1;
834
        always @(posedge i_clk)
835
                if (i_rst)
836
                        new_pc <= 1'b1;
837
                else if (w_switch_to_interrupt)
838
                        new_pc <= 1'b1;
839
                else if (w_release_from_interrupt)
840
                        new_pc <= 1'b1;
841
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
842
                        new_pc <= 1'b1;
843
                else if ((i_halt)&&(i_dbg_we)
844
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
845
                        new_pc <= 1'b1;
846
                else
847
                        new_pc <= 1'b0;
848
 
849
        //
850
        // The debug interface
851
        always @(posedge i_clk)
852
                begin
853
                        o_dbg_reg <= regset[i_dbg_reg];
854
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
855
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
856
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
857
                                o_dbg_reg <= { 25'h00, step, gie, sleep,
858
                                        ((i_dbg_reg[4])?flags:iflags) };
859
                end
860
        always @(posedge i_clk)
861
                o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy)
862
                        ||((~opvalid)&&(~i_rst))
863
                        ||((~dcdvalid)&&(~i_rst));
864
 
865
        //
866
        //
867
        // Produce accounting outputs: Account for any CPU stalls, so we can
868
        // later evaluate how well we are doing.
869
        //
870
        //
871 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
872
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
873
        assign  o_i_count  = alu_pc_valid;
874 2 dgisselq
endmodule

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