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///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, there are only 16 instruction types supported.
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory. 
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//
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//              2. Instruction Decode
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//
23
//              3. Read Operands
24
//
25
//              4. Apply Instruction
26
//
27
//              4. Write-back Results
28
//
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//      Further information about the inner workings of this CPU may be
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//      found in the spec.pdf file.  (The documentation within this file
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//      had become out of date and out of sync with the spec.pdf, so look
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//      to the spec.pdf for accurate and up to date information.)
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//
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//
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//      In general, the pipelining is controlled by three pieces of logic
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//      per stage: _ce, _stall, and _valid.  _valid means that the stage
37
//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
40
//      The difference between these control signals allows individual stages
41
//      to propagate instructions independently.  In general, the logic works
42
//      as:
43
//
44
//
45
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
46
//
47
//
48
//      always @(posedge i_clk)
49
//              if ((i_rst)||(clear_pipeline))
50
//                      (n)_valid = 0
51
//              else if (n)_ce
52
//                      (n)_valid = 1
53
//              else if (n+1)_ce
54
//                      (n)_valid = 0
55
//
56
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
57
//                      || (  (n)_valid && (n+1)_stall );
58
//
59
//      and ...
60
//
61
//      always @(posedge i_clk)
62
//              if (n)_ce
63
//                      (n)_variable = ... whatever logic for this stage
64
//
65
//      Note that a stage can stall even if no instruction is loaded into
66
//      it.
67
//
68
//
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// Creator:     Dan Gisselquist, Ph.D.
70 69 dgisselq
//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
73
//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
84
// for more details.
85
//
86
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
89
//
90
///////////////////////////////////////////////////////////////////////////////
91
//
92 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
93
// fetches are more complicated and therefore use more FPGA resources, while
94
// single fetches will cause the CPU to stall for about 5 stalls each 
95
// instruction cycle, effectively reducing the instruction count per clock to
96
// about 0.2.  However, the area cost may be worth it.  Consider:
97
//
98
//      Slice LUTs              ZipSystem       ZipCPU
99
//      Single Fetching         2521            1734
100
//      Pipelined fetching      2796            2046
101
//
102
//
103
//
104 25 dgisselq
`define CPU_CC_REG      4'he
105 2 dgisselq
`define CPU_PC_REG      4'hf
106 69 dgisselq
`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
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`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
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// Compile time defines
116 56 dgisselq
//
117
`include "cpudefs.v"
118
//
119 65 dgisselq
//
120 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
122 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
125
                // CPU interface to the wishbone bus
126 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
128
                        o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_data,
130 36 dgisselq
                        i_wb_err,
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                // Accounting/CPU usage interface
132 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
137 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
138 69 dgisselq
                        LGICACHE=6;
139 56 dgisselq
`ifdef  OPT_MULTIPLY
140
        parameter       IMPLEMENT_MPY = 1;
141
`else
142
        parameter       IMPLEMENT_MPY = 0;
143
`endif
144 71 dgisselq
`ifdef  OPT_DIVIDE
145
        parameter       IMPLEMENT_DIVIDE = 1;
146
`else
147
        parameter       IMPLEMENT_DIVIDE = 0;
148
`endif
149
`ifdef  OPT_IMPLEMENT_FPU
150
        parameter       IMPLEMENT_FPU = 1,
151
`else
152
        parameter       IMPLEMENT_FPU = 0,
153
`endif
154 69 dgisselq
                        IMPLEMENT_LOCK=1;
155
`ifdef  OPT_EARLY_BRANCHING
156
        parameter       EARLY_BRANCHING = 1;
157
`else
158
        parameter       EARLY_BRANCHING = 0;
159
`endif
160
        parameter       AW=ADDRESS_WIDTH;
161 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
162
        // Debug interface -- inputs
163 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
164 2 dgisselq
        input           [4:0]    i_dbg_reg;
165
        input                   i_dbg_we;
166
        input           [31:0]   i_dbg_data;
167
        // Debug interface -- outputs
168
        output  reg             o_dbg_stall;
169
        output  reg     [31:0]   o_dbg_reg;
170 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
171 2 dgisselq
        output  wire            o_break;
172
        // Wishbone interface -- outputs
173 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
174
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
175 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
176
        output  wire    [31:0]   o_wb_data;
177 2 dgisselq
        // Wishbone interface -- inputs
178
        input                   i_wb_ack, i_wb_stall;
179
        input           [31:0]   i_wb_data;
180 36 dgisselq
        input                   i_wb_err;
181 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
182 9 dgisselq
        output  wire            o_op_stall;
183 2 dgisselq
        output  wire            o_pf_stall;
184 9 dgisselq
        output  wire            o_i_count;
185 56 dgisselq
        //
186 65 dgisselq
`ifdef  DEBUG_SCOPE
187 56 dgisselq
        output  reg     [31:0]   o_debug;
188 65 dgisselq
`endif
189 2 dgisselq
 
190 25 dgisselq
 
191 2 dgisselq
        // Registers
192 56 dgisselq
        //
193
        //      The distributed RAM style comment is necessary on the
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        // SPARTAN6 with XST to prevent XST from oversimplifying the register
195
        // set and in the process ruining everything else.  It basically
196
        // optimizes logic away, to where it no longer works.  The logic
197
        // as described herein will work, this just makes sure XST implements
198
        // that logic.
199
        //
200
        (* ram_style = "distributed" *)
201 2 dgisselq
        reg     [31:0]   regset [0:31];
202 9 dgisselq
 
203
        // Condition codes
204 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
205
        reg     [3:0]    flags, iflags;
206 83 dgisselq
        wire    [13:0]   w_uflags, w_iflags;
207 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
208 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
209 65 dgisselq
        reg             ill_err_u, ill_err_i;
210 38 dgisselq
`else
211 65 dgisselq
        wire            ill_err_u, ill_err_i;
212 36 dgisselq
`endif
213 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
214 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
215
        wire            ifpu_err_flag, ufpu_err_flag;
216
        wire            ihalt_phase, uhalt_phase;
217 2 dgisselq
 
218 9 dgisselq
        // The master chip enable
219
        wire            master_ce;
220 2 dgisselq
 
221
        //
222
        //
223
        //      PIPELINE STAGE #1 :: Prefetch
224
        //              Variable declarations
225
        //
226 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
227 69 dgisselq
        reg     new_pc;
228 18 dgisselq
        wire    clear_pipeline;
229 69 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
230 9 dgisselq
 
231
        wire            dcd_stalled;
232 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
233 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
234
        wire    [31:0]           pf_data;
235
        wire    [31:0]           instruction;
236
        wire    [(AW-1):0]       instruction_pc;
237 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
238 2 dgisselq
 
239
        //
240
        //
241
        //      PIPELINE STAGE #2 :: Instruction Decode
242
        //              Variable declarations
243
        //
244
        //
245 83 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu;
246 69 dgisselq
        reg             opvalid_div, opvalid_fpu;
247
        wire            op_stall, dcd_ce, dcd_phase;
248
        wire    [3:0]    dcdOp;
249
        wire    [4:0]    dcdA, dcdB, dcdR;
250
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
251
        wire    [3:0]    dcdF;
252
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
253
                                dcdALU, dcdM, dcdDV, dcdFP,
254 71 dgisselq
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
255
                                dcd_pipe;
256 69 dgisselq
        reg             r_dcdvalid;
257
        wire            dcdvalid;
258
        wire    [(AW-1):0]       dcd_pc;
259
        wire    [31:0]   dcdI;
260
        wire            dcd_zI; // true if dcdI == 0
261 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
262
 
263 69 dgisselq
        wire    dcd_illegal;
264
        wire                    dcd_early_branch;
265 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
266 2 dgisselq
 
267
 
268
        //
269
        //
270
        //      PIPELINE STAGE #3 :: Read Operands
271
        //              Variable declarations
272
        //
273
        //
274
        //
275
        // Now, let's read our operands
276
        reg     [4:0]    alu_reg;
277
        reg     [3:0]    opn;
278
        reg     [4:0]    opR;
279 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
280
        reg     [(AW-1):0]       op_pc;
281 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
282 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
283 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
284 83 dgisselq
        wire    [13:0]   opFl;
285 56 dgisselq
        reg     [5:0]    r_opF;
286
        wire    [7:0]    opF;
287 69 dgisselq
        wire            op_ce, op_phase;
288 56 dgisselq
        // Some pipeline control wires
289 69 dgisselq
`ifdef  OPT_PIPELINED
290 56 dgisselq
        reg     opA_alu, opA_mem;
291
        reg     opB_alu, opB_mem;
292
`endif
293 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
294 36 dgisselq
        reg     op_illegal;
295
`endif
296 69 dgisselq
        reg     op_break;
297
        wire    op_lock;
298 2 dgisselq
 
299
 
300
        //
301
        //
302
        //      PIPELINE STAGE #4 :: ALU / Memory
303
        //              Variable declarations
304
        //
305
        //
306 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
307 69 dgisselq
        reg             alu_pc_valid;
308
        wire            alu_phase;
309 2 dgisselq
        wire            alu_ce, alu_stall;
310
        wire    [31:0]   alu_result;
311
        wire    [3:0]    alu_flags;
312 71 dgisselq
        wire            alu_valid, alu_busy;
313 2 dgisselq
        wire            set_cond;
314
        reg             alu_wr, alF_wr, alu_gie;
315 56 dgisselq
        wire            alu_illegal_op;
316 38 dgisselq
        wire            alu_illegal;
317 2 dgisselq
 
318
 
319
 
320
        wire    mem_ce, mem_stalled;
321 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
322
        wire    mem_pipe_stalled;
323
`endif
324 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
325
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
326 48 dgisselq
        wire    [4:0]            mem_wreg;
327 9 dgisselq
 
328 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
329
        wire    [(AW-1):0]       mem_addr;
330
        wire    [31:0]           mem_data, mem_result;
331 2 dgisselq
 
332 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
333
        wire    [31:0]   div_result;
334
        wire    [3:0]    div_flags;
335 2 dgisselq
 
336 69 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
337
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
338
                                &&(set_cond);
339 2 dgisselq
 
340 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
341
        wire    [31:0]   fpu_result;
342
        wire    [3:0]    fpu_flags;
343
 
344
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
345
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
346
                                &&(set_cond);
347
 
348
 
349 2 dgisselq
        //
350
        //
351
        //      PIPELINE STAGE #5 :: Write-back
352
        //              Variable declarations
353
        //
354 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
355 2 dgisselq
        wire    [4:0]    wr_reg_id;
356
        wire    [31:0]   wr_reg_vl;
357
        wire    w_switch_to_interrupt, w_release_from_interrupt;
358 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
359 2 dgisselq
 
360
 
361
 
362
        //
363
        //      MASTER: clock enable.
364
        //
365 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
366 2 dgisselq
 
367
 
368
        //
369
        //      PIPELINE STAGE #1 :: Prefetch
370
        //              Calculate stall conditions
371 65 dgisselq
        //
372
        //      These are calculated externally, within the prefetch module.
373
        //
374 2 dgisselq
 
375
        //
376
        //      PIPELINE STAGE #2 :: Instruction Decode
377
        //              Calculate stall conditions
378 69 dgisselq
`ifdef  OPT_PIPELINED
379
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
380
`else
381
        assign          dcd_ce = 1'b1;
382
`endif
383
`ifdef  OPT_PIPELINED
384
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
385
`else
386
        // If not pipelined, there will be no opvalid_ anything, and the
387
        // op_stall will be false, dcdX_stall will be false, thus we can simply
388
        // do a ...
389
        assign          dcd_stalled = 1'b0;
390
`endif
391 2 dgisselq
        //
392
        //      PIPELINE STAGE #3 :: Read Operands
393
        //              Calculate stall conditions
394 69 dgisselq
        wire    op_lock_stall;
395
`ifdef  OPT_PIPELINED
396
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
397
                        // Stall if we're stopped, and not allowed to execute
398
                        // an instruction
399
                        // (~master_ce)         // Already captured in alu_stall
400
                        //
401 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
402
                        //      i.e. if the memory is busy, or we are single
403 69 dgisselq
                        //      stepping.  This also includes our stalls for
404
                        //      op_break and op_lock, so we don't need to
405
                        //      include those as well here.
406 83 dgisselq
                        // This also includes whether or not the divide or
407
                        // floating point units are busy.
408
                        (alu_stall)
409 56 dgisselq
                        //
410
                        // Stall if we are going into memory with an operation
411
                        //      that cannot be pipelined, and the memory is
412
                        //      already busy
413 83 dgisselq
                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
414 69 dgisselq
                        )
415
                        ||(dcdvalid)&&(
416 71 dgisselq
                                // Stall if we need to wait for an operand A
417 69 dgisselq
                                // to be ready to read
418 71 dgisselq
                                (dcdA_stall)
419 69 dgisselq
                                // Likewise for B, also includes logic
420
                                // regarding immediate offset (register must
421
                                // be in register file if we need to add to
422
                                // an immediate)
423
                                ||(dcdB_stall)
424
                                // Or if we need to wait on flags to work on the
425
                                // CC register
426
                                ||(dcdF_stall)
427
                        );
428 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
429 65 dgisselq
`else
430 69 dgisselq
        assign  op_stall = (opvalid)&&(~master_ce);
431 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal));
432 65 dgisselq
`endif
433 2 dgisselq
 
434
        //
435
        //      PIPELINE STAGE #4 :: ALU / Memory
436
        //              Calculate stall conditions
437 36 dgisselq
        //
438
        // 1. Basic stall is if the previous stage is valid and the next is
439
        //      busy.  
440
        // 2. Also stall if the prior stage is valid and the master clock enable
441
        //      is de-selected
442 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
443
        //      since we don't know if it'll put us to sleep or not.
444 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
445
        //      through the ALU.  Break instructions are not allowed through
446
        //      the ALU.
447 69 dgisselq
`ifdef  OPT_PIPELINED
448 71 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
449 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
450
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
451
                                &&(wr_write_cc)) // Case 3
452 69 dgisselq
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
453
                        ||((opvalid)&&(op_break))
454
                        ||(div_busy)||(fpu_busy);
455 71 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
456 69 dgisselq
                                &&(~alu_stall)
457
                                &&(~clear_pipeline);
458
`else
459
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
460
                                ||((opvalid_alu)&&(op_break));
461 71 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall);
462 69 dgisselq
`endif
463 2 dgisselq
        //
464 65 dgisselq
 
465
        //
466
        // Note: if you change the conditions for mem_ce, you must also change
467
        // alu_pc_valid.
468
        //
469 69 dgisselq
`ifdef  OPT_PIPELINED
470
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
471 71 dgisselq
                        &&(~clear_pipeline);
472 69 dgisselq
`else
473
        // If we aren't pipelined, then no one will be changing what's in the
474
        // pipeline (i.e. clear_pipeline), while our only instruction goes
475
        // through the ... pipeline.
476 71 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled);
477 69 dgisselq
`endif
478 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
479 71 dgisselq
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
480 38 dgisselq
                                (mem_pipe_stalled)
481
                                ||((~op_pipe)&&(mem_busy))
482 69 dgisselq
                                ||(div_busy)
483
                                ||(fpu_busy)
484 38 dgisselq
                                // Stall waiting for flags to be valid
485
                                // Or waiting for a write to the PC register
486
                                // Or CC register, since that can change the
487
                                //  PC as well
488
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
489
                                        &&((wr_write_pc)||(wr_write_cc)))));
490
`else
491 69 dgisselq
`ifdef  OPT_PIPELINED
492 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
493 2 dgisselq
                                (~master_ce)
494
                                // Stall waiting for flags to be valid
495
                                // Or waiting for a write to the PC register
496 25 dgisselq
                                // Or CC register, since that can change the
497
                                //  PC as well
498
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
499 69 dgisselq
`else
500
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
501 38 dgisselq
`endif
502 69 dgisselq
`endif
503 2 dgisselq
 
504
 
505
        //
506
        //
507
        //      PIPELINE STAGE #1 :: Prefetch
508
        //
509
        //
510 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
511 9 dgisselq
        wire            pf_ce;
512
 
513 69 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
514 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
515 69 dgisselq
                        pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
516 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
517 36 dgisselq
                                        pf_valid, pf_illegal,
518
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
519
                                pf_ack, pf_stall, pf_err, i_wb_data);
520 69 dgisselq
 
521
        initial r_dcdvalid = 1'b0;
522
        always @(posedge i_clk)
523
                if (i_rst)
524
                        r_dcdvalid <= 1'b0;
525
                else if (dcd_ce)
526
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
527
                else if ((op_ce)||(clear_pipeline))
528
                        r_dcdvalid <= 1'b0;
529
        assign  dcdvalid = r_dcdvalid;
530
 
531 2 dgisselq
`else // Pipe fetch
532 69 dgisselq
 
533
`ifdef  OPT_TRADITIONAL_PFCACHE
534
        pfcache #(LGICACHE, ADDRESS_WIDTH)
535
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
536
                                        i_clear_pf_cache,
537
                                // dcd_pc,
538
                                ~dcd_stalled,
539
                                ((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
540
                                        ? dcd_branch_pc:pf_pc,
541
                                instruction, instruction_pc, pf_valid,
542
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
543
                                        pf_ack, pf_stall, pf_err, i_wb_data,
544
                                pf_illegal);
545
`else
546 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
547 69 dgisselq
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
548 36 dgisselq
                                        i_clear_pf_cache, ~dcd_stalled,
549
                                        (new_pc)?pf_pc:dcd_branch_pc,
550 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
551
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
552 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
553 69 dgisselq
//`ifdef        OPT_PRECLEAR_BUS
554
                                //((dcd_clear_bus)&&(dcdvalid))
555
                                //||((op_clear_bus)&&(opvalid))
556
                                //||
557
//`endif
558 36 dgisselq
                                (mem_cyc_lcl)||(mem_cyc_gbl),
559
                                pf_illegal);
560 69 dgisselq
`endif
561 2 dgisselq
        assign  instruction_gie = gie;
562
 
563 69 dgisselq
        initial r_dcdvalid = 1'b0;
564 2 dgisselq
        always @(posedge i_clk)
565 69 dgisselq
                if ((i_rst)||(clear_pipeline))
566
                        r_dcdvalid <= 1'b0;
567 2 dgisselq
                else if (dcd_ce)
568 69 dgisselq
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
569
                else if (op_ce)
570
                        r_dcdvalid <= 1'b0;
571
        assign  dcdvalid = r_dcdvalid;
572 36 dgisselq
`endif
573 2 dgisselq
 
574 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
575
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
576
                        IMPLEMENT_FPU)
577
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
578
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
579
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
580
                        dcd_illegal, dcd_pc, dcd_gie,
581
                        { dcdR_cc, dcdR_pc, dcdR },
582
                        { dcdA_cc, dcdA_pc, dcdA },
583
                        { dcdB_cc, dcdB_pc, dcdB },
584
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
585
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
586
                        dcdR_wr,dcdA_rd, dcdB_rd,
587
                        dcd_early_branch,
588 71 dgisselq
                        dcd_branch_pc,
589
                        dcd_pipe);
590 36 dgisselq
`else
591 69 dgisselq
        idecode_deprecated
592
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
593
                        IMPLEMENT_FPU)
594
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
595
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
596
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
597
                        dcd_illegal, dcd_pc, dcd_gie,
598
                        { dcdR_cc, dcdR_pc, dcdR },
599
                        { dcdA_cc, dcdA_pc, dcdA },
600
                        { dcdB_cc, dcdB_pc, dcdB },
601
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
602
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
603
                        dcdR_wr,dcdA_rd, dcdB_rd,
604
                        dcd_early_branch,
605 71 dgisselq
                        dcd_branch_pc,
606
                        dcd_pipe);
607 36 dgisselq
`endif
608 2 dgisselq
 
609 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
610
        reg             op_pipe;
611 2 dgisselq
 
612 38 dgisselq
        initial op_pipe = 1'b0;
613
        // To be a pipeable operation, there must be 
614
        //      two valid adjacent instructions
615
        //      Both must be memory instructions
616
        //      Both must be writes, or both must be reads
617
        //      Both operations must be to the same identical address,
618
        //              or at least a single (one) increment above that address
619 71 dgisselq
        //
620
        // However ... we need to know this before this clock, hence this is
621
        // calculated in the instruction decoder.
622 38 dgisselq
        always @(posedge i_clk)
623
                if (op_ce)
624 71 dgisselq
                        op_pipe <= dcd_pipe;
625 38 dgisselq
`endif
626
 
627 2 dgisselq
        //
628
        //
629
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
630
        //
631
        //
632 25 dgisselq
        assign  w_opA = regset[dcdA];
633
        assign  w_opB = regset[dcdB];
634 56 dgisselq
 
635
        wire    [31:0]   w_pcA_v;
636
        generate
637
        if (AW < 32)
638
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
639
        else
640
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
641
        endgenerate
642 71 dgisselq
 
643
`ifdef  OPT_PIPELINED
644
        reg     [4:0]    opA_id, opB_id;
645
        reg             opA_rd, opB_rd;
646 2 dgisselq
        always @(posedge i_clk)
647 71 dgisselq
                if (op_ce)
648
                begin
649
                        opA_id <= dcdA;
650
                        opB_id <= dcdB;
651
                        opA_rd <= dcdA_rd;
652
                        opB_rd <= dcdB_rd;
653
                end
654
`endif
655
 
656
        always @(posedge i_clk)
657 2 dgisselq
                if (op_ce) // &&(dcdvalid))
658
                begin
659
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
660
                                r_opA <= wr_reg_vl;
661 25 dgisselq
                        else if (dcdA_pc)
662 56 dgisselq
                                r_opA <= w_pcA_v;
663 25 dgisselq
                        else if (dcdA_cc)
664 83 dgisselq
                                r_opA <= { w_opA[31:14], (dcdA[4])?w_uflags:w_iflags };
665 2 dgisselq
                        else
666 25 dgisselq
                                r_opA <= w_opA;
667 69 dgisselq
`ifdef  OPT_PIPELINED
668 71 dgisselq
                end else
669 48 dgisselq
                begin // We were going to pick these up when they became valid,
670
                        // but for some reason we're stuck here as they became
671
                        // valid.  Pick them up now anyway
672 71 dgisselq
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
673
                                // r_opA <= wr_reg_vl;
674
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
675 48 dgisselq
                                r_opA <= wr_reg_vl;
676 56 dgisselq
`endif
677 2 dgisselq
                end
678 56 dgisselq
 
679 69 dgisselq
        wire    [31:0]   w_opBnI, w_pcB_v;
680 56 dgisselq
        generate
681
        if (AW < 32)
682
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
683
        else
684
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
685
        endgenerate
686
 
687 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
688 56 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
689
                : ((dcdB_pc) ? w_pcB_v
690 83 dgisselq
                : ((dcdB_cc) ? { w_opB[31:14], (dcdB[4])?w_uflags:w_iflags}
691 56 dgisselq
                : w_opB)));
692
 
693 2 dgisselq
        always @(posedge i_clk)
694
                if (op_ce) // &&(dcdvalid))
695 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
696 69 dgisselq
`ifdef  OPT_PIPELINED
697 71 dgisselq
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
698 48 dgisselq
                        r_opB <= wr_reg_vl;
699 56 dgisselq
`endif
700 2 dgisselq
 
701
        // The logic here has become more complex than it should be, no thanks
702
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
703
        // be two sets of four bits: the top bits specify what bits matter, the
704
        // bottom specify what those top bits must equal.  However, two of
705
        // conditions check whether bits are on, and those are the only two
706
        // conditions checking those bits.  Therefore, Vivado complains that
707
        // these two bits are redundant.  Hence the convoluted expression
708
        // below, arriving at what we finally want in the (now wire net)
709
        // opF.
710
        always @(posedge i_clk)
711
                if (op_ce)
712 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
713 2 dgisselq
                        case(dcdF[2:0])
714 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
715 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
716
                        // These were remapped as part of the new instruction
717
                        // set in order to make certain that the low order
718
                        // two bits contained the most commonly used 
719
                        // conditions: Always, LT, Z, and NZ.
720
                        3'h1:   r_opF <= 6'h24; // LT
721
                        3'h2:   r_opF <= 6'h11; // Z
722
                        3'h3:   r_opF <= 6'h10; // NE
723
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
724
                        3'h5:   r_opF <= 6'h20; // GE (!N)
725
`else
726 56 dgisselq
                        3'h1:   r_opF <= 6'h11; // Z
727
                        3'h2:   r_opF <= 6'h10; // NE
728
                        3'h3:   r_opF <= 6'h20; // GE (!N)
729
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
730
                        3'h5:   r_opF <= 6'h24; // LT
731 69 dgisselq
`endif
732 56 dgisselq
                        3'h6:   r_opF <= 6'h02; // C
733
                        3'h7:   r_opF <= 6'h08; // V
734 2 dgisselq
                        endcase
735 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
736 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
737 2 dgisselq
 
738 69 dgisselq
        wire    w_opvalid;
739
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid);
740 36 dgisselq
        initial opvalid     = 1'b0;
741
        initial opvalid_alu = 1'b0;
742
        initial opvalid_mem = 1'b0;
743 91 dgisselq
        initial opvalid_div = 1'b0;
744
        initial opvalid_fpu = 1'b0;
745 2 dgisselq
        always @(posedge i_clk)
746
                if (i_rst)
747 25 dgisselq
                begin
748
                        opvalid     <= 1'b0;
749
                        opvalid_alu <= 1'b0;
750
                        opvalid_mem <= 1'b0;
751
                end else if (op_ce)
752
                begin
753 2 dgisselq
                        // Do we have a valid instruction?
754
                        //   The decoder may vote to stall one of its
755
                        //   instructions based upon something we currently
756
                        //   have in our queue.  This instruction must then
757
                        //   move forward, and get a stall cycle inserted.
758
                        //   Hence, the test on dcd_stalled here.  If we must
759
                        //   wait until our operands are valid, then we aren't
760
                        //   valid yet until then.
761 69 dgisselq
                        opvalid<= w_opvalid;
762 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
763 69 dgisselq
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
764
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
765
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
766
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
767 36 dgisselq
`else
768 69 dgisselq
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
769
                        opvalid_mem <= (dcdM)&&(w_opvalid);
770
                        opvalid_div <= (dcdDV)&&(w_opvalid);
771
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
772 36 dgisselq
`endif
773 69 dgisselq
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
774 25 dgisselq
                begin
775
                        opvalid     <= 1'b0;
776
                        opvalid_alu <= 1'b0;
777
                        opvalid_mem <= 1'b0;
778 69 dgisselq
                        opvalid_div <= 1'b0;
779
                        opvalid_fpu <= 1'b0;
780 25 dgisselq
                end
781 2 dgisselq
 
782
        // Here's part of our debug interface.  When we recognize a break
783
        // instruction, we set the op_break flag.  That'll prevent this
784
        // instruction from entering the ALU, and cause an interrupt before
785
        // this instruction.  Thus, returning to this code will cause the
786
        // break to repeat and continue upon return.  To get out of this
787
        // condition, replace the break instruction with what it is supposed
788
        // to be, step through it, and then replace it back.  In this fashion,
789
        // a debugger can step through code.
790 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
791
        initial op_break = 1'b0;
792 2 dgisselq
        always @(posedge i_clk)
793 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
794
                else if (op_ce) op_break <= (dcd_break);
795
                else if ((clear_pipeline)||(~opvalid))
796
                                op_break <= 1'b0;
797 2 dgisselq
 
798 69 dgisselq
`ifdef  OPT_PIPELINED
799
        generate
800
        if (IMPLEMENT_LOCK != 0)
801
        begin
802
                reg     r_op_lock, r_op_lock_stall;
803
 
804
                initial r_op_lock_stall = 1'b0;
805
                always @(posedge i_clk)
806
                        if (i_rst)
807
                                r_op_lock_stall <= 1'b0;
808
                        else
809
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
810
                                                ||(~dcdvalid)||(~pf_valid);
811
 
812
                assign  op_lock_stall = r_op_lock_stall;
813
 
814
                initial r_op_lock = 1'b0;
815
                always @(posedge i_clk)
816
                        if (i_rst)
817
                                r_op_lock <= 1'b0;
818
                        else if ((op_ce)&&(dcd_lock))
819
                                r_op_lock <= 1'b1;
820
                        else if ((op_ce)||(clear_pipeline))
821
                                r_op_lock <= 1'b0;
822
                assign  op_lock = r_op_lock;
823
 
824
        end else begin
825
                assign  op_lock_stall = 1'b0;
826
                assign  op_lock = 1'b0;
827
        end endgenerate
828
 
829
`else
830
        assign op_lock_stall = 1'b0;
831
        assign op_lock       = 1'b0;
832
`endif
833
 
834 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
835 71 dgisselq
        initial op_illegal = 1'b0;
836 2 dgisselq
        always @(posedge i_clk)
837 71 dgisselq
                if ((i_rst)||(clear_pipeline))
838
                        op_illegal <= 1'b0;
839
                else if(op_ce)
840 69 dgisselq
`ifdef  OPT_PIPELINED
841
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
842
`else
843
                        op_illegal <= (dcd_illegal)||(dcd_lock);
844 36 dgisselq
`endif
845 69 dgisselq
`endif
846 36 dgisselq
 
847 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
848
        // set, dcd_early_branch will simply be a wire connected to zero and
849
        // this logic should just optimize.
850
        always @(posedge i_clk)
851
                if (op_ce)
852
                begin
853 83 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
854
                                &&(~dcd_early_branch)&&(~dcd_illegal);
855
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
856 71 dgisselq
                end
857 69 dgisselq
 
858 36 dgisselq
        always @(posedge i_clk)
859 2 dgisselq
                if (op_ce)
860
                begin
861
                        opn    <= dcdOp;        // Which ALU operation?
862 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
863 2 dgisselq
                        // What register will these results be written into?
864 69 dgisselq
                        opR    <= dcdR;
865
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
866 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
867
                        op_gie <= dcd_gie;
868
 
869 69 dgisselq
 
870 2 dgisselq
                        //
871 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
872 2 dgisselq
                end
873
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
874
 
875 69 dgisselq
`ifdef  OPT_VLIW
876
        reg     r_op_phase;
877
        initial r_op_phase = 1'b0;
878
        always @(posedge i_clk)
879
                if ((i_rst)||(clear_pipeline))
880
                        r_op_phase <= 1'b0;
881
                else if (op_ce)
882
                        r_op_phase <= dcd_phase;
883
        assign  op_phase = r_op_phase;
884
`else
885
        assign  op_phase = 1'b0;
886
`endif
887
 
888 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
889
        // register set but in special registers of their own.  So step one
890
        // is to select the right register.  Step to is to replace that
891
        // register with the results of an ALU or memory operation, if such
892
        // results are now available.  Otherwise, we'd need to insert a wait
893
        // state of some type.
894
        //
895
        // The alternative approach would be to define some sort of
896
        // op_stall wire, which would stall any upstream stage.
897
        // We'll create a flag here to start our coordination.  Once we
898
        // define this flag to something other than just plain zero, then
899
        // the stalls will already be in place.
900 69 dgisselq
`ifdef  OPT_PIPELINED
901 83 dgisselq
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
902 71 dgisselq
                        ?  wr_reg_vl : r_opA;
903 56 dgisselq
`else
904
        assign  opA = r_opA;
905
`endif
906 48 dgisselq
 
907 69 dgisselq
`ifdef  OPT_PIPELINED
908 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
909
        //      AND ... something that may write a register is running
910
        //      AND (series of conditions here ...)
911
        //              The operation might set flags, and we wish to read the
912
        //                      CC register
913
        //              OR ... (No other conditions)
914
        assign  dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
915
                                &&((opvalid)||(mem_rdbusy)
916
                                        ||(div_busy)||(fpu_busy))
917
                                &&((opF_wr)&&(dcdA_cc));
918 56 dgisselq
`else
919 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
920
        assign  dcdA_stall = 1'b0;
921 56 dgisselq
`endif
922 36 dgisselq
 
923 69 dgisselq
`ifdef  OPT_PIPELINED
924 71 dgisselq
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
925
                        ? wr_reg_vl: r_opB;
926 56 dgisselq
`else
927
        assign  opB = r_opB;
928
`endif
929
 
930 69 dgisselq
`ifdef  OPT_PIPELINED
931 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
932
        //      AND ... something that may write a (unknown) register is running
933
        //      AND (series of conditions here ...)
934
        //              The operation might set flags, and we wish to read the
935
        //                      CC register
936
        //              OR the operation might set register B, and we still need
937
        //                      a clock to add the offset to it
938
        assign  dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
939
                                // If the op stage isn't valid, yet something
940
                                // is running, then it must have been valid.
941
                                // We'll use the last values from that stage
942
                                // (opR_wr, opF_wr, opR) in our logic below.
943
                                &&((opvalid)||(mem_rdbusy)
944
                                        ||(div_busy)||(fpu_busy))
945
                                &&(
946 38 dgisselq
                                // Stall on memory ops writing to my register
947
                                //      (i.e. loads), or on any write to my
948
                                //      register if I have an immediate offset
949
                                // Note the exception for writing to the PC:
950
                                //      if I write to the PC, the whole next
951
                                //      instruction is invalid, not just the
952
                                //      operand.  That'll get wiped in the
953
                                //      next operation anyway, so don't stall
954 83 dgisselq
                                //      here.  This keeps a BC X, BNZ Y from
955
                                //      stalling between the two branches.
956
                                //      BC X, BRA Y is still clear, since BRA Y
957
                                //      is an early branch instruction.
958
                                //      (This exception is commented out in
959
                                //      order to help keep our logic simple, and
960
                                //      because multiple conditional branches
961
                                //      following each other constitutes a
962
                                //      fairly unusualy code structure.)
963
                                //      
964
                                ((~dcd_zI)&&(opR == dcdB)&&(opR_wr))
965
                                        // &&(opR != { op_gie, `CPU_PC_REG } )
966
                                // Stall following any instruction that will
967
                                // set the flags, if we're going to need the
968
                                // flags (CC) register for opB.
969
                                ||((opF_wr)&&(dcdB_cc))
970 38 dgisselq
                                // Stall on any ongoing memory operation that
971 71 dgisselq
                                // will write to opB -- captured above
972
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
973
                                );
974 91 dgisselq
        assign  dcdF_stall = ((~dcdF[3])
975
                                        ||((dcdA_rd)&&(dcdA_cc))
976
                                        ||((dcdB_rd)&&(dcdB_cc)))
977
                                        &&(opvalid)&&(opR_cc);
978
                                // &&(dcdvalid) is checked for elsewhere
979 56 dgisselq
`else
980 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
981
        // hazard without the pipeline?
982
        assign  dcdB_stall = 1'b0;
983 91 dgisselq
        assign  dcdF_stall = 1'b0;
984 56 dgisselq
`endif
985 2 dgisselq
        //
986
        //
987
        //      PIPELINE STAGE #4 :: Apply Instruction
988
        //
989
        //
990 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
991 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
992 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
993 71 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op,
994
                        alu_busy);
995 69 dgisselq
`else
996
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
997
                        (opvalid_alu), opn, opA, opB,
998
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
999 71 dgisselq
        assign  alu_busy = 1'b0;
1000 69 dgisselq
`endif
1001 2 dgisselq
 
1002 69 dgisselq
        generate
1003
        if (IMPLEMENT_DIVIDE != 0)
1004
        begin
1005 83 dgisselq
                div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
1006 69 dgisselq
                        opA, opB, div_busy, div_valid, div_error, div_result,
1007
                        div_flags);
1008
        end else begin
1009
                assign  div_error = 1'b1;
1010
                assign  div_busy  = 1'b0;
1011
                assign  div_valid = 1'b0;
1012
                assign  div_result= 32'h00;
1013
                assign  div_flags = 4'h0;
1014
        end endgenerate
1015
 
1016
        generate
1017
        if (IMPLEMENT_FPU != 0)
1018
        begin
1019
                //
1020
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1021
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1022
                //      fpu_flags);
1023
                //
1024
                assign  fpu_error = 1'b1;
1025
                assign  fpu_busy  = 1'b0;
1026
                assign  fpu_valid = 1'b0;
1027
                assign  fpu_result= 32'h00;
1028
                assign  fpu_flags = 4'h0;
1029
        end else begin
1030
                assign  fpu_error = 1'b1;
1031
                assign  fpu_busy  = 1'b0;
1032
                assign  fpu_valid = 1'b0;
1033
                assign  fpu_result= 32'h00;
1034
                assign  fpu_flags = 4'h0;
1035
        end endgenerate
1036
 
1037
 
1038 2 dgisselq
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1039
        initial alF_wr   = 1'b0;
1040
        initial alu_wr   = 1'b0;
1041
        always @(posedge i_clk)
1042
                if (i_rst)
1043
                begin
1044
                        alu_wr   <= 1'b0;
1045
                        alF_wr   <= 1'b0;
1046
                end else if (alu_ce)
1047
                begin
1048 65 dgisselq
                        // alu_reg <= opR;
1049 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1050
                        alF_wr  <= (opF_wr)&&(set_cond);
1051 71 dgisselq
                end else if (~alu_busy) begin
1052 2 dgisselq
                        // These are strobe signals, so clear them if not
1053
                        // set for any particular clock
1054 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1055 2 dgisselq
                        alF_wr <= 1'b0;
1056
                end
1057 69 dgisselq
 
1058
`ifdef  OPT_VLIW
1059
        reg     r_alu_phase;
1060
        initial r_alu_phase = 1'b0;
1061 2 dgisselq
        always @(posedge i_clk)
1062 69 dgisselq
                if (i_rst)
1063
                        r_alu_phase <= 1'b0;
1064
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
1065
                        r_alu_phase <= op_phase;
1066
        assign  alu_phase = r_alu_phase;
1067
`else
1068
        assign  alu_phase = 1'b0;
1069
`endif
1070
 
1071
        always @(posedge i_clk)
1072
                if ((alu_ce)||(div_ce)||(fpu_ce))
1073 65 dgisselq
                        alu_reg <= opR;
1074
                else if ((i_halt)&&(i_dbg_we))
1075
                        alu_reg <= i_dbg_reg;
1076 69 dgisselq
 
1077 65 dgisselq
        reg     [31:0]   dbg_val;
1078
        reg             dbgv;
1079
        always @(posedge i_clk)
1080
                dbg_val <= i_dbg_data;
1081
        initial dbgv = 1'b0;
1082
        always @(posedge i_clk)
1083
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
1084
        always @(posedge i_clk)
1085 2 dgisselq
                if ((alu_ce)||(mem_ce))
1086
                        alu_gie  <= op_gie;
1087
        always @(posedge i_clk)
1088 65 dgisselq
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1089
                                &&(~mem_stalled)))
1090 2 dgisselq
                        alu_pc  <= op_pc;
1091 65 dgisselq
 
1092 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1093 56 dgisselq
        reg     r_alu_illegal;
1094
        initial r_alu_illegal = 0;
1095 38 dgisselq
        always @(posedge i_clk)
1096 71 dgisselq
                if (clear_pipeline)
1097
                        r_alu_illegal <= 1'b0;
1098
                else if ((alu_ce)||(mem_ce))
1099 56 dgisselq
                        r_alu_illegal <= op_illegal;
1100
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1101 38 dgisselq
`endif
1102
 
1103 65 dgisselq
        // This _almost_ is equal to (alu_ce)||(mem_ce).  The only
1104
        // problem is that mem_ce is gated by the set_cond, and
1105
        // the PC will be valid independent of the set condition.  Hence, this
1106
        // equals (alu_ce)||(everything in mem_ce but the set condition)
1107 2 dgisselq
        initial alu_pc_valid = 1'b0;
1108
        always @(posedge i_clk)
1109 65 dgisselq
                alu_pc_valid <= ((alu_ce)
1110
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
1111 2 dgisselq
 
1112 69 dgisselq
        wire    bus_lock;
1113
`ifdef  OPT_PIPELINED
1114
        generate
1115
        if (IMPLEMENT_LOCK != 0)
1116
        begin
1117
                reg     r_bus_lock;
1118
                initial r_bus_lock = 1'b0;
1119
                always @(posedge i_clk)
1120
                        if (i_rst)
1121
                                r_bus_lock <= 1'b0;
1122
                        else if ((op_ce)&&(op_lock))
1123
                                r_bus_lock <= 1'b1;
1124
                        else if (~opvalid_mem)
1125
                                r_bus_lock <= 1'b0;
1126
                assign  bus_lock = r_bus_lock;
1127
        end else begin
1128
                assign  bus_lock = 1'b0;
1129
        end endgenerate
1130
`else
1131
        assign  bus_lock = 1'b0;
1132
`endif
1133
 
1134 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1135 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1136 38 dgisselq
                                (opn[0]), opB, opA, opR,
1137
                                mem_busy, mem_pipe_stalled,
1138
                                mem_valid, bus_err, mem_wreg, mem_result,
1139
                        mem_cyc_gbl, mem_cyc_lcl,
1140
                                mem_stb_gbl, mem_stb_lcl,
1141
                                mem_we, mem_addr, mem_data,
1142
                                mem_ack, mem_stall, mem_err, i_wb_data);
1143
 
1144
`else // PIPELINED_BUS_ACCESS
1145 71 dgisselq
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1146 2 dgisselq
                                (opn[0]), opB, opA, opR,
1147 38 dgisselq
                                mem_busy,
1148
                                mem_valid, bus_err, mem_wreg, mem_result,
1149 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1150
                                mem_stb_gbl, mem_stb_lcl,
1151
                                mem_we, mem_addr, mem_data,
1152
                                mem_ack, mem_stall, mem_err, i_wb_data);
1153 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1154 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1155 2 dgisselq
 
1156
        // Either the prefetch or the instruction gets the memory bus, but 
1157
        // never both.
1158 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1159 36 dgisselq
                // Memory access to the arbiter, priority position
1160
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1161
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1162 2 dgisselq
                // Prefetch access to the arbiter
1163 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1164
                        pf_ack, pf_stall, pf_err,
1165 2 dgisselq
                // Common wires, in and out, of the arbiter
1166 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1167
                        o_wb_we, o_wb_addr, o_wb_data,
1168
                        i_wb_ack, i_wb_stall, i_wb_err);
1169 2 dgisselq
 
1170
        //
1171
        //
1172
        //      PIPELINE STAGE #5 :: Write-back results
1173
        //
1174
        //
1175
        // This stage is not allowed to stall.  If results are ready to be
1176
        // written back, they are written back at all cost.  Sleepy CPU's
1177
        // won't prevent write back, nor debug modes, halting the CPU, nor
1178
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1179
        // as knowinig something is available for writeback.
1180
 
1181
        //
1182
        // Write back to our generic register set ...
1183
        // When shall we write back?  On one of two conditions
1184
        //      Note that the flags needed to be checked before issuing the
1185
        //      bus instruction, so they don't need to be checked here.
1186
        //      Further, alu_wr includes (set_cond), so we don't need to
1187
        //      check for that here either.
1188 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1189 83 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&
1190
                        (((alu_wr)&&(~clear_pipeline)
1191
                                &&((alu_valid)||(div_valid)||(fpu_valid)))
1192
                        ||(mem_valid));
1193 36 dgisselq
`else
1194 69 dgisselq
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
1195 36 dgisselq
`endif
1196 2 dgisselq
        // Which register shall be written?
1197 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1198
        //              One or PC, one for CC, and one for GIE match
1199 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1200
        //      FPU operation.
1201 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1202 25 dgisselq
        // Are we writing to the CC register?
1203
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1204 2 dgisselq
        // Are we writing to the PC?
1205
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1206
        // What value to write?
1207 71 dgisselq
        assign  wr_reg_vl = ((mem_valid) ? mem_result
1208
                                :((div_valid|fpu_valid))
1209
                                        ? ((div_valid) ? div_result:fpu_result)
1210
                                :((dbgv) ? dbg_val : alu_result));
1211 2 dgisselq
        always @(posedge i_clk)
1212
                if (wr_reg_ce)
1213
                        regset[wr_reg_id] <= wr_reg_vl;
1214
 
1215
        //
1216
        // Write back to the condition codes/flags register ...
1217
        // When shall we write to our flags register?  alF_wr already
1218
        // includes the set condition ...
1219 69 dgisselq
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1220 83 dgisselq
        assign  w_uflags = { uhalt_phase, ufpu_err_flag,
1221 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1222
                        1'b0, step, 1'b1, sleep,
1223
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1224 83 dgisselq
        assign  w_iflags = { ihalt_phase, ifpu_err_flag,
1225 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1226
                        break_en, 1'b0, 1'b0, sleep,
1227
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1228 69 dgisselq
 
1229
 
1230 2 dgisselq
        // What value to write?
1231
        always @(posedge i_clk)
1232
                // If explicitly writing the register itself
1233 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1234 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1235
                // Otherwise if we're setting the flags from an ALU operation
1236
                else if ((wr_flags_ce)&&(alu_gie))
1237 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1238
                                : alu_flags);
1239 2 dgisselq
 
1240
        always @(posedge i_clk)
1241 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1242 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1243
                else if ((wr_flags_ce)&&(~alu_gie))
1244 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1245
                                : alu_flags);
1246 2 dgisselq
 
1247
        // The 'break' enable  bit.  This bit can only be set from supervisor
1248
        // mode.  It control what the CPU does upon encountering a break
1249
        // instruction.
1250
        //
1251
        // The goal, upon encountering a break is that the CPU should stop and
1252
        // not execute the break instruction, choosing instead to enter into
1253
        // either interrupt mode or halt first.  
1254
        //      if ((break_en) AND (break_instruction)) // user mode or not
1255
        //              HALT CPU
1256
        //      else if (break_instruction) // only in user mode
1257
        //              set an interrupt flag, go to supervisor mode
1258
        //              allow supervisor to step the CPU.
1259
        //      Upon a CPU halt, any break condition will be reset.  The
1260
        //      external debugger will then need to deal with whatever
1261
        //      condition has taken place.
1262
        initial break_en = 1'b0;
1263
        always @(posedge i_clk)
1264
                if ((i_rst)||(i_halt))
1265
                        break_en <= 1'b0;
1266 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1267 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1268 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1269 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1270
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1271 69 dgisselq
                                &&(~div_busy)&&(~fpu_busy)
1272 36 dgisselq
                                &&(~clear_pipeline)
1273
                        ||((~alu_gie)&&(bus_err))
1274 69 dgisselq
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1275
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
1276 71 dgisselq
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
1277 36 dgisselq
`else
1278
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1279
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1280
                                &&(~clear_pipeline))
1281 38 dgisselq
                        ||((~alu_gie)&&(bus_err));
1282 36 dgisselq
`endif
1283 2 dgisselq
 
1284
 
1285
        // The sleep register.  Setting the sleep register causes the CPU to
1286
        // sleep until the next interrupt.  Setting the sleep register within
1287
        // interrupt mode causes the processor to halt until a reset.  This is
1288 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1289
        // set the sleep bit and switch to supervisor mode in the same 
1290
        // instruction: users are not allowed to halt the CPU.
1291 2 dgisselq
        always @(posedge i_clk)
1292 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1293 2 dgisselq
                        sleep <= 1'b0;
1294 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1295
                        // In supervisor mode, we have no protections.  The
1296
                        // supervisor can set the sleep bit however he wants.
1297 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1298
                        // sleep mode shouold only be possible if the interrupt
1299
                        // flag isn't set.
1300
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
1301
                        //              don't set the sleep bit
1302
                        //      otherwise however it would o.w. be set
1303
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
1304
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
1305 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1306
                        // In user mode, however, you can only set the sleep
1307
                        // mode while remaining in user mode.  You can't switch
1308
                        // to sleep mode *and* supervisor mode at the same
1309
                        // time, lest you halt the CPU.
1310
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1311 2 dgisselq
 
1312
        always @(posedge i_clk)
1313
                if ((i_rst)||(w_switch_to_interrupt))
1314
                        step <= 1'b0;
1315 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1316 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1317 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1318 2 dgisselq
                        step <= 1'b0;
1319
 
1320
        // The GIE register.  Only interrupts can disable the interrupt register
1321
        assign  w_switch_to_interrupt = (gie)&&(
1322
                        // On interrupt (obviously)
1323 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1324 2 dgisselq
                        // If we are stepping the CPU
1325 69 dgisselq
                        ||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
1326 2 dgisselq
                        // If we encounter a break instruction, if the break
1327 36 dgisselq
                        //      enable isn't set.
1328 69 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
1329
                                &&(op_break)&&(~break_en))
1330 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1331 36 dgisselq
                        // On an illegal instruction
1332 71 dgisselq
                        ||((alu_pc_valid)&&(alu_illegal))
1333 36 dgisselq
`endif
1334 71 dgisselq
                        // On division by zero.  If the divide isn't
1335
                        // implemented, div_valid and div_error will be short
1336
                        // circuited and that logic will be bypassed
1337
                        ||((div_valid)&&(div_error))
1338
                        // Same thing on a floating point error.
1339
                        ||((fpu_valid)&&(fpu_error))
1340
                        //      
1341 69 dgisselq
                        ||(bus_err)
1342 2 dgisselq
                        // If we write to the CC register
1343
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1344 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1345 2 dgisselq
                        );
1346
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1347
                        // Then if we write the CC register
1348
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1349 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1350 2 dgisselq
                        );
1351
        always @(posedge i_clk)
1352
                if (i_rst)
1353
                        gie <= 1'b0;
1354
                else if (w_switch_to_interrupt)
1355
                        gie <= 1'b0;
1356
                else if (w_release_from_interrupt)
1357
                        gie <= 1'b1;
1358
 
1359 25 dgisselq
        initial trap = 1'b0;
1360
        always @(posedge i_clk)
1361
                if (i_rst)
1362
                        trap <= 1'b0;
1363 69 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1364
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
1365 25 dgisselq
                        trap <= 1'b1;
1366
                else if (w_release_from_interrupt)
1367
                        trap <= 1'b0;
1368
 
1369 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1370 65 dgisselq
        initial ill_err_i = 1'b0;
1371 36 dgisselq
        always @(posedge i_clk)
1372
                if (i_rst)
1373 65 dgisselq
                        ill_err_i <= 1'b0;
1374
                // The debug interface can clear this bit
1375
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1376
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
1377
                        ill_err_i <= 1'b0;
1378 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
1379 65 dgisselq
                        ill_err_i <= 1'b1;
1380
        initial ill_err_u = 1'b0;
1381
        always @(posedge i_clk)
1382
                if (i_rst)
1383
                        ill_err_u <= 1'b0;
1384
                // The bit is automatically cleared on release from interrupt
1385 36 dgisselq
                else if (w_release_from_interrupt)
1386 65 dgisselq
                        ill_err_u <= 1'b0;
1387
                // If the supervisor writes to this register, clearing the
1388
                // bit, then clear it
1389
                else if (((~alu_gie)||(dbgv))
1390
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
1391
                                &&(wr_reg_id[4])&&(wr_write_cc))
1392
                        ill_err_u <= 1'b0;
1393 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
1394 65 dgisselq
                        ill_err_u <= 1'b1;
1395 38 dgisselq
`else
1396 65 dgisselq
        assign ill_err_u = 1'b0;
1397
        assign ill_err_i = 1'b0;
1398 36 dgisselq
`endif
1399 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1400
        // ever set.
1401
        initial ibus_err_flag = 1'b0;
1402 36 dgisselq
        always @(posedge i_clk)
1403
                if (i_rst)
1404 65 dgisselq
                        ibus_err_flag <= 1'b0;
1405
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1406
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
1407
                        ibus_err_flag <= 1'b0;
1408
                else if ((bus_err)&&(~alu_gie))
1409
                        ibus_err_flag <= 1'b1;
1410
        // User bus error flag -- if ever set, it will cause an interrupt to
1411
        // supervisor mode.  
1412
        initial ubus_err_flag = 1'b0;
1413
        always @(posedge i_clk)
1414
                if (i_rst)
1415
                        ubus_err_flag <= 1'b0;
1416 36 dgisselq
                else if (w_release_from_interrupt)
1417 65 dgisselq
                        ubus_err_flag <= 1'b0;
1418
                // else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4])
1419
                                // &&(i_dbg_reg == {1'b1, `CPU_CC_REG})
1420
                                // &&(~i_dbg_data[`CPU_BUSERR_BIT]))
1421
                        // ubus_err_flag <= 1'b0;
1422
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1423
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
1424
                                &&(wr_reg_id[4])&&(wr_write_cc))
1425
                        ubus_err_flag <= 1'b0;
1426 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1427 65 dgisselq
                        ubus_err_flag <= 1'b1;
1428 36 dgisselq
 
1429 69 dgisselq
        generate
1430
        if (IMPLEMENT_DIVIDE != 0)
1431
        begin
1432
                reg     r_idiv_err_flag, r_udiv_err_flag;
1433
 
1434
                // Supervisor/interrupt divide (by zero) error flag -- this will
1435
                // crash the CPU if ever set.  This bit is thus available for us
1436
                // to be able to tell if/why the CPU crashed.
1437
                initial r_idiv_err_flag = 1'b0;
1438
                always @(posedge i_clk)
1439
                        if (i_rst)
1440
                                r_idiv_err_flag <= 1'b0;
1441
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1442
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
1443
                                r_idiv_err_flag <= 1'b0;
1444
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
1445
                                r_idiv_err_flag <= 1'b1;
1446
                // User divide (by zero) error flag -- if ever set, it will
1447
                // cause a sudden switch interrupt to supervisor mode.  
1448
                initial r_udiv_err_flag = 1'b0;
1449
                always @(posedge i_clk)
1450
                        if (i_rst)
1451
                                r_udiv_err_flag <= 1'b0;
1452
                        else if (w_release_from_interrupt)
1453
                                r_udiv_err_flag <= 1'b0;
1454
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1455
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
1456
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1457
                                r_udiv_err_flag <= 1'b0;
1458
                        else if ((div_error)&&(alu_gie)&&(div_valid))
1459
                                r_udiv_err_flag <= 1'b1;
1460
 
1461
                assign  idiv_err_flag = r_idiv_err_flag;
1462
                assign  udiv_err_flag = r_udiv_err_flag;
1463
        end else begin
1464
                assign  idiv_err_flag = 1'b0;
1465
                assign  udiv_err_flag = 1'b0;
1466
        end endgenerate
1467
 
1468
        generate
1469
        if (IMPLEMENT_FPU !=0)
1470
        begin
1471
                // Supervisor/interrupt floating point error flag -- this will
1472
                // crash the CPU if ever set.
1473
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1474
                initial r_ifpu_err_flag = 1'b0;
1475
                always @(posedge i_clk)
1476
                        if (i_rst)
1477
                                r_ifpu_err_flag <= 1'b0;
1478
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1479
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
1480
                                r_ifpu_err_flag <= 1'b0;
1481
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1482
                                r_ifpu_err_flag <= 1'b1;
1483
                // User floating point error flag -- if ever set, it will cause
1484
                // a sudden switch interrupt to supervisor mode.  
1485
                initial r_ufpu_err_flag = 1'b0;
1486
                always @(posedge i_clk)
1487
                        if (i_rst)
1488
                                r_ufpu_err_flag <= 1'b0;
1489
                        else if (w_release_from_interrupt)
1490
                                r_ufpu_err_flag <= 1'b0;
1491
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1492
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
1493
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1494
                                r_ufpu_err_flag <= 1'b0;
1495
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1496
                                r_ufpu_err_flag <= 1'b1;
1497
 
1498
                assign  ifpu_err_flag = r_ifpu_err_flag;
1499
                assign  ufpu_err_flag = r_ufpu_err_flag;
1500
        end else begin
1501
                assign  ifpu_err_flag = 1'b0;
1502
                assign  ufpu_err_flag = 1'b0;
1503
        end endgenerate
1504
 
1505
`ifdef  OPT_VLIW
1506
        reg             r_ihalt_phase, r_uhalt_phase;
1507
 
1508
        initial r_ihalt_phase = 0;
1509
        initial r_uhalt_phase = 0;
1510
        always @(posedge i_clk)
1511
                if (~alu_gie)
1512
                        r_ihalt_phase <= alu_phase;
1513
        always @(posedge i_clk)
1514
                if (alu_gie)
1515
                        r_uhalt_phase <= alu_phase;
1516
                else if (w_release_from_interrupt)
1517
                        r_uhalt_phase <= 1'b0;
1518
 
1519
        assign  ihalt_phase = r_ihalt_phase;
1520
        assign  uhalt_phase = r_uhalt_phase;
1521
`else
1522
        assign  ihalt_phase = 1'b0;
1523
        assign  uhalt_phase = 1'b0;
1524
`endif
1525
 
1526 2 dgisselq
        //
1527
        // Write backs to the PC register, and general increments of it
1528
        //      We support two: upc and ipc.  If the instruction is normal,
1529
        // we increment upc, if interrupt level we increment ipc.  If
1530
        // the instruction writes the PC, we write whichever PC is appropriate.
1531
        //
1532
        // Do we need to all our partial results from the pipeline?
1533
        // What happens when the pipeline has gie and ~gie instructions within
1534
        // it?  Do we clear both?  What if a gie instruction tries to clear
1535
        // a non-gie instruction?
1536
        always @(posedge i_clk)
1537 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1538 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1539 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1540 2 dgisselq
                        upc <= alu_pc;
1541
 
1542
        always @(posedge i_clk)
1543
                if (i_rst)
1544
                        ipc <= RESET_ADDRESS;
1545
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1546 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1547 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1548 2 dgisselq
                        ipc <= alu_pc;
1549
 
1550
        always @(posedge i_clk)
1551
                if (i_rst)
1552
                        pf_pc <= RESET_ADDRESS;
1553
                else if (w_switch_to_interrupt)
1554
                        pf_pc <= ipc;
1555
                else if (w_release_from_interrupt)
1556
                        pf_pc <= upc;
1557
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1558 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1559 69 dgisselq
`ifdef  OPT_PIPELINED
1560
                else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
1561
                        pf_pc <= dcd_branch_pc + 1;
1562
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1563 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1564 69 dgisselq
`else
1565
                else if ((alu_pc_valid)&&(~clear_pipeline))
1566
                        pf_pc <= alu_pc;
1567
`endif
1568 2 dgisselq
 
1569
        initial new_pc = 1'b1;
1570
        always @(posedge i_clk)
1571 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1572 2 dgisselq
                        new_pc <= 1'b1;
1573
                else if (w_switch_to_interrupt)
1574
                        new_pc <= 1'b1;
1575
                else if (w_release_from_interrupt)
1576
                        new_pc <= 1'b1;
1577
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1578
                        new_pc <= 1'b1;
1579
                else
1580
                        new_pc <= 1'b0;
1581
 
1582
        //
1583
        // The debug interface
1584 56 dgisselq
        generate
1585
        if (AW<32)
1586
        begin
1587
                always @(posedge i_clk)
1588 2 dgisselq
                begin
1589
                        o_dbg_reg <= regset[i_dbg_reg];
1590
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1591 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1592 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1593 56 dgisselq
                        begin
1594 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1595 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1596
                        end
1597 2 dgisselq
                end
1598 56 dgisselq
        end else begin
1599
                always @(posedge i_clk)
1600
                begin
1601
                        o_dbg_reg <= regset[i_dbg_reg];
1602
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1603
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1604
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1605
                        begin
1606 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1607 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1608
                        end
1609
                end
1610
        end endgenerate
1611
 
1612 2 dgisselq
        always @(posedge i_clk)
1613 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1614 18 dgisselq
 
1615
        always @(posedge i_clk)
1616 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1617 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1618 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1619 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1620 2 dgisselq
 
1621
        //
1622
        //
1623
        // Produce accounting outputs: Account for any CPU stalls, so we can
1624
        // later evaluate how well we are doing.
1625
        //
1626
        //
1627 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1628 9 dgisselq
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1629 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1630 56 dgisselq
 
1631 65 dgisselq
`ifdef  DEBUG_SCOPE
1632 56 dgisselq
        always @(posedge i_clk)
1633 65 dgisselq
                o_debug <= {
1634 69 dgisselq
                        pf_pc[3:0], flags,
1635 56 dgisselq
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1636
                        op_ce, alu_ce, mem_ce,
1637 65 dgisselq
                        //
1638
                        master_ce, opvalid_alu, opvalid_mem,
1639
                        //
1640
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1641
                        mem_we,
1642
                        // ((opvalid_alu)&&(alu_stall))
1643
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1644
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1645
                        // opA[23:20], opA[3:0],
1646
                        gie, sleep,
1647 71 dgisselq
                        wr_reg_ce, wr_reg_vl[4:0]
1648
                /*
1649 69 dgisselq
                        i_rst, master_ce, (new_pc),
1650
                        ((dcd_early_branch)&&(dcdvalid)),
1651
                        pf_valid, pf_illegal,
1652
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1653
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1654
                        pf_pc[7:0], pf_addr[7:0]
1655 71 dgisselq
                */
1656 56 dgisselq
                        };
1657 65 dgisselq
`endif
1658 56 dgisselq
 
1659 2 dgisselq
endmodule

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