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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    cpudefs.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Some architectures have some needs, others have other needs.
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//              Some of my projects need a Zip CPU with pipelining, others
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//      can't handle the timing required to get the answer from the ALU
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//      back into the input for the ALU.  As each different projects has
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//      different needs, I can either 1) reconfigure my entire baseline prior
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//      to building each project, or 2) host a configuration file which contains
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//      the information regarding each baseline.  This file is that
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//      configuration file.  It controls how the CPU (not the system,
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//      peripherals, or other) is defined and implemented.  Several options
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//      are available within here, making the Zip CPU pipelined or not,
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//      able to handle a faster clock with more stalls or a slower clock with
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//      no stalls, etc.
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//
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//      This file encapsulates those control options.
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//
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//      The number of LUTs the Zip CPU uses varies dramatically with the
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//      options defined in this file.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`ifndef CPUDEFS_H
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`define CPUDEFS_H
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//
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//
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// The first couple options control the Zip CPU instruction set, and how
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// it handles various instructions within the set:
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//
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//
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// OPT_ILLEGAL_INSTRUCTION is part of a new section of code that is supposed
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// to recognize illegal instructions and interrupt the CPU whenever one such
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// instruction is encountered.  The goal is to create a soft floating point
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// unit via this approach, that can then be replaced with a true floating point
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// unit.  As I'm not there yet, it just catches illegal instructions and
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// interrupts the CPU on any such instruction--when defined.  Otherwise,
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// illegal instructions are quietly ignored and their behaviour is ...
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// undefined. (Many get treated like NOOPs ...)
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//
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// I recommend setting this flag so highly, that I'm likely going to remove
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// the option to turn this off in future versions of this CPU.
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//
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`define OPT_ILLEGAL_INSTRUCTION
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//
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//
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//
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// OPT_MULTIPLY controls whether or not the multiply is built and included
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// in the ALU by default.  Set this option and a parameter will be set that
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// includes the multiply.  (This parameter may still be overridden, as with
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// any parameter ...)  If the multiply is not included and
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// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
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// instruction that will then trip the illegal instruction trap.
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//
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// Either not defining this value, or defining it to zero will disable the
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// hardware multiply.  A value of '1' will cause the multiply to occurr in one
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// clock cycle only--often at the expense of the rest of the CPUs speed.
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// A value of 2 will cause the multiply to have a single delay cycle, 3 will
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// have two delay cycles, and 4 (or more) will have 3 delay cycles.
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//
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//
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`define OPT_MULTIPLY    3
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//
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//
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//
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// OPT_DIVIDE controls whether or not the divide instruction is built and
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// included into the ZipCPU by default.  Set this option and a parameter will
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// be set that causes the divide unit to be included.  (This parameter may
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// still be overridden, as with any parameter ...)  If the divide is not
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// included and OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create
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// an illegal instruction exception that will send the CPU into supervisor
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// mode.
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//
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//
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`define OPT_DIVIDE
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//
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//
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//
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// OPT_IMPLEMENT_FPU will (one day) control whether or not the floating point
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// unit (once I have one) is built and included into the ZipCPU by default.
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// At that time, if this option is set then a parameter will be set that
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// causes the floating point unit to be included.  (This parameter may
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// still be overridden, as with any parameter ...)  If the floating point unit
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// is not included and OPT_ILLEGAL_INSTRUCTION is set, then as with the
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// multiply and divide any floating point instruction will result in an illegal
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// instruction exception that will send the CPU into supervisor mode.
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//
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//
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// `define      OPT_IMPLEMENT_FPU
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//
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//
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//
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//
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// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and
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// whether or not it can issue one instruction per clock.  When set, the
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// prefetch has no cache, and only one instruction is fetched at a time.
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// This effectively sets the CPU so that only one instruction is ever
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// in the pipeline at once, and hence you may think of this as a "kill
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// pipeline" option.  However, since the pipelined fetch component uses so
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// much area on the FPGA, this is an important option to use in trimming down
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// used area if necessary.  Hence, it needs to be maintained for that purpose.
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// Be aware, though, it will drop your performance by a factor between 2x and
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// 3x.
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//
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// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
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// fetches are more complicated and therefore use more FPGA resources, while
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// single fetches will cause the CPU to stall for about 5 stalls each
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// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2.  However, the area cost may be worth it.  Consider:
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//
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//      Slice LUTs              ZipSystem       ZipCPU
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//      Single Fetching         2521            1734
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//      Pipelined fetching      2796            2046
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//      (These numbers may be dated, but should still be representative ...)
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//
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// I recommend only defining this if you "need" to, if area is tight and
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// speed isn't as important.  Otherwise, just leave this undefined.
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//
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// `define      OPT_SINGLE_FETCH
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//
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//
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//
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// The next several options are pipeline optimization options.  They make no
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// sense in a single instruction fetch mode, hence we #ifndef them so they
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// are only defined if we are in a full pipelined mode (i.e. OPT_SINGLE_FETCH
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// is not defined).
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//
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`ifndef OPT_SINGLE_FETCH
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//
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//
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//
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// OPT_PIPELINED is the natural result and opposite of using the single
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// instruction fetch unit.  If you are not using that unit, the ZipCPU will
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// be pipelined.  The option is defined here more for readability than
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// anything else, since OPT_PIPELINED makes more sense than OPT_SINGLE_FETCH,
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// well ... that and it does a better job of explaining what is going on.
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//
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// In other words, leave this define alone--lest you break the ZipCPU.
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//
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`define OPT_PIPELINED
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//
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//
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//
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// OPT_TRADITIONAL_PFCACHE allows you to switch between one of two prefetch
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// caches.  If enabled, a more traditional cache is implemented.  This more
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// traditional cache (currently) uses many more LUTs, but it also reduces
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// the stall count tremendously over the alternative hacked pipeline cache.
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// (The traditional pfcache is also pipelined, whereas the pipeline cache
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// implements a windowed approach to caching.)
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//
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// If you have the fabric to support this option, I recommend including it.
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//
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`define OPT_TRADITIONAL_PFCACHE
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//
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//
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//
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// OPT_EARLY_BRANCHING is an attempt to execute a BRA statement as early
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// as possible, to avoid as many pipeline stalls on a branch as possible.
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// It's not tremendously successful yet--BRA's still suffer stalls,
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// but I intend to keep working on this approach until the number of stalls
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// gets down to one or (ideally) zero.  (With the OPT_TRADITIONAL_PFCACHE, this
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// gets down to a single stall cycle ...)  That way a "BRA" can be used as the
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// compiler's branch prediction optimizer: BRA's barely stall, while branches
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// on conditions will always suffer about 4 stall cycles or so.
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//
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// I recommend setting this flag, so as to turn early branching on.
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//
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`define OPT_EARLY_BRANCHING
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//
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//
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//
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// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
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// can take advantaged of pipelined bus instructions.  To be eligible, the
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// operations must be identical (cannot pipeline loads and stores, just loads
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// only or stores only), and the addresses must either be identical or one up
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// from the previous address.  Further, the load/store string must all have
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// the same conditional.  This approach gains the must use, in my humble
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// opinion, when saving registers to or restoring registers from the stack
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// at the beginning/end of a procedure, or when doing a context swap.
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//
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// I recommend setting this flag, for performance reasons, especially if your
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// wishbone bus can handle pipelined bus accesses.
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//
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`define OPT_PIPELINED_BUS_ACCESS
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//
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//
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//
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//
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//
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// The instruction set defines an optional compressed instruction set (CIS)
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// complement.  These were at one time erroneously called Very Long Instruction
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// Words.  They are more appropriately referred to as compressed instructions.
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// The compressed instruction format allows two instructions to be packed into
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// the same instruction word.  Some instructions can be compressed, not all.
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// Compressed instructions take the same time to complete.  Set OPT_CIS to
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// include these double instructions as part of the instruction set.  These
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// instructions are designed to get more code density from the instruction set,
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// and to hopefully take some pain off of the performance of the pre-fetch and
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// instruction cache.
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//
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// These new instructions, however, also necessitate a change in the Zip
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// CPU--the Zip CPU can no longer execute instructions atomically.  It must
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// now execute non-CIS instructions, or CIS instruction pairs, atomically. 
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// This logic has been added into the ZipCPU, but it has not (yet) been
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// tested thoroughly.
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//
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//
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`define OPT_CIS
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//
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//
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//
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`endif  // OPT_SINGLE_FETCH
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//
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//
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//
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// Now let's talk about peripherals for a moment.  These next two defines
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// control whether the DMA controller is included in the Zip System, and
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// whether or not the 8 accounting timers are also included.  Set these to
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// include the respective peripherals, comment them out not to.
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//
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`define INCLUDE_DMA_CONTROLLER
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`define INCLUDE_ACCOUNTING_COUNTERS
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//
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//
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// `define      DEBUG_SCOPE
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//
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`endif  // CPUDEFS_H

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