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1 56 dgisselq
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    cpudefs.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Some architectures have some needs, others have other needs.
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//              Some of my projects need a Zip CPU with pipelining, others
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//      can't handle the timing required to get the answer from the ALU
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//      back into the input for the ALU.  As each different projects has
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//      different needs, I can either 1) reconfigure my entire baseline prior
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//      to building each project, or 2) host a configuration file which contains
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//      the information regarding each baseline.  This file is that
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//      configuration file.  It controls how the CPU (not the system,
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//      peripherals, or other) is defined and implemented.  Several options
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//      are available within here, making the Zip CPU pipelined or not,
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//      able to handle a faster clock with more stalls or a slower clock with
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//      no stalls, etc.
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//
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//      This file encapsulates those control options.
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//
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//      The number of LUTs the Zip CPU uses varies dramatically with the
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//      options defined in this file.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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`ifndef CPUDEFS_H
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`define CPUDEFS_H
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//
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//
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// The first couple options control the Zip CPU instruction set, and how
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// it handles various instructions within the set:
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//
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//
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// OPT_CONDITIONAL_FLAGS controls whether or not a conditional instruction
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// is allowed to set flags.  If conditional instructions can set flags, then
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// strings of conditional instructions will die whenever a flag setting 
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// instruction is executed.  If they cannot, then you can execute a string
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// of functions with no further conditions in them.  Set this flag to enable
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// strings of instructions, as these can be a lot cheaper than the pipeline
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// stalls associated with a conditional branch.
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//
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// This option will likely be changed in the future so that "CMP" and "TST"
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// instructions set the flags even if they are conditional, to allow multiple
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// conditions to be tested at once.
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//
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// I recommend setting this flag
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//
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`define OPT_CONDITIONAL_FLAGS
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//
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//
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//
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// OPT_ILLEGAL_INSTRUCTION is part of a new section of code that is supposed
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// to recognize illegal instructions and interrupt the CPU whenever one such
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// instruction is encountered.  The goal is to create a soft floating point
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// unit via this approach, that can then be replaced with a true floating point
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// unit.  As I'm not there yet, it just catches illegal instructions and
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// interrupts the CPU on any such instruction--when defined.  Otherwise,
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// illegal instructions are quietly ignored and their behaviour is ...
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// undefined. (Many get treated like NOOPs ...)
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//
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// I recommend setting this flag, although it can be taken out if area is
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// critical ...
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//
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`define OPT_ILLEGAL_INSTRUCTION
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//
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//
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//
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// OPT_MULTIPLY controls whether or not the multiply is built and included
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// in the ALU by default.  Set this option and a parameter will be set that
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// includes the multiply.  (This parameter may still be overridden, as with
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// any parameter ...)  If the multiply is not included and
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// OPT_ILLEGAL_INSTRUCTION is set, then the multiply will create an illegal
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// instruction that will then trip the illegal instruction trap.
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//
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//
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`define OPT_MULTIPLY
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//
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//
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//
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// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and 
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// whether or not it can issue one instruction per clock.  When set, the
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// prefetch has no cache, and only one instruction is fetched at a time.
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// This effectively sets the CPU so that only one instruction is ever 
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// in the pipeline at once, and hence you may think of this as a "kill 
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// pipeline" option.  However, since the pipelined fetch component uses so
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// much area on the FPGA, this is an important option to use in trimming down
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// used area if necessary.  Hence, it needs to be maintained for that purpose.
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// Be aware, though, it will drop your performance by a factor between 2x and
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// 3x.
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//
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// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
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// fetches are more complicated and therefore use more FPGA resources, while
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// single fetches will cause the CPU to stall for about 5 stalls each 
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// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2.  However, the area cost may be worth it.  Consider:
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//
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//      Slice LUTs              ZipSystem       ZipCPU
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//      Single Fetching         2521            1734
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//      Pipelined fetching      2796            2046
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//      (These numbers may be dated, but should still be representative ...)
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//
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// I recommend only defining this if you "need" to, if area is tight and
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// speed isn't as important.  Otherwise, just leave this undefined.
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//
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// `define      OPT_SINGLE_FETCH
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//
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//
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//
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// The next several options are pipeline optimization options.  They make no
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// sense in a single instruction fetch mode, hence we #ifndef them so they
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// are only defined if we are in a full pipelined mode (i.e. OPT_SINGLE_FETCH
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// is not defined).
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//
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`ifndef OPT_SINGLE_FETCH
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//
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//
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//
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// OPT_PRECLEAR_BUS allows an upcoming, unconditional, LOD/STO instruction
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// to kick the prefetch off the memory bus so that the LOD/STO instruction may
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// use the bus without waiting for the prefetch cycle to complete.  While it
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// sounds like this should speed things up, it isn't clear that it speeds up
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// programs that much--often the bus gets precleared for the LOD/STO, only
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// to have the next instruction stall because it wasn't loaded in time.
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//
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// While I recommend setting this flag, that recommendation may change in the
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// future.
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//
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`define OPT_PRECLEAR_BUS
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//
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//
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//
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// OPT_EARLY_BRANCHING is an attempt to execute a BRA statement as early
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// as possible, to avoid as many pipeline stalls on a branch as possible.
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// It's not tremendously successful yet--BRA's suffer 3 stalls instead of 5,
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// but I intend to keep working on this approach until the number of stalls
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// gets down to one or (ideally) zero.  That way a "BRA" can be used as the
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// compiler's branch prediction optimizer: BRA's don't stall, while branches on 
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// conditions will always suffer about 5 stalls or so.
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//
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// I recommend setting this flag, so as to turn early branching on.
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//
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`define OPT_EARLY_BRANCHING
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//
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//
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//
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// OPT_PIPELINED_BUS_ACCESS controls whether or not LOD/STO instructions
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// can take advantaged of pipelined bus instructions.  To be eligible, the
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// operations must be identical (cannot pipeline loads and stores, just loads
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// only or stores only), and the addresses must either be identical or one up
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// from the previous address.  Further, the load/store string must all have
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// the same conditional.  This approach gains the must use, in my humble
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// opinion, when saving registers to or restoring registers from the stack
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// at the beginning/end of a procedure, or when doing a context swap.
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//
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// I recommend setting this flag, for performance reasons, especially if your
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// wishbone bus can handle pipelined bus accesses.
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//
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`define OPT_PIPELINED_BUS_ACCESS
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//
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//
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//
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// OPT_SINGLE_CYCLE controls how the Zip CPU handles operations where the
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// second of two instructions uses a register output from the first of the
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// two.  If set, there will be no stalling between such a pair of instructions.
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// If not set, the CPU will insert a stall between such a pair to give the
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// result time to propagate to the second instruction.  Other than the existence
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// of a stall, the CPU will still yield the same results for the same
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// instructions.
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//
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// The purpose of this is really timing: With this option defined, a logical
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// or combinatorial mux is placed prior to the input of the ALU.  This mux,
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// together with whatever ALU operation is to take place, must both fit within
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// one clock cycle.  If they cannot be made to fit within the one clock cycle,
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// then either the clock must be slowed down so that they can fit, or this
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// flag needs to be turned off (not set) to get rid of the mux--hence speeding
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// up the clock while slowing down some instructions.
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//
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`define OPT_SINGLE_CYCLE
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//
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//
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`endif  // OPT_SINGLE_FETCH
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//
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//
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`endif  // CPUDEFS_H

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