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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [icontrol.v] - Blame information for rev 209

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    icontrol.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     An interrupt controller, for managing many interrupt sources.
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//
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//      This interrupt controller started from the question of how best to
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//      design a simple interrupt controller.  As such, it has a few nice
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//      qualities to it:
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//              1. This is wishbone compliant
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//              2. It sits on a 32-bit wishbone data bus
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//              3. It only consumes one address on that wishbone bus.
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//              4. There is no extra delays associated with reading this
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//                      device.
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//              5. Common operations can all be done in one clock.
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//
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//      So, how shall this be used?  First, the 32-bit word is broken down as
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//      follows:
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//
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//      Bit 31  - This is the global interrupt enable bit.  If set, interrupts
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//              will be generated and passed on as they come in.
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//      Bits 16-30      - These are specific interrupt enable lines.  If set,
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//              interrupts from source (bit#-16) will be enabled.
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//              To set this line and enable interrupts from this source, write
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//              to the register with this bit set and the global enable set.
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//              To disable this line, write to this register with global enable
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//              bit not set, but this bit set.  (Writing a zero to any of these
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//              bits has no effect, either setting or unsetting them.)
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//      Bit 15 - This is the any interrupt pin.  If any interrupt is pending,
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//              this bit will be set.
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//      Bits 0-14       - These are interrupt bits.  When set, an interrupt is
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//              pending from the corresponding source--regardless of whether
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//              it was enabled.  (If not enabled, it won't generate an
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//              interrupt, but it will still register here.)  To clear any
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//              of these bits, write a '1' to the corresponding bit.  Writing
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//              a zero to any of these bits has no effect.
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//
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//      The peripheral also sports a parameter, IUSED, which can be set
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//      to any value between 1 and (buswidth/2-1, or) 15 inclusive.  This will
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//      be the number of interrupts handled by this routine.  (Without the
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//      parameter, Vivado was complaining about unused bits.  With it, we can
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//      keep the complaints down and still use the routine).
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//
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//      To get access to more than 15 interrupts, chain these together, so
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//      that one interrupt controller device feeds another.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2017-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  icontrol(i_clk, i_reset, i_wr, i_data, o_data,
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                i_brd_ints, o_interrupt);
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        parameter       IUSED = 15, BW=32;
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        input   wire            i_clk, i_reset;
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        input   wire            i_wr;
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        input   wire    [BW-1:0] i_data;
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        output  reg     [BW-1:0] o_data;
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        input   wire    [(IUSED-1):0]    i_brd_ints;
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        output  wire            o_interrupt;
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        reg     [(IUSED-1):0]    r_int_state;
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        reg     [(IUSED-1):0]    r_int_enable;
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        wire    [(IUSED-1):0]    nxt_int_state;
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        reg             r_interrupt, r_gie;
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        wire            w_any;
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        assign  nxt_int_state = (r_int_state|i_brd_ints);
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        initial r_int_state = 0;
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        always @(posedge i_clk)
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                if (i_reset)
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                        r_int_state  <= 0;
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                else if (i_wr)
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                        r_int_state <= i_brd_ints | (r_int_state & (~i_data[(IUSED-1):0]));
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                else
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                        r_int_state <= nxt_int_state;
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        initial r_int_enable = 0;
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        always @(posedge i_clk)
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                if (i_reset)
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                        r_int_enable <= 0;
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                else if ((i_wr)&&(i_data[BW-1]))
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                        r_int_enable <= r_int_enable | i_data[(16+IUSED-1):16];
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                else if ((i_wr)&&(!i_data[BW-1]))
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                        r_int_enable <= r_int_enable & (~ i_data[(16+IUSED-1):16]);
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        initial r_gie = 1'b0;
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        always @(posedge i_clk)
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                if (i_reset)
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                        r_gie <= 1'b0;
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                else if (i_wr)
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                        r_gie <= i_data[BW-1];
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        assign  w_any = ((r_int_state & r_int_enable) != 0);
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        initial r_interrupt = 1'b0;
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        always @(posedge i_clk)
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        if (i_reset)
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                r_interrupt <= 1'b0;
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        else
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                r_interrupt <= (r_gie)&&(w_any);
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        generate
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        if (IUSED < 15)
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        begin
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                always @(posedge i_clk)
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                        o_data <= {
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                                r_gie, { {(15-IUSED){1'b0}}, r_int_enable },
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                                w_any, { {(15-IUSED){1'b0}}, r_int_state  } };
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        end else begin
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                always @(posedge i_clk)
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                        o_data <= { r_gie, r_int_enable, w_any, r_int_state };
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        end endgenerate
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        assign  o_interrupt = r_interrupt;
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        // Make verilator happy
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        // verilator lint_off UNUSED
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        wire    [30:0]   unused;
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        assign  unused = i_data[30:0];
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        // verilator lint_on  UNUSED
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`ifdef  FORMAL
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`ifdef  ICONTROL
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`define ASSUME  assume
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`else
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`define ASSUME  assert
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`endif
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        reg     f_past_valid;
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        initial f_past_valid = 1'b0;
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        always @(posedge i_clk)
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                f_past_valid <= 1'b1;
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        initial `ASSUME(i_reset);
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        always @(*)
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        if (!f_past_valid)
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                `ASSUME(i_reset);
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        always @(posedge i_clk)
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        if ((!f_past_valid)||($past(i_reset)))
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        begin
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                assert(w_any == 0);
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                assert(r_interrupt == 0);
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                assert(r_gie == 0);
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                assert(r_int_enable == 0);
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        end
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(i_reset)))
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                assert((r_int_state & $past(i_brd_ints))==$past(i_brd_ints));
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        always @(posedge i_clk)
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        if (((f_past_valid)&&(!$past(i_reset)))
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                        &&($past(r_int_state) & $past(r_int_enable))
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                        &&($past(r_gie)) )
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                assert(o_interrupt);
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        always @(posedge i_clk)
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        if ((f_past_valid)&&($past(w_any))&&(!$past(i_wr))&&(!$past(i_reset)))
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                assert(w_any);
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(r_gie)))
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                assert(!o_interrupt);
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(w_any)))
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                assert(!o_interrupt);
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr)))
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        begin
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                // Interrupts cannot be cleared, unless they are set
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                assert(r_int_state == (($past(i_brd_ints))
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                        |(($past(r_int_state))&(~$past(i_data[IUSED-1:0])))));
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                assert(r_gie == $past(i_data[BW-1]));
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        end else if ((f_past_valid)&&(!$past(i_reset)))
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        begin
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                assert(r_int_state == ($past(r_int_state)|$past(i_brd_ints)));
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                assert(r_gie == $past(r_gie));
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        end
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`endif
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endmodule

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