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1 36 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
//
4
// Filename:    wbdmac.v
5
//
6
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
7
//
8
// Purpose:     Wishbone DMA controller
9
//
10
//      This module is controllable via the wishbone, and moves values from
11
//      one location in the wishbone address space to another.  The amount of
12
//      memory moved at any given time can be up to 4kB, or equivalently 1kW.
13
//      Four registers control this DMA controller: a control/status register,
14
//      a length register, a source WB address and a destination WB address.
15
//      These register may be read at any time, but they may only be written
16
//      to when the controller is idle.
17
//
18
//      The meanings of three of the setup registers should be self explanatory:
19
//              - The length register controls the total number of words to
20
//                      transfer.
21
//              - The source address register controls where the DMA controller
22
//                      reads from.  This address may or may not be incremented
23
//                      after each read, depending upon the setting in the
24
//                      control/status register.
25
//              - The destination address register, which controls where the DMA
26
//                      controller writes to.  This address may or may not be
27
//                      incremented after each write, also depending upon the
28
//                      setting in the control/status register.
29
//
30
//      It is the control/status register, at local address zero, that needs
31
//      more definition:
32
//
33
//      Bits:
34
//      31      R       Write protect   If this is set to one, it means the
35
//                              write protect bit is set and the controller
36
//                              is therefore idle.  This bit will be set upon
37
//                              completing any transfer.
38
//      30      R       Error.          The controller stopped mid-transfer
39
//                                      after receiving a bus error.
40
//      29      R/W     inc_s_n         If set to one, the source address
41
//                              will not increment from one read to the next.
42
//      28      R/W     inc_d_n         If set to one, the destination address
43
//                              will not increment from one write to the next.
44
//      27      R       Always 0
45
//      26..16  R       nread           Indicates how many words have been read,
46
//                              and not necessarily written (yet).  This
47
//                              combined with the cfg_len parameter should tell
48
//                              exactly where the controller is at mid-transfer.
49
//      27..16  W       WriteProtect    When a 12'h3db is written to these
50
//                              bits, the write protect bit will be cleared.
51
//                              
52
//      15      R/W     on_dev_trigger  When set to '1', the controller will
53
//                              wait for an external interrupt before starting.
54
//      14..10  R/W     device_id       This determines which external interrupt
55
//                              will trigger a transfer.
56
//      9..0    R/W     transfer_len    How many bytes to transfer at one time.
57
//                              The minimum transfer length is one, while zero
58
//                              is mapped to a transfer length of 1kW.
59
//
60
//
61
//      To use this, follow this checklist:
62
//      1. Wait for any prior DMA operation to complete
63
//              (Read address 0, wait 'till either top bit is set or cfg_len==0)
64
//      2. Write values into length, source and destination address. 
65
//              (writei(3, &vals) should be sufficient for this.)
66
//      3. Enable the DMAC interrupt in whatever interrupt controller is present
67
//              on the system.
68
//      4. Write the final start command to the setup/control/status register:
69
//              Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,
70
//                      appropriately for your task
71
//              Write 12'h3db to the upper word.
72
//              Set the lower word to either all zeros, or a smaller transfer
73
//              length if desired.
74
//      5. wait() for the interrupt and the operation to complete.
75
//              Prior to completion, number of items successfully transferred
76
//              be read from the length register.  If the internal buffer is
77
//              being used, then you can read how much has been read into that
78
//              buffer by reading from bits 25..16 of this control/status
79
//              register.
80
//
81
// Creator:     Dan Gisselquist
82 69 dgisselq
//              Gisselquist Technology, LLC
83 36 dgisselq
//
84
////////////////////////////////////////////////////////////////////////////////
85
//
86 160 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
87 36 dgisselq
//
88
// This program is free software (firmware): you can redistribute it and/or
89
// modify it under the terms of  the GNU General Public License as published
90
// by the Free Software Foundation, either version 3 of the License, or (at
91
// your option) any later version.
92
//
93
// This program is distributed in the hope that it will be useful, but WITHOUT
94
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
95
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
96
// for more details.
97
//
98
// License:     GPL, v3, as defined and found on www.gnu.org,
99
//              http://www.gnu.org/licenses/gpl.html
100
//
101
//
102
///////////////////////////////////////////////////////////////////////////
103
//
104
//
105 160 dgisselq
`define DMA_IDLE        3'b000
106
`define DMA_WAIT        3'b001
107
`define DMA_READ_REQ    3'b010
108
`define DMA_READ_ACK    3'b011
109
`define DMA_PRE_WRITE   3'b100
110
`define DMA_WRITE_REQ   3'b101
111
`define DMA_WRITE_ACK   3'b110
112
 
113
module wbdmac(i_clk, i_rst,
114 36 dgisselq
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
115
                        o_swb_ack, o_swb_stall, o_swb_data,
116
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
117
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
118
                i_dev_ints,
119 69 dgisselq
                o_interrupt);
120 48 dgisselq
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
121
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
122 160 dgisselq
        input                   i_clk, i_rst;
123 36 dgisselq
        // Slave/control wishbone inputs
124
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
125
        input   [1:0]            i_swb_addr;
126
        input   [(DW-1):0]       i_swb_data;
127
        // Slave/control wishbone outputs
128
        output  reg             o_swb_ack;
129
        output  wire            o_swb_stall;
130
        output  reg [(DW-1):0]   o_swb_data;
131
        // Master/DMA wishbone control
132 160 dgisselq
        output  wire            o_mwb_cyc, o_mwb_stb, o_mwb_we;
133 48 dgisselq
        output  reg [(AW-1):0]   o_mwb_addr;
134
        output  reg [(DW-1):0]   o_mwb_data;
135 36 dgisselq
        // Master/DMA wishbone responses from the bus
136
        input                   i_mwb_ack, i_mwb_stall;
137
        input   [(DW-1):0]       i_mwb_data;
138
        input                   i_mwb_err;
139
        // The interrupt device interrupt lines
140
        input   [(DW-1):0]       i_dev_ints;
141
        // An interrupt to be set upon completion
142
        output  reg             o_interrupt;
143
        // Need to release the bus for a higher priority user
144 69 dgisselq
        //      This logic had lots of problems, so it is being
145
        //      removed.  If you want to make sure the bus is available
146
        //      for a higher priority user, adjust the transfer length
147
        //      accordingly.
148
        //
149
        // input                        i_other_busmaster_requests_bus;
150
        //
151 36 dgisselq
 
152
 
153 160 dgisselq
        reg     [2:0]            dma_state;
154
        reg                     cfg_err, cfg_len_nonzero;
155 48 dgisselq
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
156 36 dgisselq
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
157
        reg                     cfg_incs, cfg_incd;
158
        reg     [(LGDV-1):0]     cfg_dev_trigger;
159
        reg                     cfg_on_dev_trigger;
160
 
161
        // Single block operations: We'll read, then write, up to a single
162
        // memory block here.
163
 
164
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
165 160 dgisselq
        reg     [(LGMEMLEN):0]   nread, nwritten, nwacks, nracks;
166
        wire    [(AW-1):0]       bus_nracks;
167
        assign  bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };
168 36 dgisselq
 
169 160 dgisselq
        reg     last_read_request, last_read_ack,
170
                last_write_request, last_write_ack;
171
        reg     trigger, abort;
172
 
173
        initial dma_state = `DMA_IDLE;
174 36 dgisselq
        initial o_interrupt = 1'b0;
175 48 dgisselq
        initial cfg_len     = {(AW){1'b0}};
176 36 dgisselq
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
177
        initial cfg_on_dev_trigger = 1'b0;
178 160 dgisselq
        initial cfg_len_nonzero = 1'b0;
179 36 dgisselq
        always @(posedge i_clk)
180 160 dgisselq
        case(dma_state)
181
        `DMA_IDLE: begin
182
                o_mwb_addr <= cfg_raddr;
183
                nwritten   <= 0;
184
                nread      <= 0;
185
                nracks     <= 0;
186
                nwacks     <= 0;
187
                cfg_len_nonzero <= (|cfg_len);
188
 
189
                // When the slave wishbone writes, and we are in this 
190
                // (ready) configuration, then allow the DMA to be controlled
191
                // and thus to start.
192 182 dgisselq
                if ((i_swb_stb)&&(i_swb_we))
193 36 dgisselq
                begin
194 160 dgisselq
                        case(i_swb_addr)
195
                        2'b00: begin
196
                                if ((i_swb_data[27:16] == 12'hfed)
197
                                                &&(cfg_len_nonzero))
198
                                        dma_state <= `DMA_WAIT;
199
                                cfg_blocklen_sub_one
200
                                        <= i_swb_data[(LGMEMLEN-1):0]
201
                                        + {(LGMEMLEN){1'b1}};
202
                                        // i.e. -1;
203
                                cfg_dev_trigger    <= i_swb_data[14:10];
204
                                cfg_on_dev_trigger <= i_swb_data[15];
205
                                cfg_incs  <= ~i_swb_data[29];
206
                                cfg_incd  <= ~i_swb_data[28];
207 36 dgisselq
                                end
208 160 dgisselq
                        2'b01: begin
209
                                cfg_len   <=  i_swb_data[(AW-1):0];
210
                                cfg_len_nonzero <= (|i_swb_data[(AW-1):0]);
211
                                end
212
                        2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
213
                        2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
214
                        endcase
215
                end end
216
        `DMA_WAIT: begin
217
                o_mwb_addr <= cfg_raddr;
218
                nracks     <= 0;
219
                nwacks     <= 0;
220
                nwritten   <= 0;
221
                nread      <= 0;
222
                if (abort)
223
                        dma_state <= `DMA_IDLE;
224
                else if (trigger)
225
                        dma_state <= `DMA_READ_REQ;
226
                end
227
        `DMA_READ_REQ: begin
228
                nwritten  <= 0;
229 36 dgisselq
 
230 160 dgisselq
                if (~i_mwb_stall)
231 36 dgisselq
                begin
232 160 dgisselq
                        // Number of read acknowledgements needed
233
                        nracks <= nracks+1;
234
                        if (last_read_request)
235
        //((nracks == {1'b0, cfg_blocklen_sub_one})||(bus_nracks == cfg_len-1))
236
                                // Wishbone interruptus
237
                                dma_state <= `DMA_READ_ACK;
238
                        if (cfg_incs)
239
                                o_mwb_addr <= o_mwb_addr
240
                                                + {{(AW-1){1'b0}},1'b1};
241
                end
242
 
243
                if (i_mwb_err)
244
                begin
245
                        cfg_len <= 0;
246
                        dma_state <= `DMA_IDLE;
247
                end
248
                if (abort)
249
                        dma_state <= `DMA_IDLE;
250
                if (i_mwb_ack)
251
                begin
252
                        nread <= nread+1;
253
                        if (cfg_incs)
254
                                cfg_raddr  <= cfg_raddr
255
                                                + {{(AW-1){1'b0}},1'b1};
256
                end end
257
        `DMA_READ_ACK: begin
258
                nwritten  <= 0;
259
 
260
                if (i_mwb_err)
261
                begin
262
                        cfg_len <= 0;
263
                        dma_state <= `DMA_IDLE;
264
                end else if (i_mwb_ack)
265
                begin
266
                        nread <= nread+1;
267
                        if (last_read_ack) // (nread+1 == nracks)
268
                                dma_state  <= `DMA_PRE_WRITE;
269
                        if (cfg_incs)
270
                                cfg_raddr  <= cfg_raddr
271
                                                + {{(AW-1){1'b0}},1'b1};
272
                end
273
                if (abort)
274
                        dma_state <= `DMA_IDLE;
275
                end
276
        `DMA_PRE_WRITE: begin
277
                o_mwb_addr <= cfg_waddr;
278
                dma_state <= (abort)?`DMA_IDLE:`DMA_WRITE_REQ;
279
                end
280
        `DMA_WRITE_REQ: begin
281
                if (~i_mwb_stall)
282
                begin
283
                        nwritten <= nwritten+1;
284
                        if (last_write_request) // (nwritten == nread-1)
285
                                // Wishbone interruptus
286
                                dma_state <= `DMA_WRITE_ACK;
287
                        if (cfg_incd)
288 36 dgisselq
                        begin
289 160 dgisselq
                                o_mwb_addr <= o_mwb_addr
290
                                                + {{(AW-1){1'b0}},1'b1};
291
                                cfg_waddr  <= cfg_waddr
292
                                                + {{(AW-1){1'b0}},1'b1};
293 36 dgisselq
                        end
294 160 dgisselq
                end
295 36 dgisselq
 
296 160 dgisselq
                if (i_mwb_err)
297
                begin
298
                        cfg_len  <= 0;
299
                        dma_state <= `DMA_IDLE;
300
                end
301
                if (i_mwb_ack)
302
                begin
303
                        nwacks <= nwacks+1;
304
                        cfg_len <= cfg_len +{(AW){1'b1}}; // -1
305
                end
306
                if (abort)
307
                        dma_state <= `DMA_IDLE;
308
                end
309
        `DMA_WRITE_ACK: begin
310
                if (i_mwb_err)
311
                begin
312
                        cfg_len  <= 0;
313
                        nread    <= 0;
314
                        dma_state <= `DMA_IDLE;
315
                end else if (i_mwb_ack)
316
                begin
317
                        nwacks <= nwacks+1;
318
                        cfg_len <= cfg_len +{(AW){1'b1}};//cfg_len -= 1;
319
                        if (last_write_ack) // (nwacks+1 == nwritten)
320 36 dgisselq
                        begin
321
                                nread <= 0;
322 160 dgisselq
                                dma_state <= (cfg_len == 1)?`DMA_IDLE:`DMA_WAIT;
323 36 dgisselq
                        end
324
                end
325
 
326 160 dgisselq
                if (abort)
327
                        dma_state <= `DMA_IDLE;
328
                end
329
        default:
330
                dma_state <= `DMA_IDLE;
331
        endcase
332
 
333
        initial o_interrupt = 1'b0;
334
        always @(posedge i_clk)
335
                o_interrupt <= (dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack)
336
                                &&(last_write_ack)
337
                                &&(cfg_len == {{(AW-1){1'b0}},1'b1});
338
 
339
        initial cfg_err = 1'b0;
340
        always @(posedge i_clk)
341
                if (dma_state == `DMA_IDLE)
342
                begin
343 182 dgisselq
                        if ((i_swb_stb)&&(i_swb_we)&&(i_swb_addr==2'b00))
344 160 dgisselq
                                cfg_err <= 1'b0;
345
                end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
346
                        cfg_err <= 1'b1;
347
 
348
        initial last_read_request = 1'b0;
349
        always @(posedge i_clk)
350
                if ((dma_state == `DMA_WAIT)||(dma_state == `DMA_READ_REQ))
351
                begin
352
                        if ((~i_mwb_stall)&&(dma_state == `DMA_READ_REQ))
353
                        begin
354
                                last_read_request <=
355
                                (nracks + 1 == { 1'b0, cfg_blocklen_sub_one})
356
                                        ||(bus_nracks == cfg_len-2);
357
                        end else
358
                                last_read_request <=
359
                                        (nracks== { 1'b0, cfg_blocklen_sub_one})
360
                                        ||(bus_nracks == cfg_len-1);
361
                end else
362
                        last_read_request <= 1'b0;
363
 
364
        initial last_read_ack = 1'b0;
365
        always @(posedge i_clk)
366
                if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
367
                begin
368 182 dgisselq
                        if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
369 160 dgisselq
                                last_read_ack <= (nread+2 == nracks);
370
                        else
371
                                last_read_ack <= (nread+1 == nracks);
372
                end else
373
                        last_read_ack <= 1'b0;
374
 
375
        initial last_write_request = 1'b0;
376
        always @(posedge i_clk)
377
                if (dma_state == `DMA_PRE_WRITE)
378
                        last_write_request <= (nread <= 1);
379
                else if (dma_state == `DMA_WRITE_REQ)
380
                begin
381
                        if (i_mwb_stall)
382
                                last_write_request <= (nwritten >= nread-1);
383
                        else
384
                                last_write_request <= (nwritten >= nread-2);
385
                end else
386
                        last_write_request <= 1'b0;
387
 
388
        initial last_write_ack = 1'b0;
389
        always @(posedge i_clk)
390
                if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
391
                begin
392 182 dgisselq
                        if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
393 160 dgisselq
                                last_write_ack <= (nwacks+2 == nwritten);
394
                        else
395
                                last_write_ack <= (nwacks+1 == nwritten);
396
                end else
397
                        last_write_ack <= 1'b0;
398
 
399
        assign  o_mwb_cyc = (dma_state == `DMA_READ_REQ)
400
                        ||(dma_state == `DMA_READ_ACK)
401
                        ||(dma_state == `DMA_WRITE_REQ)
402
                        ||(dma_state == `DMA_WRITE_ACK);
403
 
404
        assign  o_mwb_stb = (dma_state == `DMA_READ_REQ)
405
                        ||(dma_state == `DMA_WRITE_REQ);
406
 
407
        assign  o_mwb_we = (dma_state == `DMA_PRE_WRITE)
408
                        ||(dma_state == `DMA_WRITE_REQ)
409
                        ||(dma_state == `DMA_WRITE_ACK);
410
 
411 36 dgisselq
        //
412
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
413
        // proper memory, it must have a simple address fed into it.  Hence
414
        // the read_address (rdaddr) register.  The problem is that this
415
        // register must always be one greater than the address we actually
416
        // want to read from, unless we are idling.  So ... the math is touchy.
417
        //
418
        reg     [(LGMEMLEN-1):0] rdaddr;
419
        always @(posedge i_clk)
420 160 dgisselq
                if((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT)
421
                                ||(dma_state == `DMA_WRITE_ACK))
422
                        rdaddr <= 0;
423
                else if ((dma_state == `DMA_PRE_WRITE)
424
                                ||((dma_state==`DMA_WRITE_REQ)&&(~i_mwb_stall)))
425
                        rdaddr <= rdaddr + {{(LGMEMLEN-1){1'b0}},1'b1};
426 36 dgisselq
        always @(posedge i_clk)
427 160 dgisselq
                if ((dma_state != `DMA_WRITE_REQ)||(~i_mwb_stall))
428 36 dgisselq
                        o_mwb_data <= dma_mem[rdaddr];
429
        always @(posedge i_clk)
430 160 dgisselq
                if((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
431 36 dgisselq
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
432
 
433
        always @(posedge i_clk)
434
                casez(i_swb_addr)
435 160 dgisselq
                2'b00: o_swb_data <= {  (dma_state != `DMA_IDLE), cfg_err,
436 36 dgisselq
                                        ~cfg_incs, ~cfg_incd,
437
                                        1'b0, nread,
438
                                        cfg_on_dev_trigger, cfg_dev_trigger,
439
                                        cfg_blocklen_sub_one
440
                                        };
441 48 dgisselq
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
442
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
443
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
444 36 dgisselq
                endcase
445
 
446 160 dgisselq
        // This causes us to wait a minimum of two clocks before starting: One
447
        // to go into the wait state, and then one while in the wait state to
448
        // develop the trigger.
449
        initial trigger = 1'b0;
450 36 dgisselq
        always @(posedge i_clk)
451 160 dgisselq
                trigger <=  (dma_state == `DMA_WAIT)
452
                                &&((~cfg_on_dev_trigger)
453
                                        ||(i_dev_ints[cfg_dev_trigger]));
454 36 dgisselq
 
455 160 dgisselq
        // Ack any access.  We'll quietly ignore any access where we are busy,
456
        // but ack it anyway.  In other words, before writing to the device,
457
        // double check that it isn't busy, and then write.
458
        always @(posedge i_clk)
459 182 dgisselq
                o_swb_ack <= (i_swb_stb);
460 160 dgisselq
 
461 36 dgisselq
        assign  o_swb_stall = 1'b0;
462
 
463 160 dgisselq
        initial abort = 1'b0;
464
        always @(posedge i_clk)
465 182 dgisselq
                abort <= (i_rst)||((i_swb_stb)&&(i_swb_we)
466 160 dgisselq
                        &&(i_swb_addr == 2'b00)
467
                        &&(i_swb_data == 32'hffed0000));
468
 
469 36 dgisselq
endmodule
470
 

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