OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Blame information for rev 56

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 36 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
//
4
// Filename:    wbdmac.v
5
//
6
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
7
//
8
// Purpose:     Wishbone DMA controller
9
//
10
//      This module is controllable via the wishbone, and moves values from
11
//      one location in the wishbone address space to another.  The amount of
12
//      memory moved at any given time can be up to 4kB, or equivalently 1kW.
13
//      Four registers control this DMA controller: a control/status register,
14
//      a length register, a source WB address and a destination WB address.
15
//      These register may be read at any time, but they may only be written
16
//      to when the controller is idle.
17
//
18
//      The meanings of three of the setup registers should be self explanatory:
19
//              - The length register controls the total number of words to
20
//                      transfer.
21
//              - The source address register controls where the DMA controller
22
//                      reads from.  This address may or may not be incremented
23
//                      after each read, depending upon the setting in the
24
//                      control/status register.
25
//              - The destination address register, which controls where the DMA
26
//                      controller writes to.  This address may or may not be
27
//                      incremented after each write, also depending upon the
28
//                      setting in the control/status register.
29
//
30
//      It is the control/status register, at local address zero, that needs
31
//      more definition:
32
//
33
//      Bits:
34
//      31      R       Write protect   If this is set to one, it means the
35
//                              write protect bit is set and the controller
36
//                              is therefore idle.  This bit will be set upon
37
//                              completing any transfer.
38
//      30      R       Error.          The controller stopped mid-transfer
39
//                                      after receiving a bus error.
40
//      29      R/W     inc_s_n         If set to one, the source address
41
//                              will not increment from one read to the next.
42
//      28      R/W     inc_d_n         If set to one, the destination address
43
//                              will not increment from one write to the next.
44
//      27      R       Always 0
45
//      26..16  R       nread           Indicates how many words have been read,
46
//                              and not necessarily written (yet).  This
47
//                              combined with the cfg_len parameter should tell
48
//                              exactly where the controller is at mid-transfer.
49
//      27..16  W       WriteProtect    When a 12'h3db is written to these
50
//                              bits, the write protect bit will be cleared.
51
//                              
52
//      15      R/W     on_dev_trigger  When set to '1', the controller will
53
//                              wait for an external interrupt before starting.
54
//      14..10  R/W     device_id       This determines which external interrupt
55
//                              will trigger a transfer.
56
//      9..0    R/W     transfer_len    How many bytes to transfer at one time.
57
//                              The minimum transfer length is one, while zero
58
//                              is mapped to a transfer length of 1kW.
59
//
60
//
61
//      To use this, follow this checklist:
62
//      1. Wait for any prior DMA operation to complete
63
//              (Read address 0, wait 'till either top bit is set or cfg_len==0)
64
//      2. Write values into length, source and destination address. 
65
//              (writei(3, &vals) should be sufficient for this.)
66
//      3. Enable the DMAC interrupt in whatever interrupt controller is present
67
//              on the system.
68
//      4. Write the final start command to the setup/control/status register:
69
//              Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,
70
//                      appropriately for your task
71
//              Write 12'h3db to the upper word.
72
//              Set the lower word to either all zeros, or a smaller transfer
73
//              length if desired.
74
//      5. wait() for the interrupt and the operation to complete.
75
//              Prior to completion, number of items successfully transferred
76
//              be read from the length register.  If the internal buffer is
77
//              being used, then you can read how much has been read into that
78
//              buffer by reading from bits 25..16 of this control/status
79
//              register.
80
//
81
// Creator:     Dan Gisselquist
82
//              Gisselquist Tecnology, LLC
83
//
84
// Copyright:   2015
85
//
86
//
87
////////////////////////////////////////////////////////////////////////////////
88
//
89
// Copyright (C) 2015, Gisselquist Technology, LLC
90
//
91
// This program is free software (firmware): you can redistribute it and/or
92
// modify it under the terms of  the GNU General Public License as published
93
// by the Free Software Foundation, either version 3 of the License, or (at
94
// your option) any later version.
95
//
96
// This program is distributed in the hope that it will be useful, but WITHOUT
97
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
98
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
99
// for more details.
100
//
101
// License:     GPL, v3, as defined and found on www.gnu.org,
102
//              http://www.gnu.org/licenses/gpl.html
103
//
104
//
105
///////////////////////////////////////////////////////////////////////////
106
//
107
//
108
module wbdmac(i_clk,
109
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
110
                        o_swb_ack, o_swb_stall, o_swb_data,
111
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
112
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
113
                i_dev_ints,
114
                o_interrupt,
115
                i_other_busmaster_requests_bus);
116 48 dgisselq
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
117
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
118 36 dgisselq
        input                   i_clk;
119
        // Slave/control wishbone inputs
120
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
121
        input   [1:0]            i_swb_addr;
122
        input   [(DW-1):0]       i_swb_data;
123
        // Slave/control wishbone outputs
124
        output  reg             o_swb_ack;
125
        output  wire            o_swb_stall;
126
        output  reg [(DW-1):0]   o_swb_data;
127
        // Master/DMA wishbone control
128
        output  reg             o_mwb_cyc, o_mwb_stb, o_mwb_we;
129 48 dgisselq
        output  reg [(AW-1):0]   o_mwb_addr;
130
        output  reg [(DW-1):0]   o_mwb_data;
131 36 dgisselq
        // Master/DMA wishbone responses from the bus
132
        input                   i_mwb_ack, i_mwb_stall;
133
        input   [(DW-1):0]       i_mwb_data;
134
        input                   i_mwb_err;
135
        // The interrupt device interrupt lines
136
        input   [(DW-1):0]       i_dev_ints;
137
        // An interrupt to be set upon completion
138
        output  reg             o_interrupt;
139
        // Need to release the bus for a higher priority user
140
        input                   i_other_busmaster_requests_bus;
141
 
142
 
143
        reg                     cfg_wp; // Write protect
144
        reg                     cfg_err;
145 48 dgisselq
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
146 36 dgisselq
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
147
        reg                     cfg_incs, cfg_incd;
148
        reg     [(LGDV-1):0]     cfg_dev_trigger;
149
        reg                     cfg_on_dev_trigger;
150
 
151
        // Single block operations: We'll read, then write, up to a single
152
        // memory block here.
153
 
154
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
155
        reg     [(LGMEMLEN):0]   nread, nwritten, nacks;
156 48 dgisselq
        wire    [(AW-1):0]       bus_nacks;
157
        assign  bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
158 36 dgisselq
 
159
        initial o_interrupt = 1'b0;
160
        initial o_mwb_cyc   = 1'b0;
161
        initial cfg_err     = 1'b0;
162
        initial cfg_wp      = 1'b0;
163 48 dgisselq
        initial cfg_len     = {(AW){1'b0}};
164 36 dgisselq
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
165
        initial cfg_on_dev_trigger = 1'b0;
166
        always @(posedge i_clk)
167
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
168
                begin
169
                        if ((o_mwb_stb)&&(~i_mwb_stall))
170
                        begin
171
                                nwritten <= nwritten+1;
172
                                if ((nwritten == nread-1)
173
                                        ||(i_other_busmaster_requests_bus))
174
                                        // Wishbone interruptus
175
                                        o_mwb_stb <= 1'b0;
176
                                else if (cfg_incd) begin
177
                                        o_mwb_addr <= o_mwb_addr + 1;
178
                                        cfg_waddr  <= cfg_waddr  + 1;
179
                                end
180
                                // o_mwb_data <= dma_mem[nwritten + 1];
181
                        end
182
 
183
                        if (i_mwb_err)
184
                        begin
185
                                o_mwb_cyc <= 1'b0;
186
                                cfg_err <= 1'b1;
187
                                cfg_len <= 0;
188
                                nread   <= 0;
189
                        end else if (i_mwb_ack)
190
                        begin
191
                                nacks <= nacks+1;
192
                                cfg_len <= cfg_len - 1;
193
                                if ((nacks+1 == nwritten)&&(~o_mwb_stb))
194
                                begin
195
                                        o_mwb_cyc <= 1'b0;
196
                                        nread <= 0;
197
                                        o_interrupt <= (cfg_len == 1);
198
                                        // Turn write protect back on
199
                                        cfg_wp    <= 1'b1;
200
                                end
201
                        end
202
                end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle
203
                begin
204
                        if ((o_mwb_stb)&&(~i_mwb_stall))
205
                        begin
206
                                nacks <= nacks+1;
207
                                if ((nacks == {1'b0, cfg_blocklen_sub_one})
208
                                        ||(bus_nacks <= cfg_len-1)
209
                                        ||(i_other_busmaster_requests_bus))
210
                                        // Wishbone interruptus
211
                                        o_mwb_stb <= 1'b0;
212
                                else if (cfg_incs) begin
213
                                        o_mwb_addr <= o_mwb_addr + 1;
214
                                end
215
                        end
216
 
217
                        if (i_mwb_err)
218
                        begin
219
                                o_mwb_cyc <= 1'b0;
220
                                cfg_err <= 1'b1;
221
                                cfg_len <= 0;
222
                                nread <= 0;
223
                        end else if (i_mwb_ack)
224
                        begin
225
                                nread <= nread+1;
226
                                if ((~o_mwb_stb)&&(nread+1 == nacks))
227
                                begin
228
                                        o_mwb_cyc <= 1'b0;
229
                                        nacks <= 0;
230
                                end
231
                                if (cfg_incs)
232
                                        cfg_raddr  <= cfg_raddr  + 1;
233
                                // dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
234
                        end
235
                end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
236
                begin // Initiate/continue a write cycle
237
                        o_mwb_cyc  <= 1'b1;
238
                        o_mwb_stb  <= 1'b1;
239
                        o_mwb_we   <= 1'b1;
240
                        // o_mwb_data <= dma_mem[0];
241
                        o_mwb_addr <= cfg_waddr;
242
                        // nwritten  <= 0; // Can't set to zero, in case we're
243
                        // nacks     <= 0; //   continuing a cycle
244
                end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp)
245
                                &&((~cfg_on_dev_trigger)
246
                                        ||(i_dev_ints[cfg_dev_trigger])))
247
                begin // Initiate a read cycle
248
                        o_mwb_cyc <= 1'b1;
249
                        o_mwb_stb <= 1'b1;
250
                        o_mwb_we  <= 1'b0;
251
                        o_mwb_addr<= cfg_raddr;
252
                        nwritten  <= 0;
253
                        nread     <= 0;
254
                        nacks     <= 0;
255
                end else begin
256
                        o_mwb_cyc  <= 1'b0;
257
                        o_mwb_stb  <= 1'b0;
258
                        o_mwb_we   <= 1'b0;
259
                        o_mwb_addr <= cfg_raddr;
260
                        o_interrupt<= 1'b0;
261
                        nwritten   <= 0;
262
                        if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
263
                        begin
264
                                cfg_wp <= 1'b1;
265
                                case(i_swb_addr)
266
                                2'b00: begin
267
                                        cfg_wp    <= (i_swb_data[27:16]!=12'hfed);
268
                                        cfg_blocklen_sub_one
269
                                                <= i_swb_data[(LGMEMLEN-1):0]-1;
270
                                        cfg_dev_trigger    <= i_swb_data[14:10];
271
                                        cfg_on_dev_trigger <= i_swb_data[15];
272
                                        cfg_incs  <= ~i_swb_data[29];
273
                                        cfg_incd  <= ~i_swb_data[28];
274
                                        cfg_err   <= 1'b0;
275
                                        end
276 48 dgisselq
                                2'b01: cfg_len   <=  i_swb_data[(AW-1):0];
277
                                2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
278
                                2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
279 36 dgisselq
                                endcase
280
                        end
281
                end
282
 
283
        //
284
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
285
        // proper memory, it must have a simple address fed into it.  Hence
286
        // the read_address (rdaddr) register.  The problem is that this
287
        // register must always be one greater than the address we actually
288
        // want to read from, unless we are idling.  So ... the math is touchy.
289
        //
290
        reg     [(LGMEMLEN-1):0] rdaddr;
291
        always @(posedge i_clk)
292
                if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))
293
                        // This would be the normal advance, save that we are
294
                        // already one ahead of nwritten
295
                        rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1};
296
                else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
297
                        // Here's where we do our extra advance
298
                        rdaddr <= nwritten[(LGMEMLEN-1):0]+1;
299
                else if ((~o_mwb_cyc)||(~o_mwb_we))
300
                        rdaddr <= nwritten[(LGMEMLEN-1):0];
301
        always @(posedge i_clk)
302
                if ((~o_mwb_cyc)||((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)))
303
                        o_mwb_data <= dma_mem[rdaddr];
304
        always @(posedge i_clk)
305
                if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack))
306
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
307
 
308
        always @(posedge i_clk)
309
                casez(i_swb_addr)
310
                2'b00: o_swb_data <= {  ~cfg_wp, cfg_err,
311
                                        ~cfg_incs, ~cfg_incd,
312
                                        1'b0, nread,
313
                                        cfg_on_dev_trigger, cfg_dev_trigger,
314
                                        cfg_blocklen_sub_one
315
                                        };
316 48 dgisselq
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
317
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
318
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
319 36 dgisselq
                endcase
320
 
321
        always @(posedge i_clk)
322
                if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
323
                        o_swb_ack <= 1'b1;
324
                // else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0))
325
                else
326
                        o_swb_ack <= 1'b0;
327
 
328
        assign  o_swb_stall = 1'b0;
329
 
330
endmodule
331
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.