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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbwatchdog.v] - Blame information for rev 69

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1 69 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbwatchdog.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     A Zip timer, redesigned to be a bus watchdog
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//
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//      This is a **really** stripped down Zip Timer.  All options for external
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//      control have been removed.  This timer may be reset, and ... that's 
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//      about it.  The goal is that this stripped down timer be used as a bus
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//      watchdog element.  Even at that, it's not really fully featured.  The
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//      rest of the important features can be found in the zipsystem module.
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//
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//      As a historical note, the wishbone watchdog timer began as a normal
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//      timer, with some fixed inputs.  This makes sense, if you think about it:
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//      if the goal is to interrupt a stalled wishbone transaction by inserting
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//      a bus error, then you can't use the bus to set it up or configure it
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//      simply because the bus in question is ... well, unreliable.  You're
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//      trying to make it reliable.
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//
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//      The problem with using the ziptimer in a stripped down implementation
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//      was that the fixed inputs caused the synthesis tool to complain about
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//      the use of registers values would never change.  This solves that
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//      problem by explicitly removing the cruft that would otherwise
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//      just create synthesis warnings and errors.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  wbwatchdog(i_clk, i_rst, i_ce, i_timeout, o_int);
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        parameter       BW = 32;
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        input                   i_clk, i_rst, i_ce;
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        // Inputs (these were at one time wishbone controlled ...)
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        input   [(BW-1):0]       i_timeout;
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        // Interrupt line
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        output  reg             o_int;
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        reg     [(BW-1):0]       r_value;
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        initial r_value = 0;
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        always @(posedge i_clk)
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                if (i_rst)
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                        r_value <= i_timeout[(BW-1):0];
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                else if ((i_ce)&&(~o_int))
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                        r_value <= r_value + {(BW){1'b1}}; // r_value - 1;
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        // Set the interrupt on our last tick.
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        initial o_int   = 1'b0;
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        always @(posedge i_clk)
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                if ((i_rst)||(~i_ce))
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                        o_int <= 1'b0;
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                else
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                        o_int <= (r_value == { {(BW-1){1'b0}}, 1'b1 });
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endmodule

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