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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipcounter.v] - Blame information for rev 2

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcounter.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:
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//              A very, _very_ simple counter.  It's purpose doesn't really
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//      include rollover, but it will interrupt on rollover.  It can be set,
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//      although my design concept is that it can be reset.  It cannot be
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//      halted.  It will always produce interrupts--whether or not they are 
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//      handled interrupts is another question--that's up to the interrupt
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//      controller.
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//
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//      My intention is to use this counter for process accounting: I should
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//      be able to use this to count clock ticks of processor time assigned to
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//      each task by resetting the counter at the beginning of every task
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//      interval, and reading the result at the end of the interval.  As long
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//      as the interval is less than 2^32 clocks, there should be no problem.
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//      Similarly, this can be used to measure CPU wishbone bus stalls, 
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//      prefetch stalls, or other CPU stalls (i.e. stalling as part of a JMP
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//      instruction, or a read from the condition codes following a write).
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  zipcounter(i_clk, i_ce,
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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                        o_wb_ack, o_wb_stall, o_wb_data,
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                o_int);
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        parameter       BW = 32;
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        input                           i_clk, i_ce;
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        // Wishbone inputs
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        input                           i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [(BW-1):0]       i_wb_data;
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        // Wishbone outputs
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(BW-1):0]       o_wb_data;
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        // Interrupt line
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        output  reg                     o_int;
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        initial o_wb_data = 32'h00;
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        always @(posedge i_clk)
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                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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                        o_wb_data <= i_wb_data;
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                else if (i_ce)
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                        o_wb_data <= o_wb_data + 1;
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        initial o_int = 0;
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        always @(posedge i_clk)
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                if (i_ce)
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                        o_int <= &o_wb_data;
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                else
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                        o_int <= 1'b0;
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        initial o_wb_ack = 1'b0;
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        always @(posedge i_clk)
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                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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        assign  o_wb_stall = 1'b0;
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endmodule

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