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[/] [zipcpu/] [trunk/] [rtl/] [zipbones.v] - Blame information for rev 56

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1 38 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipbones.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     In the spirit of keeping the Zip CPU small, this implements a
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//              Zip System with no peripherals: Any peripherals you wish will
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//              need to be implemented off-module.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  zipbones(i_clk, i_rst,
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                // Wishbone master interface from the CPU
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                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
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                // Incoming interrupts
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                i_ext_int,
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                // Our one outgoing interrupt
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                o_ext_int,
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                // Wishbone slave interface for debugging purposes
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                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
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                        o_dbg_ack, o_dbg_stall, o_dbg_data,
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                o_zip_debug);
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        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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                        LGICACHE=6, START_HALTED=1,
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                        AW=ADDRESS_WIDTH;
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        input   i_clk, i_rst;
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        // Wishbone master
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        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
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        output  wire    [(AW-1):0]       o_wb_addr;
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        output  wire    [31:0]   o_wb_data;
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        input                   i_wb_ack, i_wb_stall;
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        input           [31:0]   i_wb_data;
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        input                   i_wb_err;
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        // Incoming interrupts
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        input                   i_ext_int;
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        // Outgoing interrupt
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        output  wire            o_ext_int;
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        // Wishbone slave
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        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
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        input           [31:0]   i_dbg_data;
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        output  reg             o_dbg_ack;
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        output  wire            o_dbg_stall;
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        output  wire    [31:0]   o_dbg_data;
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        //
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        output  wire    [31:0]   o_zip_debug;
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        // 
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        //
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        //
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        wire    sys_cyc, sys_stb, sys_we;
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        wire    [4:0]    sys_addr;
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        wire    [(AW-1):0]       cpu_addr;
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        wire    [31:0]   sys_data;
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        wire            sys_ack, sys_stall;
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        //
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        // The external debug interface
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        //
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        // We offer only a limited interface here, requiring a pre-register
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        // write to set the local address.  This interface allows access to
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        // the Zip System on a debug basis only, and not to the rest of the
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        // wishbone bus.  Further, to access these registers, the control
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        // register must first be accessed to both stop the CPU and to 
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        // set the following address in question.  Hence all accesses require
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        // two accesses: write the address to the control register (and halt
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        // the CPU if not halted), then read/write the data from the data
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        // register.
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        //
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        wire            cpu_break, dbg_cmd_write;
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        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
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        reg     [4:0]    cmd_addr;
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        wire    [3:0]    cpu_dbg_cc;
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        assign  dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr);
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        //
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        initial cmd_reset = 1'b1;
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        always @(posedge i_clk)
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                cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6]));
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        //
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        initial cmd_halt  = 1'b1;
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        always @(posedge i_clk)
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                if (i_rst)
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                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
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                else if (dbg_cmd_write)
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                        cmd_halt <= ((i_dbg_data[10])||(i_dbg_data[8]));
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                else if ((cmd_step)||(cpu_break))
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                        cmd_halt  <= 1'b1;
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        always @(posedge i_clk)
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                if (i_rst)
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                        cmd_clear_pf_cache <= 1'b0;
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                else if (dbg_cmd_write)
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                        cmd_clear_pf_cache <= i_dbg_data[11];
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                else
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                        cmd_clear_pf_cache <= 1'b0;
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        //
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        initial cmd_step  = 1'b0;
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        always @(posedge i_clk)
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                cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]);
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        //
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        always @(posedge i_clk)
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                if (dbg_cmd_write)
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                        cmd_addr <= i_dbg_data[4:0];
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        wire    cpu_reset;
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        assign  cpu_reset = (cmd_reset)||(i_rst);
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        wire    cpu_halt, cpu_dbg_stall;
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        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
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        wire    [31:0]   cmd_data;
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        // Values:
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        //      0x0003f -> cmd_addr mask
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        //      0x00040 -> reset
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        //      0x00080 -> PIC interrrupts enabled
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        //      0x00100 -> cmd_step
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        //      0x00200 -> cmd_stall
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        //      0x00400 -> cmd_halt
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        //      0x00800 -> cmd_clear_pf_cache
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        //      0x01000 -> cc.sleep
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        //      0x02000 -> cc.gie
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        //      0x10000 -> External interrupt line is high
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        assign  cmd_data = { 7'h00, 8'h00, i_ext_int,
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                        cpu_dbg_cc,
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                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
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                        1'b0, cpu_reset, 1'b0, cmd_addr };
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        //
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        // The CPU itself
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        //
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        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
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                        cpu_we, cpu_dbg_we,
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                        cpu_op_stall, cpu_pf_stall, cpu_i_count;
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        wire    [31:0]   cpu_data;
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        wire    [31:0]   cpu_dbg_data;
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        assign cpu_dbg_we = ((i_dbg_cyc)&&(i_dbg_stb)
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                                        &&(i_dbg_we)&&(i_dbg_addr));
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        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
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                thecpu(i_clk, cpu_reset, i_ext_int,
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                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
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                                i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
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                                cpu_dbg_cc, cpu_break,
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                        o_wb_cyc, o_wb_stb,
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                                cpu_lcl_cyc, cpu_lcl_stb,
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                                o_wb_we, o_wb_addr, o_wb_data,
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                                i_wb_ack, i_wb_stall, i_wb_data,
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                                i_wb_err,
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                        cpu_op_stall, cpu_pf_stall, cpu_i_count,
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                        o_zip_debug);
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        // Return debug response values
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        assign  o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;
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        initial o_dbg_ack = 1'b0;
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        always @(posedge i_clk)
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                o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
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        assign  o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
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        assign  o_ext_int = (cmd_halt) && (~i_wb_stall);
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endmodule

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