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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 11

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 3 dgisselq
// While I hate adding delays to any bus access, these two are required
86
// to make timing close in my Basys-3 design.
87
`define DELAY_EXT_BUS
88
`define DELAY_DBG_BUS
89
//
90
//
91
// Now, where am I placing all of my peripherals?
92 2 dgisselq
`define PERIPHBASE      32'hc0000000
93
`define INTCTRL         4'h0    // 
94
`define WATCHDOG        4'h1    // Interrupt generates reset signal
95
`define CACHECTRL       4'h2    // Sets IVEC[0]
96
`define CTRINT          4'h3    // Sets IVEC[5]
97
`define TIMER_A         4'h4    // Sets IVEC[4]
98
`define TIMER_B         4'h5    // Sets IVEC[3]
99
`define TIMER_C         4'h6    // Sets IVEC[2]
100
`define JIFFIES         4'h7    // Sets IVEC[1]
101
 
102
`define MSTR_TASK_CTR   4'h8
103
`define MSTR_MSTL_CTR   4'h9
104
`define MSTR_PSTL_CTR   4'ha
105
`define MSTR_ASTL_CTR   4'hb
106
`define USER_TASK_CTR   4'hc
107
`define USER_MSTL_CTR   4'hd
108
`define USER_PSTL_CTR   4'he
109
`define USER_ASTL_CTR   4'hf
110
 
111
`define CACHEBASE       16'hc010        //
112
// `define      RTC_CLOCK       32'hc0000008    // A global something
113
// `define      BITREV          32'hc0000003
114
//
115
//      DBGCTRL
116
//              10 HALT
117
//               9 HALT(ED)
118
//               8 STEP (W=1 steps, and returns to halted)
119
//               7 INTERRUPT-FLAG
120
//               6 RESET_FLAG
121
//              ADDRESS:
122
//               5      PERIPHERAL-BIT
123
//              [4:0]   REGISTER-ADDR
124
//      DBGDATA
125
//              read/writes internal registers
126
module  zipsystem(i_clk, i_rst,
127
                // Wishbone master interface from the CPU
128
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
129
                        i_wb_ack, i_wb_stall, i_wb_data,
130
                // Incoming interrupts
131
                i_ext_int,
132
                // Wishbone slave interface for debugging purposes
133
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
134
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
135
        parameter       RESET_ADDRESS=32'h0100000;
136
        input   i_clk, i_rst;
137
        // Wishbone master
138
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
139
        output  wire    [31:0]   o_wb_addr;
140
        output  wire    [31:0]   o_wb_data;
141
        input                   i_wb_ack, i_wb_stall;
142
        input           [31:0]   i_wb_data;
143
        // Incoming interrupts
144
        input                   i_ext_int;
145
        // Wishbone slave
146
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
147
        input           [31:0]   i_dbg_data;
148
        output  wire            o_dbg_ack;
149
        output  wire            o_dbg_stall;
150
        output  wire    [31:0]   o_dbg_data;
151
 
152
        wire    [31:0]   ext_idata;
153
 
154
        // Delay the debug port by one clock, to meet timing requirements
155
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
156
        wire    [31:0]   dbg_idata, dbg_odata;
157
        reg             dbg_ack;
158 3 dgisselq
`ifdef  DELAY_DBG_BUS
159 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
160
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
161
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
162
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
163
                        dbg_ack, dbg_stall, dbg_odata);
164 3 dgisselq
`else
165
        assign  dbg_cyc     = i_dbg_cyc;
166
        assign  dbg_stb     = i_dbg_stb;
167
        assign  dbg_we      = i_dbg_we;
168
        assign  dbg_addr    = i_dbg_addr;
169
        assign  dbg_idata   = i_dbg_data;
170
        assign  o_dbg_ack   = dbg_ack;
171
        assign  o_dbg_stall = dbg_stall;
172
        assign  o_dbg_data  = dbg_odata;
173
`endif
174 2 dgisselq
 
175
        // 
176
        //
177
        //
178
        wire    sys_cyc, sys_stb, sys_we;
179
        wire    [3:0]    sys_addr;
180
        wire    [31:0]   cpu_addr;
181
        wire    [31:0]   sys_data;
182
        // wire         sys_ack, sys_stall;
183
 
184
        //
185
        // The external debug interface
186
        //
187
        // We offer only a limited interface here, requiring a pre-register
188
        // write to set the local address.  This interface allows access to
189
        // the Zip System on a debug basis only, and not to the rest of the
190
        // wishbone bus.  Further, to access these registers, the control
191
        // register must first be accessed to both stop the CPU and to 
192
        // set the following address in question.  Hence all accesses require
193
        // two accesses: write the address to the control register (and halt
194
        // the CPU if not halted), then read/write the data from the data
195
        // register.
196
        //
197 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
198 2 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step;
199
        reg     [5:0]    cmd_addr;
200 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
201
        //
202 2 dgisselq
        initial cmd_reset = 1'b1;
203 9 dgisselq
        always @(posedge i_clk)
204
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
205
        //
206 2 dgisselq
        initial cmd_halt  = 1'b1;
207
        always @(posedge i_clk)
208
                if (i_rst)
209 11 dgisselq
                        cmd_halt <= 1'b1;
210 9 dgisselq
                else if (dbg_cmd_write)
211 2 dgisselq
                        cmd_halt <= dbg_idata[10];
212 9 dgisselq
                else if ((cmd_step)||(cpu_break))
213
                        cmd_halt  <= 1'b1;
214
        //
215
        initial cmd_step  = 1'b0;
216
        always @(posedge i_clk)
217
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
218
        //
219
        always @(posedge i_clk)
220
                if (dbg_cmd_write)
221 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
222 9 dgisselq
 
223 2 dgisselq
        wire    cpu_reset;
224
        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
225
 
226
        wire    cpu_halt, cpu_dbg_stall;
227
        assign  cpu_halt = (cmd_halt)&&(~cmd_step);
228
        wire    [31:0]   pic_data;
229
        wire    [31:0]   cmd_data;
230
        assign  cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15],
231
                        cpu_reset, cmd_addr };
232
 
233
`ifdef  USE_TRAP
234
        //
235
        // The TRAP peripheral
236
        //
237
        wire            trap_ack, trap_stall, trap_int;
238
        wire    [31:0]   trap_data;
239
        ziptrap trapp(i_clk,
240
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
241
                                sys_data,
242
                                trap_ack, trap_stall, trap_data, trap_int);
243
`endif
244
 
245
        //
246
        // The WATCHDOG Timer
247
        //
248
        wire            wdt_ack, wdt_stall, wdt_reset;
249
        wire    [31:0]   wdt_data;
250
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
251
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
252
                                sys_data,
253
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
254
 
255
        //
256
        // The Flash Cache, a pre-read cache to memory that can be used to
257
        // create a fast memory access area
258
        //
259
        wire            cache_int;
260
        wire    [31:0]   cache_data;
261
        wire            cache_stb, cache_ack, cache_stall;
262
        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
263
        wire    [31:0]   fc_data, fc_addr;
264
        flashcache      #(10) manualcache(i_clk,
265
                                sys_cyc, cache_stb,
266
                                ((sys_stb)&&(sys_addr == `CACHECTRL)),
267
                                sys_we, cpu_addr[9:0], sys_data,
268
                                        cache_ack, cache_stall, cache_data,
269
                                // Need the outgoing CACHE wishbone bus
270
                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
271
                                        fc_ack, fc_stall, ext_idata,
272
                                // Cache interrupt, for upon completion
273
                                cache_int);
274
 
275
 
276
        // Counters -- for performance measurement and accounting
277
        //
278
        // Here's the stuff we'll be counting ....
279
        //
280 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
281 2 dgisselq
 
282
        //
283
        // The master counters will, in general, not be reset.  They'll be used
284
        // for an overall counter.
285
        //
286
        // Master task counter
287
        wire            mtc_ack, mtc_stall, mtc_int;
288
        wire    [31:0]   mtc_data;
289
        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
290
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
291
                                        sys_we, sys_data,
292
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
293
 
294 9 dgisselq
        // Master Operand Stall counter
295
        wire            moc_ack, moc_stall, moc_int;
296
        wire    [31:0]   moc_data;
297
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
298 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
299
                                        sys_we, sys_data,
300 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
301 2 dgisselq
 
302
        // Master PreFetch-Stall counter
303
        wire            mpc_ack, mpc_stall, mpc_int;
304
        wire    [31:0]   mpc_data;
305 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
306 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
307
                                        sys_we, sys_data,
308
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
309
 
310 9 dgisselq
        // Master Instruction counter
311
        wire            mic_ack, mic_stall, mic_int;
312
        wire    [31:0]   mic_data;
313
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
314 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
315
                                        sys_we, sys_data,
316 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
317 2 dgisselq
 
318
        //
319
        // The user counters are different from those of the master.  They will
320
        // be reset any time a task is given control of the CPU.
321
        //
322
        // User task counter
323
        wire            utc_ack, utc_stall, utc_int;
324
        wire    [31:0]   utc_data;
325
        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,
326
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
327
                                        sys_we, sys_data,
328
                                utc_ack, utc_stall, utc_data, utc_int);
329
 
330 9 dgisselq
        // User Op-Stall counter
331
        wire            uoc_ack, uoc_stall, uoc_int;
332
        wire    [31:0]   uoc_data;
333
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
334 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
335
                                        sys_we, sys_data,
336 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
337 2 dgisselq
 
338
        // User PreFetch-Stall counter
339
        wire            upc_ack, upc_stall, upc_int;
340
        wire    [31:0]   upc_data;
341 9 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
342 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
343
                                        sys_we, sys_data,
344
                                upc_ack, upc_stall, upc_data, upc_int);
345
 
346 9 dgisselq
        // User instruction counter
347
        wire            uic_ack, uic_stall, uic_int;
348
        wire    [31:0]   uic_data;
349
        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,
350 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_ASTL_CTR),
351
                                        sys_we, sys_data,
352 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
353 2 dgisselq
 
354
        // A little bit of pre-cleanup (actr = accounting counters)
355
        wire            actr_ack, actr_stall;
356
        wire    [31:0]   actr_data;
357 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
358
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
359
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
360
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
361 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
362 9 dgisselq
                                : ((moc_ack) ? moc_data
363 2 dgisselq
                                : ((mpc_ack) ? mpc_data
364 9 dgisselq
                                : ((mic_ack) ? mic_data
365 2 dgisselq
                                : ((utc_ack) ? utc_data
366 9 dgisselq
                                : ((uoc_ack) ? uoc_data
367 2 dgisselq
                                : ((upc_ack) ? upc_data
368 9 dgisselq
                                : uic_data)))))));
369 2 dgisselq
 
370
 
371
 
372
        //
373
        // Counter Interrupt controller
374
        //
375
        reg             ctri_ack;
376
        wire            ctri_stall, ctri_int, ctri_sel;
377
        wire    [7:0]    ctri_vector;
378
        wire    [31:0]   ctri_data;
379
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
380 9 dgisselq
        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
381
                                        utc_int, uoc_int, upc_int, uic_int };
382 2 dgisselq
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
383
                                sys_data, ctri_data, ctri_vector, ctri_int);
384
        always @(posedge i_clk)
385
                ctri_ack <= ctri_sel;
386
 
387
 
388
        //
389
        // Timer A
390
        //
391
        wire            tma_ack, tma_stall, tma_int;
392
        wire    [31:0]   tma_data;
393
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
394
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
395
                                sys_data,
396
                        tma_ack, tma_stall, tma_data, tma_int);
397
 
398
        //
399
        // Timer B
400
        //
401
        wire            tmb_ack, tmb_stall, tmb_int;
402
        wire    [31:0]   tmb_data;
403
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
404
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
405
                                sys_data,
406
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
407
 
408
        //
409
        // Timer C
410
        //
411
        wire            tmc_ack, tmc_stall, tmc_int;
412
        wire    [31:0]   tmc_data;
413
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
414
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
415
                                sys_data,
416
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
417
 
418
        //
419
        // JIFFIES
420
        //
421
        wire            jif_ack, jif_stall, jif_int;
422
        wire    [31:0]   jif_data;
423
        zipjiffies jiffies(i_clk, ~cmd_halt,
424
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
425
                                sys_data,
426
                        jif_ack, jif_stall, jif_data, jif_int);
427
 
428
        //
429
        // The programmable interrupt controller peripheral
430
        //
431
        wire            pic_interrupt;
432
        wire    [6:0]    int_vector;
433
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
434
                                        jif_int, cache_int };
435
        icontrol #(7)   pic(i_clk, cpu_reset,
436
                                (sys_cyc)&&(sys_stb)&&(sys_we)
437
                                        &&(sys_addr==`INTCTRL),
438
                                sys_data, pic_data,
439
                                int_vector, pic_interrupt);
440
        reg     pic_ack;
441
        always @(posedge i_clk)
442
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
443
 
444
        //
445
        // The CPU itself
446
        //
447
        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
448
        wire    [31:0]   cpu_data, wb_data;
449
        wire            cpu_ack, cpu_stall;
450
        wire    [31:0]   cpu_dbg_data;
451
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
452
                                        &&(dbg_we)&&(dbg_addr));
453
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
454
                        cpu_halt, cmd_addr[4:0], cpu_dbg_we,
455
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
456
                                cpu_break,
457
                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
458
                                cpu_ack, cpu_stall, wb_data,
459 9 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count);
460 2 dgisselq
 
461
        // Now, arbitrate the bus ... first for the local peripherals
462
        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
463
        assign  sys_stb = (cpu_cyc)
464
                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
465
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
466
 
467
        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;
468
        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
469
        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
470
        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
471
 
472
        // Return debug response values
473
        assign  dbg_odata = (~dbg_addr)?cmd_data
474
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
475
        initial dbg_ack = 1'b0;
476
        always @(posedge i_clk)
477
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
478
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
479
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
480
                                &&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));
481
 
482
        // Now for the external wishbone bus
483
        //      Need to arbitrate between the flash cache and the CPU
484
        // The way this works, though, the CPU will stall once the flash 
485
        // cache gets access to the bus--the CPU will be stuck until the 
486
        // flash cache is finished with the bus.
487
        wire            ext_cyc, ext_stb, ext_we;
488
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
489
        wire    [31:0]   ext_addr, ext_odata;
490
        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
491
                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
492
                                        fc_ack, fc_stall,
493
                        cpu_addr, cpu_data, cpu_we,
494
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
495
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
496
                        ext_addr, ext_odata, ext_we, ext_stb,
497
                                ext_cyc, ext_ack, ext_stall);
498
 
499 3 dgisselq
`ifdef  DELAY_EXT_BUS
500 2 dgisselq
        busdelay #(32,32) extbus(i_clk,
501
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
502
                                ext_ack, ext_stall, ext_idata,
503
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
504
                                i_wb_ack, i_wb_stall, i_wb_data);
505 3 dgisselq
`else
506
        assign  o_wb_cyc   = ext_cyc;
507
        assign  o_wb_stb   = ext_stb;
508
        assign  o_wb_we    = ext_we;
509
        assign  o_wb_addr  = ext_addr;
510
        assign  o_wb_data  = ext_odata;
511
        assign  ext_ack    = i_wb_ack;
512
        assign  ext_stall  = i_wb_stall;
513
        assign  ext_idata  = i_wb_data;
514
`endif
515 2 dgisselq
 
516
        wire            tmr_ack;
517
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
518
        wire    [31:0]   tmr_data;
519
        assign  tmr_data = (tma_ack)?tma_data
520
                                :(tmb_ack ? tmb_data
521
                                :(tmc_ack ? tmc_data
522
                                :jif_data));
523
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
524
                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
525
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
526
                        :(ext_idata)));
527
 
528
        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
529
                                | wdt_stall | cache_stall
530
                                | cpu_ext_stall);
531
        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
532
endmodule

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