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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 129

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63 69 dgisselq
//              Gisselquist Technology, LLC
64 2 dgisselq
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 66 dgisselq
`include "cpudefs.v"
86
//
87 36 dgisselq
// While I hate adding delays to any bus access, this next delay is required
88 3 dgisselq
// to make timing close in my Basys-3 design.
89
`define DELAY_DBG_BUS
90 36 dgisselq
// On my previous version, I needed to add a delay to access the external
91
// bus.  Activate the define below and that delay will be put back into place.
92
// This particular version no longer needs the delay in order to run at 
93
// 100 MHz.  Timing indicates I may even run this at 250 MHz without the
94
// delay too, so we're doing better.  To get rid of this, I placed the logic
95
// determining whether or not I was accessing the local system bus one clock
96
// earlier, or into the memops.v file.  This also required my wishbone bus
97
// arbiter to maintain the bus selection as well, so that got updated ...
98
// you get the picture.  But, the bottom line is that I no longer need this
99
// delay.
100 3 dgisselq
//
101 56 dgisselq
// `define      DELAY_EXT_BUS   // Required no longer!
102 3 dgisselq
//
103 36 dgisselq
//
104
// If space is tight, you might not wish to have your performance and
105
// accounting counters, so let's make those optional here
106
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
107
//      When including counters, 
108
//              Slice LUTs      ZipSystem       ZipCPU
109
//      With Counters           3315            2432
110
//      Without Counters        2796            2046
111
 
112
//
113 3 dgisselq
// Now, where am I placing all of my peripherals?
114 2 dgisselq
`define PERIPHBASE      32'hc0000000
115 36 dgisselq
`define INTCTRL         5'h0    // 
116
`define WATCHDOG        5'h1    // Interrupt generates reset signal
117 56 dgisselq
`define BUSWATCHDOG     5'h2    // Sets IVEC[0]
118 36 dgisselq
`define CTRINT          5'h3    // Sets IVEC[5]
119
`define TIMER_A         5'h4    // Sets IVEC[4]
120
`define TIMER_B         5'h5    // Sets IVEC[3]
121
`define TIMER_C         5'h6    // Sets IVEC[2]
122
`define JIFFIES         5'h7    // Sets IVEC[1]
123 2 dgisselq
 
124
 
125 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
126
`define MSTR_TASK_CTR   5'h08
127
`define MSTR_MSTL_CTR   5'h09
128
`define MSTR_PSTL_CTR   5'h0a
129
`define MSTR_INST_CTR   5'h0b
130
`define USER_TASK_CTR   5'h0c
131
`define USER_MSTL_CTR   5'h0d
132
`define USER_PSTL_CTR   5'h0e
133
`define USER_INST_CTR   5'h0f
134
`endif
135
 
136
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
137
// addresses, therefore we place it by itself and expand our address bus
138
// width here by another bit.
139
`define DMAC            5'h10
140
 
141 2 dgisselq
// `define      RTC_CLOCK       32'hc0000008    // A global something
142
// `define      BITREV          32'hc0000003
143
//
144
//      DBGCTRL
145
//              10 HALT
146
//               9 HALT(ED)
147
//               8 STEP (W=1 steps, and returns to halted)
148
//               7 INTERRUPT-FLAG
149
//               6 RESET_FLAG
150
//              ADDRESS:
151
//               5      PERIPHERAL-BIT
152
//              [4:0]   REGISTER-ADDR
153
//      DBGDATA
154
//              read/writes internal registers
155 66 dgisselq
//
156
//
157
//
158 2 dgisselq
module  zipsystem(i_clk, i_rst,
159
                // Wishbone master interface from the CPU
160
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
161 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
162 2 dgisselq
                // Incoming interrupts
163
                i_ext_int,
164 18 dgisselq
                // Our one outgoing interrupt
165
                o_ext_int,
166 2 dgisselq
                // Wishbone slave interface for debugging purposes
167
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
168 66 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data
169
`ifdef  DEBUG_SCOPE
170
                , o_cpu_debug
171
`endif
172
                );
173 48 dgisselq
        parameter       RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
174 84 dgisselq
                        LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
175 69 dgisselq
`ifdef  OPT_MULTIPLY
176
                        IMPLEMENT_MPY = 1,
177
`else
178
                        IMPLEMENT_MPY = 0,
179
`endif
180
`ifdef  OPT_DIVIDE
181
                        IMPLEMENT_DIVIDE=1,
182
`else
183
                        IMPLEMENT_DIVIDE=0,
184
`endif
185
`ifdef  OPT_IMPLEMENT_FPU
186 71 dgisselq
                        IMPLEMENT_FPU=1,
187
`else
188 69 dgisselq
                        IMPLEMENT_FPU=0,
189
`endif
190
                        IMPLEMENT_LOCK=1,
191 48 dgisselq
                        // Derived parameters
192
                        AW=ADDRESS_WIDTH;
193 2 dgisselq
        input   i_clk, i_rst;
194
        // Wishbone master
195
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
196 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
197 2 dgisselq
        output  wire    [31:0]   o_wb_data;
198
        input                   i_wb_ack, i_wb_stall;
199
        input           [31:0]   i_wb_data;
200 36 dgisselq
        input                   i_wb_err;
201 2 dgisselq
        // Incoming interrupts
202 34 dgisselq
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
203 18 dgisselq
        // Outgoing interrupt
204
        output  wire            o_ext_int;
205 2 dgisselq
        // Wishbone slave
206
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
207
        input           [31:0]   i_dbg_data;
208
        output  wire            o_dbg_ack;
209
        output  wire            o_dbg_stall;
210
        output  wire    [31:0]   o_dbg_data;
211 56 dgisselq
        //
212 66 dgisselq
`ifdef  DEBUG_SCOPE
213 56 dgisselq
        output  wire    [31:0]   o_cpu_debug;
214 66 dgisselq
`endif
215 2 dgisselq
 
216
        wire    [31:0]   ext_idata;
217
 
218 69 dgisselq
        // Handle our interrupt vector generation/coordination
219
        wire    [14:0]   main_int_vector, alt_int_vector;
220
        wire            ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int;
221
        wire            mtc_int, moc_int, mpc_int, mic_int,
222
                        utc_int, uoc_int, upc_int, uic_int;
223
        generate
224
        if (EXTERNAL_INTERRUPTS < 9)
225
                assign  main_int_vector = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
226
                                        i_ext_int, ctri_int,
227
                                        tma_int, tmb_int, tmc_int,
228
                                        jif_int, dmac_int };
229
        else
230
                assign  main_int_vector = { i_ext_int[8:0], ctri_int,
231
                                        tma_int, tmb_int, tmc_int,
232
                                        jif_int, dmac_int };
233
        endgenerate
234
        generate
235
        if (EXTERNAL_INTERRUPTS <= 9)
236
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
237
                assign  alt_int_vector = { 7'h00,
238
                                        mtc_int, moc_int, mpc_int, mic_int,
239
                                        utc_int, uoc_int, upc_int, uic_int };
240
`else
241
                assign  alt_int_vector = { 15'h00 };
242
`endif
243
        else
244
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
245
                assign  alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}},
246
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9],
247
                                        mtc_int, moc_int, mpc_int, mic_int,
248
                                        utc_int, uoc_int, upc_int, uic_int };
249
`else
250
                assign  alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}},
251
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
252
`endif
253
        endgenerate
254
 
255
 
256 2 dgisselq
        // Delay the debug port by one clock, to meet timing requirements
257
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
258
        wire    [31:0]   dbg_idata, dbg_odata;
259
        reg             dbg_ack;
260 3 dgisselq
`ifdef  DELAY_DBG_BUS
261 36 dgisselq
        wire            dbg_err, no_dbg_err;
262
        assign          dbg_err = 1'b0;
263 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
264
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
265 36 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
266 2 dgisselq
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
267 36 dgisselq
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
268 3 dgisselq
`else
269
        assign  dbg_cyc     = i_dbg_cyc;
270
        assign  dbg_stb     = i_dbg_stb;
271
        assign  dbg_we      = i_dbg_we;
272
        assign  dbg_addr    = i_dbg_addr;
273
        assign  dbg_idata   = i_dbg_data;
274
        assign  o_dbg_ack   = dbg_ack;
275
        assign  o_dbg_stall = dbg_stall;
276
        assign  o_dbg_data  = dbg_odata;
277
`endif
278 2 dgisselq
 
279
        // 
280
        //
281
        //
282
        wire    sys_cyc, sys_stb, sys_we;
283 36 dgisselq
        wire    [4:0]    sys_addr;
284 48 dgisselq
        wire    [(AW-1):0]       cpu_addr;
285 2 dgisselq
        wire    [31:0]   sys_data;
286 36 dgisselq
        wire            sys_ack, sys_stall;
287 2 dgisselq
 
288
        //
289
        // The external debug interface
290
        //
291
        // We offer only a limited interface here, requiring a pre-register
292
        // write to set the local address.  This interface allows access to
293
        // the Zip System on a debug basis only, and not to the rest of the
294
        // wishbone bus.  Further, to access these registers, the control
295
        // register must first be accessed to both stop the CPU and to 
296
        // set the following address in question.  Hence all accesses require
297
        // two accesses: write the address to the control register (and halt
298
        // the CPU if not halted), then read/write the data from the data
299
        // register.
300
        //
301 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
302 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
303 2 dgisselq
        reg     [5:0]    cmd_addr;
304 56 dgisselq
        wire    [3:0]    cpu_dbg_cc;
305 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
306
        //
307 2 dgisselq
        initial cmd_reset = 1'b1;
308 9 dgisselq
        always @(posedge i_clk)
309
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
310
        //
311 2 dgisselq
        initial cmd_halt  = 1'b1;
312
        always @(posedge i_clk)
313
                if (i_rst)
314 34 dgisselq
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
315 9 dgisselq
                else if (dbg_cmd_write)
316 36 dgisselq
                        cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
317 9 dgisselq
                else if ((cmd_step)||(cpu_break))
318
                        cmd_halt  <= 1'b1;
319 18 dgisselq
 
320
        always @(posedge i_clk)
321 56 dgisselq
                cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
322
                                        &&((dbg_idata[11])||(dbg_idata[6]));
323 9 dgisselq
        //
324
        initial cmd_step  = 1'b0;
325
        always @(posedge i_clk)
326
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
327
        //
328
        always @(posedge i_clk)
329
                if (dbg_cmd_write)
330 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
331 9 dgisselq
 
332 2 dgisselq
        wire    cpu_reset;
333 36 dgisselq
        assign  cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
334 2 dgisselq
 
335
        wire    cpu_halt, cpu_dbg_stall;
336 34 dgisselq
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
337 2 dgisselq
        wire    [31:0]   pic_data;
338
        wire    [31:0]   cmd_data;
339 18 dgisselq
        // Values:
340
        //      0x0003f -> cmd_addr mask
341
        //      0x00040 -> reset
342 69 dgisselq
        //      0x00080 -> PIC interrrupt pending
343 18 dgisselq
        //      0x00100 -> cmd_step
344
        //      0x00200 -> cmd_stall
345
        //      0x00400 -> cmd_halt
346
        //      0x00800 -> cmd_clear_pf_cache
347
        //      0x01000 -> cc.sleep
348
        //      0x02000 -> cc.gie
349 69 dgisselq
        //      0x04000 -> External (PIC) interrupt line is high
350
        //      Other external interrupts follow
351
        generate
352
        if (EXTERNAL_INTERRUPTS < 16)
353
                assign  cmd_data = { {(16-EXTERNAL_INTERRUPTS){1'b0}},
354
                                        i_ext_int,
355
                                cpu_dbg_cc,     // 4 bits
356
                                1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
357
                                pic_data[15], cpu_reset, cmd_addr };
358
        else
359
                assign  cmd_data = { i_ext_int[15:0], cpu_dbg_cc,
360
                                1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
361
                                pic_data[15], cpu_reset, cmd_addr };
362
        endgenerate
363
 
364 38 dgisselq
        wire    cpu_gie;
365
        assign  cpu_gie = cpu_dbg_cc[1];
366 2 dgisselq
 
367
        //
368
        // The WATCHDOG Timer
369
        //
370
        wire            wdt_ack, wdt_stall, wdt_reset;
371
        wire    [31:0]   wdt_data;
372
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
373
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
374
                                sys_data,
375
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
376
 
377
        //
378 56 dgisselq
        // Position two, a second watchdog timer--this time for the wishbone
379
        // bus, in order to tell/find wishbone bus lockups.  In its current
380
        // configuration, it cannot be configured and all bus accesses must
381
        // take less than the number written to this register.
382 2 dgisselq
        //
383 56 dgisselq
        reg     wdbus_ack;
384
        reg     [(AW-1):0]       r_wdbus_data;
385
        wire    [31:0]           wdbus_data;
386
        wire    [14:0]   wdbus_ignored_data;
387 69 dgisselq
        wire    reset_wdbus_timer, wdbus_int;
388 56 dgisselq
        assign  reset_wdbus_timer = ((o_wb_cyc)&&((o_wb_stb)||(i_wb_ack)));
389 69 dgisselq
        wbwatchdog #(14) watchbus(i_clk,(cpu_reset)||(reset_wdbus_timer),
390
                        o_wb_cyc, 14'h2000, wdbus_int);
391 56 dgisselq
        initial r_wdbus_data = 0;
392 36 dgisselq
        always @(posedge i_clk)
393 69 dgisselq
                if ((wdbus_int)||(cpu_ext_err))
394 56 dgisselq
                        r_wdbus_data = o_wb_addr;
395
        assign  wdbus_data = { {(32-AW){1'b0}}, r_wdbus_data };
396
        initial wdbus_ack = 1'b0;
397
        always @(posedge i_clk)
398
                wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02));
399
 
400 2 dgisselq
        // Counters -- for performance measurement and accounting
401
        //
402
        // Here's the stuff we'll be counting ....
403
        //
404 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
405 2 dgisselq
 
406 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
407 2 dgisselq
        //
408
        // The master counters will, in general, not be reset.  They'll be used
409
        // for an overall counter.
410
        //
411
        // Master task counter
412 69 dgisselq
        wire            mtc_ack, mtc_stall;
413 2 dgisselq
        wire    [31:0]   mtc_data;
414 36 dgisselq
        zipcounter      mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
415 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
416
                                        sys_we, sys_data,
417
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
418
 
419 9 dgisselq
        // Master Operand Stall counter
420 69 dgisselq
        wire            moc_ack, moc_stall;
421 9 dgisselq
        wire    [31:0]   moc_data;
422
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
423 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
424
                                        sys_we, sys_data,
425 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
426 2 dgisselq
 
427
        // Master PreFetch-Stall counter
428 69 dgisselq
        wire            mpc_ack, mpc_stall;
429 2 dgisselq
        wire    [31:0]   mpc_data;
430 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
431 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
432
                                        sys_we, sys_data,
433
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
434
 
435 9 dgisselq
        // Master Instruction counter
436 69 dgisselq
        wire            mic_ack, mic_stall;
437 9 dgisselq
        wire    [31:0]   mic_data;
438
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
439 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
440 2 dgisselq
                                        sys_we, sys_data,
441 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
442 2 dgisselq
 
443
        //
444
        // The user counters are different from those of the master.  They will
445
        // be reset any time a task is given control of the CPU.
446
        //
447
        // User task counter
448 69 dgisselq
        wire            utc_ack, utc_stall;
449 2 dgisselq
        wire    [31:0]   utc_data;
450 38 dgisselq
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
451 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
452
                                        sys_we, sys_data,
453
                                utc_ack, utc_stall, utc_data, utc_int);
454
 
455 9 dgisselq
        // User Op-Stall counter
456 69 dgisselq
        wire            uoc_ack, uoc_stall;
457 9 dgisselq
        wire    [31:0]   uoc_data;
458 38 dgisselq
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
459 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
460
                                        sys_we, sys_data,
461 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
462 2 dgisselq
 
463
        // User PreFetch-Stall counter
464 69 dgisselq
        wire            upc_ack, upc_stall;
465 2 dgisselq
        wire    [31:0]   upc_data;
466 38 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
467 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
468
                                        sys_we, sys_data,
469
                                upc_ack, upc_stall, upc_data, upc_int);
470
 
471 9 dgisselq
        // User instruction counter
472 69 dgisselq
        wire            uic_ack, uic_stall;
473 9 dgisselq
        wire    [31:0]   uic_data;
474 38 dgisselq
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
475 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
476 2 dgisselq
                                        sys_we, sys_data,
477 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
478 2 dgisselq
 
479
        // A little bit of pre-cleanup (actr = accounting counters)
480
        wire            actr_ack, actr_stall;
481
        wire    [31:0]   actr_data;
482 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
483
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
484
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
485
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
486 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
487 9 dgisselq
                                : ((moc_ack) ? moc_data
488 2 dgisselq
                                : ((mpc_ack) ? mpc_data
489 9 dgisselq
                                : ((mic_ack) ? mic_data
490 2 dgisselq
                                : ((utc_ack) ? utc_data
491 9 dgisselq
                                : ((uoc_ack) ? uoc_data
492 2 dgisselq
                                : ((upc_ack) ? upc_data
493 9 dgisselq
                                : uic_data)))))));
494 36 dgisselq
`else //        INCLUDE_ACCOUNTING_COUNTERS
495
        reg             actr_ack;
496
        wire            actr_stall;
497
        wire    [31:0]   actr_data;
498
        assign  actr_stall = 1'b0;
499
        assign  actr_data = 32'h0000;
500 2 dgisselq
 
501 36 dgisselq
        assign  mtc_int = 1'b0;
502
        assign  moc_int = 1'b0;
503
        assign  mpc_int = 1'b0;
504
        assign  mic_int = 1'b0;
505
        assign  utc_int = 1'b0;
506
        assign  uoc_int = 1'b0;
507
        assign  upc_int = 1'b0;
508
        assign  uic_int = 1'b0;
509
 
510
        always @(posedge i_clk)
511
                actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
512
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
513
 
514
        //
515
        // The DMA Controller
516
        //
517 69 dgisselq
        wire            dmac_stb, dc_err;
518 36 dgisselq
        wire    [31:0]   dmac_data;
519
        wire            dmac_ack, dmac_stall;
520
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
521 48 dgisselq
        wire    [31:0]   dc_data;
522
        wire    [(AW-1):0]       dc_addr;
523 36 dgisselq
        wire            cpu_gbl_cyc;
524
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
525 56 dgisselq
`ifdef  INCLUDE_DMA_CONTROLLER
526 48 dgisselq
        wbdmac  #(AW) dma_controller(i_clk,
527 36 dgisselq
                                sys_cyc, dmac_stb, sys_we,
528
                                        sys_addr[1:0], sys_data,
529
                                        dmac_ack, dmac_stall, dmac_data,
530
                                // Need the outgoing DMAC wishbone bus
531
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
532
                                        dc_ack, dc_stall, ext_idata, dc_err,
533
                                // External device interrupts
534 69 dgisselq
                                { 1'b0, alt_int_vector, 1'b0,
535
                                        main_int_vector[14:1], 1'b0 },
536 36 dgisselq
                                // DMAC interrupt, for upon completion
537 69 dgisselq
                                dmac_int);
538
                                // Whether or not the CPU wants the bus, and
539
                                // thus we must kick the DMAC off.
540
                                //   However, the logic required for this
541
                                //   override never worked well, so here
542
                                //   we just don't use it.
543
                                // cpu_gbl_cyc);
544 56 dgisselq
`else
545
        reg     r_dmac_ack;
546
        always @(posedge i_clk)
547
                r_dmac_ack <= (sys_cyc)&&(dmac_stb);
548
        assign  dmac_ack = r_dmac_ack;
549
        assign  dmac_data = 32'h000;
550
        assign  dmac_stall = 1'b0;
551 2 dgisselq
 
552 56 dgisselq
        assign  dc_cyc  = 1'b0;
553
        assign  dc_stb  = 1'b0;
554
        assign  dc_we   = 1'b0;
555
        assign  dc_addr = { (AW) {1'b0} };
556
        assign  dc_data = 32'h00;
557
 
558
        assign  dmac_int = 1'b0;
559
`endif
560
 
561 71 dgisselq
        wire            ctri_sel, ctri_stall;
562
        reg             ctri_ack;
563
        wire    [31:0]   ctri_data;
564 69 dgisselq
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
565
        always @(posedge i_clk)
566
                ctri_ack <= ctri_sel;
567 71 dgisselq
        assign  ctri_stall = 1'b0;
568 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
569 2 dgisselq
        //
570
        // Counter Interrupt controller
571
        //
572 69 dgisselq
        generate
573
        if (EXTERNAL_INTERRUPTS <= 9)
574
        begin
575
                icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel),
576
                                        sys_data, ctri_data, alt_int_vector[7:0],
577
                                        ctri_int);
578
        end else begin
579
                icontrol #(8+(EXTERNAL_INTERRUPTS-9))
580
                                ctri(i_clk, cpu_reset, (ctri_sel),
581
                                        sys_data, ctri_data,
582 115 dgisselq
                                        alt_int_vector[(EXTERNAL_INTERRUPTS-2):0],
583 69 dgisselq
                                        ctri_int);
584
        end endgenerate
585
 
586 36 dgisselq
`else   //      INCLUDE_ACCOUNTING_COUNTERS
587 2 dgisselq
 
588 69 dgisselq
        generate
589
        if (EXTERNAL_INTERRUPTS <= 9)
590
        begin
591
                assign  ctri_stall = 1'b0;
592
                assign  ctri_data  = 32'h0000;
593
                assign  ctri_int   = 1'b0;
594
        end else begin
595
                icontrol #(EXTERNAL_INTERRUPTS-9)
596
                                ctri(i_clk, cpu_reset, (ctri_sel),
597
                                        sys_data, ctri_data,
598
                                alt_int_vector[(EXTERNAL_INTERRUPTS-10):0],
599
                                        ctri_int);
600
        end endgenerate
601 36 dgisselq
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
602 2 dgisselq
 
603 36 dgisselq
 
604 2 dgisselq
        //
605
        // Timer A
606
        //
607 69 dgisselq
        wire            tma_ack, tma_stall;
608 2 dgisselq
        wire    [31:0]   tma_data;
609
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
610
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
611
                                sys_data,
612
                        tma_ack, tma_stall, tma_data, tma_int);
613
 
614
        //
615
        // Timer B
616
        //
617 69 dgisselq
        wire            tmb_ack, tmb_stall;
618 2 dgisselq
        wire    [31:0]   tmb_data;
619
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
620
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
621
                                sys_data,
622
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
623
 
624
        //
625
        // Timer C
626
        //
627 69 dgisselq
        wire            tmc_ack, tmc_stall;
628 2 dgisselq
        wire    [31:0]   tmc_data;
629
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
630
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
631
                                sys_data,
632
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
633
 
634
        //
635
        // JIFFIES
636
        //
637 69 dgisselq
        wire            jif_ack, jif_stall;
638 2 dgisselq
        wire    [31:0]   jif_data;
639
        zipjiffies jiffies(i_clk, ~cmd_halt,
640
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
641
                                sys_data,
642
                        jif_ack, jif_stall, jif_data, jif_int);
643
 
644
        //
645
        // The programmable interrupt controller peripheral
646
        //
647
        wire            pic_interrupt;
648 69 dgisselq
        generate
649
        if (EXTERNAL_INTERRUPTS < 9)
650
        begin
651
                icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
652
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
653
                                                &&(sys_addr==`INTCTRL),
654
                                        sys_data, pic_data,
655
                                        main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], pic_interrupt);
656
        end else begin
657
                icontrol #(15)  pic(i_clk, cpu_reset,
658
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
659
                                                &&(sys_addr==`INTCTRL),
660
                                        sys_data, pic_data,
661
                                        main_int_vector[14:0], pic_interrupt);
662
        end endgenerate
663
 
664 36 dgisselq
        wire    pic_stall;
665
        assign  pic_stall = 1'b0;
666 2 dgisselq
        reg     pic_ack;
667
        always @(posedge i_clk)
668
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
669
 
670
        //
671
        // The CPU itself
672
        //
673 36 dgisselq
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
674
                        cpu_we, cpu_dbg_we;
675 2 dgisselq
        wire    [31:0]   cpu_data, wb_data;
676 36 dgisselq
        wire            cpu_ack, cpu_stall, cpu_err;
677 2 dgisselq
        wire    [31:0]   cpu_dbg_data;
678
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
679
                                        &&(dbg_we)&&(dbg_addr));
680 69 dgisselq
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE, IMPLEMENT_MPY,
681
                        IMPLEMENT_DIVIDE, IMPLEMENT_FPU, IMPLEMENT_LOCK)
682 48 dgisselq
                thecpu(i_clk, cpu_reset, pic_interrupt,
683 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
684 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
685 18 dgisselq
                                cpu_dbg_cc, cpu_break,
686 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb,
687
                                cpu_lcl_cyc, cpu_lcl_stb,
688
                                cpu_we, cpu_addr, cpu_data,
689 2 dgisselq
                                cpu_ack, cpu_stall, wb_data,
690 36 dgisselq
                                cpu_err,
691 66 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
692
`ifdef  DEBUG_SCOPE
693
                        , o_cpu_debug
694
`endif
695
                        );
696 2 dgisselq
 
697
        // Now, arbitrate the bus ... first for the local peripherals
698 36 dgisselq
        // For the debugger to have access to the local system bus, the
699
        // following must be true:
700
        //      (dbg_cyc)       The debugger must request the bus
701
        //      (~cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
702
        //      (dbg_addr)      The debugger must be requesting its data
703
        //                              register, not just the control register
704
        // and one of two other things.  Either
705
        //      ((cpu_halt)&&(~cpu_dbg_stall))  the CPU is completely halted,
706
        // or
707
        //      (~cmd_addr[5])          we are trying to read a CPU register
708
        //                      while in motion.  Let the user beware that,
709
        //                      by not waiting for the CPU to fully halt,
710
        //                      his results may not be what he expects.
711
        //
712
        wire    sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
713
                                &&(((cpu_halt)&&(~cpu_dbg_stall))
714
                                        ||(~cmd_addr[5]));
715
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
716
        assign  sys_stb = (cpu_lcl_cyc)
717
                                ? (cpu_lcl_stb)
718 2 dgisselq
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
719
 
720 36 dgisselq
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
721
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
722
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
723 2 dgisselq
 
724
        // Return debug response values
725
        assign  dbg_odata = (~dbg_addr)?cmd_data
726
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
727
        initial dbg_ack = 1'b0;
728
        always @(posedge i_clk)
729 36 dgisselq
                dbg_ack <= (dbg_cyc)&&(~dbg_stall);
730
        assign  dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
731 2 dgisselq
 
732
        // Now for the external wishbone bus
733
        //      Need to arbitrate between the flash cache and the CPU
734
        // The way this works, though, the CPU will stall once the flash 
735
        // cache gets access to the bus--the CPU will be stuck until the 
736
        // flash cache is finished with the bus.
737 36 dgisselq
        wire            ext_cyc, ext_stb, ext_we, ext_err;
738
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
739
                                cpu_ext_err;
740 48 dgisselq
        wire    [(AW-1):0]       ext_addr;
741
        wire    [31:0]           ext_odata;
742 56 dgisselq
        wbpriarbiter #(32,AW) dmacvcpu(i_clk,
743 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
744
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
745
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
746
                                        dc_ack, dc_stall, dc_err,
747
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
748
                                ext_ack, ext_stall, ext_err);
749 2 dgisselq
 
750 3 dgisselq
`ifdef  DELAY_EXT_BUS
751 48 dgisselq
        busdelay #(AW,32) extbus(i_clk,
752 2 dgisselq
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
753 36 dgisselq
                                ext_ack, ext_stall, ext_idata, ext_err,
754 2 dgisselq
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
755 56 dgisselq
                                i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
756 3 dgisselq
`else
757
        assign  o_wb_cyc   = ext_cyc;
758
        assign  o_wb_stb   = ext_stb;
759
        assign  o_wb_we    = ext_we;
760
        assign  o_wb_addr  = ext_addr;
761
        assign  o_wb_data  = ext_odata;
762
        assign  ext_ack    = i_wb_ack;
763
        assign  ext_stall  = i_wb_stall;
764
        assign  ext_idata  = i_wb_data;
765 56 dgisselq
        assign  ext_err    = (i_wb_err)||(wdbus_int);
766 3 dgisselq
`endif
767 2 dgisselq
 
768
        wire            tmr_ack;
769
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
770
        wire    [31:0]   tmr_data;
771
        assign  tmr_data = (tma_ack)?tma_data
772
                                :(tmb_ack ? tmb_data
773
                                :(tmc_ack ? tmc_data
774
                                :jif_data));
775
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
776 36 dgisselq
                        :((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
777 2 dgisselq
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
778 56 dgisselq
                        :((wdbus_ack)?wdbus_data:(ext_idata))));
779 2 dgisselq
 
780 36 dgisselq
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
781
                                | wdt_stall | ctri_stall | actr_stall
782 69 dgisselq
                                | pic_stall | dmac_stall);
783 36 dgisselq
        assign  cpu_stall = (sys_stall)|(cpu_ext_stall);
784 56 dgisselq
        assign  sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
785 36 dgisselq
        assign  cpu_ack = (sys_ack)||(cpu_ext_ack);
786
        assign  cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
787 18 dgisselq
 
788
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
789
 
790 2 dgisselq
endmodule

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