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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 38

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 36 dgisselq
// While I hate adding delays to any bus access, this next delay is required
86 3 dgisselq
// to make timing close in my Basys-3 design.
87
`define DELAY_DBG_BUS
88 36 dgisselq
// On my previous version, I needed to add a delay to access the external
89
// bus.  Activate the define below and that delay will be put back into place.
90
// This particular version no longer needs the delay in order to run at 
91
// 100 MHz.  Timing indicates I may even run this at 250 MHz without the
92
// delay too, so we're doing better.  To get rid of this, I placed the logic
93
// determining whether or not I was accessing the local system bus one clock
94
// earlier, or into the memops.v file.  This also required my wishbone bus
95
// arbiter to maintain the bus selection as well, so that got updated ...
96
// you get the picture.  But, the bottom line is that I no longer need this
97
// delay.
98 3 dgisselq
//
99 36 dgisselq
// `define      DELAY_EXT_BUS   // Required no longer!k
100 3 dgisselq
//
101 36 dgisselq
//
102
// If space is tight, you might not wish to have your performance and
103
// accounting counters, so let's make those optional here
104
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
105
//      When including counters, 
106
//              Slice LUTs      ZipSystem       ZipCPU
107
//      With Counters           3315            2432
108
//      Without Counters        2796            2046
109
`define INCLUDE_ACCOUNTING_COUNTERS
110
 
111
//
112 3 dgisselq
// Now, where am I placing all of my peripherals?
113 2 dgisselq
`define PERIPHBASE      32'hc0000000
114 36 dgisselq
`define INTCTRL         5'h0    // 
115
`define WATCHDOG        5'h1    // Interrupt generates reset signal
116
// `define      CACHECTRL       5'h2    // Sets IVEC[0]
117
`define CTRINT          5'h3    // Sets IVEC[5]
118
`define TIMER_A         5'h4    // Sets IVEC[4]
119
`define TIMER_B         5'h5    // Sets IVEC[3]
120
`define TIMER_C         5'h6    // Sets IVEC[2]
121
`define JIFFIES         5'h7    // Sets IVEC[1]
122 2 dgisselq
 
123
 
124 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
125
`define MSTR_TASK_CTR   5'h08
126
`define MSTR_MSTL_CTR   5'h09
127
`define MSTR_PSTL_CTR   5'h0a
128
`define MSTR_INST_CTR   5'h0b
129
`define USER_TASK_CTR   5'h0c
130
`define USER_MSTL_CTR   5'h0d
131
`define USER_PSTL_CTR   5'h0e
132
`define USER_INST_CTR   5'h0f
133
`endif
134
 
135
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
136
// addresses, therefore we place it by itself and expand our address bus
137
// width here by another bit.
138
`define DMAC            5'h10
139
 
140 2 dgisselq
// `define      RTC_CLOCK       32'hc0000008    // A global something
141
// `define      BITREV          32'hc0000003
142
//
143
//      DBGCTRL
144
//              10 HALT
145
//               9 HALT(ED)
146
//               8 STEP (W=1 steps, and returns to halted)
147
//               7 INTERRUPT-FLAG
148
//               6 RESET_FLAG
149
//              ADDRESS:
150
//               5      PERIPHERAL-BIT
151
//              [4:0]   REGISTER-ADDR
152
//      DBGDATA
153
//              read/writes internal registers
154
module  zipsystem(i_clk, i_rst,
155
                // Wishbone master interface from the CPU
156
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
157 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
158 2 dgisselq
                // Incoming interrupts
159
                i_ext_int,
160 18 dgisselq
                // Our one outgoing interrupt
161
                o_ext_int,
162 2 dgisselq
                // Wishbone slave interface for debugging purposes
163
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
164
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
165 34 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, START_HALTED=1,
166
                        EXTERNAL_INTERRUPTS=1;
167 2 dgisselq
        input   i_clk, i_rst;
168
        // Wishbone master
169
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
170
        output  wire    [31:0]   o_wb_addr;
171
        output  wire    [31:0]   o_wb_data;
172
        input                   i_wb_ack, i_wb_stall;
173
        input           [31:0]   i_wb_data;
174 36 dgisselq
        input                   i_wb_err;
175 2 dgisselq
        // Incoming interrupts
176 34 dgisselq
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
177 18 dgisselq
        // Outgoing interrupt
178
        output  wire            o_ext_int;
179 2 dgisselq
        // Wishbone slave
180
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
181
        input           [31:0]   i_dbg_data;
182
        output  wire            o_dbg_ack;
183
        output  wire            o_dbg_stall;
184
        output  wire    [31:0]   o_dbg_data;
185
 
186
        wire    [31:0]   ext_idata;
187
 
188
        // Delay the debug port by one clock, to meet timing requirements
189
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
190
        wire    [31:0]   dbg_idata, dbg_odata;
191
        reg             dbg_ack;
192 3 dgisselq
`ifdef  DELAY_DBG_BUS
193 36 dgisselq
        wire            dbg_err, no_dbg_err;
194
        assign          dbg_err = 1'b0;
195 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
196
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
197 36 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
198 2 dgisselq
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
199 36 dgisselq
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
200 3 dgisselq
`else
201
        assign  dbg_cyc     = i_dbg_cyc;
202
        assign  dbg_stb     = i_dbg_stb;
203
        assign  dbg_we      = i_dbg_we;
204
        assign  dbg_addr    = i_dbg_addr;
205
        assign  dbg_idata   = i_dbg_data;
206
        assign  o_dbg_ack   = dbg_ack;
207
        assign  o_dbg_stall = dbg_stall;
208
        assign  o_dbg_data  = dbg_odata;
209
`endif
210 2 dgisselq
 
211
        // 
212
        //
213
        //
214
        wire    sys_cyc, sys_stb, sys_we;
215 36 dgisselq
        wire    [4:0]    sys_addr;
216 2 dgisselq
        wire    [31:0]   cpu_addr;
217
        wire    [31:0]   sys_data;
218 36 dgisselq
        wire            sys_ack, sys_stall;
219 2 dgisselq
 
220
        //
221
        // The external debug interface
222
        //
223
        // We offer only a limited interface here, requiring a pre-register
224
        // write to set the local address.  This interface allows access to
225
        // the Zip System on a debug basis only, and not to the rest of the
226
        // wishbone bus.  Further, to access these registers, the control
227
        // register must first be accessed to both stop the CPU and to 
228
        // set the following address in question.  Hence all accesses require
229
        // two accesses: write the address to the control register (and halt
230
        // the CPU if not halted), then read/write the data from the data
231
        // register.
232
        //
233 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
234 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
235 2 dgisselq
        reg     [5:0]    cmd_addr;
236 25 dgisselq
        wire    [1:0]    cpu_dbg_cc;
237 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
238
        //
239 2 dgisselq
        initial cmd_reset = 1'b1;
240 9 dgisselq
        always @(posedge i_clk)
241
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
242
        //
243 2 dgisselq
        initial cmd_halt  = 1'b1;
244
        always @(posedge i_clk)
245
                if (i_rst)
246 34 dgisselq
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
247 9 dgisselq
                else if (dbg_cmd_write)
248 36 dgisselq
                        cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
249 9 dgisselq
                else if ((cmd_step)||(cpu_break))
250
                        cmd_halt  <= 1'b1;
251 18 dgisselq
 
252
        always @(posedge i_clk)
253
                if (i_rst)
254
                        cmd_clear_pf_cache <= 1'b0;
255
                else if (dbg_cmd_write)
256
                        cmd_clear_pf_cache <= dbg_idata[11];
257
                else
258
                        cmd_clear_pf_cache <= 1'b0;
259 9 dgisselq
        //
260
        initial cmd_step  = 1'b0;
261
        always @(posedge i_clk)
262
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
263
        //
264
        always @(posedge i_clk)
265
                if (dbg_cmd_write)
266 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
267 9 dgisselq
 
268 2 dgisselq
        wire    cpu_reset;
269 36 dgisselq
        assign  cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
270 2 dgisselq
 
271
        wire    cpu_halt, cpu_dbg_stall;
272 34 dgisselq
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
273 2 dgisselq
        wire    [31:0]   pic_data;
274
        wire    [31:0]   cmd_data;
275 18 dgisselq
        // Values:
276
        //      0x0003f -> cmd_addr mask
277
        //      0x00040 -> reset
278 34 dgisselq
        //      0x00080 -> PIC interrrupts enabled
279 18 dgisselq
        //      0x00100 -> cmd_step
280
        //      0x00200 -> cmd_stall
281
        //      0x00400 -> cmd_halt
282
        //      0x00800 -> cmd_clear_pf_cache
283
        //      0x01000 -> cc.sleep
284
        //      0x02000 -> cc.gie
285
        //      0x10000 -> External interrupt line is high
286 34 dgisselq
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
287
                        2'b00, cpu_dbg_cc,
288 18 dgisselq
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
289
                        pic_data[15], cpu_reset, cmd_addr };
290 38 dgisselq
        wire    cpu_gie;
291
        assign  cpu_gie = cpu_dbg_cc[1];
292 2 dgisselq
 
293
`ifdef  USE_TRAP
294
        //
295
        // The TRAP peripheral
296
        //
297
        wire            trap_ack, trap_stall, trap_int;
298
        wire    [31:0]   trap_data;
299
        ziptrap trapp(i_clk,
300
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
301
                                sys_data,
302
                                trap_ack, trap_stall, trap_data, trap_int);
303
`endif
304
 
305
        //
306
        // The WATCHDOG Timer
307
        //
308
        wire            wdt_ack, wdt_stall, wdt_reset;
309
        wire    [31:0]   wdt_data;
310
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
311
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
312
                                sys_data,
313
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
314
 
315
        //
316 36 dgisselq
        // Position two ... unclaimed / unused
317 2 dgisselq
        //
318 36 dgisselq
        wire    cache_stall;
319
        assign  cache_stall = 1'b0;
320
        reg     cache_ack;
321
        always @(posedge i_clk)
322
                cache_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02);
323 2 dgisselq
        // Counters -- for performance measurement and accounting
324
        //
325
        // Here's the stuff we'll be counting ....
326
        //
327 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
328 2 dgisselq
 
329 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
330 2 dgisselq
        //
331
        // The master counters will, in general, not be reset.  They'll be used
332
        // for an overall counter.
333
        //
334
        // Master task counter
335
        wire            mtc_ack, mtc_stall, mtc_int;
336
        wire    [31:0]   mtc_data;
337 36 dgisselq
        zipcounter      mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
338 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
339
                                        sys_we, sys_data,
340
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
341
 
342 9 dgisselq
        // Master Operand Stall counter
343
        wire            moc_ack, moc_stall, moc_int;
344
        wire    [31:0]   moc_data;
345
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
346 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
347
                                        sys_we, sys_data,
348 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
349 2 dgisselq
 
350
        // Master PreFetch-Stall counter
351
        wire            mpc_ack, mpc_stall, mpc_int;
352
        wire    [31:0]   mpc_data;
353 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
354 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
355
                                        sys_we, sys_data,
356
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
357
 
358 9 dgisselq
        // Master Instruction counter
359
        wire            mic_ack, mic_stall, mic_int;
360
        wire    [31:0]   mic_data;
361
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
362 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
363 2 dgisselq
                                        sys_we, sys_data,
364 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
365 2 dgisselq
 
366
        //
367
        // The user counters are different from those of the master.  They will
368
        // be reset any time a task is given control of the CPU.
369
        //
370
        // User task counter
371
        wire            utc_ack, utc_stall, utc_int;
372
        wire    [31:0]   utc_data;
373 38 dgisselq
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
374 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
375
                                        sys_we, sys_data,
376
                                utc_ack, utc_stall, utc_data, utc_int);
377
 
378 9 dgisselq
        // User Op-Stall counter
379
        wire            uoc_ack, uoc_stall, uoc_int;
380
        wire    [31:0]   uoc_data;
381 38 dgisselq
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
382 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
383
                                        sys_we, sys_data,
384 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
385 2 dgisselq
 
386
        // User PreFetch-Stall counter
387
        wire            upc_ack, upc_stall, upc_int;
388
        wire    [31:0]   upc_data;
389 38 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
390 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
391
                                        sys_we, sys_data,
392
                                upc_ack, upc_stall, upc_data, upc_int);
393
 
394 9 dgisselq
        // User instruction counter
395
        wire            uic_ack, uic_stall, uic_int;
396
        wire    [31:0]   uic_data;
397 38 dgisselq
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
398 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
399 2 dgisselq
                                        sys_we, sys_data,
400 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
401 2 dgisselq
 
402
        // A little bit of pre-cleanup (actr = accounting counters)
403
        wire            actr_ack, actr_stall;
404
        wire    [31:0]   actr_data;
405 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
406
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
407
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
408
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
409 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
410 9 dgisselq
                                : ((moc_ack) ? moc_data
411 2 dgisselq
                                : ((mpc_ack) ? mpc_data
412 9 dgisselq
                                : ((mic_ack) ? mic_data
413 2 dgisselq
                                : ((utc_ack) ? utc_data
414 9 dgisselq
                                : ((uoc_ack) ? uoc_data
415 2 dgisselq
                                : ((upc_ack) ? upc_data
416 9 dgisselq
                                : uic_data)))))));
417 36 dgisselq
`else //        INCLUDE_ACCOUNTING_COUNTERS
418
        reg             actr_ack;
419
        wire            actr_stall;
420
        wire    [31:0]   actr_data;
421
        assign  actr_stall = 1'b0;
422
        assign  actr_data = 32'h0000;
423 2 dgisselq
 
424 36 dgisselq
        wire    utc_int, uoc_int, upc_int, uic_int;
425
        wire    mtc_int, moc_int, mpc_int, mic_int;
426
        assign  mtc_int = 1'b0;
427
        assign  moc_int = 1'b0;
428
        assign  mpc_int = 1'b0;
429
        assign  mic_int = 1'b0;
430
        assign  utc_int = 1'b0;
431
        assign  uoc_int = 1'b0;
432
        assign  upc_int = 1'b0;
433
        assign  uic_int = 1'b0;
434
 
435
        always @(posedge i_clk)
436
                actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
437
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
438
 
439
        //
440
        // The DMA Controller
441
        //
442
        wire            dmac_int, dmac_stb, dc_err;
443
        wire    [31:0]   dmac_data;
444
        wire            dmac_ack, dmac_stall;
445
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
446
        wire    [31:0]   dc_data, dc_addr;
447
        wire            cpu_gbl_cyc;
448
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
449
        wbdmac  dma_controller(i_clk,
450
                                sys_cyc, dmac_stb, sys_we,
451
                                        sys_addr[1:0], sys_data,
452
                                        dmac_ack, dmac_stall, dmac_data,
453
                                // Need the outgoing DMAC wishbone bus
454
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
455
                                        dc_ack, dc_stall, ext_idata, dc_err,
456
                                // External device interrupts
457
                                { {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int },
458
                                // DMAC interrupt, for upon completion
459
                                dmac_int,
460
                                // Whether or not the CPU wants the bus
461
                                cpu_gbl_cyc);
462 2 dgisselq
 
463
 
464 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
465 2 dgisselq
        //
466
        // Counter Interrupt controller
467
        //
468
        reg             ctri_ack;
469
        wire            ctri_stall, ctri_int, ctri_sel;
470
        wire    [7:0]    ctri_vector;
471
        wire    [31:0]   ctri_data;
472
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
473 9 dgisselq
        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
474
                                        utc_int, uoc_int, upc_int, uic_int };
475 2 dgisselq
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
476
                                sys_data, ctri_data, ctri_vector, ctri_int);
477
        always @(posedge i_clk)
478
                ctri_ack <= ctri_sel;
479 36 dgisselq
        assign  ctri_stall = 1'b0;
480
`else   //      INCLUDE_ACCOUNTING_COUNTERS
481
        reg     ctri_ack;
482
        wire    ctri_stall, ctri_int;
483
        wire    [31:0]   ctri_data;
484
        assign  ctri_stall = 1'b0;
485
        assign  ctri_data  = 32'h0000;
486
        assign  ctri_int   = 1'b0;
487 2 dgisselq
 
488 36 dgisselq
        always @(posedge i_clk)
489
                ctri_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
490
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
491 2 dgisselq
 
492 36 dgisselq
 
493 2 dgisselq
        //
494
        // Timer A
495
        //
496
        wire            tma_ack, tma_stall, tma_int;
497
        wire    [31:0]   tma_data;
498
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
499
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
500
                                sys_data,
501
                        tma_ack, tma_stall, tma_data, tma_int);
502
 
503
        //
504
        // Timer B
505
        //
506
        wire            tmb_ack, tmb_stall, tmb_int;
507
        wire    [31:0]   tmb_data;
508
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
509
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
510
                                sys_data,
511
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
512
 
513
        //
514
        // Timer C
515
        //
516
        wire            tmc_ack, tmc_stall, tmc_int;
517
        wire    [31:0]   tmc_data;
518
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
519
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
520
                                sys_data,
521
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
522
 
523
        //
524
        // JIFFIES
525
        //
526
        wire            jif_ack, jif_stall, jif_int;
527
        wire    [31:0]   jif_data;
528
        zipjiffies jiffies(i_clk, ~cmd_halt,
529
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
530
                                sys_data,
531
                        jif_ack, jif_stall, jif_data, jif_int);
532
 
533
        //
534
        // The programmable interrupt controller peripheral
535
        //
536
        wire            pic_interrupt;
537 34 dgisselq
        wire    [(5+EXTERNAL_INTERRUPTS):0]      int_vector;
538 2 dgisselq
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
539 36 dgisselq
                                        jif_int, dmac_int };
540 34 dgisselq
        icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
541 2 dgisselq
                                (sys_cyc)&&(sys_stb)&&(sys_we)
542
                                        &&(sys_addr==`INTCTRL),
543
                                sys_data, pic_data,
544
                                int_vector, pic_interrupt);
545 36 dgisselq
        wire    pic_stall;
546
        assign  pic_stall = 1'b0;
547 2 dgisselq
        reg     pic_ack;
548
        always @(posedge i_clk)
549
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
550
 
551
        //
552
        // The CPU itself
553
        //
554 36 dgisselq
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
555
                        cpu_we, cpu_dbg_we;
556 2 dgisselq
        wire    [31:0]   cpu_data, wb_data;
557 36 dgisselq
        wire            cpu_ack, cpu_stall, cpu_err;
558 2 dgisselq
        wire    [31:0]   cpu_dbg_data;
559
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
560
                                        &&(dbg_we)&&(dbg_addr));
561
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
562 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
563 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
564 18 dgisselq
                                cpu_dbg_cc, cpu_break,
565 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb,
566
                                cpu_lcl_cyc, cpu_lcl_stb,
567
                                cpu_we, cpu_addr, cpu_data,
568 2 dgisselq
                                cpu_ack, cpu_stall, wb_data,
569 36 dgisselq
                                cpu_err,
570 9 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count);
571 2 dgisselq
 
572
        // Now, arbitrate the bus ... first for the local peripherals
573 36 dgisselq
        // For the debugger to have access to the local system bus, the
574
        // following must be true:
575
        //      (dbg_cyc)       The debugger must request the bus
576
        //      (~cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
577
        //      (dbg_addr)      The debugger must be requesting its data
578
        //                              register, not just the control register
579
        // and one of two other things.  Either
580
        //      ((cpu_halt)&&(~cpu_dbg_stall))  the CPU is completely halted,
581
        // or
582
        //      (~cmd_addr[5])          we are trying to read a CPU register
583
        //                      while in motion.  Let the user beware that,
584
        //                      by not waiting for the CPU to fully halt,
585
        //                      his results may not be what he expects.
586
        //
587
        wire    sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
588
                                &&(((cpu_halt)&&(~cpu_dbg_stall))
589
                                        ||(~cmd_addr[5]));
590
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
591
        assign  sys_stb = (cpu_lcl_cyc)
592
                                ? (cpu_lcl_stb)
593 2 dgisselq
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
594
 
595 36 dgisselq
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
596
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
597
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
598 2 dgisselq
 
599
        // Return debug response values
600
        assign  dbg_odata = (~dbg_addr)?cmd_data
601
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
602
        initial dbg_ack = 1'b0;
603
        always @(posedge i_clk)
604 36 dgisselq
                dbg_ack <= (dbg_cyc)&&(~dbg_stall);
605
        assign  dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
606 2 dgisselq
 
607
        // Now for the external wishbone bus
608
        //      Need to arbitrate between the flash cache and the CPU
609
        // The way this works, though, the CPU will stall once the flash 
610
        // cache gets access to the bus--the CPU will be stuck until the 
611
        // flash cache is finished with the bus.
612 36 dgisselq
        wire            ext_cyc, ext_stb, ext_we, ext_err;
613
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
614
                                cpu_ext_err;
615 2 dgisselq
        wire    [31:0]   ext_addr, ext_odata;
616 36 dgisselq
        wbpriarbiter #(32,32) dmacvcpu(i_clk, i_rst,
617
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
618
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
619
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
620
                                        dc_ack, dc_stall, dc_err,
621
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
622
                                ext_ack, ext_stall, ext_err);
623 2 dgisselq
 
624 3 dgisselq
`ifdef  DELAY_EXT_BUS
625 2 dgisselq
        busdelay #(32,32) extbus(i_clk,
626
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
627 36 dgisselq
                                ext_ack, ext_stall, ext_idata, ext_err,
628 2 dgisselq
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
629 36 dgisselq
                                i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
630 3 dgisselq
`else
631
        assign  o_wb_cyc   = ext_cyc;
632
        assign  o_wb_stb   = ext_stb;
633
        assign  o_wb_we    = ext_we;
634
        assign  o_wb_addr  = ext_addr;
635
        assign  o_wb_data  = ext_odata;
636
        assign  ext_ack    = i_wb_ack;
637
        assign  ext_stall  = i_wb_stall;
638
        assign  ext_idata  = i_wb_data;
639 36 dgisselq
        assign  ext_err    = i_wb_err;
640 3 dgisselq
`endif
641 2 dgisselq
 
642
        wire            tmr_ack;
643
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
644
        wire    [31:0]   tmr_data;
645
        assign  tmr_data = (tma_ack)?tma_data
646
                                :(tmb_ack ? tmb_data
647
                                :(tmc_ack ? tmc_data
648
                                :jif_data));
649
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
650 36 dgisselq
                        :((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
651 2 dgisselq
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
652
                        :(ext_idata)));
653
 
654 36 dgisselq
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
655
                                | wdt_stall | ctri_stall | actr_stall
656
                                | pic_stall | dmac_stall | cache_stall);
657
        assign  cpu_stall = (sys_stall)|(cpu_ext_stall);
658
        assign  sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|cache_ack);
659
        assign  cpu_ack = (sys_ack)||(cpu_ext_ack);
660
        assign  cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
661 18 dgisselq
 
662
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
663
 
664 2 dgisselq
endmodule

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