OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 48

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 36 dgisselq
// While I hate adding delays to any bus access, this next delay is required
86 3 dgisselq
// to make timing close in my Basys-3 design.
87
`define DELAY_DBG_BUS
88 36 dgisselq
// On my previous version, I needed to add a delay to access the external
89
// bus.  Activate the define below and that delay will be put back into place.
90
// This particular version no longer needs the delay in order to run at 
91
// 100 MHz.  Timing indicates I may even run this at 250 MHz without the
92
// delay too, so we're doing better.  To get rid of this, I placed the logic
93
// determining whether or not I was accessing the local system bus one clock
94
// earlier, or into the memops.v file.  This also required my wishbone bus
95
// arbiter to maintain the bus selection as well, so that got updated ...
96
// you get the picture.  But, the bottom line is that I no longer need this
97
// delay.
98 3 dgisselq
//
99 36 dgisselq
// `define      DELAY_EXT_BUS   // Required no longer!k
100 3 dgisselq
//
101 36 dgisselq
//
102
// If space is tight, you might not wish to have your performance and
103
// accounting counters, so let's make those optional here
104
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
105
//      When including counters, 
106
//              Slice LUTs      ZipSystem       ZipCPU
107
//      With Counters           3315            2432
108
//      Without Counters        2796            2046
109
`define INCLUDE_ACCOUNTING_COUNTERS
110
 
111
//
112 3 dgisselq
// Now, where am I placing all of my peripherals?
113 2 dgisselq
`define PERIPHBASE      32'hc0000000
114 36 dgisselq
`define INTCTRL         5'h0    // 
115
`define WATCHDOG        5'h1    // Interrupt generates reset signal
116
// `define      CACHECTRL       5'h2    // Sets IVEC[0]
117
`define CTRINT          5'h3    // Sets IVEC[5]
118
`define TIMER_A         5'h4    // Sets IVEC[4]
119
`define TIMER_B         5'h5    // Sets IVEC[3]
120
`define TIMER_C         5'h6    // Sets IVEC[2]
121
`define JIFFIES         5'h7    // Sets IVEC[1]
122 2 dgisselq
 
123
 
124 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
125
`define MSTR_TASK_CTR   5'h08
126
`define MSTR_MSTL_CTR   5'h09
127
`define MSTR_PSTL_CTR   5'h0a
128
`define MSTR_INST_CTR   5'h0b
129
`define USER_TASK_CTR   5'h0c
130
`define USER_MSTL_CTR   5'h0d
131
`define USER_PSTL_CTR   5'h0e
132
`define USER_INST_CTR   5'h0f
133
`endif
134
 
135
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
136
// addresses, therefore we place it by itself and expand our address bus
137
// width here by another bit.
138
`define DMAC            5'h10
139
 
140 2 dgisselq
// `define      RTC_CLOCK       32'hc0000008    // A global something
141
// `define      BITREV          32'hc0000003
142
//
143
//      DBGCTRL
144
//              10 HALT
145
//               9 HALT(ED)
146
//               8 STEP (W=1 steps, and returns to halted)
147
//               7 INTERRUPT-FLAG
148
//               6 RESET_FLAG
149
//              ADDRESS:
150
//               5      PERIPHERAL-BIT
151
//              [4:0]   REGISTER-ADDR
152
//      DBGDATA
153
//              read/writes internal registers
154
module  zipsystem(i_clk, i_rst,
155
                // Wishbone master interface from the CPU
156
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
157 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
158 2 dgisselq
                // Incoming interrupts
159
                i_ext_int,
160 18 dgisselq
                // Our one outgoing interrupt
161
                o_ext_int,
162 2 dgisselq
                // Wishbone slave interface for debugging purposes
163
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
164
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
165 48 dgisselq
        parameter       RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
166
                        LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
167
                        // Derived parameters
168
                        AW=ADDRESS_WIDTH;
169 2 dgisselq
        input   i_clk, i_rst;
170
        // Wishbone master
171
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
172 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
173 2 dgisselq
        output  wire    [31:0]   o_wb_data;
174
        input                   i_wb_ack, i_wb_stall;
175
        input           [31:0]   i_wb_data;
176 36 dgisselq
        input                   i_wb_err;
177 2 dgisselq
        // Incoming interrupts
178 34 dgisselq
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
179 18 dgisselq
        // Outgoing interrupt
180
        output  wire            o_ext_int;
181 2 dgisselq
        // Wishbone slave
182
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
183
        input           [31:0]   i_dbg_data;
184
        output  wire            o_dbg_ack;
185
        output  wire            o_dbg_stall;
186
        output  wire    [31:0]   o_dbg_data;
187
 
188
        wire    [31:0]   ext_idata;
189
 
190
        // Delay the debug port by one clock, to meet timing requirements
191
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
192
        wire    [31:0]   dbg_idata, dbg_odata;
193
        reg             dbg_ack;
194 3 dgisselq
`ifdef  DELAY_DBG_BUS
195 36 dgisselq
        wire            dbg_err, no_dbg_err;
196
        assign          dbg_err = 1'b0;
197 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
198
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
199 36 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
200 2 dgisselq
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
201 36 dgisselq
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
202 3 dgisselq
`else
203
        assign  dbg_cyc     = i_dbg_cyc;
204
        assign  dbg_stb     = i_dbg_stb;
205
        assign  dbg_we      = i_dbg_we;
206
        assign  dbg_addr    = i_dbg_addr;
207
        assign  dbg_idata   = i_dbg_data;
208
        assign  o_dbg_ack   = dbg_ack;
209
        assign  o_dbg_stall = dbg_stall;
210
        assign  o_dbg_data  = dbg_odata;
211
`endif
212 2 dgisselq
 
213
        // 
214
        //
215
        //
216
        wire    sys_cyc, sys_stb, sys_we;
217 36 dgisselq
        wire    [4:0]    sys_addr;
218 48 dgisselq
        wire    [(AW-1):0]       cpu_addr;
219 2 dgisselq
        wire    [31:0]   sys_data;
220 36 dgisselq
        wire            sys_ack, sys_stall;
221 2 dgisselq
 
222
        //
223
        // The external debug interface
224
        //
225
        // We offer only a limited interface here, requiring a pre-register
226
        // write to set the local address.  This interface allows access to
227
        // the Zip System on a debug basis only, and not to the rest of the
228
        // wishbone bus.  Further, to access these registers, the control
229
        // register must first be accessed to both stop the CPU and to 
230
        // set the following address in question.  Hence all accesses require
231
        // two accesses: write the address to the control register (and halt
232
        // the CPU if not halted), then read/write the data from the data
233
        // register.
234
        //
235 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
236 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
237 2 dgisselq
        reg     [5:0]    cmd_addr;
238 25 dgisselq
        wire    [1:0]    cpu_dbg_cc;
239 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
240
        //
241 2 dgisselq
        initial cmd_reset = 1'b1;
242 9 dgisselq
        always @(posedge i_clk)
243
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
244
        //
245 2 dgisselq
        initial cmd_halt  = 1'b1;
246
        always @(posedge i_clk)
247
                if (i_rst)
248 34 dgisselq
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
249 9 dgisselq
                else if (dbg_cmd_write)
250 36 dgisselq
                        cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
251 9 dgisselq
                else if ((cmd_step)||(cpu_break))
252
                        cmd_halt  <= 1'b1;
253 18 dgisselq
 
254
        always @(posedge i_clk)
255
                if (i_rst)
256
                        cmd_clear_pf_cache <= 1'b0;
257
                else if (dbg_cmd_write)
258
                        cmd_clear_pf_cache <= dbg_idata[11];
259
                else
260
                        cmd_clear_pf_cache <= 1'b0;
261 9 dgisselq
        //
262
        initial cmd_step  = 1'b0;
263
        always @(posedge i_clk)
264
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
265
        //
266
        always @(posedge i_clk)
267
                if (dbg_cmd_write)
268 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
269 9 dgisselq
 
270 2 dgisselq
        wire    cpu_reset;
271 36 dgisselq
        assign  cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
272 2 dgisselq
 
273
        wire    cpu_halt, cpu_dbg_stall;
274 34 dgisselq
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
275 2 dgisselq
        wire    [31:0]   pic_data;
276
        wire    [31:0]   cmd_data;
277 18 dgisselq
        // Values:
278
        //      0x0003f -> cmd_addr mask
279
        //      0x00040 -> reset
280 34 dgisselq
        //      0x00080 -> PIC interrrupts enabled
281 18 dgisselq
        //      0x00100 -> cmd_step
282
        //      0x00200 -> cmd_stall
283
        //      0x00400 -> cmd_halt
284
        //      0x00800 -> cmd_clear_pf_cache
285
        //      0x01000 -> cc.sleep
286
        //      0x02000 -> cc.gie
287
        //      0x10000 -> External interrupt line is high
288 34 dgisselq
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
289
                        2'b00, cpu_dbg_cc,
290 18 dgisselq
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
291
                        pic_data[15], cpu_reset, cmd_addr };
292 38 dgisselq
        wire    cpu_gie;
293
        assign  cpu_gie = cpu_dbg_cc[1];
294 2 dgisselq
 
295
`ifdef  USE_TRAP
296
        //
297
        // The TRAP peripheral
298
        //
299
        wire            trap_ack, trap_stall, trap_int;
300
        wire    [31:0]   trap_data;
301
        ziptrap trapp(i_clk,
302
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
303
                                sys_data,
304
                                trap_ack, trap_stall, trap_data, trap_int);
305
`endif
306
 
307
        //
308
        // The WATCHDOG Timer
309
        //
310
        wire            wdt_ack, wdt_stall, wdt_reset;
311
        wire    [31:0]   wdt_data;
312
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
313
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
314
                                sys_data,
315
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
316
 
317
        //
318 36 dgisselq
        // Position two ... unclaimed / unused
319 2 dgisselq
        //
320 36 dgisselq
        wire    cache_stall;
321
        assign  cache_stall = 1'b0;
322
        reg     cache_ack;
323
        always @(posedge i_clk)
324
                cache_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02);
325 2 dgisselq
        // Counters -- for performance measurement and accounting
326
        //
327
        // Here's the stuff we'll be counting ....
328
        //
329 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
330 2 dgisselq
 
331 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
332 2 dgisselq
        //
333
        // The master counters will, in general, not be reset.  They'll be used
334
        // for an overall counter.
335
        //
336
        // Master task counter
337
        wire            mtc_ack, mtc_stall, mtc_int;
338
        wire    [31:0]   mtc_data;
339 36 dgisselq
        zipcounter      mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
340 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
341
                                        sys_we, sys_data,
342
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
343
 
344 9 dgisselq
        // Master Operand Stall counter
345
        wire            moc_ack, moc_stall, moc_int;
346
        wire    [31:0]   moc_data;
347
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
348 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
349
                                        sys_we, sys_data,
350 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
351 2 dgisselq
 
352
        // Master PreFetch-Stall counter
353
        wire            mpc_ack, mpc_stall, mpc_int;
354
        wire    [31:0]   mpc_data;
355 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
356 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
357
                                        sys_we, sys_data,
358
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
359
 
360 9 dgisselq
        // Master Instruction counter
361
        wire            mic_ack, mic_stall, mic_int;
362
        wire    [31:0]   mic_data;
363
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
364 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
365 2 dgisselq
                                        sys_we, sys_data,
366 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
367 2 dgisselq
 
368
        //
369
        // The user counters are different from those of the master.  They will
370
        // be reset any time a task is given control of the CPU.
371
        //
372
        // User task counter
373
        wire            utc_ack, utc_stall, utc_int;
374
        wire    [31:0]   utc_data;
375 38 dgisselq
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
376 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
377
                                        sys_we, sys_data,
378
                                utc_ack, utc_stall, utc_data, utc_int);
379
 
380 9 dgisselq
        // User Op-Stall counter
381
        wire            uoc_ack, uoc_stall, uoc_int;
382
        wire    [31:0]   uoc_data;
383 38 dgisselq
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
384 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
385
                                        sys_we, sys_data,
386 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
387 2 dgisselq
 
388
        // User PreFetch-Stall counter
389
        wire            upc_ack, upc_stall, upc_int;
390
        wire    [31:0]   upc_data;
391 38 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
392 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
393
                                        sys_we, sys_data,
394
                                upc_ack, upc_stall, upc_data, upc_int);
395
 
396 9 dgisselq
        // User instruction counter
397
        wire            uic_ack, uic_stall, uic_int;
398
        wire    [31:0]   uic_data;
399 38 dgisselq
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
400 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
401 2 dgisselq
                                        sys_we, sys_data,
402 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
403 2 dgisselq
 
404
        // A little bit of pre-cleanup (actr = accounting counters)
405
        wire            actr_ack, actr_stall;
406
        wire    [31:0]   actr_data;
407 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
408
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
409
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
410
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
411 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
412 9 dgisselq
                                : ((moc_ack) ? moc_data
413 2 dgisselq
                                : ((mpc_ack) ? mpc_data
414 9 dgisselq
                                : ((mic_ack) ? mic_data
415 2 dgisselq
                                : ((utc_ack) ? utc_data
416 9 dgisselq
                                : ((uoc_ack) ? uoc_data
417 2 dgisselq
                                : ((upc_ack) ? upc_data
418 9 dgisselq
                                : uic_data)))))));
419 36 dgisselq
`else //        INCLUDE_ACCOUNTING_COUNTERS
420
        reg             actr_ack;
421
        wire            actr_stall;
422
        wire    [31:0]   actr_data;
423
        assign  actr_stall = 1'b0;
424
        assign  actr_data = 32'h0000;
425 2 dgisselq
 
426 36 dgisselq
        wire    utc_int, uoc_int, upc_int, uic_int;
427
        wire    mtc_int, moc_int, mpc_int, mic_int;
428
        assign  mtc_int = 1'b0;
429
        assign  moc_int = 1'b0;
430
        assign  mpc_int = 1'b0;
431
        assign  mic_int = 1'b0;
432
        assign  utc_int = 1'b0;
433
        assign  uoc_int = 1'b0;
434
        assign  upc_int = 1'b0;
435
        assign  uic_int = 1'b0;
436
 
437
        always @(posedge i_clk)
438
                actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
439
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
440
 
441
        //
442
        // The DMA Controller
443
        //
444
        wire            dmac_int, dmac_stb, dc_err;
445
        wire    [31:0]   dmac_data;
446
        wire            dmac_ack, dmac_stall;
447
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
448 48 dgisselq
        wire    [31:0]   dc_data;
449
        wire    [(AW-1):0]       dc_addr;
450 36 dgisselq
        wire            cpu_gbl_cyc;
451
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
452 48 dgisselq
        wbdmac  #(AW) dma_controller(i_clk,
453 36 dgisselq
                                sys_cyc, dmac_stb, sys_we,
454
                                        sys_addr[1:0], sys_data,
455
                                        dmac_ack, dmac_stall, dmac_data,
456
                                // Need the outgoing DMAC wishbone bus
457
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
458
                                        dc_ack, dc_stall, ext_idata, dc_err,
459
                                // External device interrupts
460
                                { {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int },
461
                                // DMAC interrupt, for upon completion
462
                                dmac_int,
463
                                // Whether or not the CPU wants the bus
464
                                cpu_gbl_cyc);
465 2 dgisselq
 
466
 
467 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
468 2 dgisselq
        //
469
        // Counter Interrupt controller
470
        //
471
        reg             ctri_ack;
472
        wire            ctri_stall, ctri_int, ctri_sel;
473
        wire    [7:0]    ctri_vector;
474
        wire    [31:0]   ctri_data;
475
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
476 9 dgisselq
        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
477
                                        utc_int, uoc_int, upc_int, uic_int };
478 2 dgisselq
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
479
                                sys_data, ctri_data, ctri_vector, ctri_int);
480
        always @(posedge i_clk)
481
                ctri_ack <= ctri_sel;
482 36 dgisselq
        assign  ctri_stall = 1'b0;
483
`else   //      INCLUDE_ACCOUNTING_COUNTERS
484
        reg     ctri_ack;
485
        wire    ctri_stall, ctri_int;
486
        wire    [31:0]   ctri_data;
487
        assign  ctri_stall = 1'b0;
488
        assign  ctri_data  = 32'h0000;
489
        assign  ctri_int   = 1'b0;
490 2 dgisselq
 
491 36 dgisselq
        always @(posedge i_clk)
492
                ctri_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
493
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
494 2 dgisselq
 
495 36 dgisselq
 
496 2 dgisselq
        //
497
        // Timer A
498
        //
499
        wire            tma_ack, tma_stall, tma_int;
500
        wire    [31:0]   tma_data;
501
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
502
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
503
                                sys_data,
504
                        tma_ack, tma_stall, tma_data, tma_int);
505
 
506
        //
507
        // Timer B
508
        //
509
        wire            tmb_ack, tmb_stall, tmb_int;
510
        wire    [31:0]   tmb_data;
511
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
512
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
513
                                sys_data,
514
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
515
 
516
        //
517
        // Timer C
518
        //
519
        wire            tmc_ack, tmc_stall, tmc_int;
520
        wire    [31:0]   tmc_data;
521
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
522
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
523
                                sys_data,
524
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
525
 
526
        //
527
        // JIFFIES
528
        //
529
        wire            jif_ack, jif_stall, jif_int;
530
        wire    [31:0]   jif_data;
531
        zipjiffies jiffies(i_clk, ~cmd_halt,
532
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
533
                                sys_data,
534
                        jif_ack, jif_stall, jif_data, jif_int);
535
 
536
        //
537
        // The programmable interrupt controller peripheral
538
        //
539
        wire            pic_interrupt;
540 34 dgisselq
        wire    [(5+EXTERNAL_INTERRUPTS):0]      int_vector;
541 2 dgisselq
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
542 36 dgisselq
                                        jif_int, dmac_int };
543 34 dgisselq
        icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
544 2 dgisselq
                                (sys_cyc)&&(sys_stb)&&(sys_we)
545
                                        &&(sys_addr==`INTCTRL),
546
                                sys_data, pic_data,
547
                                int_vector, pic_interrupt);
548 36 dgisselq
        wire    pic_stall;
549
        assign  pic_stall = 1'b0;
550 2 dgisselq
        reg     pic_ack;
551
        always @(posedge i_clk)
552
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
553
 
554
        //
555
        // The CPU itself
556
        //
557 36 dgisselq
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
558
                        cpu_we, cpu_dbg_we;
559 2 dgisselq
        wire    [31:0]   cpu_data, wb_data;
560 36 dgisselq
        wire            cpu_ack, cpu_stall, cpu_err;
561 2 dgisselq
        wire    [31:0]   cpu_dbg_data;
562
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
563
                                        &&(dbg_we)&&(dbg_addr));
564 48 dgisselq
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
565
                thecpu(i_clk, cpu_reset, pic_interrupt,
566 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
567 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
568 18 dgisselq
                                cpu_dbg_cc, cpu_break,
569 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb,
570
                                cpu_lcl_cyc, cpu_lcl_stb,
571
                                cpu_we, cpu_addr, cpu_data,
572 2 dgisselq
                                cpu_ack, cpu_stall, wb_data,
573 36 dgisselq
                                cpu_err,
574 9 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count);
575 2 dgisselq
 
576
        // Now, arbitrate the bus ... first for the local peripherals
577 36 dgisselq
        // For the debugger to have access to the local system bus, the
578
        // following must be true:
579
        //      (dbg_cyc)       The debugger must request the bus
580
        //      (~cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
581
        //      (dbg_addr)      The debugger must be requesting its data
582
        //                              register, not just the control register
583
        // and one of two other things.  Either
584
        //      ((cpu_halt)&&(~cpu_dbg_stall))  the CPU is completely halted,
585
        // or
586
        //      (~cmd_addr[5])          we are trying to read a CPU register
587
        //                      while in motion.  Let the user beware that,
588
        //                      by not waiting for the CPU to fully halt,
589
        //                      his results may not be what he expects.
590
        //
591
        wire    sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
592
                                &&(((cpu_halt)&&(~cpu_dbg_stall))
593
                                        ||(~cmd_addr[5]));
594
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
595
        assign  sys_stb = (cpu_lcl_cyc)
596
                                ? (cpu_lcl_stb)
597 2 dgisselq
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
598
 
599 36 dgisselq
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
600
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
601
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
602 2 dgisselq
 
603
        // Return debug response values
604
        assign  dbg_odata = (~dbg_addr)?cmd_data
605
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
606
        initial dbg_ack = 1'b0;
607
        always @(posedge i_clk)
608 36 dgisselq
                dbg_ack <= (dbg_cyc)&&(~dbg_stall);
609
        assign  dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
610 2 dgisselq
 
611
        // Now for the external wishbone bus
612
        //      Need to arbitrate between the flash cache and the CPU
613
        // The way this works, though, the CPU will stall once the flash 
614
        // cache gets access to the bus--the CPU will be stuck until the 
615
        // flash cache is finished with the bus.
616 36 dgisselq
        wire            ext_cyc, ext_stb, ext_we, ext_err;
617
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
618
                                cpu_ext_err;
619 48 dgisselq
        wire    [(AW-1):0]       ext_addr;
620
        wire    [31:0]           ext_odata;
621
        wbpriarbiter #(32,AW) dmacvcpu(i_clk, i_rst,
622 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
623
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
624
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
625
                                        dc_ack, dc_stall, dc_err,
626
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
627
                                ext_ack, ext_stall, ext_err);
628 2 dgisselq
 
629 3 dgisselq
`ifdef  DELAY_EXT_BUS
630 48 dgisselq
        busdelay #(AW,32) extbus(i_clk,
631 2 dgisselq
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
632 36 dgisselq
                                ext_ack, ext_stall, ext_idata, ext_err,
633 2 dgisselq
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
634 36 dgisselq
                                i_wb_ack, i_wb_stall, i_wb_data, i_wb_err);
635 3 dgisselq
`else
636
        assign  o_wb_cyc   = ext_cyc;
637
        assign  o_wb_stb   = ext_stb;
638
        assign  o_wb_we    = ext_we;
639
        assign  o_wb_addr  = ext_addr;
640
        assign  o_wb_data  = ext_odata;
641
        assign  ext_ack    = i_wb_ack;
642
        assign  ext_stall  = i_wb_stall;
643
        assign  ext_idata  = i_wb_data;
644 36 dgisselq
        assign  ext_err    = i_wb_err;
645 3 dgisselq
`endif
646 2 dgisselq
 
647
        wire            tmr_ack;
648
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
649
        wire    [31:0]   tmr_data;
650
        assign  tmr_data = (tma_ack)?tma_data
651
                                :(tmb_ack ? tmb_data
652
                                :(tmc_ack ? tmc_data
653
                                :jif_data));
654
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
655 36 dgisselq
                        :((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
656 2 dgisselq
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
657
                        :(ext_idata)));
658
 
659 36 dgisselq
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
660
                                | wdt_stall | ctri_stall | actr_stall
661
                                | pic_stall | dmac_stall | cache_stall);
662
        assign  cpu_stall = (sys_stall)|(cpu_ext_stall);
663
        assign  sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|cache_ack);
664
        assign  cpu_ack = (sys_ack)||(cpu_ext_ack);
665
        assign  cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
666 18 dgisselq
 
667
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
668
 
669 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.