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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 56

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 36 dgisselq
// While I hate adding delays to any bus access, this next delay is required
86 3 dgisselq
// to make timing close in my Basys-3 design.
87
`define DELAY_DBG_BUS
88 36 dgisselq
// On my previous version, I needed to add a delay to access the external
89
// bus.  Activate the define below and that delay will be put back into place.
90
// This particular version no longer needs the delay in order to run at 
91
// 100 MHz.  Timing indicates I may even run this at 250 MHz without the
92
// delay too, so we're doing better.  To get rid of this, I placed the logic
93
// determining whether or not I was accessing the local system bus one clock
94
// earlier, or into the memops.v file.  This also required my wishbone bus
95
// arbiter to maintain the bus selection as well, so that got updated ...
96
// you get the picture.  But, the bottom line is that I no longer need this
97
// delay.
98 3 dgisselq
//
99 56 dgisselq
// `define      DELAY_EXT_BUS   // Required no longer!
100 3 dgisselq
//
101 36 dgisselq
//
102
// If space is tight, you might not wish to have your performance and
103
// accounting counters, so let's make those optional here
104
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
105
//      When including counters, 
106
//              Slice LUTs      ZipSystem       ZipCPU
107
//      With Counters           3315            2432
108
//      Without Counters        2796            2046
109
`define INCLUDE_ACCOUNTING_COUNTERS
110
 
111
//
112 3 dgisselq
// Now, where am I placing all of my peripherals?
113 2 dgisselq
`define PERIPHBASE      32'hc0000000
114 36 dgisselq
`define INTCTRL         5'h0    // 
115
`define WATCHDOG        5'h1    // Interrupt generates reset signal
116 56 dgisselq
`define BUSWATCHDOG     5'h2    // Sets IVEC[0]
117 36 dgisselq
`define CTRINT          5'h3    // Sets IVEC[5]
118
`define TIMER_A         5'h4    // Sets IVEC[4]
119
`define TIMER_B         5'h5    // Sets IVEC[3]
120
`define TIMER_C         5'h6    // Sets IVEC[2]
121
`define JIFFIES         5'h7    // Sets IVEC[1]
122 2 dgisselq
 
123
 
124 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
125
`define MSTR_TASK_CTR   5'h08
126
`define MSTR_MSTL_CTR   5'h09
127
`define MSTR_PSTL_CTR   5'h0a
128
`define MSTR_INST_CTR   5'h0b
129
`define USER_TASK_CTR   5'h0c
130
`define USER_MSTL_CTR   5'h0d
131
`define USER_PSTL_CTR   5'h0e
132
`define USER_INST_CTR   5'h0f
133
`endif
134
 
135
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
136
// addresses, therefore we place it by itself and expand our address bus
137
// width here by another bit.
138
`define DMAC            5'h10
139
 
140 2 dgisselq
// `define      RTC_CLOCK       32'hc0000008    // A global something
141
// `define      BITREV          32'hc0000003
142
//
143
//      DBGCTRL
144
//              10 HALT
145
//               9 HALT(ED)
146
//               8 STEP (W=1 steps, and returns to halted)
147
//               7 INTERRUPT-FLAG
148
//               6 RESET_FLAG
149
//              ADDRESS:
150
//               5      PERIPHERAL-BIT
151
//              [4:0]   REGISTER-ADDR
152
//      DBGDATA
153
//              read/writes internal registers
154
module  zipsystem(i_clk, i_rst,
155
                // Wishbone master interface from the CPU
156
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
157 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
158 2 dgisselq
                // Incoming interrupts
159
                i_ext_int,
160 18 dgisselq
                // Our one outgoing interrupt
161
                o_ext_int,
162 2 dgisselq
                // Wishbone slave interface for debugging purposes
163
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
164 56 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
165
                o_cpu_debug);
166 48 dgisselq
        parameter       RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
167
                        LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
168
                        // Derived parameters
169
                        AW=ADDRESS_WIDTH;
170 2 dgisselq
        input   i_clk, i_rst;
171
        // Wishbone master
172
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
173 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
174 2 dgisselq
        output  wire    [31:0]   o_wb_data;
175
        input                   i_wb_ack, i_wb_stall;
176
        input           [31:0]   i_wb_data;
177 36 dgisselq
        input                   i_wb_err;
178 2 dgisselq
        // Incoming interrupts
179 34 dgisselq
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
180 18 dgisselq
        // Outgoing interrupt
181
        output  wire            o_ext_int;
182 2 dgisselq
        // Wishbone slave
183
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
184
        input           [31:0]   i_dbg_data;
185
        output  wire            o_dbg_ack;
186
        output  wire            o_dbg_stall;
187
        output  wire    [31:0]   o_dbg_data;
188 56 dgisselq
        //
189
        output  wire    [31:0]   o_cpu_debug;
190 2 dgisselq
 
191
        wire    [31:0]   ext_idata;
192
 
193
        // Delay the debug port by one clock, to meet timing requirements
194
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
195
        wire    [31:0]   dbg_idata, dbg_odata;
196
        reg             dbg_ack;
197 3 dgisselq
`ifdef  DELAY_DBG_BUS
198 36 dgisselq
        wire            dbg_err, no_dbg_err;
199
        assign          dbg_err = 1'b0;
200 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
201
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
202 36 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
203 2 dgisselq
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
204 36 dgisselq
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
205 3 dgisselq
`else
206
        assign  dbg_cyc     = i_dbg_cyc;
207
        assign  dbg_stb     = i_dbg_stb;
208
        assign  dbg_we      = i_dbg_we;
209
        assign  dbg_addr    = i_dbg_addr;
210
        assign  dbg_idata   = i_dbg_data;
211
        assign  o_dbg_ack   = dbg_ack;
212
        assign  o_dbg_stall = dbg_stall;
213
        assign  o_dbg_data  = dbg_odata;
214
`endif
215 2 dgisselq
 
216
        // 
217
        //
218
        //
219
        wire    sys_cyc, sys_stb, sys_we;
220 36 dgisselq
        wire    [4:0]    sys_addr;
221 48 dgisselq
        wire    [(AW-1):0]       cpu_addr;
222 2 dgisselq
        wire    [31:0]   sys_data;
223 36 dgisselq
        wire            sys_ack, sys_stall;
224 2 dgisselq
 
225
        //
226
        // The external debug interface
227
        //
228
        // We offer only a limited interface here, requiring a pre-register
229
        // write to set the local address.  This interface allows access to
230
        // the Zip System on a debug basis only, and not to the rest of the
231
        // wishbone bus.  Further, to access these registers, the control
232
        // register must first be accessed to both stop the CPU and to 
233
        // set the following address in question.  Hence all accesses require
234
        // two accesses: write the address to the control register (and halt
235
        // the CPU if not halted), then read/write the data from the data
236
        // register.
237
        //
238 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
239 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
240 2 dgisselq
        reg     [5:0]    cmd_addr;
241 56 dgisselq
        wire    [3:0]    cpu_dbg_cc;
242 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
243
        //
244 2 dgisselq
        initial cmd_reset = 1'b1;
245 9 dgisselq
        always @(posedge i_clk)
246
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
247
        //
248 2 dgisselq
        initial cmd_halt  = 1'b1;
249
        always @(posedge i_clk)
250
                if (i_rst)
251 34 dgisselq
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
252 9 dgisselq
                else if (dbg_cmd_write)
253 36 dgisselq
                        cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
254 9 dgisselq
                else if ((cmd_step)||(cpu_break))
255
                        cmd_halt  <= 1'b1;
256 18 dgisselq
 
257
        always @(posedge i_clk)
258 56 dgisselq
                cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
259
                                        &&((dbg_idata[11])||(dbg_idata[6]));
260 9 dgisselq
        //
261
        initial cmd_step  = 1'b0;
262
        always @(posedge i_clk)
263
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
264
        //
265
        always @(posedge i_clk)
266
                if (dbg_cmd_write)
267 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
268 9 dgisselq
 
269 2 dgisselq
        wire    cpu_reset;
270 36 dgisselq
        assign  cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
271 2 dgisselq
 
272
        wire    cpu_halt, cpu_dbg_stall;
273 34 dgisselq
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
274 2 dgisselq
        wire    [31:0]   pic_data;
275
        wire    [31:0]   cmd_data;
276 18 dgisselq
        // Values:
277
        //      0x0003f -> cmd_addr mask
278
        //      0x00040 -> reset
279 34 dgisselq
        //      0x00080 -> PIC interrrupts enabled
280 18 dgisselq
        //      0x00100 -> cmd_step
281
        //      0x00200 -> cmd_stall
282
        //      0x00400 -> cmd_halt
283
        //      0x00800 -> cmd_clear_pf_cache
284
        //      0x01000 -> cc.sleep
285
        //      0x02000 -> cc.gie
286
        //      0x10000 -> External interrupt line is high
287 34 dgisselq
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
288 56 dgisselq
                        cpu_dbg_cc,
289 18 dgisselq
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
290
                        pic_data[15], cpu_reset, cmd_addr };
291 38 dgisselq
        wire    cpu_gie;
292
        assign  cpu_gie = cpu_dbg_cc[1];
293 2 dgisselq
 
294
`ifdef  USE_TRAP
295
        //
296
        // The TRAP peripheral
297
        //
298
        wire            trap_ack, trap_stall, trap_int;
299
        wire    [31:0]   trap_data;
300
        ziptrap trapp(i_clk,
301
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
302
                                sys_data,
303
                                trap_ack, trap_stall, trap_data, trap_int);
304
`endif
305
 
306
        //
307
        // The WATCHDOG Timer
308
        //
309
        wire            wdt_ack, wdt_stall, wdt_reset;
310
        wire    [31:0]   wdt_data;
311
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
312
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
313
                                sys_data,
314
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
315
 
316
        //
317 56 dgisselq
        // Position two, a second watchdog timer--this time for the wishbone
318
        // bus, in order to tell/find wishbone bus lockups.  In its current
319
        // configuration, it cannot be configured and all bus accesses must
320
        // take less than the number written to this register.
321 2 dgisselq
        //
322 56 dgisselq
        reg     wdbus_ack;
323
        reg     [(AW-1):0]       r_wdbus_data;
324
        wire    [31:0]           wdbus_data;
325
        wire    [14:0]   wdbus_ignored_data;
326
        wire    reset_wdbus_timer, wdbus_int, wdbus_ack_ignored, wdbus_stall;
327
        assign  reset_wdbus_timer = ((o_wb_cyc)&&((o_wb_stb)||(i_wb_ack)));
328
        //      o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
329
        //              i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
330
        ziptimer #(15) watchbus(i_clk, (cpu_reset), o_wb_cyc,
331
                        reset_wdbus_timer, reset_wdbus_timer, 1'b1, 15'h2000,
332
                        wdbus_ack_ignored, wdbus_stall, wdbus_ignored_data,
333
                        wdbus_int);
334
        initial r_wdbus_data = 0;
335 36 dgisselq
        always @(posedge i_clk)
336 56 dgisselq
                if (wdbus_int)
337
                        r_wdbus_data = o_wb_addr;
338
        assign  wdbus_data = { {(32-AW){1'b0}}, r_wdbus_data };
339
        initial wdbus_ack = 1'b0;
340
        always @(posedge i_clk)
341
                wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02));
342
 
343 2 dgisselq
        // Counters -- for performance measurement and accounting
344
        //
345
        // Here's the stuff we'll be counting ....
346
        //
347 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
348 2 dgisselq
 
349 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
350 2 dgisselq
        //
351
        // The master counters will, in general, not be reset.  They'll be used
352
        // for an overall counter.
353
        //
354
        // Master task counter
355
        wire            mtc_ack, mtc_stall, mtc_int;
356
        wire    [31:0]   mtc_data;
357 36 dgisselq
        zipcounter      mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
358 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
359
                                        sys_we, sys_data,
360
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
361
 
362 9 dgisselq
        // Master Operand Stall counter
363
        wire            moc_ack, moc_stall, moc_int;
364
        wire    [31:0]   moc_data;
365
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
366 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
367
                                        sys_we, sys_data,
368 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
369 2 dgisselq
 
370
        // Master PreFetch-Stall counter
371
        wire            mpc_ack, mpc_stall, mpc_int;
372
        wire    [31:0]   mpc_data;
373 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
374 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
375
                                        sys_we, sys_data,
376
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
377
 
378 9 dgisselq
        // Master Instruction counter
379
        wire            mic_ack, mic_stall, mic_int;
380
        wire    [31:0]   mic_data;
381
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
382 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
383 2 dgisselq
                                        sys_we, sys_data,
384 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
385 2 dgisselq
 
386
        //
387
        // The user counters are different from those of the master.  They will
388
        // be reset any time a task is given control of the CPU.
389
        //
390
        // User task counter
391
        wire            utc_ack, utc_stall, utc_int;
392
        wire    [31:0]   utc_data;
393 38 dgisselq
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
394 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
395
                                        sys_we, sys_data,
396
                                utc_ack, utc_stall, utc_data, utc_int);
397
 
398 9 dgisselq
        // User Op-Stall counter
399
        wire            uoc_ack, uoc_stall, uoc_int;
400
        wire    [31:0]   uoc_data;
401 38 dgisselq
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
402 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
403
                                        sys_we, sys_data,
404 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
405 2 dgisselq
 
406
        // User PreFetch-Stall counter
407
        wire            upc_ack, upc_stall, upc_int;
408
        wire    [31:0]   upc_data;
409 38 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
410 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
411
                                        sys_we, sys_data,
412
                                upc_ack, upc_stall, upc_data, upc_int);
413
 
414 9 dgisselq
        // User instruction counter
415
        wire            uic_ack, uic_stall, uic_int;
416
        wire    [31:0]   uic_data;
417 38 dgisselq
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
418 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
419 2 dgisselq
                                        sys_we, sys_data,
420 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
421 2 dgisselq
 
422
        // A little bit of pre-cleanup (actr = accounting counters)
423
        wire            actr_ack, actr_stall;
424
        wire    [31:0]   actr_data;
425 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
426
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
427
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
428
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
429 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
430 9 dgisselq
                                : ((moc_ack) ? moc_data
431 2 dgisselq
                                : ((mpc_ack) ? mpc_data
432 9 dgisselq
                                : ((mic_ack) ? mic_data
433 2 dgisselq
                                : ((utc_ack) ? utc_data
434 9 dgisselq
                                : ((uoc_ack) ? uoc_data
435 2 dgisselq
                                : ((upc_ack) ? upc_data
436 9 dgisselq
                                : uic_data)))))));
437 36 dgisselq
`else //        INCLUDE_ACCOUNTING_COUNTERS
438
        reg             actr_ack;
439
        wire            actr_stall;
440
        wire    [31:0]   actr_data;
441
        assign  actr_stall = 1'b0;
442
        assign  actr_data = 32'h0000;
443 2 dgisselq
 
444 36 dgisselq
        wire    utc_int, uoc_int, upc_int, uic_int;
445
        wire    mtc_int, moc_int, mpc_int, mic_int;
446
        assign  mtc_int = 1'b0;
447
        assign  moc_int = 1'b0;
448
        assign  mpc_int = 1'b0;
449
        assign  mic_int = 1'b0;
450
        assign  utc_int = 1'b0;
451
        assign  uoc_int = 1'b0;
452
        assign  upc_int = 1'b0;
453
        assign  uic_int = 1'b0;
454
 
455
        always @(posedge i_clk)
456
                actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
457
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
458
 
459
        //
460
        // The DMA Controller
461
        //
462
        wire            dmac_int, dmac_stb, dc_err;
463
        wire    [31:0]   dmac_data;
464
        wire            dmac_ack, dmac_stall;
465
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
466 48 dgisselq
        wire    [31:0]   dc_data;
467
        wire    [(AW-1):0]       dc_addr;
468 36 dgisselq
        wire            cpu_gbl_cyc;
469
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
470 56 dgisselq
// `define      INCLUDE_DMA_CONTROLLER
471
`ifdef  INCLUDE_DMA_CONTROLLER
472 48 dgisselq
        wbdmac  #(AW) dma_controller(i_clk,
473 36 dgisselq
                                sys_cyc, dmac_stb, sys_we,
474
                                        sys_addr[1:0], sys_data,
475
                                        dmac_ack, dmac_stall, dmac_data,
476
                                // Need the outgoing DMAC wishbone bus
477
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
478
                                        dc_ack, dc_stall, ext_idata, dc_err,
479
                                // External device interrupts
480
                                { {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int },
481
                                // DMAC interrupt, for upon completion
482
                                dmac_int,
483
                                // Whether or not the CPU wants the bus
484
                                cpu_gbl_cyc);
485 56 dgisselq
`else
486
        reg     r_dmac_ack;
487
        always @(posedge i_clk)
488
                r_dmac_ack <= (sys_cyc)&&(dmac_stb);
489
        assign  dmac_ack = r_dmac_ack;
490
        assign  dmac_data = 32'h000;
491
        assign  dmac_stall = 1'b0;
492 2 dgisselq
 
493 56 dgisselq
        assign  dc_cyc  = 1'b0;
494
        assign  dc_stb  = 1'b0;
495
        assign  dc_we   = 1'b0;
496
        assign  dc_addr = { (AW) {1'b0} };
497
        assign  dc_data = 32'h00;
498
 
499
        assign  dmac_int = 1'b0;
500
`endif
501
 
502
 
503 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
504 2 dgisselq
        //
505
        // Counter Interrupt controller
506
        //
507
        reg             ctri_ack;
508
        wire            ctri_stall, ctri_int, ctri_sel;
509
        wire    [7:0]    ctri_vector;
510
        wire    [31:0]   ctri_data;
511
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
512 9 dgisselq
        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
513
                                        utc_int, uoc_int, upc_int, uic_int };
514 2 dgisselq
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
515
                                sys_data, ctri_data, ctri_vector, ctri_int);
516
        always @(posedge i_clk)
517
                ctri_ack <= ctri_sel;
518 36 dgisselq
        assign  ctri_stall = 1'b0;
519
`else   //      INCLUDE_ACCOUNTING_COUNTERS
520
        reg     ctri_ack;
521
        wire    ctri_stall, ctri_int;
522
        wire    [31:0]   ctri_data;
523
        assign  ctri_stall = 1'b0;
524
        assign  ctri_data  = 32'h0000;
525
        assign  ctri_int   = 1'b0;
526 2 dgisselq
 
527 36 dgisselq
        always @(posedge i_clk)
528
                ctri_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
529
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
530 2 dgisselq
 
531 36 dgisselq
 
532 2 dgisselq
        //
533
        // Timer A
534
        //
535
        wire            tma_ack, tma_stall, tma_int;
536
        wire    [31:0]   tma_data;
537
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
538
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
539
                                sys_data,
540
                        tma_ack, tma_stall, tma_data, tma_int);
541
 
542
        //
543
        // Timer B
544
        //
545
        wire            tmb_ack, tmb_stall, tmb_int;
546
        wire    [31:0]   tmb_data;
547
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
548
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
549
                                sys_data,
550
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
551
 
552
        //
553
        // Timer C
554
        //
555
        wire            tmc_ack, tmc_stall, tmc_int;
556
        wire    [31:0]   tmc_data;
557
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
558
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
559
                                sys_data,
560
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
561
 
562
        //
563
        // JIFFIES
564
        //
565
        wire            jif_ack, jif_stall, jif_int;
566
        wire    [31:0]   jif_data;
567
        zipjiffies jiffies(i_clk, ~cmd_halt,
568
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
569
                                sys_data,
570
                        jif_ack, jif_stall, jif_data, jif_int);
571
 
572
        //
573
        // The programmable interrupt controller peripheral
574
        //
575
        wire            pic_interrupt;
576 34 dgisselq
        wire    [(5+EXTERNAL_INTERRUPTS):0]      int_vector;
577 2 dgisselq
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
578 36 dgisselq
                                        jif_int, dmac_int };
579 34 dgisselq
        icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
580 2 dgisselq
                                (sys_cyc)&&(sys_stb)&&(sys_we)
581
                                        &&(sys_addr==`INTCTRL),
582
                                sys_data, pic_data,
583
                                int_vector, pic_interrupt);
584 36 dgisselq
        wire    pic_stall;
585
        assign  pic_stall = 1'b0;
586 2 dgisselq
        reg     pic_ack;
587
        always @(posedge i_clk)
588
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
589
 
590
        //
591
        // The CPU itself
592
        //
593 36 dgisselq
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
594
                        cpu_we, cpu_dbg_we;
595 2 dgisselq
        wire    [31:0]   cpu_data, wb_data;
596 36 dgisselq
        wire            cpu_ack, cpu_stall, cpu_err;
597 2 dgisselq
        wire    [31:0]   cpu_dbg_data;
598
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
599
                                        &&(dbg_we)&&(dbg_addr));
600 48 dgisselq
        zipcpu  #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
601
                thecpu(i_clk, cpu_reset, pic_interrupt,
602 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
603 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
604 18 dgisselq
                                cpu_dbg_cc, cpu_break,
605 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb,
606
                                cpu_lcl_cyc, cpu_lcl_stb,
607
                                cpu_we, cpu_addr, cpu_data,
608 2 dgisselq
                                cpu_ack, cpu_stall, wb_data,
609 36 dgisselq
                                cpu_err,
610 56 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count,
611
                        o_cpu_debug);
612 2 dgisselq
 
613
        // Now, arbitrate the bus ... first for the local peripherals
614 36 dgisselq
        // For the debugger to have access to the local system bus, the
615
        // following must be true:
616
        //      (dbg_cyc)       The debugger must request the bus
617
        //      (~cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
618
        //      (dbg_addr)      The debugger must be requesting its data
619
        //                              register, not just the control register
620
        // and one of two other things.  Either
621
        //      ((cpu_halt)&&(~cpu_dbg_stall))  the CPU is completely halted,
622
        // or
623
        //      (~cmd_addr[5])          we are trying to read a CPU register
624
        //                      while in motion.  Let the user beware that,
625
        //                      by not waiting for the CPU to fully halt,
626
        //                      his results may not be what he expects.
627
        //
628
        wire    sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
629
                                &&(((cpu_halt)&&(~cpu_dbg_stall))
630
                                        ||(~cmd_addr[5]));
631
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
632
        assign  sys_stb = (cpu_lcl_cyc)
633
                                ? (cpu_lcl_stb)
634 2 dgisselq
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
635
 
636 36 dgisselq
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
637
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
638
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
639 2 dgisselq
 
640
        // Return debug response values
641
        assign  dbg_odata = (~dbg_addr)?cmd_data
642
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
643
        initial dbg_ack = 1'b0;
644
        always @(posedge i_clk)
645 36 dgisselq
                dbg_ack <= (dbg_cyc)&&(~dbg_stall);
646
        assign  dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
647 2 dgisselq
 
648
        // Now for the external wishbone bus
649
        //      Need to arbitrate between the flash cache and the CPU
650
        // The way this works, though, the CPU will stall once the flash 
651
        // cache gets access to the bus--the CPU will be stuck until the 
652
        // flash cache is finished with the bus.
653 36 dgisselq
        wire            ext_cyc, ext_stb, ext_we, ext_err;
654
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
655
                                cpu_ext_err;
656 48 dgisselq
        wire    [(AW-1):0]       ext_addr;
657
        wire    [31:0]           ext_odata;
658 56 dgisselq
        wbpriarbiter #(32,AW) dmacvcpu(i_clk,
659 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data,
660
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
661
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
662
                                        dc_ack, dc_stall, dc_err,
663
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
664
                                ext_ack, ext_stall, ext_err);
665 2 dgisselq
 
666 3 dgisselq
`ifdef  DELAY_EXT_BUS
667 48 dgisselq
        busdelay #(AW,32) extbus(i_clk,
668 2 dgisselq
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
669 36 dgisselq
                                ext_ack, ext_stall, ext_idata, ext_err,
670 2 dgisselq
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
671 56 dgisselq
                                i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
672 3 dgisselq
`else
673
        assign  o_wb_cyc   = ext_cyc;
674
        assign  o_wb_stb   = ext_stb;
675
        assign  o_wb_we    = ext_we;
676
        assign  o_wb_addr  = ext_addr;
677
        assign  o_wb_data  = ext_odata;
678
        assign  ext_ack    = i_wb_ack;
679
        assign  ext_stall  = i_wb_stall;
680
        assign  ext_idata  = i_wb_data;
681 56 dgisselq
        assign  ext_err    = (i_wb_err)||(wdbus_int);
682 3 dgisselq
`endif
683 2 dgisselq
 
684
        wire            tmr_ack;
685
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
686
        wire    [31:0]   tmr_data;
687
        assign  tmr_data = (tma_ack)?tma_data
688
                                :(tmb_ack ? tmb_data
689
                                :(tmc_ack ? tmc_data
690
                                :jif_data));
691
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
692 36 dgisselq
                        :((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
693 2 dgisselq
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
694 56 dgisselq
                        :((wdbus_ack)?wdbus_data:(ext_idata))));
695 2 dgisselq
 
696 36 dgisselq
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
697
                                | wdt_stall | ctri_stall | actr_stall
698 56 dgisselq
                                | pic_stall | dmac_stall | wdbus_stall);
699 36 dgisselq
        assign  cpu_stall = (sys_stall)|(cpu_ext_stall);
700 56 dgisselq
        assign  sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
701 36 dgisselq
        assign  cpu_ack = (sys_ack)||(cpu_ext_ack);
702
        assign  cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
703 18 dgisselq
 
704
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
705
 
706 2 dgisselq
endmodule

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