OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sim/] [verilator/] [README.md] - Blame information for rev 209

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 209 dgisselq
## The ZipCPU's Simulator
2
 
3
This directory contains the basic ZipCPU simulator.
4
 
5
Ok, even this isn't the *best* simulator of the ZipCPU.  While this simulator
6
*is* fully functional, it only simulates the
7
[ZipCPU](../../rtl/core/zipcpu.v), encased in either the
8
[ZipSystem](../../rtl/zipsystem.v)
9
or the [ZipBones](../../rtl/zipbones.v),
10
plus [memory](memsim.cpp).  This simulator doesn't handle any interactions
11
with the
12
[flash](http://opencores.org/project,qspiflash), the
13
[serial port](https://github.com/ZipCPU/wbuart32), the
14
[SD-card](https://github.com/ZipCPU/sdspi), etc.  All of these interactions
15
(and more) are available from the
16
[simulator](https://github.com/ZipCPU/zbasic/tree/master/sim/verilated)
17
within the
18
[ZBasic repository](https://github.com/ZipCPU/zbasic).
19
 
20
However, this simulator *is* very basic to the CPU's functionality.  If you
21
just want to know if the CPU works by itself, if it can properly execute the
22
instructions given to it--even to the point of testing
23
interrupts etc, then this simulation will work.  It's just not fully
24
functional for testing all of the other peripheral components necessary
25
to make a CPU useful.

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.