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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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[/] [zipcpu/] [trunk/] [sw/] [gas-zippatch.patch] - Blame information for rev 202

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Line No. Rev Author Line
1 202 dgisselq
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/archures.c binutils-2.27-zip/bfd/archures.c
2
--- binutils-2.27/bfd/archures.c        2016-08-03 03:36:50.000000000 -0400
3
+++ binutils-2.27-zip/bfd/archures.c    2017-01-04 14:22:45.000000000 -0500
4
@@ -525,6 +525,8 @@
5
 .#define bfd_mach_nios2r2      2
6
 .  bfd_arch_visium,    {* Visium *}
7
 .#define bfd_mach_visium       1
8
+.  bfd_arch_zip,       {* ZipCPU *}
9
+.#define bfd_mach_zip          0
10
 .  bfd_arch_last
11
 .  };
12
 */
13
@@ -655,6 +657,7 @@
14
 extern const bfd_arch_info_type bfd_xgate_arch;
15
 extern const bfd_arch_info_type bfd_z80_arch;
16
 extern const bfd_arch_info_type bfd_z8k_arch;
17
+extern const bfd_arch_info_type bfd_zip_arch;
18
 
19
 static const bfd_arch_info_type * const bfd_archures_list[] =
20
   {
21
@@ -744,6 +747,7 @@
22
     &bfd_xgate_arch,
23
     &bfd_z80_arch,
24
     &bfd_z8k_arch,
25
+    &bfd_zip_arch,
26
 #endif
27
 
28
 };
29
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/bfd-in2.h binutils-2.27-zip/bfd/bfd-in2.h
30
--- binutils-2.27/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400
31
+++ binutils-2.27-zip/bfd/bfd-in2.h     2017-01-04 22:04:11.000000000 -0500
32
@@ -2336,6 +2336,8 @@
33
 #define bfd_mach_nios2r2       2
34
   bfd_arch_visium,     /* Visium */
35
 #define bfd_mach_visium        1
36
+  bfd_arch_zip,        /* ZipCPU */
37
+#define bfd_mach_zip           0
38
   bfd_arch_last
39
   };
40
 
41
@@ -6335,6 +6337,22 @@
42
   BFD_RELOC_VISIUM_HI16_PCREL,
43
   BFD_RELOC_VISIUM_LO16_PCREL,
44
   BFD_RELOC_VISIUM_IM16_PCREL,
45
+
46
+/* ZipCPU - 32 bit absolute value for LJMP instruction  */
47
+  BFD_RELOC_ZIP_VALUE,
48
+
49
+/* ZipCPU - 18-bit PC-relative offset for BRA (ADD #x,PC) instructions  */
50
+  BFD_RELOC_ZIP_BRANCH,
51
+
52
+/* ZipCPU value relocations  */
53
+  BFD_RELOC_ZIP_OPB_IMM,
54
+  BFD_RELOC_ZIP_OPB_OFFSET,
55
+  BFD_RELOC_ZIP_OPB_PCREL,
56
+  BFD_RELOC_ZIP_MOV_OFFSET,
57
+  BFD_RELOC_ZIP_MOV_PCREL,
58
+  BFD_RELOC_ZIP_LDI,
59
+  BFD_RELOC_ZIP_LLO,
60
+  BFD_RELOC_ZIP_BREV,
61
   BFD_RELOC_UNUSED };
62
 
63
 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
64
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/config.bfd binutils-2.27-zip/bfd/config.bfd
65
--- binutils-2.27/bfd/config.bfd        2016-08-03 03:36:50.000000000 -0400
66
+++ binutils-2.27-zip/bfd/config.bfd    2016-12-31 17:11:00.961307172 -0500
67
@@ -1742,6 +1742,10 @@
68
     targ_underscore=yes
69
     ;;
70
 
71
+  zip*)
72
+    targ_defvec=zip_elf32_vec
73
+    ;;
74
+
75
   *-*-ieee*)
76
     targ_defvec=ieee_vec
77
     ;;
78
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/configure binutils-2.27-zip/bfd/configure
79
--- binutils-2.27/bfd/configure 2016-08-03 04:33:36.000000000 -0400
80
+++ binutils-2.27-zip/bfd/configure     2016-12-31 17:12:22.360697343 -0500
81
@@ -14542,6 +14542,7 @@
82
     xtensa_elf32_le_vec)        tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
83
     z80_coff_vec)               tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
84
     z8k_coff_vec)               tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
85
+    zip_elf32_vec)              tb="$tb elf32-zip.lo elf32.lo $elf" ;;
86
 
87
     # These appear out of order in targets.c
88
     srec_vec)                   tb="$tb srec.lo" ;;
89
@@ -14924,6 +14925,9 @@
90
   x86_64-*-netbsd* | x86_64-*-openbsd*)
91
        COREFILE=netbsd-core.lo
92
        ;;
93
+  zip*)
94
+       COREFILE=netbsd-core.lo
95
+       ;;
96
   esac
97
 
98
   case "$COREFILE" in
99
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/configure.ac binutils-2.27-zip/bfd/configure.ac
100
--- binutils-2.27/bfd/configure.ac      2016-08-03 03:36:50.000000000 -0400
101
+++ binutils-2.27-zip/bfd/configure.ac  2016-12-31 17:13:38.600136486 -0500
102
@@ -717,6 +717,7 @@
103
     xtensa_elf32_le_vec)        tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
104
     z80_coff_vec)               tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
105
     z8k_coff_vec)               tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
106
+    zip_elf32_vec)              tb="$tb elf32-zip.lo elf32.lo $elf" ;;
107
 
108
     # These appear out of order in targets.c
109
     srec_vec)                   tb="$tb srec.lo" ;;
110
@@ -1092,6 +1093,9 @@
111
   x86_64-*-netbsd* | x86_64-*-openbsd*)
112
        COREFILE=netbsd-core.lo
113
        ;;
114
+  zip*)
115
+       COREFILE=netbsd-core.lo
116
+       ;;
117
   esac
118
 
119
   case "$COREFILE" in
120
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/cpu-zip.c binutils-2.27-zip/bfd/cpu-zip.c
121
--- binutils-2.27/bfd/cpu-zip.c 1969-12-31 19:00:00.000000000 -0500
122
+++ binutils-2.27-zip/bfd/cpu-zip.c     2017-01-04 14:26:27.000000000 -0500
123
@@ -0,0 +1,65 @@
124
+////////////////////////////////////////////////////////////////////////////////
125
+//
126
+// Filename:   tc-zip.c
127
+//
128
+// Project:    Zip CPU backend for GNU Binutils
129
+//
130
+// Purpose:    BFD support for the Zip CPU architecture.
131
+//
132
+//             This file is part of BFD, the Binary File Descriptor library.
133
+//
134
+// Creator:    Dan Gisselquist, Ph.D.
135
+//             Gisselquist Technology, LLC
136
+//
137
+////////////////////////////////////////////////////////////////////////////////
138
+//
139
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
140
+//
141
+// This program is free software (firmware): you can redistribute it and/or
142
+// modify it under the terms of  the GNU General Public License as published
143
+// by the Free Software Foundation, either version 3 of the License, or (at
144
+// your option) any later version.
145
+//
146
+// This program is distributed in the hope that it will be useful, but WITHOUT
147
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
148
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
149
+// for more details.
150
+//
151
+// You should have received a copy of the GNU General Public License along
152
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
153
+// target there if the PDF file isn't present.)  If not, see
154
+// <http://www.gnu.org/licenses/> for a copy.
155
+//
156
+// License:    GPL, v3, as defined and found on www.gnu.org,
157
+//             http://www.gnu.org/licenses/gpl.html
158
+//
159
+//
160
+////////////////////////////////////////////////////////////////////////////////
161
+#include "sysdep.h"
162
+#include "bfd.h"
163
+#include "libbfd.h"
164
+
165
+const bfd_arch_info_type
166
+bfd_zip_arch =
167
+{
168
+  32,                          // There's 32 bits_per_word.
169
+  32,                          // There's 34 bits_per_address.
170
+  8,                           // There's 32 bits_per_byte.
171
+  bfd_arch_zip,                        // One of enum bfd_architecture, defined
172
+                               // in archures.c and provided in
173
+                               // generated header files.
174
+  bfd_mach_zip,                        // Random BFD-internal number for this
175
+                               // machine, similarly listed in
176
+                               // archures.c.  Not emitted in output.
177
+  "zip",                       // The arch_name.
178
+  "zip",                       // The printable name is the same.
179
+  2,                           // Section alignment power; each section
180
+                               // is aligned to (only) 2^2 (i.e. 4) bytes.
181
+  TRUE,                                // This is the default "machine".
182
+  bfd_default_compatible,      // Architecture comparison function
183
+  bfd_default_scan,            // String to architecture conversion
184
+  bfd_arch_default_fill,       // Default fill.
185
+  NULL                         // Pointer to next bfd_arch_info_type in
186
+                               // the same family.
187
+};
188
+
189
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/archures.texi binutils-2.27-zip/bfd/doc/archures.texi
190
--- binutils-2.27/bfd/doc/archures.texi 2016-08-03 04:36:22.000000000 -0400
191
+++ binutils-2.27-zip/bfd/doc/archures.texi     2016-12-31 17:14:43.103668704 -0500
192
@@ -492,6 +492,8 @@
193
 #define bfd_mach_nios2r2       2
194
   bfd_arch_visium,     /* Visium */
195
 #define bfd_mach_visium        1
196
+  bfd_mach_zip,
197
+#define bfd_mach_zip           0
198
   bfd_arch_last
199
   @};
200
 @end example
201
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/bfd.info binutils-2.27-zip/bfd/doc/bfd.info
202
--- binutils-2.27/bfd/doc/bfd.info      2016-08-03 04:36:22.000000000 -0400
203
+++ binutils-2.27-zip/bfd/doc/bfd.info  2017-01-04 14:40:21.000000000 -0500
204
@@ -8466,6 +8466,8 @@
205
      #define bfd_mach_nios2r2       2
206
        bfd_arch_visium,     /* Visium */
207
      #define bfd_mach_visium        1
208
+       bfd_arch_zip,        /* ZipCPU */
209
+     #define bfd_mach_zip           0
210
        bfd_arch_last
211
        };
212
 
213
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/reloc.texi binutils-2.27-zip/bfd/doc/reloc.texi
214
--- binutils-2.27/bfd/doc/reloc.texi    2016-08-03 04:36:22.000000000 -0400
215
+++ binutils-2.27-zip/bfd/doc/reloc.texi        2016-12-31 17:17:15.950640091 -0500
216
@@ -4214,6 +4214,19 @@
217
 @deffnx {} BFD_RELOC_VISIUM_IM16_PCREL
218
 Visium Relocations.
219
 @end deffn
220
+@deffn {} BFD_RELOC_ZIP_VALUE
221
+@deffnx {} BFD_RELOC_OPB_IMM
222
+@deffnx {} BFD_RELOC_OPB_OFFSET
223
+@deffnx {} BFD_RELOC_OPB_PCREL
224
+@deffnx {} BFD_RELOC_OPB_GOTREL
225
+@deffnx {} BFD_RELOC_MOV_OFFSET
226
+@deffnx {} BFD_RELOC_MOV_PCREL
227
+@deffnx {} BFD_RELOC_MOV_GOTREL
228
+@deffnx {} BFD_RELOC_ZIP_LDI
229
+@deffnx {} BFD_RELOC_ZIP_LLO
230
+@deffnx {} BFD_RELOC_ZIP_LHI
231
+ZipCPU relocations
232
+@end deffn
233
 
234
 @example
235
 
236
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/elf32-zip.c binutils-2.27-zip/bfd/elf32-zip.c
237
--- binutils-2.27/bfd/elf32-zip.c       1969-12-31 19:00:00.000000000 -0500
238
+++ binutils-2.27-zip/bfd/elf32-zip.c   2017-01-24 13:54:25.214097101 -0500
239
@@ -0,0 +1,1134 @@
240
+////////////////////////////////////////////////////////////////////////////////
241
+//
242
+// Filename:   tc-zip.c
243
+//
244
+// Project:    Zip CPU backend for GNU Binutils
245
+//
246
+// Purpose:    Zip-specific support for 32-bit ELF.
247
+//
248
+//     This file is part of BFD, the Binary File Descriptor library.
249
+//
250
+// Creator:    Dan Gisselquist, Ph.D.
251
+//             Gisselquist Technology, LLC
252
+//
253
+////////////////////////////////////////////////////////////////////////////////
254
+//
255
+// Copyright (C) 2016, Gisselquist Technology, LLC
256
+//
257
+// This program is free software (firmware): you can redistribute it and/or
258
+// modify it under the terms of  the GNU General Public License as published
259
+// by the Free Software Foundation, either version 3 of the License, or (at
260
+// your option) any later version.
261
+//
262
+// This program is distributed in the hope that it will be useful, but WITHOUT
263
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
264
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
265
+// for more details.
266
+//
267
+// You should have received a copy of the GNU General Public License along
268
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
269
+// target there if the PDF file isn't present.)  If not, see
270
+// <http://www.gnu.org/licenses/> for a copy.
271
+//
272
+// License:    GPL, v3, as defined and found on www.gnu.org,
273
+//             http://www.gnu.org/licenses/gpl.html
274
+//
275
+//
276
+////////////////////////////////////////////////////////////////////////////////
277
+#include "sysdep.h"
278
+#include "bfd.h"
279
+#include "bfdlink.h"
280
+#include "libbfd.h"
281
+#include "elf-bfd.h"
282
+#include "elf/zip.h"
283
+#include <limits.h>
284
+#include <stdint.h>
285
+
286
+#define        zip_relocation  bfd_elf_generic_reloc
287
+
288
+static bfd_reloc_status_type
289
+zip_brev_relocation(bfd *, arelent *, asymbol *, void *, asection *,
290
+               bfd *, char **error_messsage);
291
+static uint32_t zip_bitreverse(uint32_t v);
292
+
293
+/* Forward declarations.  */
294
+static reloc_howto_type zip_elf_howto_table [] =
295
+{
296
+  /* This reloc does nothing.  */
297
+  HOWTO (R_ZIP_NONE,           /* type */
298
+        0,                     /* rightshift */
299
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
300
+        32,                    /* bitsize */
301
+        FALSE,                 /* pc_relative */
302
+        0,                     /* bitpos */
303
+        complain_overflow_dont, /* complain_on_overflow */
304
+        zip_relocation,        /* special_function */
305
+        "R_ZIP_NONE",          /* name */
306
+        FALSE,                 /* partial_inplace */
307
+        0,                     /* src_mask */
308
+        0,                     /* dst_mask */
309
+        FALSE),                /* pcrel_offset */
310
+
311
+  /* A 32 bit absolute relocation.  */
312
+  HOWTO (R_ZIP_VALUE,          /* type */
313
+        0,                     /* rightshift */
314
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
315
+        32,                    /* bitsize */
316
+        FALSE,                 /* pc_relative */
317
+        0,                     /* bitpos */
318
+        complain_overflow_dont, /* complain_on_overflow */
319
+        zip_relocation,        /* special_function */
320
+        "R_ZIP_VALUE",         /* name */
321
+        FALSE,                 /* partial_inplace */
322
+        0x00000000,            /* src_mask */
323
+        0xffffffff,            /* dst_mask */
324
+        FALSE),                /* pcrel_offset */
325
+
326
+  HOWTO (R_ZIP_BREV,           /* type -- LDIHI, but with bitreverse */
327
+        0,                     /* rightshift */
328
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
329
+        16,                    /* bitsize */
330
+        FALSE,                 /* pc_relative */
331
+        0,                     /* bitpos */
332
+        complain_overflow_bitfield, /* complain_on_overflow */
333
+        zip_brev_relocation,    /* special_function--needed for the bitreverse */
334
+        "R_ZIP_BREV",          /* name */
335
+        FALSE,                 /* partial_inplace */
336
+        0,                     /* src_mask */
337
+        0x0003ffff,            /* dst_mask */
338
+        FALSE),                /* pcrel_offset */
339
+
340
+  HOWTO (R_ZIP_LLO,            /* type */
341
+        0,                     /* rightshift */
342
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
343
+        23,                    /* bitsize */
344
+        FALSE,                 /* pc_relative */
345
+        0,                     /* bitpos */
346
+        complain_overflow_dont, /* don't complain_on_overflow */
347
+        zip_relocation,         /* special_function */
348
+        "R_ZIP_LLO",           /* name */
349
+        FALSE,                 /* partial_inplace */
350
+        0,                     /* src_mask */
351
+        0x0000ffff,            /* dst_mask */
352
+        FALSE),                /* pcrel_offset */
353
+
354
+  HOWTO (R_ZIP_LDI,            /* type */
355
+        0,                     /* rightshift */
356
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
357
+        23,                    /* bitsize */
358
+        FALSE,                 /* pc_relative */
359
+        0,                     /* bitpos */
360
+        complain_overflow_signed, /* complain_on_overflow */
361
+        zip_relocation,         /* special_function */
362
+        "R_ZIP_LDI",           /* name */
363
+        FALSE,                 /* partial_inplace */
364
+        0,                     /* src_mask */
365
+        0x007fffff,            /* dst_mask */
366
+        FALSE),                /* pcrel_offset */
367
+
368
+  /* An 18 bit pc-relative relocation.  */
369
+  HOWTO (R_ZIP_BRANCH,         /* type */
370
+        0,                     /* rightshift */
371
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
372
+        18,                    /* bitsize */
373
+        TRUE,                  /* pc_relative */
374
+        0,                     /* bitpos */
375
+        complain_overflow_signed, /* complain_on_overflow */
376
+        zip_relocation,        /* special_function */
377
+        "R_ZIP_BRANCH",        /* name */
378
+        FALSE,                 /* partial_inplace */
379
+        0x00000000,            /* src_mask */
380
+        0x0003fffc,            /* dst_mask */
381
+        TRUE),         /* pcrel_offset */
382
+
383
+  /* An 18 bit operand B immediate.  */
384
+  HOWTO (R_ZIP_OPB_IMM,        /* type */
385
+        0,                     /* rightshift */
386
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
387
+        18,                    /* bitsize */
388
+        FALSE,                 /* pc_relative */
389
+        0,                     /* bitpos */
390
+        complain_overflow_signed, /* complain_on_overflow */
391
+        zip_relocation,        /* special_function */
392
+        "R_ZIP_OPB_IMM",       /* name */
393
+        FALSE,                 /* partial_inplace */
394
+        0x00000000,            /* src_mask */
395
+        0x0003ffff,            /* dst_mask */
396
+        FALSE),                        /* pcrel_offset */
397
+
398
+  /* An 18 bit relocation.  */
399
+  HOWTO (R_ZIP_OPB_OFFSET,     /* type */
400
+        0,                     /* rightshift */
401
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
402
+        14,                    /* bitsize */
403
+        FALSE,                 /* pc_relative */
404
+        0,                     /* bitpos */
405
+        complain_overflow_signed, /* complain_on_overflow */
406
+        zip_relocation,        /* special_function */
407
+        "R_ZIP_OPB_OFFSET",    /* name */
408
+        FALSE,                 /* partial_inplace */
409
+        0x00000000,            /* src_mask */
410
+        0x00003fff,            /* dst_mask-14 bits */
411
+        FALSE),                        /* pcrel_offset */
412
+
413
+  /* An 18 bit operand B immediate, but relative to the current PC.  */
414
+  HOWTO (R_ZIP_OPB_PCREL,      /* type */
415
+        2,                     /* rightshift */
416
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
417
+        14,                    /* bitsize */
418
+        TRUE,                  /* pc_relative */
419
+        0,                     /* bitpos */
420
+        complain_overflow_signed, /* complain_on_overflow */
421
+        zip_relocation,        /* special_function */
422
+        "R_ZIP_OPB_PCREL",     /* name */
423
+        FALSE,                 /* partial_inplace */
424
+        0x00000000,            /* src_mask */
425
+        0x00003fff,            /* dst_mask-14 bits */
426
+        TRUE),                 /* pcrel_offset */
427
+
428
+  /* An 18 bit operand B immediate, but relative to the Global Offset Table. */
429
+  //HOWTO (R_ZIP_OPB_GOTREL,   /* type */
430
+        //0,                   /* rightshift */
431
+        //2,                   /* size (0 = byte, 1 = short, 2 = long) */
432
+        //18,                  /* bitsize */
433
+        //FALSE,                       /* pc_relative */
434
+        //0,                   /* bitpos */
435
+        //complain_overflow_signed, /* complain_on_overflow */
436
+        //zip_relocation,      /* special_function */
437
+        //"R_ZIP_OPB_GOTREL",  /* name */
438
+        //FALSE,                       /* partial_inplace */
439
+        //0x00000000,          /* src_mask */
440
+        //0x0003ffff,          /* dst_mask-14 bits */
441
+        //FALSE),              /* pcrel_offset */
442
+
443
+  /* */
444
+  HOWTO (R_ZIP_MOV_OFFSET,     /* type */
445
+        0,                     /* rightshift */
446
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
447
+        13,                    /* bitsize */
448
+        FALSE,                 /* pc_relative */
449
+        0,                     /* bitpos */
450
+        complain_overflow_signed, /* complain_on_overflow */
451
+        zip_relocation,         /* special_function */
452
+        "R_ZIP_MOV_OFFSET",    /* name */
453
+        FALSE,                 /* partial_inplace */
454
+        0,                     /* src_mask */
455
+        0x00001fff,            /* dst_mask */
456
+        FALSE),                /* pcrel_offset */
457
+
458
+  /* */
459
+  HOWTO (R_ZIP_MOV_PCREL,      /* type */
460
+        2,                     /* rightshift */
461
+        2,                     /* size (0 = byte, 1 = short, 2 = long) */
462
+        13,                    /* bitsize */
463
+        TRUE,                  /* pc_relative */
464
+        0,                     /* bitpos */
465
+        complain_overflow_signed, /* complain_on_overflow */
466
+        zip_relocation,         /* special_function */
467
+        "R_ZIP_MOV_PCREL",     /* name */
468
+        FALSE,                 /* partial_inplace */
469
+        0,                     /* src_mask */
470
+        0x00001fff,            /* dst_mask */
471
+        TRUE)                  /* pcrel_offset */
472
+
473
+  /* */
474
+  //HOWTO (R_ZIP_MOV_GOTREL,   /* type */
475
+        //0,                   /* rightshift */
476
+        //2,                   /* size (0 = byte, 1 = short, 2 = long) */
477
+        //13,                  /* bitsize */
478
+        //FALSE,                       /* pc_relative */
479
+        //0,                   /* bitpos */
480
+        //complain_overflow_signed, /* complain_on_overflow */
481
+        //zip_relocation,       /* special_function */
482
+        //"R_ZIP_MOV_GOTREL",  /* name */
483
+        //FALSE,                       /* partial_inplace */
484
+        //0,                   /* src_mask */
485
+        //0x00001fff,          /* dst_mask */
486
+        //FALSE),              /* pcrel_offset */
487
+
488
+};
489
+
490
+/* This structure is used to map BFD reloc codes to Zip ELF relocations */
491
+
492
+struct elf_reloc_map
493
+{
494
+  bfd_reloc_code_real_type bfd_reloc_val;
495
+  unsigned int elf_reloc_val;
496
+};
497
+
498
+static const struct elf_reloc_map zip_reloc_map [] =
499
+{
500
+  { BFD_RELOC_NONE,            R_ZIP_NONE },
501
+  { BFD_RELOC_ZIP_VALUE,       R_ZIP_VALUE },
502
+  { BFD_RELOC_ZIP_BRANCH,      R_ZIP_BRANCH },
503
+  { BFD_RELOC_ZIP_OPB_IMM,     R_ZIP_OPB_IMM },
504
+  { BFD_RELOC_ZIP_OPB_OFFSET,  R_ZIP_OPB_OFFSET },
505
+  { BFD_RELOC_ZIP_MOV_OFFSET,  R_ZIP_MOV_OFFSET },
506
+  { BFD_RELOC_ZIP_LDI,         R_ZIP_LDI },
507
+  { BFD_RELOC_ZIP_LLO,         R_ZIP_LLO },
508
+  { BFD_RELOC_ZIP_BREV,                R_ZIP_BREV },
509
+  { BFD_RELOC_14,              R_ZIP_OPB_OFFSET },
510
+  { BFD_RELOC_16,              R_ZIP_LLO },
511
+  { BFD_RELOC_32,              R_ZIP_VALUE },
512
+  { BFD_RELOC_ZIP_OPB_PCREL,   R_ZIP_OPB_PCREL },
513
+  { BFD_RELOC_ZIP_MOV_PCREL,   R_ZIP_MOV_PCREL }
514
+  // { BFD_RELOC_ZIP_OPB_GOTREL,       R_ZIP_OPB_GOTREL },
515
+  // { BFD_RELOC_ZIP_MOV_GOTREL,       R_ZIP_MOV_GOTREL },
516
+};
517
+
518
+/* Given a BFD reloc code, return the howto structure for the corresponding
519
+ * Zip ELF relocation. */
520
+static reloc_howto_type *
521
+zip_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
522
+                       bfd_reloc_code_real_type code)
523
+{
524
+  unsigned int i;
525
+
526
+  for (i = 0; i < sizeof (zip_reloc_map) / sizeof (zip_reloc_map[0]); i++)
527
+    if (zip_reloc_map [i].bfd_reloc_val == code)
528
+      return & zip_elf_howto_table [(int)zip_reloc_map[i].elf_reloc_val];
529
+
530
+  return NULL;
531
+}
532
+
533
+static reloc_howto_type *
534
+zip_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
535
+{
536
+  unsigned int i;
537
+
538
+  for (i = 0;
539
+       i < sizeof (zip_elf_howto_table) / sizeof (zip_elf_howto_table[0]);
540
+       i++)
541
+    if (zip_elf_howto_table[i].name != NULL
542
+       && strcasecmp (zip_elf_howto_table[i].name, r_name) == 0)
543
+      return &zip_elf_howto_table[i];
544
+
545
+  return NULL;
546
+}
547
+
548
+/* Given an ELF reloc, fill in the howto field of a relent. */
549
+static void
550
+zip_elf_info_to_howto(bfd * abfd ATTRIBUTE_UNUSED,
551
+                        arelent * cache_ptr,
552
+                        Elf_Internal_Rela * dst)
553
+{
554
+       unsigned int r;
555
+
556
+       r = ELF32_R_TYPE(dst->r_info);
557
+       BFD_ASSERT (r < (unsigned int) R_ZIP_max);
558
+       cache_ptr->howto = &zip_elf_howto_table [r];
559
+}
560
+
561
+static bfd_boolean
562
+zip_elf_relocate_section(bfd *output_bfd,
563
+                       struct bfd_link_info *info,
564
+                       bfd *input_bfd,
565
+                       asection *input_section,
566
+                       bfd_byte *contents,
567
+                       Elf_Internal_Rela *relocs,
568
+                       Elf_Internal_Sym *local_syms,
569
+                       asection **local_sections)
570
+{
571
+       Elf_Internal_Shdr               *symtab_hdr;
572
+       struct  elf_link_hash_entry     **sym_hashes;
573
+       Elf_Internal_Rela               *rel, *relend;
574
+
575
+       symtab_hdr = &elf_tdata(input_bfd)->symtab_hdr;
576
+       sym_hashes = elf_sym_hashes(input_bfd);
577
+       relend     = relocs+input_section->reloc_count;
578
+
579
+       for(rel=relocs; rel<relend; rel++) {
580
+               reloc_howto_type                *howto;
581
+               unsigned long                   r_symndx;
582
+               Elf_Internal_Sym                *sym;
583
+               asection                        *sec;
584
+               struct elf_link_hash_entry      *h;
585
+               bfd_vma                         relocation;
586
+               bfd_reloc_status_type           r;
587
+               const char                      *name = NULL;
588
+               int                             r_type;
589
+
590
+               r_type = ELF32_R_TYPE(rel->r_info);
591
+               r_symndx = ELF32_R_SYM(rel->r_info);
592
+
593
+               if ((r_type < 0) || (r_type >= (int)R_ZIP_max))
594
+               {
595
+                       bfd_set_error(bfd_error_bad_value);
596
+                       return FALSE;
597
+               }
598
+
599
+               howto = zip_elf_howto_table + ELF32_R_TYPE(rel->r_info);
600
+               h = NULL;
601
+               sym = NULL;
602
+               sec = NULL;
603
+
604
+               if (r_symndx < symtab_hdr->sh_info)
605
+               {
606
+                       sym = local_syms + r_symndx;
607
+                       sec = local_sections[r_symndx];
608
+                       relocation = _bfd_elf_rela_local_sym(output_bfd, sym, &sec, rel);
609
+                       name = bfd_elf_string_from_elf_section
610
+                               (input_bfd, symtab_hdr->sh_link, sym->st_name);
611
+                       name = (name == NULL) ? bfd_section_name(input_bfd, sec)
612
+                                       : name;
613
+               } else {
614
+                       bfd_boolean unresolved_reloc, warned, ignored;
615
+
616
+                       RELOC_FOR_GLOBAL_SYMBOL(info, input_bfd, input_section,
617
+                               rel, r_symndx, symtab_hdr, sym_hashes, h, sec,
618
+                               relocation, unresolved_reloc, warned, ignored);
619
+               }
620
+
621
+               if ((sec != NULL)&&(discarded_section(sec))) {
622
+                       RELOC_AGAINST_DISCARDED_SECTION(info, input_bfd,
623
+                               input_section, rel, 1, relend, howto, 0,
624
+                               contents);
625
+               }
626
+
627
+               if (bfd_link_relocatable(info))
628
+                       continue;
629
+
630
+               if (howto->type == R_ZIP_BREV) {
631
+                       if (rel->r_offset > bfd_get_section_limit(input_bfd, input_section)) {
632
+                               r = bfd_reloc_outofrange;
633
+                       } else {
634
+                               uint32_t        brev_reloc;
635
+                               bfd_byte        *location;
636
+                               bfd_vma         insn;
637
+
638
+                               location = contents + rel->r_offset * bfd_octets_per_byte(input_bfd);
639
+
640
+                               relocation += rel->r_addend;
641
+                               brev_reloc= zip_bitreverse(relocation);
642
+                               insn = bfd_get_32(input_bfd, location);
643
+                               insn = ((insn & ~howto->dst_mask)
644
+                               |(((insn & howto->src_mask)+brev_reloc)&howto->dst_mask));
645
+                               bfd_put_32(input_bfd, insn, location);
646
+                               r = bfd_reloc_ok;
647
+                       }
648
+               } else {
649
+                       r = _bfd_final_link_relocate(howto, input_bfd,
650
+                               input_section,
651
+                               contents, rel->r_offset,
652
+                               relocation,
653
+                               rel->r_addend);
654
+               }
655
+
656
+
657
+               if (r != bfd_reloc_ok)
658
+               {
659
+                       const char *msg = NULL;
660
+
661
+                       switch(r)
662
+                       {
663
+                               case bfd_reloc_overflow:
664
+                                       info->callbacks->reloc_overflow(
665
+                                               info, (h?&h->root:NULL),
666
+                                               name, howto->name,
667
+                                               (bfd_vma)0, input_bfd,
668
+                                               input_section, rel->r_offset);
669
+                                       break;
670
+                               case bfd_reloc_undefined:
671
+                                       info->callbacks->undefined_symbol(
672
+                                               info, name, input_bfd,
673
+                                               input_section, rel->r_offset,
674
+                                               TRUE);
675
+                                       break;
676
+                               case bfd_reloc_outofrange:
677
+                                       msg = _("internal error: out of range error");
678
+                                       break;
679
+                               case bfd_reloc_notsupported:
680
+                                       msg = _("internal error: unsupported relocation");
681
+                                       break;
682
+                               case bfd_reloc_dangerous:
683
+                                       msg = _("internal error: dangerous relocation");
684
+                                       break;
685
+                               default:
686
+                                       msg = _("internal error: unknown error");
687
+                                       break;
688
+                       }
689
+
690
+                       if (msg)
691
+                               info->callbacks->warning(info, msg, name,
692
+                                       input_bfd, input_section,
693
+                                       rel->r_offset);
694
+
695
+                       if (!r)
696
+                               return FALSE;
697
+               }
698
+       }
699
+       return TRUE;
700
+}
701
+
702
+static uint32_t
703
+zip_bitreverse(uint32_t v) {
704
+       unsigned r = 0, b;
705
+
706
+       for(b=0; b<32; b++, v>>=1)
707
+               r = (r<<1)|(v&1);
708
+
709
+       return r;
710
+}
711
+
712
+static bfd_reloc_status_type
713
+zip_brev_relocation(bfd *abfd,
714
+               arelent *reloc_entry,
715
+               asymbol *symbol,
716
+               void *data,
717
+               asection *input_section,
718
+               bfd *output_bfd,
719
+               char **error_message)
720
+{
721
+       bfd_vma relocation;
722
+       bfd_size_type octets = reloc_entry->address * bfd_octets_per_byte(abfd);
723
+       bfd_vma output_base = 0;
724
+       reloc_howto_type *howto = reloc_entry->howto;
725
+
726
+       // If this isn't a final relocation, then just use the generic
727
+       // relocation function.
728
+       if (output_bfd != NULL) {
729
+               return zip_relocation(abfd, reloc_entry, symbol, data,
730
+                       input_section, output_bfd, error_message);
731
+       }
732
+
733
+       // Otherwise, we need to adjust our file itself with this value ...
734
+       // Check that our relocation lies within the file, and particularly
735
+       // the section we think it should.  (This should really be an assert...)
736
+       if (reloc_entry->address > bfd_get_section_limit(abfd, input_section))
737
+               return bfd_reloc_outofrange;
738
+
739
+       // Get symbol value
740
+       if (bfd_is_com_section(symbol->section))
741
+               relocation = 0;
742
+       else
743
+               relocation = symbol->value;
744
+
745
+       /* Convert input-section relative symbol value to absolute */
746
+       if ((!howto->partial_inplace)
747
+                       ||(symbol->section->output_section == NULL))
748
+               output_base = 0;
749
+       else
750
+               output_base = symbol->section->output_section->vma;
751
+
752
+       relocation += output_base + symbol->section->output_offset;
753
+
754
+       /* Add in supplied addend. */
755
+       relocation += reloc_entry->addend;
756
+
757
+       // BREV does not handle PC relative offsets
758
+
759
+       // Ignore overflow checking ... BREV handles the top 18 bits of a 32-bit
760
+       // number.  Overflow would mean overflowing the 32-bit address space--
761
+       // not possible.
762
+       //
763
+       // if howto->complain_on_overflow ...
764
+
765
+       // relocation >>= howto->rightshift;    // = 0
766
+       // relocation <<= howto->bitpos;        // = 0
767
+
768
+       // Logic (nearly) copied from reloc.c:bfd_perform_relocation
769
+       unsigned        insn = bfd_get_32(abfd, (bfd_byte *)data + octets);
770
+
771
+       // Here's why we are going through this pain!
772
+       insn = zip_bitreverse((unsigned)insn);
773
+
774
+       // Now we can continue as before....
775
+       insn = ((insn&(~howto->dst_mask))
776
+               |(((insn&howto->src_mask)+relocation)&howto->dst_mask));
777
+       bfd_put_32(abfd, (bfd_vma)insn, (bfd_byte *)data + octets);
778
+
779
+       return bfd_reloc_ok;
780
+}
781
+
782
+// Zip Defines
783
+#define        TARGET_BIG_SYM  zip_elf32_vec
784
+#define        TARGET_BIG_NAME "elf32-zip"
785
+
786
+#define        ELF_ARCH        bfd_arch_zip
787
+// #define ELF_TARGET_ID               ZIP_ELF_DATA
788
+#define        ELF_MACHINE_CODE        EM_ZIP
789
+
790
+#define        ELF_MAXPAGESIZE         0x1000
791
+#define        ARCH_SIZE               32
792
+
793
+
794
+#define bfd_elf32_bfd_define_common_symbol     bfd_generic_define_common_symbol
795
+
796
+
797
+#define        bfd_elf32_bfd_reloc_type_lookup zip_elf_reloc_type_lookup
798
+#define        bfd_elf32_bfd_reloc_name_lookup zip_elf_reloc_name_lookup
799
+#define        elf_info_to_howto_rel   0
800
+#define        elf_info_to_howto       zip_elf_info_to_howto
801
+#define        elf_backend_relocate_section    zip_elf_relocate_section
802
+#define        elf_backend_rela_normal         1
803
+
804
+// Default ELF32 defines from elf32-target.h that we would've normally included
805
+// here, had we not been a OCTETS_PER_BYTE=4 machine
806
+
807
+#define        bfd_elf32_close_and_cleanup _bfd_elf_close_and_cleanup
808
+#define bfd_elf32_bfd_free_cached_info _bfd_free_cached_info
809
+#define bfd_elf32_get_section_contents _bfd_generic_get_section_contents
810
+#define bfd_elf32_canonicalize_dynamic_symtab \
811
+  _bfd_elf_canonicalize_dynamic_symtab
812
+#define bfd_elf32_get_synthetic_symtab _bfd_elf_get_synthetic_symtab
813
+#define bfd_elf32_canonicalize_reloc   _bfd_elf_canonicalize_reloc
814
+#define bfd_elf32_find_nearest_line    _bfd_elf_find_nearest_line
815
+#define bfd_elf32_find_line            _bfd_elf_find_line
816
+#define bfd_elf32_find_inliner_info    _bfd_elf_find_inliner_info
817
+#define bfd_elf32_read_minisymbols     _bfd_elf_read_minisymbols
818
+#define bfd_elf32_minisymbol_to_symbol _bfd_elf_minisymbol_to_symbol
819
+#define bfd_elf32_get_dynamic_symtab_upper_bound \
820
+  _bfd_elf_get_dynamic_symtab_upper_bound
821
+#define bfd_elf32_get_lineno           _bfd_elf_get_lineno
822
+#define bfd_elf32_get_reloc_upper_bound _bfd_elf_get_reloc_upper_bound
823
+#define bfd_elf32_get_symbol_info      _bfd_elf_get_symbol_info
824
+#define bfd_elf32_get_symbol_version_string    _bfd_elf_get_symbol_version_string
825
+#define bfd_elf32_canonicalize_symtab  _bfd_elf_canonicalize_symtab
826
+#define bfd_elf32_get_symtab_upper_bound _bfd_elf_get_symtab_upper_bound
827
+#define bfd_elf32_make_empty_symbol    _bfd_elf_make_empty_symbol
828
+#define bfd_elf32_new_section_hook     _bfd_elf_new_section_hook
829
+#define bfd_elf32_set_arch_mach                _bfd_elf_set_arch_mach
830
+#define bfd_elf32_set_section_contents _bfd_elf_set_section_contents
831
+#define bfd_elf32_sizeof_headers       _bfd_elf_sizeof_headers
832
+#define bfd_elf32_write_object_contents _bfd_elf_write_object_contents
833
+#define bfd_elf32_write_corefile_contents _bfd_elf_write_corefile_contents
834
+
835
+#define bfd_elf32_get_section_contents_in_window \
836
+  _bfd_generic_get_section_contents_in_window
837
+
838
+#define elf_backend_can_refcount 0
839
+#define elf_backend_want_got_plt 0
840
+#define elf_backend_plt_readonly 0
841
+#define elf_backend_want_plt_sym 0
842
+#define elf_backend_plt_not_loaded 0
843
+#define elf_backend_plt_alignment 2
844
+#define elf_backend_want_dynbss 1
845
+#define elf_backend_want_p_paddr_set_to_zero 0
846
+#define elf_backend_default_execstack 1
847
+#define elf_backend_caches_rawsize 0
848
+#define elf_backend_extern_protected_data 0
849
+#define elf_backend_stack_align 4
850
+#define elf_backend_strtab_flags 0
851
+
852
+#define bfd_elf32_bfd_debug_info_start bfd_void
853
+#define bfd_elf32_bfd_debug_info_end   bfd_void
854
+#define bfd_elf32_bfd_debug_info_accumulate \
855
+  ((void (*) (bfd*, struct bfd_section *)) bfd_void)
856
+
857
+#define bfd_elf32_bfd_get_relocated_section_contents \
858
+  bfd_generic_get_relocated_section_contents
859
+
860
+#define bfd_elf32_bfd_relax_section bfd_generic_relax_section
861
+
862
+#define elf_backend_can_gc_sections 1
863
+#define elf_backend_can_refcount 0
864
+#define elf_backend_want_got_sym 1
865
+#define elf_backend_gc_keep            _bfd_elf_gc_keep
866
+#define elf_backend_gc_mark_dynamic_ref        bfd_elf_gc_mark_dynamic_ref_symbol
867
+#define elf_backend_gc_mark_hook       _bfd_elf_gc_mark_hook
868
+#define elf_backend_gc_mark_extra_sections _bfd_elf_gc_mark_extra_sections
869
+#define elf_backend_gc_sweep_hook      NULL
870
+#define bfd_elf32_bfd_gc_sections bfd_elf_gc_sections
871
+
872
+#ifndef bfd_elf32_bfd_merge_sections
873
+#define bfd_elf32_bfd_merge_sections _bfd_elf_merge_sections
874
+#endif
875
+
876
+#ifndef bfd_elf32_bfd_is_group_section
877
+#define bfd_elf32_bfd_is_group_section bfd_elf_is_group_section
878
+#endif
879
+
880
+#ifndef bfd_elf32_bfd_discard_group
881
+#define bfd_elf32_bfd_discard_group bfd_generic_discard_group
882
+#endif
883
+
884
+#ifndef bfd_elf32_section_already_linked
885
+#define bfd_elf32_section_already_linked _bfd_elf_section_already_linked
886
+#endif
887
+
888
+#ifndef bfd_elf32_bfd_define_common_symbol
889
+#define bfd_elf32_bfd_define_common_symbol bfd_generic_define_common_symbol
890
+#endif
891
+
892
+#ifndef bfd_elf32_bfd_lookup_section_flags
893
+#define bfd_elf32_bfd_lookup_section_flags bfd_elf_lookup_section_flags
894
+#endif
895
+
896
+#ifndef bfd_elf32_bfd_make_debug_symbol
897
+#define bfd_elf32_bfd_make_debug_symbol \
898
+  ((asymbol * (*) (bfd *, void *, unsigned long)) bfd_nullvoidptr)
899
+#endif
900
+
901
+#ifndef bfd_elf32_bfd_copy_private_symbol_data
902
+#define bfd_elf32_bfd_copy_private_symbol_data _bfd_elf_copy_private_symbol_data
903
+#endif
904
+
905
+#ifndef bfd_elf32_bfd_copy_private_section_data
906
+#define bfd_elf32_bfd_copy_private_section_data \
907
+  _bfd_elf_copy_private_section_data
908
+#endif
909
+#ifndef bfd_elf32_bfd_copy_private_header_data
910
+#define bfd_elf32_bfd_copy_private_header_data \
911
+  _bfd_elf_copy_private_header_data
912
+#endif
913
+#ifndef bfd_elf32_bfd_copy_private_bfd_data
914
+#define bfd_elf32_bfd_copy_private_bfd_data \
915
+  _bfd_elf_copy_private_bfd_data
916
+#endif
917
+#ifndef bfd_elf32_bfd_print_private_bfd_data
918
+#define bfd_elf32_bfd_print_private_bfd_data \
919
+  _bfd_elf_print_private_bfd_data
920
+#endif
921
+#ifndef bfd_elf32_bfd_merge_private_bfd_data
922
+#define bfd_elf32_bfd_merge_private_bfd_data \
923
+  ((bfd_boolean (*) (bfd *, bfd *)) bfd_true)
924
+#endif
925
+#ifndef bfd_elf32_bfd_set_private_flags
926
+#define bfd_elf32_bfd_set_private_flags \
927
+  ((bfd_boolean (*) (bfd *, flagword)) bfd_true)
928
+#endif
929
+#ifndef bfd_elf32_bfd_is_local_label_name
930
+#define bfd_elf32_bfd_is_local_label_name _bfd_elf_is_local_label_name
931
+#endif
932
+#ifndef bfd_elf32_bfd_is_target_special_symbol
933
+#define bfd_elf32_bfd_is_target_special_symbol \
934
+  ((bfd_boolean (*) (bfd *, asymbol *)) bfd_false)
935
+#endif
936
+
937
+#ifndef bfd_elf32_get_dynamic_reloc_upper_bound
938
+#define bfd_elf32_get_dynamic_reloc_upper_bound \
939
+  _bfd_elf_get_dynamic_reloc_upper_bound
940
+#endif
941
+#ifndef bfd_elf32_canonicalize_dynamic_reloc
942
+#define bfd_elf32_canonicalize_dynamic_reloc _bfd_elf_canonicalize_dynamic_reloc
943
+#endif
944
+
945
+#define bfd_elf32_bfd_link_hash_table_create _bfd_elf_link_hash_table_create
946
+#define bfd_elf32_bfd_link_add_symbols bfd_elf_link_add_symbols
947
+#define bfd_elf32_bfd_final_link       bfd_elf_final_link
948
+
949
+#define bfd_elf32_bfd_link_just_syms   _bfd_elf_link_just_syms
950
+
951
+#define bfd_elf32_bfd_copy_link_hash_symbol_type \
952
+  _bfd_elf_copy_link_hash_symbol_type
953
+
954
+#define bfd_elf32_bfd_link_split_section _bfd_generic_link_split_section
955
+#define bfd_elf32_bfd_link_check_relocs _bfd_generic_link_check_relocs
956
+#define bfd_elf32_archive_p bfd_generic_archive_p
957
+#define bfd_elf32_write_archive_contents _bfd_write_archive_contents
958
+#define bfd_elf32_mkobject bfd_elf_make_object
959
+#define bfd_elf32_mkcorefile bfd_elf_mkcorefile
960
+#define bfd_elf32_mkarchive _bfd_generic_mkarchive
961
+#define bfd_elf32_print_symbol bfd_elf_print_symbol
962
+#define elf_symbol_leading_char 0
963
+
964
+#define elf_backend_arch_data NULL
965
+
966
+#ifndef ELF_TARGET_ID
967
+#define ELF_TARGET_ID  GENERIC_ELF_DATA
968
+#endif
969
+
970
+#ifndef ELF_OSABI
971
+#define ELF_OSABI ELFOSABI_NONE
972
+#endif
973
+
974
+#define ELF_COMMONPAGESIZE ELF_MAXPAGESIZE
975
+#define ELF_MINPAGESIZE ELF_COMMONPAGESIZE
976
+
977
+#if ELF_COMMONPAGESIZE > ELF_MAXPAGESIZE
978
+# error ELF_COMMONPAGESIZE > ELF_MAXPAGESIZE
979
+#endif
980
+#if ELF_MINPAGESIZE > ELF_COMMONPAGESIZE
981
+# error ELF_MINPAGESIZE > ELF_COMMONPAGESIZE
982
+#endif
983
+
984
+#ifndef ELF_DYNAMIC_SEC_FLAGS
985
+/* Note that we set the SEC_IN_MEMORY flag for these sections.  */
986
+#define ELF_DYNAMIC_SEC_FLAGS                  \
987
+  (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS     \
988
+   | SEC_IN_MEMORY | SEC_LINKER_CREATED)
989
+#endif
990
+
991
+#define elf_backend_collect FALSE
992
+#define elf_backend_type_change_ok FALSE
993
+
994
+#define elf_backend_sym_is_global      0
995
+#define elf_backend_object_p           0
996
+#define elf_backend_symbol_processing  0
997
+#define elf_backend_symbol_table_processing    0
998
+#define elf_backend_get_symbol_type 0
999
+#define elf_backend_archive_symbol_lookup _bfd_elf_archive_symbol_lookup
1000
+#define elf_backend_name_local_section_symbols 0
1001
+#define elf_backend_section_processing 0
1002
+#define elf_backend_section_from_shdr  _bfd_elf_make_section_from_shdr
1003
+#define elf_backend_section_flags      0
1004
+#define elf_backend_get_sec_type_attr  _bfd_elf_get_sec_type_attr
1005
+#define elf_backend_section_from_phdr  _bfd_elf_make_section_from_phdr
1006
+#define elf_backend_fake_sections      0
1007
+#define elf_backend_section_from_bfd_section   0
1008
+#define elf_backend_add_symbol_hook    0
1009
+#define elf_backend_link_output_symbol_hook 0
1010
+#define elf_backend_create_dynamic_sections 0
1011
+#define elf_backend_omit_section_dynsym _bfd_elf_link_omit_section_dynsym
1012
+#define elf_backend_relocs_compatible _bfd_elf_default_relocs_compatible
1013
+#define elf_backend_check_relocs       0
1014
+#define elf_backend_check_directives   0
1015
+#define elf_backend_notice_as_needed   _bfd_elf_notice_as_needed
1016
+#define elf_backend_adjust_dynamic_symbol 0
1017
+#define elf_backend_always_size_sections 0
1018
+#define elf_backend_size_dynamic_sections 0
1019
+#define elf_backend_init_index_section \
1020
+ ((void (*) (bfd *, struct bfd_link_info *)) bfd_void)
1021
+#define elf_backend_finish_dynamic_symbol      0
1022
+#define elf_backend_finish_dynamic_sections    0
1023
+#define elf_backend_begin_write_processing     0
1024
+#define elf_backend_final_write_processing     0
1025
+#define elf_backend_additional_program_headers 0
1026
+#define elf_backend_modify_segment_map 0
1027
+#ifndef elf_backend_modify_program_headers
1028
+#define elf_backend_modify_program_headers     0
1029
+#endif
1030
+#ifndef elf_backend_ecoff_debug_swap
1031
+#define elf_backend_ecoff_debug_swap   0
1032
+#endif
1033
+#ifndef elf_backend_bfd_from_remote_memory
1034
+#define elf_backend_bfd_from_remote_memory _bfd_elf32_bfd_from_remote_memory
1035
+#endif
1036
+#ifndef elf_backend_got_header_size
1037
+#define elf_backend_got_header_size    0
1038
+#endif
1039
+#ifndef elf_backend_got_elt_size
1040
+#define elf_backend_got_elt_size _bfd_elf_default_got_elt_size
1041
+#endif
1042
+#ifndef elf_backend_obj_attrs_vendor
1043
+#define elf_backend_obj_attrs_vendor           NULL
1044
+#endif
1045
+#ifndef elf_backend_obj_attrs_section
1046
+#define elf_backend_obj_attrs_section          NULL
1047
+#endif
1048
+#ifndef elf_backend_obj_attrs_arg_type
1049
+#define elf_backend_obj_attrs_arg_type         NULL
1050
+#endif
1051
+#ifndef elf_backend_obj_attrs_section_type
1052
+#define elf_backend_obj_attrs_section_type             SHT_GNU_ATTRIBUTES
1053
+#endif
1054
+#ifndef elf_backend_obj_attrs_order
1055
+#define elf_backend_obj_attrs_order            NULL
1056
+#endif
1057
+#define elf_backend_obj_attrs_handle_unknown   NULL
1058
+#define elf_backend_static_tls_alignment       1
1059
+#define elf_backend_post_process_headers       _bfd_elf_post_process_headers
1060
+#define elf_backend_print_symbol_all           NULL
1061
+#define elf_backend_output_arch_local_syms     NULL
1062
+#define elf_backend_output_arch_syms           NULL
1063
+#define elf_backend_copy_indirect_symbol  _bfd_elf_link_hash_copy_indirect
1064
+#define elf_backend_hide_symbol                _bfd_elf_link_hash_hide_symbol
1065
+#define elf_backend_fixup_symbol               NULL
1066
+#define elf_backend_merge_symbol_attribute     NULL
1067
+#define elf_backend_get_target_dtag            NULL
1068
+#define elf_backend_ignore_undef_symbol                NULL
1069
+#define elf_backend_emit_relocs                        _bfd_elf_link_output_relocs
1070
+#define elf_backend_count_relocs               NULL
1071
+#define elf_backend_count_additional_relocs    NULL
1072
+#define elf_backend_sort_relocs_p              NULL
1073
+#define elf_backend_grok_prstatus              NULL
1074
+#define elf_backend_grok_psinfo                        NULL
1075
+#define elf_backend_write_core_note            NULL
1076
+#define elf_backend_lookup_section_flags_hook  NULL
1077
+#define elf_backend_reloc_type_class           _bfd_elf_reloc_type_class
1078
+#define elf_backend_discard_info               NULL
1079
+#define elf_backend_ignore_discarded_relocs    NULL
1080
+#define elf_backend_action_discarded _bfd_elf_default_action_discarded
1081
+#define elf_backend_eh_frame_address_size _bfd_elf_eh_frame_address_size
1082
+#define elf_backend_can_make_relative_eh_frame _bfd_elf_can_make_relative
1083
+#define elf_backend_can_make_lsda_relative_eh_frame    _bfd_elf_can_make_relative
1084
+#define elf_backend_encode_eh_address          _bfd_elf_encode_eh_address
1085
+#define elf_backend_write_section              NULL
1086
+#define elf_backend_mips_irix_compat           NULL
1087
+#define elf_backend_mips_rtype_to_howto                NULL
1088
+
1089
+/* Previously, backends could only use SHT_REL or SHT_RELA relocation
1090
+   sections, but not both.  They defined USE_REL to indicate SHT_REL
1091
+   sections, and left it undefined to indicated SHT_RELA sections.
1092
+   For backwards compatibility, we still support this usage.  */
1093
+#ifndef USE_REL
1094
+#define USE_REL 0
1095
+#endif
1096
+
1097
+/* Use these in new code.  */
1098
+#define elf_backend_may_use_rel_p USE_REL
1099
+#define elf_backend_may_use_rela_p !USE_REL
1100
+#define elf_backend_default_use_rela_p !USE_REL
1101
+#define elf_backend_rela_plts_and_copies_p elf_backend_default_use_rela_p
1102
+
1103
+#ifndef elf_backend_rela_normal
1104
+#define elf_backend_rela_normal 0
1105
+#endif
1106
+
1107
+#define elf_backend_plt_sym_val NULL
1108
+#define elf_backend_relplt_name NULL
1109
+
1110
+#define ELF_MACHINE_ALT1 0
1111
+#define ELF_MACHINE_ALT2 0
1112
+
1113
+#ifndef elf_backend_size_info
1114
+#define elf_backend_size_info _bfd_elf32_size_info
1115
+#endif
1116
+
1117
+#define elf_backend_special_sections NULL
1118
+#define elf_backend_sign_extend_vma 0
1119
+#define elf_backend_link_order_error_handler _bfd_default_error_handler
1120
+#define elf_backend_common_definition _bfd_elf_common_definition
1121
+#define elf_backend_common_section_index _bfd_elf_common_section_index
1122
+#define elf_backend_common_section _bfd_elf_common_section
1123
+
1124
+#define elf_backend_merge_symbol NULL
1125
+#define elf_backend_hash_symbol _bfd_elf_hash_symbol
1126
+#define elf_backend_is_function_type _bfd_elf_is_function_type
1127
+#define elf_backend_maybe_function_sym _bfd_elf_maybe_function_sym
1128
+#define elf_backend_get_reloc_section _bfd_elf_get_reloc_section
1129
+#define elf_backend_copy_special_section_fields NULL
1130
+#define elf_backend_compact_eh_encoding NULL
1131
+#define elf_backend_cant_unwind_opcode 0
1132
+
1133
+#define elf_match_priority \
1134
+  (ELF_ARCH == bfd_arch_unknown ? 2 : ELF_OSABI == ELFOSABI_NONE ? 1 : 0)
1135
+
1136
+extern const struct elf_size_info _bfd_elf32_size_info;
1137
+
1138
+static struct elf_backend_data elf32_bed =
1139
+{
1140
+  ELF_ARCH,                    /* arch */
1141
+  ELF_TARGET_ID,               /* target_id */
1142
+  ELF_MACHINE_CODE,            /* elf_machine_code */
1143
+  ELF_OSABI,                   /* elf_osabi  */
1144
+  ELF_MAXPAGESIZE,             /* maxpagesize */
1145
+  ELF_MINPAGESIZE,             /* minpagesize */
1146
+  ELF_COMMONPAGESIZE,          /* commonpagesize */
1147
+  ELF_DYNAMIC_SEC_FLAGS,       /* dynamic_sec_flags */
1148
+  elf_backend_arch_data,
1149
+  elf_info_to_howto,
1150
+  elf_info_to_howto_rel,
1151
+  elf_backend_sym_is_global,
1152
+  elf_backend_object_p,
1153
+  elf_backend_symbol_processing,
1154
+  elf_backend_symbol_table_processing,
1155
+  elf_backend_get_symbol_type,
1156
+  elf_backend_archive_symbol_lookup,
1157
+  elf_backend_name_local_section_symbols,
1158
+  elf_backend_section_processing,
1159
+  elf_backend_section_from_shdr,
1160
+  elf_backend_section_flags,
1161
+  elf_backend_get_sec_type_attr,
1162
+  elf_backend_section_from_phdr,
1163
+  elf_backend_fake_sections,
1164
+  elf_backend_section_from_bfd_section,
1165
+  elf_backend_add_symbol_hook,
1166
+  elf_backend_link_output_symbol_hook,
1167
+  elf_backend_create_dynamic_sections,
1168
+  elf_backend_omit_section_dynsym,
1169
+  elf_backend_relocs_compatible,
1170
+  elf_backend_check_relocs,
1171
+  elf_backend_check_directives,
1172
+  elf_backend_notice_as_needed,
1173
+  elf_backend_adjust_dynamic_symbol,
1174
+  elf_backend_always_size_sections,
1175
+  elf_backend_size_dynamic_sections,
1176
+  elf_backend_init_index_section,
1177
+  elf_backend_relocate_section,
1178
+  elf_backend_finish_dynamic_symbol,
1179
+  elf_backend_finish_dynamic_sections,
1180
+  elf_backend_begin_write_processing,
1181
+  elf_backend_final_write_processing,
1182
+  elf_backend_additional_program_headers,
1183
+  elf_backend_modify_segment_map,
1184
+  elf_backend_modify_program_headers,
1185
+  elf_backend_gc_keep,
1186
+  elf_backend_gc_mark_dynamic_ref,
1187
+  elf_backend_gc_mark_hook,
1188
+  elf_backend_gc_mark_extra_sections,
1189
+  elf_backend_gc_sweep_hook,
1190
+  elf_backend_post_process_headers,
1191
+  elf_backend_print_symbol_all,
1192
+  elf_backend_output_arch_local_syms,
1193
+  elf_backend_output_arch_syms,
1194
+  elf_backend_copy_indirect_symbol,
1195
+  elf_backend_hide_symbol,
1196
+  elf_backend_fixup_symbol,
1197
+  elf_backend_merge_symbol_attribute,
1198
+  elf_backend_get_target_dtag,
1199
+  elf_backend_ignore_undef_symbol,
1200
+  elf_backend_emit_relocs,
1201
+  elf_backend_count_relocs,
1202
+  elf_backend_count_additional_relocs,
1203
+  elf_backend_sort_relocs_p,
1204
+  elf_backend_grok_prstatus,
1205
+  elf_backend_grok_psinfo,
1206
+  elf_backend_write_core_note,
1207
+  elf_backend_lookup_section_flags_hook,
1208
+  elf_backend_reloc_type_class,
1209
+  elf_backend_discard_info,
1210
+  elf_backend_ignore_discarded_relocs,
1211
+  elf_backend_action_discarded,
1212
+  elf_backend_eh_frame_address_size,
1213
+  elf_backend_can_make_relative_eh_frame,
1214
+  elf_backend_can_make_lsda_relative_eh_frame,
1215
+  elf_backend_encode_eh_address,
1216
+  elf_backend_write_section,
1217
+  elf_backend_mips_irix_compat,
1218
+  elf_backend_mips_rtype_to_howto,
1219
+  elf_backend_ecoff_debug_swap,
1220
+  elf_backend_bfd_from_remote_memory,
1221
+  elf_backend_plt_sym_val,
1222
+  elf_backend_common_definition,
1223
+  elf_backend_common_section_index,
1224
+  elf_backend_common_section,
1225
+  elf_backend_merge_symbol,
1226
+  elf_backend_hash_symbol,
1227
+  elf_backend_is_function_type,
1228
+  elf_backend_maybe_function_sym,
1229
+  elf_backend_get_reloc_section,
1230
+  elf_backend_copy_special_section_fields,
1231
+  elf_backend_link_order_error_handler,
1232
+  elf_backend_relplt_name,
1233
+  ELF_MACHINE_ALT1,
1234
+  ELF_MACHINE_ALT2,
1235
+  &elf_backend_size_info,
1236
+  elf_backend_special_sections,
1237
+  elf_backend_got_header_size,
1238
+  elf_backend_got_elt_size,
1239
+  elf_backend_obj_attrs_vendor,
1240
+  elf_backend_obj_attrs_section,
1241
+  elf_backend_obj_attrs_arg_type,
1242
+  elf_backend_obj_attrs_section_type,
1243
+  elf_backend_obj_attrs_order,
1244
+  elf_backend_obj_attrs_handle_unknown,
1245
+  elf_backend_compact_eh_encoding,
1246
+  elf_backend_cant_unwind_opcode,
1247
+  elf_backend_static_tls_alignment,
1248
+  elf_backend_stack_align,
1249
+  elf_backend_strtab_flags,
1250
+  elf_backend_collect,
1251
+  elf_backend_type_change_ok,
1252
+  elf_backend_may_use_rel_p,
1253
+  elf_backend_may_use_rela_p,
1254
+  elf_backend_default_use_rela_p,
1255
+  elf_backend_rela_plts_and_copies_p,
1256
+  elf_backend_rela_normal,
1257
+  elf_backend_sign_extend_vma,
1258
+  elf_backend_want_got_plt,
1259
+  elf_backend_plt_readonly,
1260
+  elf_backend_want_plt_sym,
1261
+  elf_backend_plt_not_loaded,
1262
+  elf_backend_plt_alignment,
1263
+  elf_backend_can_gc_sections,
1264
+  elf_backend_can_refcount,
1265
+  elf_backend_want_got_sym,
1266
+  elf_backend_want_dynbss,
1267
+  elf_backend_want_p_paddr_set_to_zero,
1268
+  elf_backend_default_execstack,
1269
+  elf_backend_caches_rawsize,
1270
+  elf_backend_extern_protected_data
1271
+};
1272
+
1273
+/* Forward declaration for use when initialising alternative_target field.  */
1274
+
1275
+#ifdef TARGET_BIG_SYM
1276
+const bfd_target TARGET_BIG_SYM =
1277
+{
1278
+  /* name: identify kind of target */
1279
+  TARGET_BIG_NAME,
1280
+
1281
+  /* flavour: general indication about file */
1282
+  bfd_target_elf_flavour,
1283
+
1284
+  /* byteorder: data is big endian */
1285
+  BFD_ENDIAN_BIG,
1286
+
1287
+  /* header_byteorder: header is also big endian */
1288
+  BFD_ENDIAN_BIG,
1289
+
1290
+  /* object_flags: mask of all file flags */
1291
+  (HAS_RELOC | EXEC_P | HAS_LINENO | HAS_DEBUG | HAS_SYMS | HAS_LOCALS
1292
+   | DYNAMIC | WP_TEXT | D_PAGED | BFD_COMPRESS | BFD_DECOMPRESS
1293
+   | BFD_COMPRESS_GABI | BFD_CONVERT_ELF_COMMON | BFD_USE_ELF_STT_COMMON),
1294
+
1295
+  /* section_flags: mask of all section flags */
1296
+  (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY
1297
+   | SEC_CODE | SEC_DATA | SEC_DEBUGGING | SEC_EXCLUDE | SEC_SORT_ENTRIES
1298
+   | SEC_SMALL_DATA | SEC_MERGE | SEC_STRINGS | SEC_GROUP),
1299
+
1300
+   /* leading_symbol_char: is the first char of a user symbol
1301
+      predictable, and if so what is it */
1302
+  elf_symbol_leading_char,
1303
+
1304
+  /* ar_pad_char: pad character for filenames within an archive header
1305
+     FIXME:  this really has nothing to do with ELF, this is a characteristic
1306
+     of the archiver and/or os and should be independently tunable */
1307
+  '/',
1308
+
1309
+  /* ar_max_namelen: maximum number of characters in an archive header
1310
+     FIXME:  this really has nothing to do with ELF, this is a characteristic
1311
+     of the archiver and should be independently tunable.  The System V ABI,
1312
+     Chapter 7 (Formats & Protocols), Archive section sets this as 15.  */
1313
+  15,
1314
+
1315
+  elf_match_priority,
1316
+
1317
+  /* Routines to byte-swap various sized integers from the data sections */
1318
+  bfd_getb64, bfd_getb_signed_64, bfd_putb64,
1319
+    bfd_getb32, bfd_getb_signed_32, bfd_putb32,
1320
+    bfd_getb16, bfd_getb_signed_16, bfd_putb16,
1321
+
1322
+  /* Routines to byte-swap various sized integers from the file headers */
1323
+  bfd_getb64, bfd_getb_signed_64, bfd_putb64,
1324
+    bfd_getb32, bfd_getb_signed_32, bfd_putb32,
1325
+    bfd_getb16, bfd_getb_signed_16, bfd_putb16,
1326
+
1327
+  /* bfd_check_format: check the format of a file being read */
1328
+  { _bfd_dummy_target,         /* unknown format */
1329
+    bfd_elf32_object_p,                /* assembler/linker output (object file) */
1330
+    bfd_elf32_archive_p,       /* an archive */
1331
+    bfd_elf32_core_file_p      /* a core file */
1332
+  },
1333
+
1334
+  /* bfd_set_format: set the format of a file being written */
1335
+  { bfd_false,
1336
+    bfd_elf32_mkobject,
1337
+    bfd_elf32_mkarchive,
1338
+    bfd_elf32_mkcorefile
1339
+  },
1340
+
1341
+  /* bfd_write_contents: write cached information into a file being written */
1342
+  { bfd_false,
1343
+    bfd_elf32_write_object_contents,
1344
+    bfd_elf32_write_archive_contents,
1345
+    bfd_elf32_write_corefile_contents,
1346
+  },
1347
+
1348
+  BFD_JUMP_TABLE_GENERIC (bfd_elf32),
1349
+  BFD_JUMP_TABLE_COPY (bfd_elf32),
1350
+  BFD_JUMP_TABLE_CORE (bfd_elf32),
1351
+#ifdef bfd_elf32_archive_functions
1352
+  BFD_JUMP_TABLE_ARCHIVE (bfd_elf32_archive),
1353
+#else
1354
+  BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
1355
+#endif
1356
+  BFD_JUMP_TABLE_SYMBOLS (bfd_elf32),
1357
+  BFD_JUMP_TABLE_RELOCS (bfd_elf32),
1358
+  BFD_JUMP_TABLE_WRITE (bfd_elf32),
1359
+  BFD_JUMP_TABLE_LINK (bfd_elf32),
1360
+  BFD_JUMP_TABLE_DYNAMIC (bfd_elf32),
1361
+
1362
+  /* Alternative endian target.  */
1363
+#ifdef TARGET_LITTLE_SYM
1364
+  & TARGET_LITTLE_SYM,
1365
+#else
1366
+  NULL,
1367
+#endif
1368
+
1369
+  /* backend_data: */
1370
+  &elf32_bed
1371
+};
1372
+#endif
1373
+
1374
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/libbfd.h binutils-2.27-zip/bfd/libbfd.h
1375
--- binutils-2.27/bfd/libbfd.h  2016-08-03 03:36:51.000000000 -0400
1376
+++ binutils-2.27-zip/bfd/libbfd.h      2017-01-04 22:04:11.000000000 -0500
1377
@@ -3125,6 +3125,16 @@
1378
   "BFD_RELOC_VISIUM_HI16_PCREL",
1379
   "BFD_RELOC_VISIUM_LO16_PCREL",
1380
   "BFD_RELOC_VISIUM_IM16_PCREL",
1381
+  "BFD_RELOC_ZIP_VALUE",
1382
+  "BFD_RELOC_ZIP_BRANCH",
1383
+  "BFD_RELOC_ZIP_OPB_IMM",
1384
+  "BFD_RELOC_ZIP_OPB_OFFSET",
1385
+  "BFD_RELOC_ZIP_OPB_PCREL",
1386
+  "BFD_RELOC_ZIP_MOV_OFFSET",
1387
+  "BFD_RELOC_ZIP_MOV_PCREL",
1388
+  "BFD_RELOC_ZIP_LDI",
1389
+  "BFD_RELOC_ZIP_LLO",
1390
+  "BFD_RELOC_ZIP_BREV",
1391
  "@@overflow: BFD_RELOC_UNUSED@@",
1392
 };
1393
 #endif
1394
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/Makefile.am binutils-2.27-zip/bfd/Makefile.am
1395
--- binutils-2.27/bfd/Makefile.am       2016-08-03 03:36:50.000000000 -0400
1396
+++ binutils-2.27-zip/bfd/Makefile.am   2016-12-31 17:26:07.151146300 -0500
1397
@@ -173,7 +173,8 @@
1398
        cpu-xstormy16.lo \
1399
        cpu-xtensa.lo \
1400
        cpu-z80.lo \
1401
-       cpu-z8k.lo
1402
+       cpu-z8k.lo \
1403
+       cpu-zip.lo
1404
 
1405
 ALL_MACHINES_CFILES = \
1406
        cpu-aarch64.c \
1407
@@ -260,7 +261,8 @@
1408
        cpu-xstormy16.c \
1409
        cpu-xtensa.c \
1410
        cpu-z80.c \
1411
-       cpu-z8k.c
1412
+       cpu-z8k.c \
1413
+       cpu-zip.c
1414
 
1415
 # The .o files needed by all of the 32 bit vectors that are configured into
1416
 # target_vector in targets.c if configured with --enable-targets=all.
1417
@@ -382,6 +384,7 @@
1418
        elf32-xgate.lo \
1419
        elf32-xstormy16.lo \
1420
        elf32-xtensa.lo \
1421
+       elf32-zip.lo \
1422
        elf32.lo \
1423
        elflink.lo \
1424
        elfxx-sparc.lo \
1425
@@ -574,6 +577,7 @@
1426
        elf32-xgate.c \
1427
        elf32-xstormy16.c \
1428
        elf32-xtensa.c \
1429
+       elf32-zip.c \
1430
        elf32.c \
1431
        elflink.c \
1432
        elfxx-sparc.c \
1433
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/Makefile.in binutils-2.27-zip/bfd/Makefile.in
1434
--- binutils-2.27/bfd/Makefile.in       2016-08-03 04:06:27.000000000 -0400
1435
+++ binutils-2.27-zip/bfd/Makefile.in   2017-01-04 14:29:55.000000000 -0500
1436
@@ -505,7 +505,8 @@
1437
        cpu-xstormy16.lo \
1438
        cpu-xtensa.lo \
1439
        cpu-z80.lo \
1440
-       cpu-z8k.lo
1441
+       cpu-z8k.lo \
1442
+       cpu-zip.lo
1443
 
1444
 ALL_MACHINES_CFILES = \
1445
        cpu-aarch64.c \
1446
@@ -592,7 +593,8 @@
1447
        cpu-xstormy16.c \
1448
        cpu-xtensa.c \
1449
        cpu-z80.c \
1450
-       cpu-z8k.c
1451
+       cpu-z8k.c \
1452
+       cpu-zip.c
1453
 
1454
 
1455
 # The .o files needed by all of the 32 bit vectors that are configured into
1456
@@ -715,6 +717,7 @@
1457
        elf32-xgate.lo \
1458
        elf32-xstormy16.lo \
1459
        elf32-xtensa.lo \
1460
+       elf32-zip.lo \
1461
        elf32.lo \
1462
        elflink.lo \
1463
        elfxx-sparc.lo \
1464
@@ -907,6 +910,7 @@
1465
        elf32-xgate.c \
1466
        elf32-xstormy16.c \
1467
        elf32-xtensa.c \
1468
+       elf32-zip.c \
1469
        elf32.c \
1470
        elflink.c \
1471
        elfxx-sparc.c \
1472
@@ -1437,6 +1441,7 @@
1473
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xtensa.Plo@am__quote@
1474
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-z80.Plo@am__quote@
1475
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-z8k.Plo@am__quote@
1476
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-zip.Plo@am__quote@
1477
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/demo64.Plo@am__quote@
1478
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf1.Plo@am__quote@
1479
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf2.Plo@am__quote@
1480
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/merge.c binutils-2.27-zip/bfd/merge.c
1481
--- binutils-2.27/bfd/merge.c   2016-08-03 03:36:51.000000000 -0400
1482
+++ binutils-2.27-zip/bfd/merge.c       2017-01-02 14:48:54.000000000 -0500
1483
@@ -826,7 +826,7 @@
1484
   else
1485
     {
1486
       contents = NULL;
1487
-      pos = sec->output_section->filepos + sec->output_offset;
1488
+      pos = sec->output_section->filepos + sec->output_offset * bfd_octets_per_byte(output_bfd);
1489
       if (bfd_seek (output_bfd, pos, SEEK_SET) != 0)
1490
        return FALSE;
1491
     }
1492
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/reloc.c binutils-2.27-zip/bfd/reloc.c
1493
--- binutils-2.27/bfd/reloc.c   2016-08-03 03:36:51.000000000 -0400
1494
+++ binutils-2.27-zip/bfd/reloc.c       2017-01-04 22:03:52.000000000 -0500
1495
@@ -7697,7 +7697,32 @@
1496
   BFD_RELOC_VISIUM_IM16_PCREL
1497
 ENUMDOC
1498
   Visium Relocations.
1499
-
1500
+ENUM
1501
+  BFD_RELOC_ZIP_VALUE
1502
+ENUMDOC
1503
+  ZipCPU - 32 bit absolute value for LJMP instruction
1504
+ENUM
1505
+  BFD_RELOC_ZIP_BRANCH
1506
+ENUMDOC
1507
+  ZipCPU - 18-bit PC-relative offset for BRA (ADD #x,PC) instructions
1508
+ENUM
1509
+  BFD_RELOC_ZIP_OPB_IMM
1510
+ENUMX
1511
+  BFD_RELOC_ZIP_OPB_OFFSET
1512
+ENUMX
1513
+  BFD_RELOC_ZIP_OPB_PCREL
1514
+ENUMX
1515
+  BFD_RELOC_ZIP_MOV_OFFSET
1516
+ENUMX
1517
+  BFD_RELOC_ZIP_MOV_PCREL
1518
+ENUMX
1519
+  BFD_RELOC_ZIP_LDI
1520
+ENUMX
1521
+  BFD_RELOC_ZIP_LLO
1522
+ENUMX
1523
+  BFD_RELOC_ZIP_BREV
1524
+ENUMDOC
1525
+  ZipCPU value relocations
1526
 ENDSENUM
1527
   BFD_RELOC_UNUSED
1528
 CODE_FRAGMENT
1529
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/targets.c binutils-2.27-zip/bfd/targets.c
1530
--- binutils-2.27/bfd/targets.c 2016-08-03 03:36:51.000000000 -0400
1531
+++ binutils-2.27-zip/bfd/targets.c     2016-12-31 17:37:14.021847080 -0500
1532
@@ -910,6 +910,7 @@
1533
 extern const bfd_target xtensa_elf32_le_vec;
1534
 extern const bfd_target z80_coff_vec;
1535
 extern const bfd_target z8k_coff_vec;
1536
+extern const bfd_target zip_elf32_vec;
1537
 
1538
 /* These are always included.  */
1539
 extern const bfd_target srec_vec;
1540
@@ -1441,6 +1442,8 @@
1541
        &z80_coff_vec,
1542
 
1543
        &z8k_coff_vec,
1544
+
1545
+       &zip_elf32_vec,
1546
 #endif /* not SELECT_VECS */
1547
 
1548
 /* Always support S-records, for convenience.  */
1549
diff -Naur '--exclude=*.swp' binutils-2.27/binutils/readelf.c binutils-2.27-zip/binutils/readelf.c
1550
--- binutils-2.27/binutils/readelf.c    2016-08-03 03:36:51.000000000 -0400
1551
+++ binutils-2.27-zip/binutils/readelf.c        2016-12-31 17:40:19.908241961 -0500
1552
@@ -154,6 +154,7 @@
1553
 #include "elf/xgate.h"
1554
 #include "elf/xstormy16.h"
1555
 #include "elf/xtensa.h"
1556
+#include "elf/zip.h"
1557
 
1558
 #include "getopt.h"
1559
 #include "libiberty.h"
1560
@@ -800,6 +801,7 @@
1561
     case EM_XTENSA_OLD:
1562
     case EM_MICROBLAZE:
1563
     case EM_MICROBLAZE_OLD:
1564
+    case EM_ZIP:
1565
       return TRUE;
1566
 
1567
     case EM_68HC05:
1568
@@ -1476,6 +1478,10 @@
1569
        case EM_ALTERA_NIOS2:
1570
          rtype = elf_nios2_reloc_type (type);
1571
          break;
1572
+
1573
+       case EM_ZIP:
1574
+         rtype = elf_zip_reloc_type (type);
1575
+         break;
1576
        }
1577
 
1578
       if (rtype == NULL)
1579
@@ -2339,6 +2345,7 @@
1580
     case EM_TILEGX:            return "Tilera TILE-Gx multicore architecture family";
1581
     case EM_CUDA:              return "NVIDIA CUDA architecture";
1582
     case EM_XGATE:             return "Motorola XGATE embedded processor";
1583
+    case EM_ZIP:               return "Gisselquist Technology ZipCPU";
1584
     default:
1585
       snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine);
1586
       return buff;
1587
@@ -11659,6 +11666,8 @@
1588
     case EM_XTENSA_OLD:
1589
     case EM_XTENSA:
1590
       return reloc_type == 1; /* R_XTENSA_32.  */
1591
+    case EM_ZIP:
1592
+      return reloc_type == 1; /* R_ZIP_32.  */
1593
     default:
1594
       {
1595
        static unsigned int prev_warn = 0;
1596
@@ -11735,6 +11744,8 @@
1597
     case EM_XTENSA_OLD:
1598
     case EM_XTENSA:
1599
       return reloc_type == 14; /* R_XTENSA_32_PCREL.  */
1600
+    case EM_ZIP:
1601
+      return FALSE; /*  */
1602
     default:
1603
       /* Do not abort or issue an error message here.  Not all targets use
1604
         pc-relative 32-bit relocs in their DWARF debug information and we
1605
@@ -11944,6 +11955,7 @@
1606
     case EM_TI_C6000:/* R_C6000_NONE.  */
1607
     case EM_X86_64:  /* R_X86_64_NONE.  */
1608
     case EM_XC16X:
1609
+    case EM_ZIP:
1610
       return reloc_type == 0;
1611
 
1612
     case EM_AARCH64:
1613
diff -Naur '--exclude=*.swp' binutils-2.27/config.sub binutils-2.27-zip/config.sub
1614
--- binutils-2.27/config.sub    2016-08-03 03:36:51.000000000 -0400
1615
+++ binutils-2.27-zip/config.sub        2017-01-11 14:20:34.804049801 -0500
1616
@@ -316,7 +316,7 @@
1617
        | visium \
1618
        | we32k \
1619
        | x86 | xc16x | xstormy16 | xtensa \
1620
-       | z8k | z80)
1621
+       | z8k | z80 )
1622
                basic_machine=$basic_machine-unknown
1623
                ;;
1624
        c54x)
1625
@@ -355,6 +355,14 @@
1626
        xscaleel)
1627
                basic_machine=armel-unknown
1628
                ;;
1629
+       zip-*-linux*)
1630
+               basic_machine=zip
1631
+               os=-linux
1632
+               ;;
1633
+       zip*)
1634
+               basic_machine=zip-unknown
1635
+               os=-elf
1636
+               ;;
1637
 
1638
        # We use `pc' rather than `unknown'
1639
        # because (1) that's what they normally are, and
1640
diff -Naur '--exclude=*.swp' binutils-2.27/configure binutils-2.27-zip/configure
1641
--- binutils-2.27/configure     2016-08-03 03:54:55.000000000 -0400
1642
+++ binutils-2.27-zip/configure 2017-01-08 20:37:33.566336786 -0500
1643
@@ -3548,6 +3548,9 @@
1644
   ft32-*-*)
1645
     noconfigdirs="$noconfigdirs ${libgcj}"
1646
     ;;
1647
+  zip*)
1648
+    noconfigdirs="$noconfigdirs ${libgcj}"
1649
+    ;;
1650
   *-*-lynxos*)
1651
     noconfigdirs="$noconfigdirs ${libgcj}"
1652
     ;;
1653
@@ -3575,6 +3578,9 @@
1654
     *-*-aix*)
1655
        noconfigdirs="$noconfigdirs target-libgo"
1656
        ;;
1657
+    zip*)
1658
+       noconfigdirs="$noconfigdirs target-libgo"
1659
+       ;;
1660
     esac
1661
 fi
1662
 
1663
@@ -3974,6 +3980,9 @@
1664
   vax-*-*)
1665
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
1666
     ;;
1667
+  zip*)
1668
+    noconfigdirs="$noconfigdirs gdb gprof"
1669
+    ;;
1670
 esac
1671
 
1672
 # If we aren't building newlib, then don't build libgloss, since libgloss
1673
diff -Naur '--exclude=*.swp' binutils-2.27/configure.ac binutils-2.27-zip/configure.ac
1674
--- binutils-2.27/configure.ac  2016-08-03 04:37:38.000000000 -0400
1675
+++ binutils-2.27-zip/configure.ac      2017-01-08 20:41:54.836485336 -0500
1676
@@ -884,6 +884,9 @@
1677
   ft32-*-*)
1678
     noconfigdirs="$noconfigdirs ${libgcj}"
1679
     ;;
1680
+  zip*)
1681
+    noconfigdirs="$noconfigdirs ${libgcj}"
1682
+    ;;
1683
   *-*-lynxos*)
1684
     noconfigdirs="$noconfigdirs ${libgcj}"
1685
     ;;
1686
@@ -911,6 +914,9 @@
1687
     *-*-aix*)
1688
        noconfigdirs="$noconfigdirs target-libgo"
1689
        ;;
1690
+    zip*)
1691
+       noconfigdirs="$noconfigdirs target-libgo"
1692
+       ;;
1693
     esac
1694
 fi
1695
 
1696
@@ -1310,6 +1316,9 @@
1697
   vax-*-*)
1698
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
1699
     ;;
1700
+  zip*)
1701
+    noconfigdirs="$noconfigdirs ${libgcj} gdb sim gprof"
1702
+    ;;
1703
 esac
1704
 
1705
 # If we aren't building newlib, then don't build libgloss, since libgloss
1706
diff -Naur '--exclude=*.swp' binutils-2.27/gas/config/tc-zip.c binutils-2.27-zip/gas/config/tc-zip.c
1707
--- binutils-2.27/gas/config/tc-zip.c   1969-12-31 19:00:00.000000000 -0500
1708
+++ binutils-2.27-zip/gas/config/tc-zip.c       2017-03-08 17:57:01.048791909 -0500
1709
@@ -0,0 +1,3329 @@
1710
+////////////////////////////////////////////////////////////////////////////////
1711
+//
1712
+// Filename:   tc-zip.c
1713
+//
1714
+// Project:    Zip CPU backend for GNU Binutils
1715
+//
1716
+// Purpose:    This is the main file associated with the Zip Assembler.  By
1717
+//             that I mean that it handles all of the ZipCPU specifics.  The
1718
+//     rest of the files you find in this directory, mostly tc-cpuname.c and
1719
+//     such, handle other CPUs.  This one handles the ZipCPU.  The goal in
1720
+//     doing this is so that nothing else changes when changes need to be made
1721
+//     to a CPU, and that changes to the assembler in general shouldn't impact
1722
+//     the CPU specific processing.
1723
+//
1724
+//     I'll let you be the judge as to how well this file meets that goal.
1725
+//
1726
+// Creator:    Dan Gisselquist, Ph.D.
1727
+//             Gisselquist Technology, LLC
1728
+//
1729
+////////////////////////////////////////////////////////////////////////////////
1730
+//
1731
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
1732
+//
1733
+// This program is free software (firmware): you can redistribute it and/or
1734
+// modify it under the terms of  the GNU General Public License as published
1735
+// by the Free Software Foundation, either version 3 of the License, or (at
1736
+// your option) any later version.
1737
+//
1738
+// This program is distributed in the hope that it will be useful, but WITHOUT
1739
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
1740
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1741
+// for more details.
1742
+//
1743
+// You should have received a copy of the GNU General Public License along
1744
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
1745
+// target there if the PDF file isn't present.)  If not, see
1746
+// <http://www.gnu.org/licenses/> for a copy.
1747
+//
1748
+// License:    GPL, v3, as defined and found on www.gnu.org,
1749
+//             http://www.gnu.org/licenses/gpl.html
1750
+//
1751
+//
1752
+////////////////////////////////////////////////////////////////////////////////
1753
+#include "as.h"
1754
+
1755
+#include <stdlib.h>
1756
+#include <string.h>
1757
+#include <stdint.h>
1758
+#include <ctype.h>
1759
+
1760
+#include "frags.h"
1761
+#include "struc-symbol.h"
1762
+#include "symbols.h"
1763
+#include "config/tc-zip.h"
1764
+#include "elf/zip.h"
1765
+
1766
+// #define     ZIP_DEBUG
1767
+
1768
+const  char    comment_chars[] = ";#";
1769
+const  char    line_comment_chars[] = ";#";
1770
+// Characters which separate lines (newline need to be listed)
1771
+const  char    line_separator_chars[] = "";
1772
+
1773
+// Characters defining floating point numbers, such as 0f<floatingpt#>
1774
+const  char    FLT_CHARS[] = "fFrR";
1775
+
1776
+// Characters that may be used for an exponent in floating point numbers
1777
+const  char    EXP_CHARS[] = "eE";
1778
+
1779
+static int     cis_mergable = 0; // tc_check_label, tc_frob_label
1780
+
1781
+// zip_param_got is a flag that we'll set to know if we need to reference a
1782
+// global offset table.  Since nothing we've done has yet needed that table,
1783
+// we'll keep this undefined for now.
1784
+//
1785
+// static int  zip_param_got = 0;
1786
+static int     zip_param_cis = 1;
1787
+static int     zip_param_small = 0;
1788
+static int     zip_param_use_machine  = 1;
1789
+
1790
+typedef        struct  {
1791
+       int     m_known;
1792
+       int32_t m_value;
1793
+       symbolS *m_addsy, *m_subsy;
1794
+} MACHINEVALUE;
1795
+
1796
+typedef        struct  {
1797
+       MACHINEVALUE    r[ZIP_USER_REGS];
1798
+} MACHINEREGS;
1799
+
1800
+MACHINEREGS    zipm;
1801
+
1802
+static void zip_clear_machine(MACHINEREGS *pzipm);
1803
+
1804
+void   md_begin(void) {
1805
+       cis_mergable = FALSE;
1806
+       //
1807
+       record_alignment(text_section, 2);
1808
+       record_alignment(data_section, 2);
1809
+       //
1810
+       lex_type['['] = lex_type['A'];
1811
+       //
1812
+       zip_clear_machine(&zipm);
1813
+}
1814
+
1815
+void   md_end(void) { }
1816
+
1817
+void   zip_cons_align(int n) {
1818
+       int     lg;
1819
+       for(lg=0; ((1<<lg)<n)&&(lg<2); lg++)
1820
+               ;
1821
+       do_align(lg, NULL, 0, (1<<lg)-1);
1822
+}
1823
+
1824
+void   zip_flush_pending_output(void) {
1825
+       // If the Assembler is going to stuff things into our output stream,
1826
+       // then we need to make certain that any instructions that follow
1827
+       // dont try to merge with anything previous.  i.e., CIS = false.
1828
+       cis_mergable = FALSE;
1829
+}
1830
+
1831
+int    zip_address_bytes(void) { return 4; }
1832
+
1833
+const  pseudo_typeS    md_pseudo_table[] =
1834
+{
1835
+       { "word", cons, 4 },    // ZipCPU word size is 4, not 2
1836
+       { "long", cons, 8 },    // ZipCPU longs are 64-bits, not 32
1837
+       { "quad", cons,16 },    // ZipCPU QUAD-words are 128-bits, not 64
1838
+       { NULL, NULL, 0 }
1839
+};
1840
+
1841
+#define        ZIP_CC_SLEEP    0x010
1842
+#define        ZIP_CC_GIE      0x020
1843
+#define        ZIP_CC_STEP     0x040
1844
+
1845
+#define        SIM_OPCODE      0x77800000      // 0111.x111.1000. .... 0_111.x_111.10....
1846
+#define        NOOP_OPCODE     0x77c00000      // 0111.x111.1100. .... 0_111.x_111.11....
1847
+
1848
+typedef  struct {
1849
+       bfd_reloc_code_real_type        r_type;
1850
+       symbolS                         *r_sym;
1851
+       int                             r_pcrel;
1852
+       long                            r_fr_offset;
1853
+       fixS                            *r_fix;
1854
+       // Could also be char *name and bfd_reloc_code_real_type
1855
+} ZIPRELOC;
1856
+
1857
+// In case the instruction ...
1858
+#define        ZIP_MAX_NAUX    3 // Number of auxilliary instruction codes used
1859
+typedef        struct {
1860
+       int             i_naux;
1861
+       unsigned        i_code, // The actual machine language instruction
1862
+                       i_aux[ZIP_MAX_NAUX];
1863
+       ZIP_OPCODE      i_op;
1864
+       ZIP_CONDITION   i_cnd;
1865
+       ZIP_REG         i_areg; // = ZIP_RNONE for no register
1866
+       ZIP_REG         i_breg;
1867
+       int             i_imm;
1868
+       ZIPRELOC        *i_rp;
1869
+} ZIPIS;
1870
+
1871
+static ZIPIS *
1872
+zip_copy_insn(const ZIPIS *old) {
1873
+       ZIPIS *nw = (ZIPIS *)xmalloc(sizeof(ZIPIS));
1874
+
1875
+       memcpy((char *)nw, (char *)old, sizeof(ZIPIS));
1876
+
1877
+       return nw;
1878
+}
1879
+
1880
+static uint32_t
1881
+zip_brev(uint32_t v) {
1882
+       unsigned r=0, b;
1883
+
1884
+       for(b=0; b<32; b++, v>>=1)
1885
+               r = (r<<1)|(v&1);
1886
+
1887
+       return r;
1888
+}
1889
+
1890
+static const   int MACH_VUNKNOWN = 0, MACH_VKNOWN = 1, MACH_VUPPERKNOWN = 2,
1891
+                       MACH_VSYMKNOWN = 3;
1892
+
1893
+static void
1894
+zip_clear_machine(MACHINEREGS *pzipm) {
1895
+       int     i;
1896
+
1897
+#ifdef ZIP_DEBUG
1898
+       fprintf(stderr, "MACHINE, CLEAR\n");
1899
+#endif
1900
+       for(i=0; i<ZIP_USER_REGS; i++)
1901
+               pzipm->r[i].m_known = MACH_VUNKNOWN;
1902
+       for(i=0; i<ZIP_USER_REGS; i++)
1903
+               pzipm->r[i].m_addsy = NULL;
1904
+       for(i=0; i<ZIP_USER_REGS; i++)
1905
+               pzipm->r[i].m_subsy = NULL;
1906
+}
1907
+
1908
+static void
1909
+zip_advance_machine(MACHINEREGS *pzipm, ZIPIS *insn) {
1910
+       int             bval = insn->i_imm;
1911
+       int             bknown;
1912
+       MACHINEVALUE    *av, *bv;
1913
+
1914
+       if (!zip_param_use_machine) {
1915
+               // zip_clear_machine(pzipm);
1916
+               return;
1917
+       }
1918
+
1919
+       // The next three instructions don't change any machine values
1920
+       if((insn->i_op == ZIPO_SW)||(insn->i_op == ZIPO_SH)
1921
+               ||(insn->i_op==ZIPO_SB)
1922
+               ||(insn->i_op == ZIPO_CMP)||(insn->i_op == ZIPO_TST))
1923
+               return;
1924
+
1925
+       //
1926
+       // What remains to be done is to include symbols into the machine
1927
+       // state.  For now, we state that anything with a symbol becomes
1928
+       // unknown.
1929
+       //
1930
+       if ((insn->i_op == ZIPO_LJSR)||(insn->i_op == ZIPO_JSR)) {
1931
+               zip_clear_machine(pzipm);
1932
+               return;
1933
+       }
1934
+       if ((insn->i_rp)&&(insn->i_areg<ZIP_CC)) {
1935
+               bknown = MACH_VUNKNOWN;
1936
+               if((insn->i_op==ZIPO_LDI)&&(insn->i_cnd == ZIPC_ALWAYS)) {
1937
+                       pzipm->r[insn->i_areg].m_known = MACH_VSYMKNOWN;
1938
+                       pzipm->r[insn->i_areg].m_value = insn->i_imm;
1939
+                       pzipm->r[insn->i_areg].m_addsy = insn->i_rp->r_sym;
1940
+                       pzipm->r[insn->i_areg].m_subsy = NULL;
1941
+                       return;
1942
+               } else if ((insn->i_breg == ZIP_PC)&&(insn->i_op == ZIPO_MOV)
1943
+                               &&(insn->i_cnd == ZIPC_ALWAYS)) {
1944
+                       pzipm->r[insn->i_areg].m_known = MACH_VSYMKNOWN;
1945
+                       pzipm->r[insn->i_areg].m_value = insn->i_imm;
1946
+                       pzipm->r[insn->i_areg].m_addsy = insn->i_rp->r_sym;
1947
+                       pzipm->r[insn->i_areg].m_subsy = NULL;
1948
+                       return;
1949
+               }
1950
+       } else if (insn->i_rp) {
1951
+               bknown = MACH_VUNKNOWN;
1952
+       } else if (ZIP_RNONE == insn->i_breg)
1953
+               // B-Op is an immediate only
1954
+               bknown = MACH_VKNOWN;
1955
+       else if (insn->i_breg >= ZIP_CC)
1956
+               bknown = MACH_VUNKNOWN;
1957
+       else if (insn->i_imm == 0)
1958
+               bknown = (pzipm->r[insn->i_breg].m_known);
1959
+       else // If we have an immediate plus a value, can't know UPPER anymore
1960
+               bknown = (pzipm->r[insn->i_breg].m_known == MACH_VKNOWN)
1961
+                                       ? MACH_VKNOWN : MACH_VUNKNOWN;
1962
+
1963
+       if (insn->i_breg < ZIP_USER_REGS)
1964
+               bval += pzipm->r[insn->i_breg].m_value;
1965
+
1966
+       if (insn->i_areg >= ZIP_USER_REGS) {
1967
+#ifdef ZIP_DEBUG
1968
+               fprintf(stderr, "MACHINE, A-REG[%02x] out of bounds\n", insn->i_areg);
1969
+#endif
1970
+               return; // Nothing to do -- no change to machine
1971
+       } else if (insn->i_areg == ZIP_PC) {
1972
+#ifdef ZIP_DEBUG
1973
+               fprintf(stderr, "MACHINE, CLEAR ON JUMP\n");
1974
+#endif
1975
+               zip_clear_machine(pzipm);
1976
+               return;
1977
+       } else if ((insn->i_areg == ZIP_CC)&&(insn->i_op == ZIPO_AND)) {
1978
+#ifdef ZIP_DEBUG
1979
+               fprintf(stderr, "MACHINE, CLEAR ON ANDing to CC\n");
1980
+#endif
1981
+               zip_clear_machine(pzipm);
1982
+       } else if ((insn->i_areg == ZIP_CC)&&(
1983
+                       (insn->i_op == ZIPO_LDI)
1984
+                       ||(insn->i_op == ZIPO_LW)
1985
+                       ||(insn->i_op == ZIPO_CLR)
1986
+                       ||(insn->i_op == ZIPO_LDILO))) {
1987
+#ifdef ZIP_DEBUG
1988
+               fprintf(stderr, "MACHINE, CLEAR ON setting CC\n");
1989
+#endif
1990
+               zip_clear_machine(pzipm);
1991
+               return;
1992
+       } else if (insn->i_areg >= ZIP_CC) {
1993
+#ifdef ZIP_DEBUG
1994
+               fprintf(stderr, "MACHINE, Not tracking CC or PC changes\n");
1995
+#endif
1996
+               pzipm->r[insn->i_areg].m_known = MACH_VUNKNOWN;
1997
+               return;
1998
+       }
1999
+
2000
+       av = &pzipm->r[insn->i_areg];
2001
+       if (insn->i_breg < ZIP_CC)
2002
+               bv = &pzipm->r[insn->i_breg];
2003
+       else
2004
+               bv = NULL;
2005
+
2006
+       if (ZIPC_ALWAYS != insn->i_cnd) {
2007
+#ifdef ZIP_DEBUG
2008
+               fprintf(stderr, "MACHINE, CONDITIONAL\n");
2009
+#endif
2010
+               if ((ZIPO_LDILO == insn->i_op)
2011
+                               &&((av->m_known == MACH_VKNOWN)
2012
+                                       ||(av->m_known == MACH_VUPPERKNOWN)))
2013
+                       av->m_known = MACH_VUPPERKNOWN;
2014
+               else if ((ZIPO_LDI == insn->i_op)||(ZIPO_LDIn == insn->i_op))
2015
+                       ; // We'll catch this in a moment
2016
+               else
2017
+                       av->m_known = MACH_VUNKNOWN;
2018
+       } switch(insn->i_op) {
2019
+               case    ZIPO_SUB:
2020
+                       av->m_known = (av->m_known==MACH_VKNOWN)
2021
+                                       ? MACH_VKNOWN:MACH_VUNKNOWN;
2022
+                       av->m_value -= bval;
2023
+                       if (bknown != MACH_VKNOWN)
2024
+                               av->m_known = MACH_VUNKNOWN;
2025
+                       break;
2026
+               case    ZIPO_AND:
2027
+                       av->m_value &= bval;
2028
+                       if ((bknown == MACH_VUPPERKNOWN)&&(bval == 0)) {
2029
+                               if (av->m_known == MACH_VKNOWN)
2030
+                                       av->m_known = MACH_VUPPERKNOWN;
2031
+                               else if (av->m_known != MACH_VUPPERKNOWN)
2032
+                                       av->m_known = MACH_VUNKNOWN;
2033
+                       } else if (bknown != MACH_VKNOWN)
2034
+                               av->m_known = MACH_VUNKNOWN;
2035
+                       break;
2036
+               case    ZIPO_ADD:
2037
+                       av->m_value += bval;
2038
+                       if (bknown != MACH_VKNOWN)
2039
+                               av->m_known = MACH_VUNKNOWN;
2040
+                       break;
2041
+               case    ZIPO_OR:
2042
+                       av->m_value |= bval;
2043
+                       if (bknown == MACH_VUPPERKNOWN) {
2044
+                               if (av->m_known == MACH_VKNOWN)
2045
+                                       av->m_known = MACH_VUPPERKNOWN;
2046
+                               else if (av->m_known != MACH_VUPPERKNOWN)
2047
+                                       av->m_known = MACH_VUNKNOWN;
2048
+                       } else if (bknown != MACH_VKNOWN)
2049
+                               av->m_known = MACH_VUNKNOWN;
2050
+                       break;
2051
+               case    ZIPO_XOR:
2052
+                       av->m_value ^= bval;
2053
+                       if (bknown == MACH_VUPPERKNOWN) {
2054
+                               if (av->m_known == MACH_VKNOWN)
2055
+                                       av->m_known = MACH_VUPPERKNOWN;
2056
+                               else if (av->m_known != MACH_VUPPERKNOWN)
2057
+                                       av->m_known = MACH_VUNKNOWN;
2058
+                       } else if (bknown != MACH_VKNOWN)
2059
+                               av->m_known = MACH_VUNKNOWN;
2060
+                       break;
2061
+               case    ZIPO_LDI: case ZIPO_LDIn:
2062
+                       // Although the h/w instruction has no conditions, our
2063
+                       // decoding may have conditions until we finish
2064
+                       // working out what the actual result is.  Hence, we
2065
+                       // need to be aware of any conditions from above.
2066
+#ifdef ZIP_DEBUG
2067
+                       fprintf(stderr, "MACHINE, LDI -> %02x\n", insn->i_areg);
2068
+#endif
2069
+                       av->m_value = bval;
2070
+                       if (insn->i_cnd != ZIPC_ALWAYS) {
2071
+                               // if ((bknown)&&(bvalue == insn->i_imm))
2072
+                                       // pzipm->r[insn->i_areg].m_known = MACH_VKNOWN;
2073
+                       } else {
2074
+                               av->m_known = MACH_VKNOWN;
2075
+                       } break;
2076
+               case    ZIPO_LDILO:
2077
+#ifdef ZIP_DEBUG
2078
+                       fprintf(stderr, "MACHINE, LDILO -> %02x\n", insn->i_areg);
2079
+#endif
2080
+                       av->m_value &= ~0x0ffff;
2081
+                       av->m_value |= bval &0x0ffff;
2082
+                       if ((av->m_known == MACH_VUPPERKNOWN)
2083
+                                       &&(bknown == MACH_VKNOWN)
2084
+                                       &&(ZIPC_ALWAYS == insn->i_cnd))
2085
+                               av->m_known = MACH_VKNOWN;
2086
+                       break;
2087
+               case    ZIPO_BREV:
2088
+                       av->m_value = zip_brev(bval);
2089
+                       if (ZIPC_ALWAYS == insn->i_cnd)
2090
+                               av->m_known = (bknown == MACH_VKNOWN)?MACH_VKNOWN:MACH_VUNKNOWN;
2091
+                       else if ((bknown == MACH_VKNOWN)
2092
+                               &&(  (av->m_known == MACH_VKNOWN)
2093
+                                  ||(av->m_known == MACH_VUPPERKNOWN))
2094
+                               &&((((zip_brev(bval)^av->m_value)&0x0ffff)==0)))
2095
+                               av->m_known = MACH_VUPPERKNOWN;
2096
+                       break;
2097
+               case    ZIPO_MOV:
2098
+#ifdef ZIP_DEBUG
2099
+                       fprintf(stderr, "MACHINE, MOV -> %02x\n", insn->i_areg);
2100
+#endif
2101
+                       av->m_value = bval;
2102
+                       if (ZIPC_ALWAYS == insn->i_cnd) {
2103
+                               av->m_known = bknown;
2104
+                               if (bknown == MACH_VSYMKNOWN) {
2105
+                                       if (!bv) { av->m_known = MACH_VUNKNOWN;}
2106
+                                       else {
2107
+                                       av->m_value = bv->m_value + insn->i_imm;
2108
+                                       av->m_addsy = bv->m_addsy;
2109
+                                       av->m_subsy = bv->m_subsy;
2110
+                                       }
2111
+                               }
2112
+                       } else if (
2113
+                               ((av->m_known == MACH_VKNOWN)
2114
+                                 ||(av->m_known == MACH_VUPPERKNOWN))
2115
+                               &&((bknown == MACH_VKNOWN)
2116
+                                 ||(bknown == MACH_VUPPERKNOWN))
2117
+                               &&(((bval^av->m_value)&0xffff0000)==0))
2118
+                               av->m_known = MACH_VUPPERKNOWN;
2119
+                       else
2120
+                               av->m_known = MACH_VUNKNOWN;
2121
+                       av->m_value = bval;
2122
+                       break;
2123
+               case    ZIPO_CLR:
2124
+                       if (insn->i_cnd == ZIPC_ALWAYS)
2125
+                               av->m_known = MACH_VKNOWN;
2126
+                       else if ((av->m_value & 0xffff0000)==0) {
2127
+                               if (((av->m_known == MACH_VKNOWN)
2128
+                                       ||(av->m_known == MACH_VUPPERKNOWN))
2129
+                                       &&(((av->m_value ^ bval)&0xffff0000)==0))
2130
+                                       av->m_known = MACH_VUPPERKNOWN;
2131
+                               else
2132
+                                       av->m_known = MACH_VUNKNOWN;
2133
+                       } av->m_value = 0;
2134
+                       break;
2135
+               // Store's don't change any regs
2136
+               case    ZIPO_SW: case ZIPO_SH: case ZIPO_SB:
2137
+               case    ZIPO_SIM: case ZIPO_NOOP:
2138
+               case    ZIPO_SDUMP: case ZIPO_NDUMP:
2139
+               case    ZIPO_BREAK: case ZIPO_LOCK:
2140
+               case    ZIPO_CMP:  case ZIPO_TST:
2141
+                       // These don't change any registers
2142
+                       break;
2143
+               // Result of loading a byte or halfword always clears the upper
2144
+               // half word
2145
+               case    ZIPO_LB: case   ZIPO_LH:
2146
+                       if (insn->i_cnd == ZIPC_ALWAYS) {
2147
+                               av->m_known = MACH_VUPPERKNOWN;
2148
+                               av->m_value = 0;
2149
+                       } else
2150
+                               av->m_known = MACH_VUNKNOWN;
2151
+                       break;
2152
+               case    ZIPO_LW:
2153
+               default:
2154
+#ifdef ZIP_DEBUG
2155
+                       fprintf(stderr, "MACHINE, DEFAULT, %02x -> unknown\n", insn->i_areg);
2156
+#endif
2157
+                       av->m_known = MACH_VUNKNOWN;
2158
+                       break;
2159
+       }
2160
+
2161
+       pzipm->r[ZIP_CC].m_known = MACH_VUNKNOWN;
2162
+       pzipm->r[ZIP_PC].m_known = MACH_VUNKNOWN;
2163
+}
2164
+
2165
+#ifdef ZIP_DEBUG
2166
+static void
2167
+zip_debug_machine(MACHINEREGS *pzipm) {
2168
+       int     i;
2169
+       for(i=0; i<ZIP_USER_REGS; i++) {
2170
+               if (pzipm->r[i].m_known == MACH_VKNOWN)
2171
+                       fprintf(stderr, "MACH-KNOW[Y][%2x] = %08x\n",
2172
+                               i, pzipm->r[i].m_value);
2173
+               else if (pzipm->r[i].m_known == MACH_VUPPERKNOWN)
2174
+                       fprintf(stderr, "MACH-KNOW[U][%2x] = %04x\n",
2175
+                               i, (pzipm->r[i].m_value>>16)&0x0ffff);
2176
+       }
2177
+}
2178
+#endif
2179
+
2180
+
2181
+/*
2182
+ * Option processing
2183
+ *
2184
+ * While not yet implemented, we do have a need for multiple options.  These
2185
+ * include:
2186
+ *
2187
+ *     (not yet supported)
2188
+ *     -got    Use a global offset table to place unknown jump locations into.
2189
+ *
2190
+ *     (not yet supported)
2191
+ *     -relax  Implement only relaxed instructions.  This implies that all
2192
+ *             branches fit within 18-bits of the current PC, or equivalently
2193
+ *             that all of the code fits within 1MB.
2194
+ *
2195
+ *     (not yet supported)
2196
+ *     -no-relax       Don't relax any instructions.  That means that all
2197
+ *             branches will be implemented as LOD (PC),PC ; .int #Address
2198
+ *             and all conditional branches as LOD 1(PC),PC; BRA 1; .int #addr.
2199
+ *             This also implies LDI's of unknown values will always be
2200
+ *             converted to LDILO/LDIHI pairs and never converted back to
2201
+ *             LDI's--even when the final value is known.
2202
+ *
2203
+ *     -cis    Attempt to compress instructions into the CIS instruction
2204
+ *             set.
2205
+ *
2206
+ *     (Something for stating the starting address of the routine in memory...)
2207
+ *
2208
+ *     Other (not yet supported) long options
2209
+ *
2210
+ *     -nopipe Attempts to use a lock instruction will result in an error.
2211
+ *     -nomul  Attempts to use multiply instructions will result in an error.
2212
+ *     -nodiv  Attempts to use divide instructions will result in an error.
2213
+ *     -nofpu  Attempts to use floating point unit insn will cause an error.
2214
+ *
2215
+ *
2216
+ */
2217
+#define        OPTION_CIS      (OPTION_MD_BASE+1)
2218
+#define        OPTION_NOCIS    (OPTION_MD_BASE+2)
2219
+#define        OPTION_ZIPM     (OPTION_MD_BASE+3)
2220
+#define        OPTION_NOZIPM   (OPTION_MD_BASE+4)
2221
+#define        OPTION_GOT      (OPTION_MD_BASE+5)
2222
+#define        OPTION_SMALL    (OPTION_MD_BASE+6)      // No LW(PC),PC insns
2223
+
2224
+const char     *md_shortopts = "";
2225
+struct option  md_longopts[] =
2226
+{
2227
+       { "cis",   no_argument, NULL, OPTION_CIS },
2228
+       { "nocis", no_argument, NULL, OPTION_NOCIS },
2229
+       { "zipm",   no_argument, NULL, OPTION_ZIPM },
2230
+       { "nozipm", no_argument, NULL, OPTION_NOZIPM },
2231
+       { "small",  no_argument, NULL, OPTION_SMALL },
2232
+       // { "got",  no_argument, NULL, OPTION_GOT },
2233
+       { NULL, no_argument, NULL, 0}
2234
+};
2235
+size_t md_longopts_size = sizeof(md_longopts);
2236
+
2237
+/* We have no target specific options yet, so these next two fucntions are
2238
+ * are empty.
2239
+ */
2240
+int
2241
+md_parse_option(int c, const char *arg ATTRIBUTE_UNUSED)
2242
+{
2243
+       // printf("Option %d, %s\n", c, (arg)?arg : "(Null)");
2244
+       if (c==0)
2245
+               return 1;
2246
+       switch(c) {
2247
+               case 0: return 1;
2248
+               case OPTION_CIS:   zip_param_cis = 1; return 1; break;
2249
+               case OPTION_NOCIS: zip_param_cis = 0; return 1; break;
2250
+               case OPTION_ZIPM:   zip_param_use_machine = 1; return 1; break;
2251
+               case OPTION_NOZIPM: zip_param_use_machine = 0; return 1; break;
2252
+               // case OPTION_GOT : zip_param_got  = 1; return 1; break;
2253
+               default: break;
2254
+       }
2255
+       return 0; // We didn't handle this option
2256
+}
2257
+
2258
+void
2259
+md_show_usage(FILE *stream ATTRIBUTE_UNUSED)
2260
+{
2261
+       fprintf(stream, _("Zip CPU options:\n"));
2262
+       fprintf(stream, _("\n"
2263
+"-cis\t\tAttempt to compress instructions into two instructions per word.\n"));
2264
+       //fprintf(stream, _(
2265
+// "-got\t\tGenerate position independent code by referencing all symbols\n"
2266
+// "\t\tthrough a Global Offset Table.\n"));
2267
+}
2268
+
2269
+
2270
+symbolS *
2271
+md_undefined_symbol(char *name ATTRIBUTE_UNUSED)
2272
+{
2273
+//#warning "This is where other architectures check for any GOT references"
2274
+       return NULL;
2275
+}
2276
+
2277
+void
2278
+md_operand(expressionS *op ATTRIBUTE_UNUSED)
2279
+{
2280
+       /* Empty for now -- what is this for? */
2281
+}
2282
+
2283
+#ifdef ZIP_DEBUG
2284
+static void
2285
+zip_dump_sym(symbolS *sym)
2286
+{
2287
+       if (!sym) {
2288
+               fprintf(stderr, "SYM(NULL)");
2289
+       } else {
2290
+               fprintf(stderr, "Dumping symbol fields\n");
2291
+               fprintf(stderr, "SYM(%s) %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s - 0x%08x\n",
2292
+                       S_GET_NAME(sym),
2293
+                       (S_IS_LOCAL(sym))?"Local ":"",
2294
+                       (S_IS_DEFINED(sym))?"Defined ":"",
2295
+                       (S_IS_EXTERNAL(sym))?"extern ":"",
2296
+                       (S_IS_FUNCTION(sym))?"(func) ":"",
2297
+                       (S_IS_WEAK(sym))?"Weak ":"",
2298
+                       (S_IS_WEAKREFD(sym))?"(Weak Ref-D) ":"",
2299
+                       (S_IS_WEAKREFR(sym))?"(Weak Refr) ":"",
2300
+                       (S_IS_DEBUG(sym))?"DEBUG ":"",
2301
+                       (S_IS_VOLATILE(sym))?"Volatile ":"",
2302
+                       (S_IS_FORWARD_REF(sym))?"Fwd Ref ":"",
2303
+                       (S_IS_COMMON(sym))?"Common ":"",
2304
+                       (S_GET_SEGMENT(sym)==absolute_section)?"AbsoluteS ":"",
2305
+                       (S_GET_SEGMENT(sym)==expr_section)?"ExpressionS ":"",
2306
+                       (S_GET_SEGMENT(sym)==reg_section)?"RegisterS ":"",
2307
+                       (S_GET_SEGMENT(sym)==undefined_section)?"UndefinedS ":"",
2308
+                       (symbol_resolved_p(sym))?"Resolved ":"",
2309
+                       (unsigned)S_GET_VALUE(sym));
2310
+       }
2311
+}
2312
+
2313
+static void
2314
+zip_dump_insn(ZIPIS *insn) {
2315
+       fprintf(stderr, "INSN:DUMP ");
2316
+       switch(insn->i_op) {
2317
+               case ZIPO_SUB:   fprintf(stderr, "%7s", "SUB"); break;
2318
+               case ZIPO_AND:   fprintf(stderr, "%7s", "AND"); break;
2319
+               case ZIPO_ADD:   fprintf(stderr, "%7s", "ADD"); break;
2320
+               case ZIPO_OR:    fprintf(stderr, "%7s", "OR"); break;
2321
+               case ZIPO_XOR:   fprintf(stderr, "%7s", "XOR"); break;
2322
+               case ZIPO_LSR:   fprintf(stderr, "%7s", "LSR"); break;
2323
+               case ZIPO_LSL:   fprintf(stderr, "%7s", "LSL"); break;
2324
+               case ZIPO_ASR:   fprintf(stderr, "%7s", "ASR"); break;
2325
+               case ZIPO_LDI:   fprintf(stderr, "%7s", "LDI"); break;
2326
+               case ZIPO_MPYUHI:fprintf(stderr, "%7s", "MPYUHI");break;
2327
+               case ZIPO_MPYSHI:fprintf(stderr, "%7s", "MPYSHI");break;
2328
+               case ZIPO_LDILO: fprintf(stderr, "%7s", "LDILO"); break;
2329
+               case ZIPO_BREV:  fprintf(stderr, "%7s", "BREV");  break;
2330
+               case ZIPO_MOV:   fprintf(stderr, "%7s", "MOV");   break;
2331
+               case ZIPO_CMP:   fprintf(stderr, "%7s", "CMP");   break;
2332
+               case ZIPO_TST:   fprintf(stderr, "%7s", "TST");   break;
2333
+               case ZIPO_LW:    fprintf(stderr, "%7s", "LW");    break;
2334
+               case ZIPO_SW:    fprintf(stderr, "%7s", "SW");    break;
2335
+               case ZIPO_LH:    fprintf(stderr, "%7s", "LH");    break;
2336
+               case ZIPO_SH:    fprintf(stderr, "%7s", "SH");    break;
2337
+               case ZIPO_LB:    fprintf(stderr, "%7s", "LB");    break;
2338
+               case ZIPO_SB:    fprintf(stderr, "%7s", "SB");    break;
2339
+               case ZIPO_DIVU:  fprintf(stderr, "%7s", "DIVU");  break;
2340
+               case ZIPO_DIVS:  fprintf(stderr, "%7s", "DIVS");  break;
2341
+               case ZIPO_FPADD: fprintf(stderr, "%7s", "FPADD"); break;
2342
+               case ZIPO_FPSUB: fprintf(stderr, "%7s", "FPSUB"); break;
2343
+               //
2344
+               case ZIPO_NOOP:  fprintf(stderr, "%7s", "NOOP");  break;
2345
+               case ZIPO_BREAK: fprintf(stderr, "%7s", "BREAK"); break;
2346
+               case ZIPO_LOCK:  fprintf(stderr, "%7s", "LOCK");  break;
2347
+               case ZIPO_TRAP:  fprintf(stderr, "%7s", "TRAP");  break;
2348
+               case ZIPO_CLR:   fprintf(stderr, "%7s", "CLR");   break;
2349
+               case ZIPO_HALT:  fprintf(stderr, "%7s", "HALT");  break;
2350
+               case ZIPO_WAIT:  fprintf(stderr, "%7s", "WAIT");  break;
2351
+               case ZIPO_STEP:  fprintf(stderr, "%7s", "STEP");  break;
2352
+               case ZIPO_RTU:   fprintf(stderr, "%7s", "RTU");   break;
2353
+               case ZIPO_BRA:   fprintf(stderr, "%7s", "BRA");   break;
2354
+               case ZIPO_BUSY:  fprintf(stderr, "%7s", "BUSY");  break;
2355
+               case ZIPO_JMP:   fprintf(stderr, "%7s", "JMP");   break;
2356
+               case ZIPO_NOT:   fprintf(stderr, "%7s", "NOT");   break;
2357
+               case ZIPO_NEG:   fprintf(stderr, "%7s", "NEG");   break;
2358
+               //
2359
+               case ZIPO_SIM:   fprintf(stderr, "%7s", "SIM");   break;
2360
+               case ZIPO_SDUMP: fprintf(stderr, "%7s", "SDUMP"); break;
2361
+               case ZIPO_SEXIT: fprintf(stderr, "%7s", "SEXIT"); break;
2362
+               case ZIPO_SOUT:  fprintf(stderr, "%7s", "SOUT");  break;
2363
+               case ZIPO_NDUMP: fprintf(stderr, "%7s", "NDUMP"); break;
2364
+               case ZIPO_NEXIT: fprintf(stderr, "%7s", "NEXIT"); break;
2365
+               case ZIPO_NOUT:  fprintf(stderr, "%7s", "OUT");   break;
2366
+               //
2367
+               case ZIPO_LJMP: fprintf(stderr, "%7s", "LJMP"); break;
2368
+               case ZIPO_LJSR: fprintf(stderr, "%7s", "LJSR");   break;
2369
+               //
2370
+               case ZIPO_SEXTH:fprintf(stderr, "%7s", "SEXTH");   break;
2371
+               case ZIPO_SEXTB:fprintf(stderr, "%7s", "SEXTB");   break;
2372
+               default:
2373
+                       fprintf(stderr, "%d", insn->i_op); break;
2374
+       }
2375
+       switch(insn->i_cnd) {
2376
+               case ZIPC_Z: fprintf(stderr, "%-3s", ".Z"); break;
2377
+               case ZIPC_LT: fprintf(stderr, "%-3s", ".LT"); break;
2378
+               case ZIPC_C: fprintf(stderr, "%-3s", ".C"); break;
2379
+               case ZIPC_V: fprintf(stderr, "%-3s", ".V"); break;
2380
+               case ZIPC_NZ: fprintf(stderr, "%-3s", ".NE"); break;
2381
+               case ZIPC_GE: fprintf(stderr, "%-3s", ".GE"); break;
2382
+               case ZIPC_NC: fprintf(stderr, "%-3s", ".NC"); break;
2383
+               case ZIPC_ALWAYS:
2384
+               default:
2385
+                       break;
2386
+       } fprintf(stderr, " %d", (int)insn->i_cnd);
2387
+
2388
+       fprintf(stderr, "\n\tAREG = %d\n\tB = ", insn->i_areg);
2389
+       if (insn->i_rp) {
2390
+               if (insn->i_imm != 0)
2391
+                       fprintf(stderr, "$%d + ", insn->i_imm);
2392
+               fprintf(stderr, "%s ", (insn->i_rp->r_sym) ?
2393
+                       S_GET_NAME(insn->i_rp->r_sym) : "(null)");
2394
+       } else
2395
+               fprintf(stderr, "%d[%08x] (no sym)", insn->i_imm, insn->i_imm);
2396
+       if (insn->i_breg != ZIP_RNONE)
2397
+               fprintf(stderr, "+ R%d", insn->i_breg);
2398
+       fprintf(stderr, "\n");
2399
+       if (insn->i_rp)
2400
+               fprintf(stderr, "\t@%ld (offset w/in instruction frag)\n", insn->i_rp->r_fr_offset);
2401
+       fprintf(stderr, "\tINSN:CODE %08x", insn->i_code);
2402
+       {
2403
+               int     i;
2404
+               for(i=0; (i<insn->i_naux)&&(i<ZIP_MAX_NAUX); i++)
2405
+                       fprintf(stderr, ":%08x", insn->i_aux[i]);
2406
+       }
2407
+       fprintf(stderr, "\n\tDUMPED\n");
2408
+}
2409
+#endif
2410
+
2411
+static ZIP_CONDITION
2412
+zip_negate_condition(ZIP_CONDITION c) {
2413
+       switch(c) {
2414
+               case ZIPC_Z:    return ZIPC_NZ; break;
2415
+               case ZIPC_LT:   return ZIPC_GE; break;
2416
+               case ZIPC_C:    return ZIPC_NC; break;
2417
+               case ZIPC_NZ:   return ZIPC_Z; break;
2418
+               case ZIPC_GE:   return ZIPC_LT; break;
2419
+               case ZIPC_NC:   return ZIPC_C; break;
2420
+               case ZIPC_ALWAYS:       return ZIPC_ALWAYS; break;
2421
+               default:
2422
+                       break;
2423
+       } gas_assert((0)&&("Cannot negate condition\n"));
2424
+       return ZIPC_ALWAYS;
2425
+}
2426
+
2427
+static const char *zip_skip_white_spaces(const char *str) {
2428
+       if (!str)
2429
+               return NULL;
2430
+       while((*str)&&(isspace(*str)))
2431
+               str++;
2432
+       return str;
2433
+}
2434
+
2435
+static const char *
2436
+zip_parse_condition(const char *str, ZIP_CONDITION *condn) {
2437
+       if ((strcasecmp(str, "Z")==0)
2438
+                       ||(strcasecmp(str, "EQ")==0)) {
2439
+               *condn = ZIPC_Z;
2440
+       } else if ((strcasecmp(str, "LT")==0)
2441
+                       ||(strcasecmp(str, "N")==0)) {
2442
+               *condn = ZIPC_LT;
2443
+       } else if ((strcasecmp(str, "C")==0)
2444
+                       ||(strcasecmp(str, "LTU")==0)) {
2445
+               *condn = ZIPC_C;
2446
+       } else if (strcasecmp(str, "V")==0) {
2447
+               *condn = ZIPC_V;
2448
+       } else if((strcasecmp(str, "NZ")==0)
2449
+                       ||(strcasecmp(str, "NE")==0)) {
2450
+               *condn = ZIPC_NZ;
2451
+       } else if ((strcasecmp(str, "GE")==0)
2452
+                       ||(strcasecmp(str, "GTE")==0)) {
2453
+               *condn = ZIPC_GE;
2454
+       } else if ((strcasecmp(str, "NC")==0)
2455
+                       ||(strcasecmp(str, "GEU")==0)) {
2456
+               *condn = ZIPC_NC;
2457
+       } else {
2458
+               return "Unrecognized condition";
2459
+       }
2460
+
2461
+       return NULL;
2462
+}
2463
+
2464
+static const char *zip_parse_reg(const char *str, ZIP_REG *regid) {
2465
+       const char *ustr = str;
2466
+       int     userreg = 0;
2467
+
2468
+       ustr = zip_skip_white_spaces(str);
2469
+
2470
+       if (toupper(ustr[0]) == 'U') {
2471
+               ustr = str+1;
2472
+               userreg = 0x10;
2473
+       } else if ((toupper(ustr[0]) == 'S')&&(strcasecmp(ustr, "SP")!=0)) {
2474
+               ustr = str+1;
2475
+       }
2476
+
2477
+       /*
2478
+       if (strcasecmp(ustr, "GBL")==0) {
2479
+               *regid = userreg + 11;
2480
+               ustr += 3;
2481
+       } else
2482
+       */
2483
+       if (strcasecmp(ustr, "LR")==0) {
2484
+               *regid = userreg + 0;
2485
+               ustr += 2;
2486
+       } else if (strcasecmp(ustr, "FP")==0) {
2487
+               *regid = userreg + 12;
2488
+               ustr += 2;
2489
+       } else if (strcasecmp(ustr, "SP")==0) {
2490
+               *regid = userreg + 13;
2491
+               ustr += 2;
2492
+       } else if (strcasecmp(ustr, "CC")==0) {
2493
+               *regid = userreg + 14;
2494
+               ustr += 2;
2495
+       } else if (strcasecmp(ustr, "PC")==0) {
2496
+               *regid = userreg + 15;
2497
+               ustr += 2;
2498
+       } else if (('r' == tolower(ustr[0]))
2499
+                       &&(isdigit(ustr[1]))
2500
+                       &&((!isdigit(ustr[2]))
2501
+                               ||(!isdigit(ustr[3])))) {
2502
+               *regid = atoi(ustr+1);
2503
+               if ((*regid > 15)||(*regid < 0))
2504
+                       return "Register does not exist";
2505
+               *regid += userreg;
2506
+
2507
+               if (!isdigit(ustr[2]))
2508
+                       ustr+=2;
2509
+               else
2510
+                       ustr+=3;
2511
+       } else {
2512
+               *regid = ZIP_RNONE;
2513
+               return "Unknown register";
2514
+       }
2515
+
2516
+       // Registers names are terminated by something other than letters
2517
+       // and numbers.  Things like ')', ',', or '\0' should terminate a
2518
+       // register.  Here, we only double check that the register is not
2519
+       // terminated by another letter or a number.
2520
+       if ((*ustr)&&((isalpha(*ustr))||(isdigit(*ustr))))
2521
+               return "Unrecognized register";
2522
+
2523
+       return NULL;
2524
+}
2525
+
2526
+// Parse a 'B' operand
2527
+static const char *
2528
+zip_parse_bop(const char *bop, ZIPIS *insn) {
2529
+       // There are a couple forms for what we can expect in a B operand:
2530
+       //      The first three require no relocations ...
2531
+       //              1. A simple number
2532
+       //              2. Number + Register
2533
+       //              3. Number(Register)
2534
+       //              4. Register by itself
2535
+       //              Good form is to replace this number with the possibility
2536
+       //              of a constant expression ...  The number may be any of
2537
+       //              [+-](0[xX][0-9a-fA-F]+|(0[0-7]+)|(0-9)+)
2538
+       //      The next four may require a relocation
2539
+       //              4. Label + Register
2540
+       //              5. Label(Register)
2541
+       //              6. Label (Register is implied: PC, if moving or jumping
2542
+       //                      to the PC, or GBL if loading a value or if
2543
+       //                      the offset ends up being unknown)
2544
+       //              Good form allows an expression instead of a label,
2545
+       //              that can be evaluated at ... sometime.
2546
+       //              7. Number(Label)
2547
+       //
2548
+       // We will support:
2549
+       //      (Number|Label)?( "("Register")" | "+"Register )
2550
+       //
2551
+       char    lbl[512], *lblp = lbl;
2552
+       const char      *ptr;
2553
+       insn->i_imm = 0;
2554
+       *lblp = '\0';
2555
+
2556
+       if (strlen(bop)>sizeof(lbl)-1)
2557
+               as_fatal( _("Label length too long"));
2558
+       // printf("RAW-OP-B: %s %s\n", bop, (insn->i_rp)?"(i_rp != NULL)":"");
2559
+
2560
+       // Do we start with a number?
2561
+       {
2562
+               int     sgn = 0;
2563
+
2564
+               ptr = zip_skip_white_spaces(bop);
2565
+               if ('$' == *ptr)
2566
+                       ptr = zip_skip_white_spaces(ptr+1);
2567
+
2568
+               if ('+' == *ptr)
2569
+                       ptr++;
2570
+               else if ('-' == *ptr) {
2571
+                       sgn = 1;
2572
+                       ptr++;
2573
+               }
2574
+
2575
+               if ('$' == *ptr)
2576
+                       ptr = zip_skip_white_spaces(ptr+1);
2577
+               ptr = zip_skip_white_spaces(ptr);
2578
+               if ('$' == *ptr)
2579
+                       ptr = zip_skip_white_spaces(ptr+1);
2580
+
2581
+               if ((*ptr)&&(isdigit(*ptr))) {
2582
+                       char *end = (char *)ptr;
2583
+                       unsigned long v = strtoul(ptr, &end, 0);
2584
+                       // We start with a number
2585
+                       if (sgn)
2586
+                               insn->i_imm = (int)(-v);
2587
+                       else
2588
+                               insn->i_imm = (int)(v);
2589
+                       ptr = (const char *)end;
2590
+
2591
+                       // Permit a string of Num [[+-] Num]*
2592
+                       // This is necessary for the DI instructions within the
2593
+                       // compiler.
2594
+                       while( ((*ptr == '+')||(*ptr == '-'))
2595
+                               &&(isdigit(ptr[1])) ) {
2596
+                               sgn = (*ptr == '-');
2597
+                               v = strtoul(&ptr[1], &end, 0);
2598
+                               if (sgn) v = -v;
2599
+                               insn->i_imm += (int)v;
2600
+                               ptr = (const char *)end;
2601
+                       }
2602
+               } else if ((*ptr)&&(
2603
+                               (isalpha(*ptr))
2604
+                               ||('*'==*ptr)
2605
+                               ||('.'==*ptr)
2606
+                               ||('_'==*ptr))) {
2607
+                       // We start with an identifier
2608
+                       // printf("OP-B ( \'%s\' ) starts with an identifier (%c)\n",
2609
+                               // bop, *ptr);
2610
+
2611
+                       // Skip any compiler inserted prefix (if present)
2612
+                       if ('*' == *ptr)
2613
+                               ptr++;
2614
+                       while((*ptr)&&(
2615
+                                       (isalpha(*ptr))
2616
+                                       ||(isdigit(*ptr))
2617
+                                       ||('_' == *ptr)
2618
+                                       ||('$' == *ptr)
2619
+                                       ||('.' == *ptr)))
2620
+                               *lblp++ = *ptr++;
2621
+                       *lblp = '\0';
2622
+                       // printf("LBL was %s\n", lbl);
2623
+
2624
+                       // This could still be a register ... can't tell yet
2625
+                       if (sgn)
2626
+                               return "ERR: Not expecting a signed label!";
2627
+
2628
+                       ptr = zip_skip_white_spaces(ptr);
2629
+               }
2630
+       }
2631
+
2632
+       ptr = zip_skip_white_spaces(ptr);
2633
+
2634
+       const   char *err = NULL;
2635
+
2636
+       if ((*ptr == '+')&&(ptr[1] == '('))
2637
+               ptr++;
2638
+       if ((*ptr)&&(*ptr == '(')) {
2639
+               // Form #3: Number(register)
2640
+               char *end = strchr(ptr+1, ')');
2641
+               if (NULL == end)
2642
+                       return "Un-matched \'(\', cannot find \')\'";
2643
+               *end = '\0';
2644
+               // printf("Looking for a register in %s\n", ptr+1);
2645
+               err = zip_parse_reg(ptr+1, &insn->i_breg);
2646
+               if (err) {
2647
+                       // Must've been a symbol
2648
+                       if (lbl[0] != '\0') // Already have a symbol in this
2649
+                               return err;     // expression!
2650
+                       ptr++;
2651
+                       while((*ptr)&&(
2652
+                                       (isalpha(*ptr))
2653
+                                       ||(isdigit(*ptr))
2654
+                                       ||('_' == *ptr)
2655
+                                       ||('$' == *ptr)
2656
+                                       ||('.' == *ptr)))
2657
+                               *lblp++ = *ptr++;
2658
+                       *lblp = '\0';
2659
+                       insn->i_breg = ZIP_RNONE;
2660
+                       ptr = zip_skip_white_spaces(ptr);
2661
+                       if (*ptr != '\0')
2662
+                               return "ERR: Expression within parenthesis not supported";
2663
+                       err = NULL;
2664
+               }
2665
+               // printf("Found a register, %s -> %d\n", ptr+1, insn->i_breg);
2666
+       } else if ((*ptr)&&((*ptr == '+')||(*ptr == '-'))) {
2667
+               if ((*lbl)&&(zip_parse_reg(lbl, &insn->i_breg) == NULL)) {
2668
+                       // Register+Number
2669
+                       // Skip to the end to process what follows
2670
+                       *lbl = '\0'; // Label wasn't a symbol, so let's clear it
2671
+               } else {
2672
+                       // Number/label+Register
2673
+                       while((('+' == *ptr)||('-' == *ptr))
2674
+                                       &&(ptr[1])
2675
+                                       &&((isdigit(ptr[1]))
2676
+                                       ||((ptr[0] == '+')
2677
+                                               &&(ptr[1] == '-')
2678
+                                               &&(ptr[2])
2679
+                                               &&(isdigit(ptr[2]))))) {
2680
+                               char *end;
2681
+
2682
+                               if ((*ptr == '+')&&(isdigit(ptr[1])))
2683
+                                       insn->i_imm += strtoul(ptr, &end, 0);
2684
+                               else if ((*ptr == '+')&&(ptr[1] == '-')
2685
+                                               &&(isdigit(ptr[2])))
2686
+                                       insn->i_imm -= strtoul(ptr+2, &end, 0);
2687
+                               else if ((*ptr == '-')&&(isdigit(ptr[1])))
2688
+                                       insn->i_imm -= strtoul(ptr+1, &end, 0);
2689
+                               else {
2690
+                                       fprintf(stderr, "GAS: Cannot comprehend %s\n", ptr);
2691
+                                       gas_assert((0)&&("Should never get here"));
2692
+                               }
2693
+                               ptr = (const char *)end;
2694
+                       }
2695
+                       if (('+' == *ptr)&&((err = zip_parse_reg(ptr+1, &insn->i_breg))==NULL)) {
2696
+                               // Let's skip to the end of the register
2697
+                               ptr++;
2698
+                               while(isalpha(*ptr))
2699
+                                       ptr++;
2700
+                               while(isdigit(*ptr))
2701
+                                       ptr++;
2702
+                       } else if (('(' == *ptr)&&((err = zip_parse_reg(ptr+1, &insn->i_breg))==NULL)) {
2703
+                               ptr++;
2704
+                               while((*ptr)&&(')' != *ptr))
2705
+                                       ptr++;
2706
+                               ptr++;
2707
+                       } else {
2708
+                               // OOps!! Must've been a label + number
2709
+                               err = NULL;
2710
+                       }
2711
+               }
2712
+       } else if ((*lbl)&&(NULL == zip_parse_reg(lbl, &insn->i_breg))) {
2713
+               // Form: Register (only)
2714
+               insn->i_imm = 0;
2715
+               // printf("OP-B ( \'%s\' ) Had a register, %s -> %d\n", bop,
2716
+                       // lbl, insn->i_breg);
2717
+               *lbl = '\0';
2718
+       } else if (*lbl) {
2719
+               // Form: Label or Number (only)
2720
+               insn->i_breg = ZIP_RNONE;
2721
+       }
2722
+
2723
+       // Look for a +number at the end
2724
+       if ((*ptr)&&((*ptr == '+')||(*ptr == '-'))) {
2725
+               // printf("Looking at a plus: %s\n", ptr);
2726
+               int     sgn = (*ptr == '-')?1:0;
2727
+
2728
+               if (sgn) {
2729
+                       // printf("... I meant a minus\n");
2730
+                       ptr++;
2731
+               }
2732
+
2733
+               ptr = zip_skip_white_spaces(ptr);
2734
+               if ('$' == *ptr)
2735
+                       ptr = zip_skip_white_spaces(ptr+1);
2736
+
2737
+               if ('+' == *ptr)
2738
+                       ptr++;
2739
+               if ('-' == *ptr) {
2740
+                       sgn = !sgn;
2741
+                       ptr++;
2742
+               }
2743
+
2744
+               ptr = zip_skip_white_spaces(ptr);
2745
+               if ('$' == *ptr)
2746
+                       ptr = zip_skip_white_spaces(ptr+1);
2747
+               if ('-' == *ptr) {
2748
+                       sgn = !sgn;
2749
+                       ptr++;
2750
+               }
2751
+
2752
+               if ((*ptr)&&(isdigit(*ptr))) {
2753
+                       char *end = (char *)ptr;
2754
+
2755
+                       // printf("Parsing #: %s\n", ptr);
2756
+                       // While the following might make the most sense,
2757
+                       //    if (sgn) *--ptr = '-';
2758
+                       // the string is read-only, so we can't change it.
2759
+                       // Instead we do ...
2760
+                       unsigned long v = (sgn)?
2761
+                               -strtoul(ptr, &end, 0) : strtoul(ptr, &end, 0);
2762
+                       insn->i_imm += v;
2763
+                       ptr = (const char *)end;
2764
+               }
2765
+       }
2766
+
2767
+       if (*lbl) {
2768
+               // printf("i_rp = %s\n", (insn->i_rp)?"(Null)":"not NULL");
2769
+               symbolS *sym = symbol_find_or_make(lbl);
2770
+               sym->sy_flags.sy_used = TRUE;
2771
+               // segT seg = S_GET_SEGMENT(sym);
2772
+#ifdef ZIP_DEBUG
2773
+               zip_dump_sym(sym);
2774
+#endif
2775
+               if (insn->i_breg == ZIP_PC) {
2776
+                       // New pc-relative relocation,
2777
+                       // ???
2778
+                       // symbolP = symbol_create(FAKE_LABEL_NAME,
2779
+                               // absolute_section, 0 &zero_address_frag);
2780
+                       // symbol_set_value_expression(symbolP, expressionP);
2781
+                       // resolve_symbol_value(symbolP);
2782
+                       insn->i_rp =(ZIPRELOC *)xmalloc(sizeof(ZIPRELOC));
2783
+                       insn->i_rp->r_sym = sym;
2784
+                       insn->i_rp->r_pcrel = TRUE;
2785
+                       insn->i_rp->r_fr_offset = 0;
2786
+                       insn->i_rp->r_fix = NULL;
2787
+                       insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_PCREL;
2788
+                       // symbol_make(name??)
2789
+                       // symbol_find_or_make(name)
2790
+                       // symbol_relc_make_sym
2791
+                       // symbol_relc_make_value
2792
+                       // symbol_find(name)
2793
+                       // symbol_find_noref(name, noref)
2794
+                       // symbol_find_exact(name)
2795
+                       // symbol_find_exact_noref(name, noref)
2796
+                       // symbol_find_or_make(name)
2797
+                       // symbol_make(name)
2798
+                       // symbol_new(name, seg, value, frag)
2799
+                       //      preferred call over symbol create
2800
+                       //      calls symbol_create internal
2801
+                       // symbol_create(name, segment, value, frag)
2802
+                       //
2803
+                       // local_symbol_make(name, section, value, frag)
2804
+                       // symbol_clone(sym, int)
2805
+                       // symbol_temp_new(seg, value, frag)
2806
+                       // symbol_temp_new_now(void)
2807
+                       // symbol_temp_make(void)
2808
+                       // colon(void)
2809
+                       //      Called when symbol: starts a line
2810
+                       //      Calls symbol_new(name, now_seg, frag_now_fix(),
2811
+                       //              frag_now);
2812
+                       //              symbol_table_insert(symbolP)
2813
+                       //
2814
+                       // expr_build_dot returns a symbol pointing to the
2815
+                       //      current location ...
2816
+                       //
2817
+                       // Useful:
2818
+                       //      frag_now is current frag
2819
+                       //      S_SET_VALUE(symbolP, frag_now_fix()) ???
2820
+                       //      now_seg must be the current segment
2821
+                       //      S_SET_SETGMENT(symbolP, now_seg);
2822
+               /*
2823
+               } else if((zip_param_got)&&(insn->i_breg == ZIP_GBL)) {
2824
+                       // New GOT-relative relocation
2825
+                       insn->i_rp =(ZIPRELOC *)xmalloc(sizeof(ZIPRELOC));
2826
+                       insn->i_rp->r_sym = sym;
2827
+                       insn->i_rp->r_pcrel = FALSE;
2828
+                       insn->i_rp->r_fr_offset = 0;
2829
+                       insn->i_rp->r_fix = NULL;
2830
+               */
2831
+               } else {
2832
+                       insn->i_rp =(ZIPRELOC *)xmalloc(sizeof(ZIPRELOC));
2833
+                       insn->i_rp->r_sym = sym;
2834
+                       insn->i_rp->r_pcrel = FALSE;
2835
+                       insn->i_rp->r_fr_offset = 0;
2836
+                       insn->i_rp->r_fix = NULL;
2837
+                       if (insn->i_breg != ZIP_RNONE)
2838
+                               insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_OFFSET;
2839
+                       else
2840
+                               insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_IMM;
2841
+               }
2842
+       }
2843
+
2844
+       return  err;
2845
+}
2846
+
2847
+static int     fits_within(int nbits, int value) {
2848
+       // -2 fits_within two bits
2849
+       // -1 fits_within two bits
2850
+       //  1 fits_within two bits
2851
+       //  2 does not
2852
+       //
2853
+       if (value > 0)
2854
+               return (value <   (1l<<(nbits-1))) ? 1:0;
2855
+       else
2856
+               return (value >= -(1l<<(nbits-1))) ? 1:0;
2857
+}
2858
+
2859
+static const char *zip_parse(const char *line, ZIPIS *insn) {
2860
+       const char      *err = NULL, *opstr = NULL;
2861
+       char    *alt;
2862
+       int     i;
2863
+       char *cndp = NULL;
2864
+       // Two (possible) tokens left:
2865
+       //      the left of the comma, and the right of the comma
2866
+       const char      *left, *right, *eol;
2867
+       typedef enum    {
2868
+               TWO_OP,         // Standard for most instructions
2869
+               IMM_OP,         // Immediate operand only
2870
+               BACKWARDS_TWO,  // Only used by STO REG,Off(REG)
2871
+               NO_OP,          // Used by NOOP, BUSY, HALT, RTU, LOCK, etc
2872
+               ONE_OR_TWO_OP,  // Only used by TST
2873
+               MAYBE_ONE_IMM,  // Only used by BREAK, NOOP, SIM
2874
+               MAYBE_ONE_REG,  // Only used by SDUMP, NDUMP
2875
+               MAYBE_ONE_IMM_OR_REG,   // Only used by SEXIT, NEXIT, SOUT, NOUT
2876
+               MAYBE_OPB,      // Only used by TRAP
2877
+               ONE_REGISTER,   // Only used by CLR, CLRF, and NOT
2878
+               OP_ADDRESS,     // Only used by BRA, BRA.C, and LINK
2879
+               OP_B,           // Only used by JMP
2880
+               TWO_REGISTER,   // Only used by FP instructions
2881
+               ILLEGAL_FORM    // Never used, for debugging only
2882
+       } FORMTYPE;
2883
+
2884
+       FORMTYPE        insn_form = ILLEGAL_FORM; // Make sure we set this
2885
+
2886
+
2887
+
2888
+#ifdef ZIP_DEBUG
2889
+       fprintf(stderr, "**** Parsing %s\n", line);
2890
+#endif
2891
+
2892
+       insn->i_naux = 0;
2893
+       insn->i_op   = ZIPO_NOOP;
2894
+       insn->i_cnd  = ZIPC_ALWAYS;
2895
+       insn->i_areg = ZIP_RNONE;
2896
+       insn->i_breg = ZIP_RNONE;
2897
+       insn->i_imm  = 0;
2898
+       insn->i_rp   = NULL;
2899
+       insn->i_code = NOOP_OPCODE;
2900
+       for(i=0; i<ZIP_MAX_NAUX; i++)
2901
+               insn->i_aux[i]  = NOOP_OPCODE;
2902
+
2903
+       // The opcode is given between whitespace and a period, or whitespace
2904
+       // and whitespace
2905
+       alt = strdup(zip_skip_white_spaces(line));
2906
+       if ((*alt)=='[') {
2907
+               // Instruction starts with condition codes-- a feature we
2908
+               // needed to add in order to support GCC conditional execution
2909
+               // macro
2910
+               cndp = strtok(alt,"] \t")+1;
2911
+               if (!cndp)
2912
+                       return "Mismatched parenthesis--an attempt at a condition?";
2913
+               if (strlen(cndp) > 3)
2914
+                       return "Invalid condition (too long)";
2915
+
2916
+               opstr = strtok(NULL, " \t");
2917
+               if (!opstr)
2918
+                       return "Condition not followed by valid opcode";
2919
+       } else {
2920
+               opstr = strtok(alt, " \t"); // Get our opcode
2921
+               if (!opstr) {
2922
+                       free(alt);
2923
+                       return "Invalid Instruction";
2924
+               }
2925
+       }
2926
+       // See if our token contains a '.' within it
2927
+       //      GCC allows conditions beginning a line, as in ...
2928
+       //              (CND)   Opcode  B,A
2929
+       //      such a condition, if present, was detected above.
2930
+       //
2931
+       //      If not, we now look for a condition written in our original
2932
+       //      format of ...
2933
+       //              Opcode.CND B,A
2934
+       //      and we look for it here.
2935
+       //
2936
+       if (!cndp) {
2937
+               cndp = strchr(opstr, '.');
2938
+               // If we found such a condition, we need to fix the opstr
2939
+               // so that it no longer includes the condition.  Hence, let's
2940
+               // place a NULL within the alt string and push our condition
2941
+               // forward to the first non '.' value.
2942
+               if (cndp)
2943
+                       *cndp++ = '\0';
2944
+       }
2945
+       if (strcasecmp(opstr, "SUB")==0) {
2946
+               insn->i_op = ZIPO_SUB;
2947
+               insn_form = TWO_OP;
2948
+       } else if (strcasecmp(opstr, "AND")==0) {
2949
+               insn->i_op = ZIPO_AND;
2950
+               insn_form = TWO_OP;
2951
+       } else if (strcasecmp(opstr, "ADD")==0) {
2952
+               insn->i_op = ZIPO_ADD;
2953
+               insn_form = TWO_OP;
2954
+       } else if (strcasecmp(opstr, "OR")==0) {
2955
+               insn->i_op = ZIPO_OR;
2956
+               insn_form = TWO_OP;
2957
+       } else if (strcasecmp(opstr, "XOR")==0) {
2958
+               insn->i_op = ZIPO_XOR;
2959
+               insn_form = TWO_OP;
2960
+       } else if (strcasecmp(opstr, "LSR")==0) {
2961
+               insn->i_op = ZIPO_LSR;
2962
+               insn_form = TWO_OP;
2963
+       } else if (strcasecmp(opstr, "LSL")==0) {
2964
+               insn->i_op = ZIPO_LSL;
2965
+               insn_form = TWO_OP;
2966
+       } else if (strcasecmp(opstr, "ASR")==0) {
2967
+               insn->i_op = ZIPO_ASR;
2968
+               insn_form = TWO_OP;
2969
+       } else if (strcasecmp(opstr, "BREV")==0) {
2970
+               insn->i_op = ZIPO_BREV;                 // BREV b+Rb,Ra, or
2971
+               insn_form = ONE_OR_TWO_OP;              // BREV Rx -> BREV Rx,Rx
2972
+       } else if((strcasecmp(opstr, "LDILO")==0)
2973
+                       ||(strcasecmp(opstr, "LLO")==0)) {
2974
+               insn->i_op = ZIPO_LDILO;
2975
+               insn_form = TWO_OP;
2976
+       } else if (strcasecmp(opstr, "MPYUHI")==0) {    // MPUHI
2977
+               insn->i_op = ZIPO_MPYUHI;
2978
+               insn_form = TWO_OP;
2979
+       } else if (strcasecmp(opstr, "MPYSHI")==0) {    // MPSHI
2980
+               insn->i_op = ZIPO_MPYSHI;
2981
+               insn_form = TWO_OP;
2982
+       } else if (strcasecmp(opstr, "MPY")==0) {
2983
+               insn_form = TWO_OP;
2984
+               insn->i_op = ZIPO_MPY;
2985
+       } else if (strcasecmp(opstr, "MOV")==0) {
2986
+               insn->i_op = ZIPO_MOV;
2987
+               insn_form = TWO_OP;
2988
+       } else if (strcasecmp(opstr, "DIVU")==0) {
2989
+               insn->i_op = ZIPO_DIVU;
2990
+               insn_form = TWO_OP;
2991
+       } else if (strcasecmp(opstr, "DIVS")==0) {
2992
+               insn->i_op = ZIPO_DIVS;
2993
+               insn_form = TWO_OP;
2994
+       } else if (strcasecmp(opstr, "CMP")==0) {
2995
+               insn->i_op = ZIPO_CMP;
2996
+               insn_form = TWO_OP;
2997
+       } else if ((strcasecmp(opstr, "TST")==0)
2998
+               ||(strcasecmp(opstr, "TEST")==0)) {
2999
+               insn->i_op = ZIPO_TST;                  // TST b+Rb,Ra, or
3000
+               insn_form = ONE_OR_TWO_OP;              // TST Rx -> TST -1,Rx
3001
+       } else if (strcasecmp(opstr, "LW")==0) {
3002
+               insn->i_op = ZIPO_LW;
3003
+               insn_form = TWO_OP;
3004
+       } else if (strcasecmp(opstr, "SW")==0) {
3005
+               insn->i_op = ZIPO_SW;
3006
+               insn_form = BACKWARDS_TWO;
3007
+       } else if (strcasecmp(opstr, "LH")==0) {
3008
+               insn->i_op = ZIPO_LH;
3009
+               insn_form = TWO_OP;
3010
+       } else if (strcasecmp(opstr, "SH")==0) {
3011
+               insn->i_op = ZIPO_SH;
3012
+               insn_form = BACKWARDS_TWO;
3013
+       } else if (strcasecmp(opstr, "LB")==0) {
3014
+               insn->i_op = ZIPO_LB;
3015
+               insn_form = TWO_OP;
3016
+       } else if (strcasecmp(opstr, "SB")==0) {
3017
+               insn->i_op = ZIPO_SB;
3018
+               insn_form = BACKWARDS_TWO;
3019
+       } else if (strcasecmp(opstr, "LDI")==0) {
3020
+               insn->i_op = ZIPO_LDI;
3021
+               insn_form = IMM_OP;
3022
+       } else if (strcasecmp(opstr, "FPADD")==0) {
3023
+               insn->i_op = ZIPO_FPADD;
3024
+               insn_form = TWO_REGISTER;
3025
+       } else if (strcasecmp(opstr, "FPSUB")==0) {
3026
+               insn->i_op = ZIPO_FPSUB;
3027
+               insn_form = TWO_REGISTER;
3028
+       } else if (strcasecmp(opstr, "FPMUL")==0) {
3029
+               insn->i_op = ZIPO_FPMPY;
3030
+               insn_form = TWO_REGISTER;
3031
+       } else if (strcasecmp(opstr, "FPDIV")==0) {
3032
+               insn->i_op = ZIPO_FPDIV;
3033
+               insn_form = TWO_REGISTER;
3034
+       } else if (strcasecmp(opstr, "FPI2F")==0) {
3035
+               insn->i_op = ZIPO_FPI2F;
3036
+               insn_form = TWO_OP;
3037
+       } else if (strcasecmp(opstr, "FPF2I")==0) {
3038
+               insn->i_op = ZIPO_FPF2I;
3039
+               insn_form = TWO_REGISTER;
3040
+       } else if ((strcasecmp(opstr, "BRK")==0)
3041
+               ||(strcasecmp(opstr, "BREAK")==0)) {
3042
+               insn->i_op = ZIPO_BREAK;
3043
+               insn->i_imm= 0;
3044
+               insn_form = MAYBE_ONE_IMM;
3045
+       } else if (strcasecmp(opstr, "LOCK")==0) {
3046
+               insn->i_op = ZIPO_LOCK;
3047
+               insn_form = NO_OP;
3048
+       // Now for some derived instructions
3049
+       } else if (strcasecmp(opstr, "TRAP")==0) {
3050
+               insn->i_op = ZIPO_TRAP;
3051
+               insn_form = MAYBE_OPB;
3052
+       } else if (strcasecmp(opstr, "CLR")==0) {
3053
+               insn->i_op = ZIPO_CLR;
3054
+               insn_form = ONE_REGISTER;
3055
+       } else if (strcasecmp(opstr, "BRA")==0) {
3056
+               insn->i_op = ZIPO_BRA;
3057
+               insn_form = OP_ADDRESS;
3058
+       } else if (strcasecmp(opstr, "LJMP")==0) {
3059
+               insn->i_op = ZIPO_LJMP;
3060
+               insn->i_breg = ZIP_RNONE;
3061
+               insn->i_imm  = 0;
3062
+               insn_form = OP_ADDRESS;
3063
+       } else if (strcasecmp(opstr, "BZ")==0) {
3064
+               insn->i_op = ZIPO_BRA;
3065
+               insn->i_cnd = ZIPC_Z;
3066
+               insn_form = OP_ADDRESS;
3067
+       } else if (strcasecmp(opstr, "BLT")==0) {
3068
+               insn->i_op = ZIPO_BRA;
3069
+               insn->i_cnd = ZIPC_LT;
3070
+               insn_form = OP_ADDRESS;
3071
+       } else if (strcasecmp(opstr, "BC")==0) {
3072
+               insn->i_op = ZIPO_BRA;
3073
+               insn->i_cnd = ZIPC_C;
3074
+               insn_form = OP_ADDRESS;
3075
+       } else if (strcasecmp(opstr, "BV")==0) {
3076
+               insn->i_op = ZIPO_BRA;
3077
+               insn->i_cnd = ZIPC_V;
3078
+               insn_form = OP_ADDRESS;
3079
+       } else if (strcasecmp(opstr, "BNZ")==0) {
3080
+               insn->i_op = ZIPO_BRA;
3081
+               insn->i_cnd = ZIPC_NZ;
3082
+               insn_form = OP_ADDRESS;
3083
+       } else if (strcasecmp(opstr, "BGE")==0) {
3084
+               insn->i_op = ZIPO_BRA;
3085
+               insn->i_cnd = ZIPC_GE;
3086
+               insn_form = OP_ADDRESS;
3087
+       } else if (strcasecmp(opstr, "BNC")==0) {
3088
+               insn->i_op = ZIPO_BRA;
3089
+               insn->i_cnd = ZIPC_NC;
3090
+               insn_form = OP_ADDRESS;
3091
+       } else if (strcasecmp(opstr, "HALT")==0) {
3092
+               insn->i_op = ZIPO_HALT;
3093
+               insn->i_imm = ZIP_CC_SLEEP;
3094
+               insn->i_areg= ZIP_CC;
3095
+               insn_form = NO_OP;
3096
+       } else if (strcasecmp(opstr, "WAIT")==0) {
3097
+               insn->i_op = ZIPO_WAIT;
3098
+               insn->i_imm = ZIP_CC_SLEEP | ZIP_CC_GIE;
3099
+               insn->i_areg= ZIP_CC;
3100
+               insn_form = NO_OP;
3101
+       } else if (strcasecmp(opstr, "STEP")==0) {
3102
+               insn->i_op = ZIPO_STEP;
3103
+               insn->i_imm = ZIP_CC_STEP | ZIP_CC_GIE;
3104
+               insn->i_areg= ZIP_CC;
3105
+               insn_form = NO_OP;
3106
+       } else if ((strcasecmp(opstr, "RTU")==0)
3107
+                       ||(strcasecmp(opstr, "IRET")==0)) {
3108
+               insn->i_op = ZIPO_RTU;
3109
+               insn->i_imm = ZIP_CC_GIE;
3110
+               insn->i_areg = ZIP_CC;
3111
+               insn_form = NO_OP;
3112
+       } else if (strcasecmp(opstr, "BUSY")==0) {
3113
+               insn->i_op = ZIPO_BUSY;
3114
+               insn->i_imm= -4;
3115
+               insn->i_areg = ZIP_PC;
3116
+               insn->i_breg = ZIP_RNONE;
3117
+               insn_form = NO_OP;
3118
+       } else if (strcasecmp(opstr, "JMP")==0) {
3119
+               insn->i_op = ZIPO_JMP;
3120
+               insn->i_areg = ZIP_PC;
3121
+               insn_form = OP_B;
3122
+       } else if ((strcasecmp(opstr, "RETN")==0)
3123
+                       ||(strcasecmp(opstr, "RTN")==0)) {
3124
+               insn->i_op = ZIPO_JMP;
3125
+               insn->i_areg = ZIP_PC;
3126
+               insn->i_breg = ZIP_LR;
3127
+               insn->i_imm  = 0;
3128
+               insn_form = NO_OP;
3129
+       } else if (strcasecmp(opstr, "NOT")==0) {
3130
+               insn->i_op = ZIPO_NOT;
3131
+               insn->i_imm = -1;
3132
+               insn_form = ONE_REGISTER;
3133
+       } else if (strcasecmp(opstr, "NEG")==0) {
3134
+               insn->i_op = ZIPO_NEG;
3135
+               insn->i_imm = 0;
3136
+               insn_form = ONE_OR_TWO_OP;
3137
+       } else if (strcasecmp(opstr, "LJSR")==0) {
3138
+               insn->i_op   = ZIPO_LJSR;
3139
+               insn->i_breg = ZIP_RNONE;
3140
+               insn->i_imm  = 0;
3141
+               insn_form    = OP_ADDRESS;
3142
+       } else if (strcasecmp(opstr, "JSR")==0) {
3143
+               insn->i_op = ZIPO_JSR;
3144
+               insn->i_imm = 0;
3145
+               insn_form = OP_ADDRESS;
3146
+       } else if ((strcasecmp(opstr, "NOP")==0)
3147
+                       ||(strcasecmp(opstr, "NOOP")==0)) {
3148
+               insn->i_op = ZIPO_NOOP;
3149
+               insn_form = MAYBE_ONE_IMM;
3150
+       } else if (strcasecmp(opstr, "SIM")==0) {
3151
+               insn->i_op = ZIPO_SIM;
3152
+               insn->i_imm= 0;
3153
+               insn_form = MAYBE_ONE_IMM;
3154
+       } else if (strcasecmp(opstr, "SNOOP")==0) {
3155
+               insn->i_op = ZIPO_SIM;
3156
+               insn->i_imm= 0;
3157
+               insn_form = MAYBE_ONE_IMM;
3158
+       } else if (strcasecmp(opstr, "SDUMP")==0) {
3159
+               insn->i_op = ZIPO_SDUMP;
3160
+               insn->i_imm= 0;
3161
+               insn_form = MAYBE_ONE_REG;
3162
+       } else if (strcasecmp(opstr, "SEXIT")==0) {
3163
+               insn->i_op = ZIPO_SEXIT;
3164
+               insn->i_imm= 0;
3165
+               insn_form = MAYBE_ONE_IMM_OR_REG;
3166
+       } else if (strcasecmp(opstr, "SOUT")==0) {
3167
+               insn->i_op = ZIPO_SOUT;
3168
+               insn->i_imm= 0;
3169
+               insn_form = MAYBE_ONE_IMM_OR_REG;
3170
+       } else if (strcasecmp(opstr, "NDUMP")==0) {
3171
+               insn->i_op = ZIPO_NDUMP;
3172
+               insn->i_imm= 0;
3173
+               insn_form = MAYBE_ONE_REG;
3174
+       } else if (strcasecmp(opstr, "NEXIT")==0) {
3175
+               insn->i_op = ZIPO_NEXIT;
3176
+               insn->i_imm= 0;
3177
+               insn_form = MAYBE_ONE_IMM_OR_REG;
3178
+       } else if (strcasecmp(opstr, "SEXTB")==0) {
3179
+               insn->i_op = ZIPO_SEXTB;
3180
+               insn->i_imm= 0;
3181
+               insn_form = ONE_REGISTER;
3182
+       } else if (strcasecmp(opstr, "SEXTH")==0) {
3183
+               insn->i_op = ZIPO_SEXTH;
3184
+               insn->i_imm= 0;
3185
+               insn_form = ONE_REGISTER;
3186
+       } else if (strcasecmp(opstr, "NOUT")==0) {
3187
+               insn->i_op = ZIPO_NOUT;
3188
+               insn->i_imm= 0;
3189
+               insn_form = MAYBE_ONE_IMM_OR_REG;
3190
+       } else {
3191
+               free(alt);
3192
+               return "Unrecognized op-code";
3193
+       }
3194
+
3195
+       if (cndp) {
3196
+               // We have a condition
3197
+               if (insn->i_cnd != ZIPC_ALWAYS) {
3198
+                       err = "Instruction cannot take an additional condition";
3199
+               } else {
3200
+                       err = zip_parse_condition(cndp, &insn->i_cnd);
3201
+               }
3202
+       } if (err) {
3203
+               free(alt);
3204
+               return err;
3205
+       }
3206
+
3207
+       if (strchr(line, ',')!=NULL)
3208
+               left = strtok(NULL, ",");
3209
+       else
3210
+               left  = strtok(NULL, " \t,");
3211
+       right = (left)  ? strtok(NULL, " \t") : NULL;
3212
+       eol   = (right) ? strtok(NULL, " \t") : NULL;
3213
+       if (eol != NULL) {
3214
+               free(alt);
3215
+               return "Too many tokens on one line";
3216
+       }
3217
+
3218
+       switch(insn_form) {
3219
+               case TWO_OP:
3220
+                       err = zip_parse_bop(left,insn);
3221
+                       if (!err)
3222
+                               err = zip_parse_reg(right,&insn->i_areg);
3223
+                       break;
3224
+               case IMM_OP:
3225
+                       err = zip_parse_bop(left,insn);
3226
+                       if ((!err)&&(insn->i_breg == ZIP_RNONE))
3227
+                               err = zip_parse_reg(right,&insn->i_areg);
3228
+                       else if (!err)
3229
+                               err = "LDI can only load immediates, not registers";
3230
+                       break;
3231
+               case BACKWARDS_TWO:
3232
+                       err = zip_parse_reg(left,&insn->i_areg);
3233
+                       if (!err)
3234
+                               err = zip_parse_bop(right,insn);
3235
+                       break;
3236
+               case MAYBE_ONE_IMM:
3237
+                       if (NULL != right)
3238
+                               err = "Wrong number of operands!";
3239
+                       else if (left) {
3240
+                               err = zip_parse_bop(left,insn);
3241
+                               if ((!err)&&(insn->i_breg != ZIP_RNONE))
3242
+                                       err = "BREAK arguments can only be immediates";
3243
+                       }
3244
+                       break;
3245
+               case MAYBE_ONE_IMM_OR_REG:
3246
+                       if (NULL != right)
3247
+                               err = "Wrong number of operands!";
3248
+                       else if (left) {
3249
+                               err = zip_parse_bop(left,insn);
3250
+                               if ((!err)&&(insn->i_breg != ZIP_RNONE)
3251
+                                       &&(insn->i_imm != 0))
3252
+                                       err = "EXIT arguments can only be immediates or register, not both";
3253
+                       }
3254
+                       break;
3255
+               case MAYBE_ONE_REG:
3256
+                       if (NULL != right)
3257
+                               err = "Wrong number of operands!";
3258
+                       else if (left) {
3259
+                               err = zip_parse_bop(left,insn);
3260
+                               if ((!err)&&(insn->i_breg != ZIP_RNONE)&&(insn->i_imm))
3261
+                                       err = "xDUMP instructions can handle immediates or registers, not both";
3262
+                       } else {
3263
+                               insn->i_breg = ZIP_RNONE;
3264
+                               insn->i_imm  = 0;
3265
+                       } break;
3266
+               case NO_OP:
3267
+                       if ((NULL != left)||(NULL != right))
3268
+                               err = "Wrong number of operands!";
3269
+                       break;
3270
+               case ONE_OR_TWO_OP:
3271
+                       // This is a reference to the test instruction, which
3272
+                       // can either be
3273
+                       //      A. TEST a,Rx, or TEST Rx,.
3274
+                       // or   B. BRA  a,Rx, or BRA Rx,.
3275
+                       if (NULL != right) {
3276
+                               err = zip_parse_bop(left,insn);
3277
+                               if (!err)
3278
+                                       err = zip_parse_reg(right,&insn->i_areg);
3279
+                               if (!err)
3280
+                                       err = zip_parse_bop(left,insn);
3281
+                       } else {
3282
+                               zip_parse_reg(left, &insn->i_areg);
3283
+                               if (insn->i_op == ZIPO_BREV) {
3284
+                                       insn->i_breg = insn->i_areg;
3285
+                                       insn->i_imm = 0;
3286
+                               } else {
3287
+                                       insn->i_breg = ZIP_RNONE;
3288
+                                       insn->i_imm = -1;
3289
+                               }
3290
+                       } break;
3291
+               case ONE_REGISTER:
3292
+                       // CLR, CLRF, or NOT
3293
+                       insn->i_breg = ZIP_RNONE;
3294
+                       if (NULL != right)
3295
+                               err = "Instruction opcode expects only one operand";
3296
+                       else
3297
+                               err = zip_parse_reg(left,&insn->i_areg);
3298
+                       break;
3299
+               case OP_ADDRESS:
3300
+                       // JSR or BRA instruction
3301
+                       //      This is different from OP_B below, in that this
3302
+                       //      form implies a PC relative addressing, which
3303
+                       //      may not be clear from the operands given
3304
+                       if (NULL != right)
3305
+                               err = "Instruction opcode expects only one operand";
3306
+                       else {
3307
+                               if ((NULL == strchr(left,'('))
3308
+                                       &&(NULL == strchr(left,'+'))) {
3309
+                                       char    *longerstr = (char *)xmalloc(strlen(left)+6);
3310
+                                       // If not stated, assume PC relative
3311
+                                       strcpy(longerstr,left);
3312
+                                       strcat(longerstr, "(PC)");
3313
+                                       err = zip_parse_bop(longerstr, insn);
3314
+                                       free(longerstr);
3315
+                               } else
3316
+                                       err = zip_parse_bop(left, insn);
3317
+                       }
3318
+
3319
+                       break;
3320
+               case MAYBE_OPB:
3321
+                       // JMP or TRAP instruction
3322
+                       if (NULL != right)
3323
+                               err = "Instruction opcode expects only one operand";
3324
+                       else if (NULL == left) {
3325
+                               insn->i_breg = ZIP_RNONE;
3326
+                               insn->i_imm = 0;
3327
+                               break;
3328
+                       } // Fall through
3329
+               case OP_B: // Operand B only (A is implied)
3330
+                       // JMP or TRAP instruction
3331
+                       if (NULL != right)
3332
+                               err = "Instruction opcode expects only one operand";
3333
+                       else
3334
+                               err = zip_parse_bop(left, insn);
3335
+                       if (insn->i_op == ZIPO_JMP)
3336
+                               insn->i_areg = ZIP_PC;
3337
+                       else // if insn->i_op == TRAP
3338
+                               insn->i_areg = ZIP_CC;
3339
+                       break;
3340
+               case TWO_REGISTER:
3341
+                       // These are the floating point instructions, which
3342
+                       // can't handle immediate offsets.
3343
+                       err = zip_parse_reg(right, &insn->i_areg);
3344
+                       if (!err)
3345
+                               err = zip_parse_reg(left, &insn->i_breg);
3346
+                       break;
3347
+               default:        // case ILLEGAL_FORM
3348
+                       err = "Unknown instruction format!";
3349
+                       break;
3350
+       }
3351
+
3352
+       if (err)
3353
+               return (err);
3354
+
3355
+       switch(insn->i_op) {
3356
+               case ZIPO_SUB:  case ZIPO_AND: case ZIPO_ADD: case ZIPO_OR:
3357
+               case ZIPO_XOR:  case ZIPO_LSR: case ZIPO_LSL: case ZIPO_ASR:
3358
+               case ZIPO_BREV:
3359
+               case ZIPO_MPYUHI: case ZIPO_MPYSHI:
3360
+               case ZIPO_MPY:
3361
+                       break;
3362
+               case ZIPO_LDILO:
3363
+                       if (!fits_within(16, insn->i_imm))
3364
+                               gas_assert((insn->i_imm & (~0x0ffff))==0);
3365
+                       insn->i_imm &= 0x0ffff;
3366
+                       break;
3367
+               case ZIPO_DIVU: case ZIPO_DIVS:
3368
+                       if (0x0e == (insn->i_areg & 0x0f))
3369
+                               err = "Divide instructions cannot result in CC or PC regs";
3370
+                       else if (insn->i_rp)
3371
+                               err = "Relocations not applicable for divides";
3372
+                       break;
3373
+                       break;
3374
+               case ZIPO_MOV:
3375
+                       if (insn->i_breg == ZIP_RNONE)
3376
+                               insn->i_op = ZIPO_LDI;
3377
+                       break;
3378
+               case ZIPO_CMP: case ZIPO_TST:
3379
+                       break;
3380
+               case ZIPO_LW: case ZIPO_SW:
3381
+               case ZIPO_LH: case ZIPO_SH:
3382
+               case ZIPO_LB: case ZIPO_SB:
3383
+                       break;
3384
+               case ZIPO_LDI: case ZIPO_LDIn:
3385
+                       break;
3386
+               case ZIPO_FPADD: case ZIPO_FPSUB:
3387
+               case ZIPO_FPMPY: case ZIPO_FPDIV:
3388
+               case ZIPO_FPF2I: case ZIPO_FPI2F:
3389
+                       if (0x0e == (insn->i_areg & 0x0f))
3390
+                               err = "Floating point operations cannot result in CC or PC regs";
3391
+                       else if (insn->i_rp)
3392
+                               err = "Relocations not applicable for floating point ops";
3393
+                       break;
3394
+               case ZIPO_TRAP:
3395
+                       insn->i_areg = ZIP_CC;
3396
+                       if (insn->i_breg == ZIP_RNONE) {
3397
+                               if (insn->i_cnd == ZIPC_ALWAYS)
3398
+                                       insn->i_op = ZIPO_LDI;
3399
+                               else if (fits_within(16, insn->i_imm))
3400
+                                       insn->i_op = ZIPO_LDILO;
3401
+                               else if (fits_within(18, zip_brev(insn->i_imm)))
3402
+                                       insn->i_op = ZIPO_BREV;
3403
+                               else
3404
+                                       err = "TRAP immediate not supported";
3405
+                       } else
3406
+                               insn->i_op = ZIPO_MOV;
3407
+                       break;
3408
+               case ZIPO_CLR:
3409
+                       insn->i_op = ZIPO_LDI;
3410
+                       insn->i_imm = 0;
3411
+                       break;
3412
+               case ZIPO_JMP:
3413
+                       if (insn->i_breg != ZIP_RNONE)
3414
+                               insn->i_op = ZIPO_MOV;  // JMP A+Rx
3415
+                       else
3416
+                               insn->i_op = ZIPO_BRA;  // JMP lbl = BRA lbl
3417
+                       // Fall through
3418
+               case ZIPO_BRA: // Leave as ZIPO_BRA until we assemble it
3419
+                       insn->i_areg = ZIP_PC;
3420
+                       break;
3421
+               case ZIPO_HALT: case ZIPO_WAIT: case ZIPO_RTU: case ZIPO_STEP:
3422
+                       insn->i_op = ZIPO_OR;
3423
+                       break;
3424
+               case ZIPO_BUSY:
3425
+                       insn->i_op = ZIPO_ADD;
3426
+                       break;
3427
+               case ZIPO_NOT:
3428
+                       insn->i_op = ZIPO_XOR;
3429
+                       insn->i_imm  = -1;
3430
+                       insn->i_breg = ZIP_RNONE;
3431
+                       break;
3432
+               case ZIPO_NEG:
3433
+                       if (insn->i_breg == ZIP_RNONE) {
3434
+                               insn->i_breg = insn->i_areg;
3435
+                               // This would've been set to -1 by the ONE or
3436
+                               // TWO op code.  Here, we set it back to zero.
3437
+                               insn->i_imm  = 0;
3438
+                       }
3439
+                       // insn->i_op = ZIPO_NEG; /// Can't collapse this yet
3440
+                       break;
3441
+               case ZIPO_BREAK:
3442
+                       insn->i_op = ZIPO_BREAK;
3443
+                       insn->i_areg = ZIP_RNONE;
3444
+                       insn->i_breg = ZIP_RNONE;
3445
+                       // insn->i_imm  = ... whatever it was set to
3446
+                       break;
3447
+               case ZIPO_LOCK:
3448
+                       insn->i_op = ZIPO_LOCK;
3449
+                       insn->i_areg = ZIP_RNONE;
3450
+                       insn->i_breg = ZIP_RNONE;
3451
+                       insn->i_imm  = 0;
3452
+                       break;
3453
+               case ZIPO_SDUMP:
3454
+                       insn->i_op = ZIPO_SIM;
3455
+                       if (insn->i_breg != ZIP_RNONE) {
3456
+                               insn->i_imm = (int)insn->i_breg + 0x0200;
3457
+                               insn->i_breg = ZIP_RNONE;
3458
+                       } else
3459
+                               insn->i_imm = 0x2ff;
3460
+                       break;
3461
+               case ZIPO_NDUMP:
3462
+                       insn->i_op = ZIPO_NOOP;
3463
+                       if (insn->i_breg != ZIP_RNONE) {
3464
+                               insn->i_imm = (int)insn->i_breg + 0x0200;
3465
+                               insn->i_breg = ZIP_RNONE;
3466
+                       } else
3467
+                               insn->i_imm = 0x2ff;
3468
+                       break;
3469
+               case ZIPO_SEXIT:
3470
+                       insn->i_op = ZIPO_SIM;
3471
+                       if (insn->i_breg != ZIP_RNONE)
3472
+                               insn->i_imm = 0x300 + (insn->i_breg & 0x01f);
3473
+                       else
3474
+                               insn->i_imm = 0x100 + (insn->i_imm & 0x0ff);
3475
+                       insn->i_breg = ZIP_RNONE;
3476
+                       break;
3477
+               case ZIPO_NEXIT:
3478
+                       insn->i_op = ZIPO_NOOP;
3479
+                       if (insn->i_breg != ZIP_RNONE)
3480
+                               insn->i_imm = 0x300 + (insn->i_breg & 0x01f);
3481
+                       else
3482
+                               insn->i_imm = 0x100 + (insn->i_imm & 0x0ff);
3483
+                       insn->i_breg = ZIP_RNONE;
3484
+                       break;
3485
+               case ZIPO_SOUT:
3486
+                       insn->i_op = ZIPO_SIM;
3487
+                       if (insn->i_breg != ZIP_RNONE)
3488
+                               insn->i_imm = 0x220 + (insn->i_breg & 0x01f);
3489
+                       else
3490
+                               insn->i_imm = 0x400 + (insn->i_imm & 0x0ff);
3491
+                       insn->i_breg = ZIP_RNONE;
3492
+                       break;
3493
+               case ZIPO_NOUT:
3494
+                       insn->i_op = ZIPO_NOOP;
3495
+                       if (insn->i_breg != ZIP_RNONE)
3496
+                               insn->i_imm = 0x220 + (insn->i_breg & 0x01f);
3497
+                       else
3498
+                               insn->i_imm = 0x400 + (insn->i_imm & 0x0ff);
3499
+                       insn->i_breg = ZIP_RNONE;
3500
+                       break;
3501
+               case ZIPO_SIM:
3502
+               case ZIPO_NOOP:
3503
+                       break;
3504
+               case ZIPO_LJMP: case ZIPO_LJSR:
3505
+                       if (insn->i_breg == ZIP_PC)
3506
+                               insn->i_breg = ZIP_RNONE;
3507
+                       if (insn->i_breg != ZIP_RNONE) {
3508
+                               err = "Indirect long jumps and long JSRs are not supported";
3509
+                       } break;
3510
+               case ZIPO_JSR:
3511
+                       break;
3512
+               case ZIPO_SEXTB: case ZIPO_SEXTH:
3513
+                       break;
3514
+               default:
3515
+                       return "Internal error -- unrecognized internal opcode";
3516
+                       break;
3517
+       } if (err) {
3518
+               free(alt);
3519
+               return err;
3520
+       }
3521
+
3522
+       if ((insn->i_op != ZIPO_MOV)&&(
3523
+                       ((insn->i_areg != ZIP_RNONE)&&(insn->i_areg >= 0x10))
3524
+                       ||((insn->i_breg != ZIP_RNONE)&&(insn->i_breg >= 0x10)))) {
3525
+               if (insn->i_rp)
3526
+                       free(insn->i_rp);
3527
+               insn->i_rp = NULL;
3528
+               free(alt);
3529
+               return "Only MOV instructions can reference explicit user registers";
3530
+       }
3531
+
3532
+       free(alt);
3533
+
3534
+       // We do nothing more to build the opcode here --- all we are doing
3535
+       // is parsing.
3536
+       return err;
3537
+}
3538
+
3539
+#define        NOOPGROUP(OP,IMM) ((0x78000000)|((((OP)+0x1c-ZIPO_BREAK)&0x01f)<<22)|((IMM) & 0x003fffff))
3540
+#define        DBLREGOP(OP,CND,IMM,B,A) ((((OP)&0x01f)<<22)|(((A)&0x0f)<<27)   \
3541
+                       | (((CND)&0x07)<<19)|(1<<18)|(((B)&0x0f)<<14)   \
3542
+                       | ((IMM) & 0x03fff))
3543
+#define        SMPLMOV(CND,IMM,B,A)    (((ZIPO_MOV&0x01f)<<22)|(((A)&0x0f)<<27)        \
3544
+                       | (((CND)&0x07)<<19)|(((B)&0x0f)<<14)|((IMM) & 0x01fff))
3545
+#define        IMMOP(OP,CND,IMM,A)     ((((OP)&0x01f)<<22)|(((A)&0x0f)<<27)    \
3546
+                       | (((CND)&0x07)<<19)|((IMM) & 0x03ffff))
3547
+#define        LDIOP(IMM,A)    ((ZIPO_LDI<<22)|(((A)&0x0f)<<27)|((IMM) & 0x07fffff))
3548
+
3549
+
3550
+/*
3551
+ *     CIS support code
3552
+ *
3553
+ *     Assuming that the instruction (a) is not a CIS instruction, this looks
3554
+ *     up the immediate value encoded in the instruction.  The purpose is to
3555
+ *     determine whether or not this instruction can be merged with the
3556
+ *     previous (or next) instruction in CIS mode.
3557
+ *
3558
+ */
3559
+static int
3560
+zip_non_cis_immediate(const unsigned a)
3561
+{
3562
+       ZIP_OPCODE      op = (ZIP_OPCODE)((a>>22)&0x1f);
3563
+       int             imm;
3564
+
3565
+       switch(op) {
3566
+               case    ZIPO_MOV:
3567
+                       imm = (a & 0x01fff); if (a&0x1000) imm |= -0x1000; break;
3568
+               case    ZIPO_LDI:
3569
+                       imm = (a & 0x03fffff); break;
3570
+               case    ZIPO_LDIn:
3571
+                       imm = (a & 0x03fffff); imm |= -0x0200000; break;
3572
+/*
3573
+ * While this makes conceptual sense, it doesn't match the CPU.  Hence let's
3574
+ * comment it out and make certain things still work.
3575
+               case    ZIPO_LDILO:
3576
+#ifndef        LONG_MPY
3577
+               case ZIPO_LDIHI: // BREVx would rm LDIHI
3578
+#endif
3579
+                       imm = (a & 0x0ffff); break;
3580
+*/
3581
+               default:
3582
+                       if (a & 0x040000) {
3583
+                               imm = (a & 0x03fff);
3584
+                               if (a & 0x2000) imm |= -0x02000;
3585
+                       } else {
3586
+                               imm = (a & 0x03ffff);
3587
+                               if (a & 0x020000)
3588
+                                       imm |= -0x020000;
3589
+                       }
3590
+       }
3591
+
3592
+       return imm;
3593
+}
3594
+
3595
+static int
3596
+zip_can_merge(const unsigned a, const unsigned b)
3597
+{
3598
+       // Can't merge instructions if merging isnt turned on
3599
+       if (!zip_param_cis)
3600
+               return 0;
3601
+
3602
+       // 1. Can't merge anything that's already merged
3603
+       if ((a|b) & 0x80000000)
3604
+               return 0;
3605
+       ZIP_OPCODE      opa, opb;
3606
+       ZIP_CONDITION   ac, bc;
3607
+       int     imma, immb;
3608
+
3609
+       // Get the 5-bit operands for each
3610
+       opa = (a>>22)&0x1f;
3611
+       opb = (b>>22)&0x1f;
3612
+
3613
+       // 2. Can only merge if both are unconditional
3614
+       ac = ((a>>19)&0x07);
3615
+       bc = ((b>>19)&0x07);
3616
+       if ((opa != ZIPO_LDI)&&(opa != ZIPO_LDIn)&&(ac != ZIPC_ALWAYS))
3617
+               return 0;
3618
+       if ((opb != ZIPO_LDI)&&(opb != ZIPO_LDIn)&&(bc != ZIPC_ALWAYS))
3619
+               return 0;
3620
+
3621
+       // Only some instructions can be merged
3622
+       switch(opa) {
3623
+               case ZIPO_SUB: case ZIPO_AND: case ZIPO_ADD: case ZIPO_CMP:
3624
+               case ZIPO_LW:  case ZIPO_SW:  case ZIPO_LDI: case ZIPO_MOV:
3625
+               case ZIPO_LDIn:
3626
+                       break;
3627
+               default:
3628
+                       return 0;
3629
+       } switch(opb) {
3630
+               case ZIPO_SUB: case ZIPO_AND: case ZIPO_ADD: case ZIPO_CMP:
3631
+               case ZIPO_LW:  case ZIPO_SW:  case ZIPO_LDI: case ZIPO_MOV:
3632
+               case ZIPO_LDIn:
3633
+                       break;
3634
+               default:
3635
+                       return 0;
3636
+       }
3637
+
3638
+       // Prohibit moves to/from user regs to merge
3639
+       if ((opa == ZIPO_MOV)&&(a & 0x44000))
3640
+               return 0;
3641
+       if ((opb == ZIPO_MOV)&&(b & 0x44000))
3642
+               return 0;
3643
+       imma = zip_non_cis_immediate(a);
3644
+       immb = zip_non_cis_immediate(b);
3645
+
3646
+       if (!fits_within(8,imma)) {
3647
+               // fprintf(stderr, "As immediate is out of range\n");
3648
+               return 0;
3649
+       } if (!fits_within(8,immb)) {
3650
+               // fprintf(stderr, "Bs immediate is out of range\n");
3651
+               return 0;
3652
+       }
3653
+
3654
+       // if abreg & 0x010, or bbreg & 0x010, then the register is being
3655
+       // used.
3656
+       int aareg = (a>>27)&0x00f;
3657
+       int abreg = (a>>14)&0x01f;
3658
+       int bbreg = (b>>14)&0x01f;
3659
+
3660
+       switch(opa) {
3661
+               case ZIPO_MOV:
3662
+                       if (!fits_within(3,imma))
3663
+                               return 0;
3664
+                       if (aareg == ZIP_CC)
3665
+                               return 0;
3666
+                       break;
3667
+               case ZIPO_LDI: case ZIPO_LDIn:
3668
+                       if (!fits_within(8,imma))
3669
+                               return 0;
3670
+                       if (aareg == ZIP_CC)
3671
+                               return 0;
3672
+                       break;
3673
+               case ZIPO_ADD: case ZIPO_SUB: case ZIPO_AND:
3674
+                       if (aareg == ZIP_CC)
3675
+                               return 0;
3676
+               case ZIPO_CMP:
3677
+                       if ((abreg&0x10)==0) {
3678
+                               if (!fits_within(7,imma)) {
3679
+                                       return 0;
3680
+                               }
3681
+                       } else { // if (abreg&0x10)
3682
+                               if (!fits_within(3,imma))
3683
+                                       return 0;
3684
+                       } break;
3685
+               case ZIPO_LW: case ZIPO_SW:
3686
+                       if (aareg == ZIP_CC)
3687
+                               return 0;
3688
+                       if ((abreg&0x010)==0) {
3689
+                               return 0;
3690
+                       } else if (abreg== 0x10 + ZIP_SP) {
3691
+                               if (!fits_within(7,imma))
3692
+                                       return 0;
3693
+                       } else {
3694
+                               if (!fits_within(3,imma))
3695
+                                       return 0;
3696
+                       } break;
3697
+               default:
3698
+                       fprintf(stderr, "Unknown op, %d\n", opa);
3699
+                       return 0;
3700
+       }
3701
+
3702
+       switch(opb) {
3703
+               case ZIPO_MOV:
3704
+                       if (!fits_within(3,immb)) {
3705
+                               return 0;
3706
+                       } break;
3707
+               case ZIPO_LDI: case ZIPO_LDIn:
3708
+                       if (!fits_within(8,immb)) {
3709
+                               return 0;
3710
+                       } break;
3711
+               case ZIPO_ADD: case ZIPO_SUB: case ZIPO_CMP: case ZIPO_AND:
3712
+                       if ((bbreg&0x10)==0) {
3713
+                               if (!fits_within(7,immb))
3714
+                                       return 0;
3715
+                       } else { // if (bbreg&0x10)
3716
+                               if (!fits_within(3,immb))
3717
+                                       return 0;
3718
+                       } break;
3719
+               case ZIPO_LW: case ZIPO_SW:
3720
+                       if ((bbreg&0x010)==0) {
3721
+                               return 0;
3722
+                       } else if (bbreg== 0x10+ZIP_SP) {
3723
+                               if (!fits_within(7,immb))
3724
+                                       return 0;
3725
+                       } else {
3726
+                               if (!fits_within(3,immb))
3727
+                                       return 0;
3728
+                       } break;
3729
+               default:
3730
+                       return 0;
3731
+       }
3732
+
3733
+       return 1;
3734
+}
3735
+
3736
+static unsigned
3737
+zip_insn_merge(const unsigned a, const unsigned b)
3738
+{
3739
+       // 1. We already know we can merge these, so skip our can-merge checks
3740
+       ZIP_OPCODE      opa, opb;
3741
+       unsigned int    retv = 0;
3742
+
3743
+       // Get our two opcodes
3744
+       opa = (a>>22)&0x1f; opb = (b>>22)&0x1f;
3745
+
3746
+       // Truncate LDI opcodes back to their original values
3747
+       if (opa == 0x019) opa = 0x018;
3748
+       if (opb == 0x019) opb = 0x018;
3749
+       retv = 0x80008000;
3750
+
3751
+       // Start with the destination registers
3752
+       retv |= (a & 0x78000000);
3753
+       retv |= (b & 0x78000000) >> (27-11);
3754
+
3755
+       // Then the new OpCodes
3756
+       switch(opa) {
3757
+       case ZIPO_SUB:  retv |= (ZIPV_SUB<<24); break;
3758
+       case ZIPO_AND:  retv |= (ZIPV_AND<<24); break;
3759
+       case ZIPO_ADD:  retv |= (ZIPV_ADD<<24); break;
3760
+       case ZIPO_CMP:  retv |= (ZIPV_CMP<<24); break;
3761
+       case ZIPO_LW:   retv |= (ZIPV_LW <<24); break;
3762
+       case ZIPO_SW:   retv |= (ZIPV_SW <<24); break;
3763
+// 8e40
3764
+// 1.0001.110_0100_0000
3765
+       case ZIPO_LDI:  retv |= (ZIPV_LDI<<24); break;
3766
+       case ZIPO_MOV:  retv |= (ZIPV_MOV<<24); break;
3767
+       default: gas_assert(0);
3768
+       }
3769
+
3770
+       switch(opb) {
3771
+       case ZIPO_SUB:  retv |= (ZIPV_SUB<<8); break;
3772
+       case ZIPO_AND:  retv |= (ZIPV_AND<<8); break;
3773
+       case ZIPO_ADD:  retv |= (ZIPV_ADD<<8); break;
3774
+       case ZIPO_CMP:  retv |= (ZIPV_CMP<<8); break;
3775
+       case ZIPO_LW:   retv |= (ZIPV_LW <<8); break;
3776
+       case ZIPO_SW:   retv |= (ZIPV_SW <<8); break;
3777
+       case ZIPO_LDI:  retv |= (ZIPV_LDI<<8); break;
3778
+       case ZIPO_MOV:  retv |= (ZIPV_MOV<<8); break;
3779
+       default: gas_assert(0);
3780
+       }
3781
+
3782
+       // The new CIS has no condition codes
3783
+
3784
+       // Now for OpB, instruction A
3785
+       if (opa == ZIPO_LDI)
3786
+               retv |= (a & 0xff)<<16;
3787
+       else if (opa == ZIPO_MOV) {
3788
+               retv |= 1<<23;                  // Using a register? always4mov
3789
+               retv |= ((a>>14)&0x0f)<<19;     // OpB register
3790
+               retv |= (a & 0x7)<<16;          // Offset
3791
+       } else if(((opa == ZIPO_LW)||(opa == ZIPO_SW))
3792
+                       &&(((a>>14)&0x1f)==0x10 + ZIP_SP)) {
3793
+               // 7-bit immediate for loads or stores referencing the stack
3794
+               retv |= (a & 0x07f)<<16;
3795
+       } else if ((a>>18)&1) {
3796
+               // OpB ... with a register
3797
+               retv |= 1<<23;                  // Using a register?
3798
+               retv |= ((a>>14)&0x0f)<<19;     // OpB register
3799
+               retv |= (a&0x07)<<16;           // OpB constant
3800
+       } else {
3801
+               // OpB ... with constant offsets only
3802
+               retv |= (a&0x07f)<<16;
3803
+       }
3804
+
3805
+
3806
+       // Now for OpB, instruction B
3807
+       if (opb == ZIPO_LDI)
3808
+               retv |= (b & 0xff);
3809
+       else if (opb == ZIPO_MOV) {
3810
+               retv |= (1<<7);                 // Using a register? always4mov
3811
+               retv |= ((b>>14)&0x0f)<<3;      // OpB register
3812
+               retv |= (b & 0x7);              // Offset
3813
+       } else if(((opb == ZIPO_LW)||(opb == ZIPO_SW))
3814
+                       &&(((b>>14)&0x1f)==0x10 + ZIP_SP)) {
3815
+               retv |= (b & 0x07f);
3816
+       } else if ((b>>18)&1) {
3817
+               // OpB ... with a register
3818
+               retv |= 1<<7;                   // Using a register?
3819
+               retv |= ((b>>14)&0x0f)<<3;      // OpB register
3820
+               retv |= (b&0x07);               // OpB constant
3821
+       } else {
3822
+               // OpB ... with constant offsets only
3823
+               retv |= (b&0x07f);
3824
+       }
3825
+
3826
+       return retv;
3827
+}
3828
+
3829
+void
3830
+zip_check_label(symbolS *label ATTRIBUTE_UNUSED)
3831
+{
3832
+       // On any symbol, we need to make sure that we can jump to this
3833
+       // address, therefore we cannot merge the previous instruction with
3834
+       // another one that might follow.
3835
+       cis_mergable = FALSE;
3836
+       //
3837
+       // Likewise, our shadow virtual machine values may be ... unknown
3838
+       // upon any jump to this location.  Hence, we declare them unknown
3839
+       // here.
3840
+       zip_clear_machine(&zipm);
3841
+}
3842
+
3843
+// UNITS:
3844
+//     Offset  (target byte units)
3845
+//     Address (host byte units)
3846
+//     Sym     (target byte units)
3847
+//     Stretch (target byte units)
3848
+//
3849
+static void
3850
+zip_assemble_insn_words(fragS *fragP, segT seg, ZIPIS *insn, int relax_state,
3851
+               long stretch, MACHINEREGS *pzipm)
3852
+{
3853
+#ifdef ZIP_DEBUG
3854
+fprintf(stderr, "ZIP-ASSEMBLE-INSN-WORDS\n");
3855
+       zip_dump_insn(insn);
3856
+       if ((insn->i_rp)||(relax_state))
3857
+               zip_dump_sym(insn->i_rp->r_sym);
3858
+#endif
3859
+       unsigned long   symv = 0;
3860
+       int     sym_defined = 0, this_segment = 0, sym_known = 0;
3861
+       symbolS *sym = NULL;
3862
+       unsigned        immv = insn->i_imm;
3863
+
3864
+       if (insn->i_rp) {
3865
+               fragS   *sym_frag;
3866
+
3867
+               sym = insn->i_rp->r_sym;
3868
+               symv = ((sym)&&(S_IS_DEFINED(sym))) ? (S_GET_VALUE(sym)) : 0;
3869
+               sym_frag = symbol_get_frag(sym);
3870
+               this_segment = (S_GET_SEGMENT(sym) == seg);
3871
+
3872
+#ifdef ZIP_DEBUG
3873
+               fprintf(stderr, "SYMV(%s) = %08lx + %08lx -> %08lx\n",
3874
+                       S_GET_NAME(sym),
3875
+                       S_GET_VALUE(sym), fragP->fr_offset,
3876
+                       S_GET_VALUE(sym) + fragP->fr_offset);
3877
+#endif
3878
+               symv += fragP->fr_offset;
3879
+               // The immediate value has been included in the fragP->fr_offset
3880
+               // So, to keep us from applying it twice, we'll zero it here.
3881
+               immv = 0;
3882
+
3883
+#ifdef ZIP_DEBUG
3884
+               { int this_frag = (sym_frag == fragP);
3885
+               fprintf(stderr, "Determined symbol is %sin this frag, and %sin this segment\n", (this_frag)?"":"not ", (this_segment)?"":"not ");
3886
+               }
3887
+#endif
3888
+
3889
+               if ((stretch != 0)
3890
+                       &&( sym_frag->relax_marker != fragP->relax_marker)
3891
+                       &&(this_segment)) {
3892
+                       if ((stretch < 0)
3893
+                               ||(sym_frag->region == fragP->region))
3894
+                               symv += stretch;
3895
+                       else if (symv < fragP->fr_address)
3896
+                               symv = fragP->fr_next->fr_address;
3897
+               }
3898
+       }
3899
+
3900
+       // At this point, if the symbol is "defined" that only means that
3901
+       // the address is known--not that we can know it via GET_VALUE above
3902
+       // here.  There are a couple of possibilities: it could be a known
3903
+       // offset into a fragment, it could be a known offset into a segment,
3904
+       // it could be a known memory address, or it could be a known value.
3905
+       //
3906
+       // If the value is an offset into our current fragment, then we can
3907
+       // get at it via PC relative addressing.
3908
+       //
3909
+       // If the symbol is an offset into our current segment, often the
3910
+       // .text segment, we may also be able to get to it via PC relative
3911
+       // addressing.  However, we won't know until the fragment's are placed
3912
+       // together to create this segment.  This will be before writing
3913
+       // the file to disk.
3914
+       //
3915
+       // If the symbol is in the absolute segment, then we should try to
3916
+       // get to it via an absolute 32-bit offset reference--since we don't
3917
+       // know (and won't know until the final link) where we are currently
3918
+       // located within memory.
3919
+       //
3920
+       // The same is true of the undefined segment--we just don't know any
3921
+       // PC offsets to that segment.
3922
+       //
3923
+       // But if the address is to a GOT segment, we should be able to assume
3924
+       // it's offset from the beginning of that segment.
3925
+       //
3926
+       //
3927
+       if ((relax_state)&&(insn->i_rp))
3928
+               sym_defined = S_IS_DEFINED(insn->i_rp->r_sym);
3929
+
3930
+       /*
3931
+       sym_known = (sym_defined)&&
3932
+                       ((S_GET_SEGMENT(sym) == absolute_section)
3933
+                       ||(S_GET_SEGMENT(sym) == expr_section)
3934
+                       ||(this_frag)
3935
+                       ||((this_segment)&&(fragP->fr_address != 0))
3936
+                       );
3937
+       */
3938
+       sym_known = (sym_defined)&&(insn->i_rp->r_pcrel)&&(this_segment);
3939
+       if ((!sym_known)&&(sym_defined)&&(!S_FORCE_RELOC(sym, 0))) {
3940
+               if (this_segment)
3941
+                       sym_known = 1;
3942
+               else if (S_GET_SEGMENT(sym)==absolute_section)
3943
+                       sym_known = 1;
3944
+       }
3945
+#ifdef ZIP_DEBUG
3946
+       if (sym_known)
3947
+               fprintf(stderr, "%08lx@%08lx/%08lx - SYM(%s)-KNOWN %s%s%s%s%s\n",
3948
+                       (unsigned long)fragP->fr_literal,
3949
+                       fragP->fr_address,
3950
+                       (unsigned long)symv, S_GET_NAME(sym),
3951
+                       (S_GET_SEGMENT(sym) == absolute_section)?" abs":"",
3952
+                       (S_GET_SEGMENT(sym) == expr_section)?" expr":"",
3953
+                       (symbol_get_frag(sym)==fragP)?" this-frag ":"",
3954
+                       ((this_segment)&&(fragP->fr_address != 0))?" this-seg ":"",
3955
+                       insn->i_rp->r_pcrel?" (PC-REL)":" (ABS)");
3956
+       else if (insn->i_rp)
3957
+               fprintf(stderr, "%08lx@%08lx/%08lx - SYM(%s) -- not known (yet) %s%s%s%s%s%s\n",
3958
+                       (unsigned long)fragP->fr_literal, fragP->fr_address,
3959
+                       (unsigned long)symv, S_GET_NAME(sym),
3960
+                       (!sym_defined)?"-- not defined":"",
3961
+                       (S_GET_SEGMENT(sym) == absolute_section)?" abs":"",
3962
+                       (S_GET_SEGMENT(sym) == expr_section)?" expr":"",
3963
+                       (symbol_get_frag(sym)==fragP)?" this-frag ":"",
3964
+                       (this_segment)?" this-seg ":"",
3965
+                       ((this_segment)&&(fragP->fr_address != 0))?" this-off ":""
3966
+                       );
3967
+
3968
+       fprintf(stderr, "SYM-DEF %d,%d,%d,%d, IMM = %08x\n",
3969
+               sym_defined, sym_known,
3970
+               (insn->i_rp)&&(symbol_get_frag(insn->i_rp->r_sym)==fragP)?1:0,
3971
+               this_segment, insn->i_imm);
3972
+#endif
3973
+       switch(insn->i_op) {
3974
+       case ZIPO_LDI: // May or may not be conditional
3975
+               if ((sym_known)&&(this_segment)
3976
+                       &&(fits_within(13,immv+symv-fragP->fr_address-insn->i_rp->r_fr_offset-sizeof(uint32_t)))) {
3977
+                       // Turn this into a MOV x(PC),Rx
3978
+                       insn->i_breg = ZIP_PC;
3979
+                       insn->i_op = ZIPO_MOV;
3980
+                       insn->i_naux = 0;
3981
+                       zip_assemble_insn_words(fragP, seg, insn, relax_state,
3982
+                               stretch, pzipm);
3983
+                       // Tested--this works
3984
+                       return;
3985
+               }
3986
+
3987
+               // 0.111.x111.11
3988
+               insn->i_aux[0] = 0x7fc00000; // NOOP -- if never used.
3989
+               immv += symv;
3990
+               if (((!insn->i_rp)||(sym_known))
3991
+                               &&(insn->i_cnd == ZIPC_ALWAYS)
3992
+                               &&(fits_within(23, immv))) {
3993
+                       insn->i_naux = 0;
3994
+                       insn->i_code = LDIOP(immv,insn->i_areg);
3995
+               } else if (((!insn->i_rp)||(sym_known))
3996
+                               &&(fits_within(18, zip_brev(immv)))) {
3997
+                       // Can we do this with a BREV instruction using an
3998
+                       // immediate?  If so, we can then conditionally load
3999
+                       // the top 18 bist of any value ...
4000
+                       //
4001
+                       insn->i_naux = 0;
4002
+                       insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd,
4003
+                                       zip_brev(immv),
4004
+                                       insn->i_areg&0x0f);
4005
+                       if (insn->i_rp)
4006
+                               insn->i_rp->r_type = BFD_RELOC_NONE;
4007
+// 0000 1110 0000 0000 0000 0000 0100 0000
4008
+               } else if (((!insn->i_rp)||(sym_known))
4009
+                               &&(insn->i_cnd == ZIPC_ALWAYS)
4010
+                               &&(fits_within(23, immv))) {
4011
+                       insn->i_naux = 0;
4012
+                       insn->i_code = LDIOP(immv,insn->i_areg);
4013
+               } else if ((zip_param_use_machine)&&(pzipm)&&((!insn->i_rp)||(sym_known))
4014
+                       &&(pzipm->r[insn->i_areg].m_known)
4015
+                       &&(0==((immv^pzipm->r[insn->i_areg].m_value)
4016
+                                       & 0x0ffff0000))) {
4017
+                       // Replace LDI with LDILO
4018
+                       insn->i_naux = 0;
4019
+                       insn->i_code=IMMOP(ZIPO_LDILO, insn->i_cnd,
4020
+                                       (immv&0x0ffff), insn->i_areg);
4021
+
4022
+                       pzipm->r[insn->i_areg].m_value = immv;
4023
+                       if (ZIPC_ALWAYS == insn->i_cnd) {
4024
+                               // Henceforth, we only know the bottom 16bits
4025
+                               // of this register
4026
+                               pzipm->r[insn->i_areg].m_known = MACH_VUPPERKNOWN;
4027
+                       } else
4028
+                               pzipm->r[insn->i_areg].m_known = MACH_VKNOWN;
4029
+               } else {
4030
+                       //
4031
+                       // If the symbol isn't defined, then any immv value
4032
+                       // will work--we have to come back anyway.
4033
+                       //
4034
+                       int known_bypass = 0, i;
4035
+
4036
+                       if ((zip_param_use_machine)&&(pzipm)&&(
4037
+                                       ((!insn->i_rp)
4038
+                                               &&(!fits_within(4,immv)))
4039
+                                       ||((insn->i_rp)&&(sym_known)))) {
4040
+                               for(i=0; i<14; i++) {
4041
+                                       int offset = immv-pzipm->r[i].m_value;
4042
+                                       if ((pzipm->r[i].m_known==MACH_VKNOWN)
4043
+                                               &&(fits_within(13, offset))
4044
+                                               &&((insn->i_rp)
4045
+                                                       ||(!fits_within(4, immv)))
4046
+                                               ) {
4047
+                                               // Pick the closest value ... if
4048
+                                               // there's a choice
4049
+                                               if ((!known_bypass)
4050
+                                                       ||(abs(offset)<known_bypass))
4051
+                                                       continue;
4052
+                                               insn->i_naux = 0;
4053
+                                               insn->i_op = ZIPO_MOV;
4054
+                                               insn->i_breg = i;
4055
+                                               insn->i_imm = offset;
4056
+
4057
+                                               insn->i_code = SMPLMOV(
4058
+                                                       insn->i_cnd, offset,
4059
+                                                       i, insn->i_areg);
4060
+                                               known_bypass = abs(offset);
4061
+                                               if (known_bypass==0)
4062
+                                                       known_bypass = 1;
4063
+                                       }
4064
+                               } known_bypass = (known_bypass)?1:0;
4065
+                       } if (!known_bypass) {
4066
+                               // BREV Extension would modify this statement
4067
+                               insn->i_naux = 1;
4068
+                               insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd,
4069
+                                       zip_brev(immv)&0x01ffff, insn->i_areg);
4070
+                               insn->i_aux[0]=IMMOP(ZIPO_LDILO, insn->i_cnd,
4071
+                                       (immv&0x0ffff), insn->i_areg);
4072
+                               if (insn->i_rp)
4073
+                                       insn->i_rp->r_type = BFD_RELOC_ZIP_LDI;
4074
+                               else if ((zip_param_cis)&&(zip_can_merge(insn->i_code, insn->i_aux[0]))) {
4075
+                                       insn->i_code = zip_insn_merge(insn->i_code, insn->i_aux[0]);
4076
+                                       insn->i_naux = 0;
4077
+                               }
4078
+                       } else {
4079
+fprintf(stderr, "known-bypass\n");
4080
+                       }
4081
+               }
4082
+#ifdef ZIP_DEBUG
4083
+               fprintf(stderr, "LDI %04x:%04x,%d Instruction assembled into %08x : %08x\n",
4084
+                       (immv>>16)&0x0ffff,
4085
+                       immv & 0x0ffff, insn->i_areg,
4086
+                       insn->i_code, insn->i_aux[0]);
4087
+#endif
4088
+               break;
4089
+       case ZIPO_BRA: // Includes both conditional and unconditional branches
4090
+#ifdef ZIP_DEBUG
4091
+               fprintf(stderr, "ZIPO--BRA (ADDR = %08lx, OFFSET = %08lx)\n",
4092
+                               fragP->fr_address,
4093
+                               (insn->i_rp)?insn->i_rp->r_fr_offset:0);
4094
+#endif
4095
+               if (insn->i_rp)
4096
+                       immv += (int)(symv
4097
+                               - fragP->fr_address
4098
+                               - (insn->i_rp->r_fr_offset+sizeof(uint32_t)));
4099
+
4100
+#ifdef ZIP_DEBUG
4101
+               if (!fits_within(18,immv))
4102
+                       fprintf(stderr, "doesn't fit in 18 bits\n");
4103
+#endif
4104
+               if (zip_param_small) {
4105
+                       //
4106
+                       // We can fit (or so we are told), so short jump code
4107
+                       // to an unknown location ...
4108
+                       //
4109
+                       insn->i_naux = 0;
4110
+                       insn->i_aux[0] = NOOP_OPCODE;
4111
+                       insn->i_aux[1] = NOOP_OPCODE;
4112
+                       insn->i_code = IMMOP(ZIPO_ADD, insn->i_cnd,
4113
+                               immv, ZIP_PC); // Add value to PC
4114
+                       insn->i_rp->r_pcrel = TRUE;
4115
+                       // No relocation is required--we just did it
4116
+                       insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_PCREL;
4117
+                       // Tested--this works
4118
+               } else if ((!sym_known)||(!fits_within(18,immv))) {
4119
+                       insn->i_op = ZIPO_LJMP;
4120
+
4121
+                       zip_assemble_insn_words(fragP, seg, insn, relax_state, stretch, pzipm);
4122
+                       insn->i_op = ZIPO_BRA;
4123
+               } else {
4124
+                       //
4125
+                       // We can fit, so short jump code ...
4126
+                       //
4127
+                       insn->i_naux = 0;
4128
+                       insn->i_aux[0] = NOOP_OPCODE;
4129
+                       insn->i_aux[1] = NOOP_OPCODE;
4130
+                       insn->i_code = IMMOP(ZIPO_ADD, insn->i_cnd,
4131
+                               immv, ZIP_PC); // Add value to PC
4132
+                       insn->i_rp->r_pcrel = TRUE;
4133
+                       // No relocation is required--we just did it
4134
+                       insn->i_rp->r_type = BFD_RELOC_NONE;
4135
+               }
4136
+#ifdef ZIP_DEBUG
4137
+               fprintf(stderr, "BRA %08lx->%08x(%d,%d) assembled into(%d) %08x : %08x : %08x\n",
4138
+                       symv, immv, sym_defined, relax_state,
4139
+                       insn->i_naux, insn->i_code,
4140
+                       insn->i_aux[0], insn->i_aux[1]);
4141
+#endif
4142
+               break;
4143
+       case    ZIPO_LJMP:
4144
+               //
4145
+               // Long jump code
4146
+               //
4147
+               // I expect this to be true, since we should always
4148
+               // be branching (or jumping) to a location defined by a
4149
+               // symbol.
4150
+               if (insn->i_rp) {
4151
+                       insn->i_rp->r_pcrel = FALSE;
4152
+                       insn->i_rp->r_type = BFD_RELOC_ZIP_VALUE;
4153
+               } insn->i_breg = ZIP_RNONE;
4154
+#ifdef ZIP_DEBUG
4155
+               fprintf(stderr, "LJMP IMM = %08x = %d\n", immv, immv);
4156
+#endif
4157
+               if (insn->i_cnd == ZIPC_ALWAYS) {
4158
+                       insn->i_naux = 1;
4159
+                       insn->i_code=DBLREGOP(ZIPO_LW,ZIPC_ALWAYS,
4160
+                               0,ZIP_PC,ZIP_PC); // Load into PC register
4161
+                       insn->i_aux[0] = 0; // Value to load
4162
+               } else {
4163
+                       // A conditional long jump
4164
+                       insn->i_naux = 2;
4165
+                       insn->i_code=DBLREGOP(ZIPO_LW,insn->i_cnd,
4166
+                               1,ZIP_PC,ZIP_PC); // Conditional load to PC
4167
+                       insn->i_aux[0]=IMMOP(ZIPO_ADD,ZIPC_ALWAYS,
4168
+                               1,ZIP_PC); // Skip an instruction
4169
+                       insn->i_aux[1] = 0;
4170
+               } if (!insn->i_rp)
4171
+                       insn->i_aux[insn->i_naux-1] = immv;
4172
+               break;
4173
+       case ZIPO_MOV:
4174
+               //
4175
+               // We could go a little wild here:
4176
+               //      MOV val,Rx
4177
+               // Could be quietly compiled into
4178
+               //      LDI val,Rx      (if Rx is not a user register)
4179
+               // whereas
4180
+               //      MOV BIGVAL(Ry),Rx
4181
+               // could be quietly compiled into
4182
+               //      LDI BIGVAL,Rx
4183
+               //      ADD.Z Ry,Rx     (Note the contortions to avoid adjusting
4184
+               //      ADD.NZ Ry,Rx    ... the flag bits)
4185
+               // This would give us access to full 32-bit offsets ...
4186
+               // as long as neither Rx nor Ry was a user register.  On the
4187
+               // other hand, if we knew the flag bits would be set between
4188
+               // now and the next conditional instruction, we could do a
4189
+               //      LDI BIGVAL,Rx
4190
+               //      ADD Ry,Rx
4191
+               // and be okay with it.
4192
+               //
4193
+               // For now we just handle our normal 13 bit signed immediate
4194
+               //      offsets.
4195
+               //
4196
+               if (insn->i_rp) {
4197
+                       // MOV label(Rb),Ra
4198
+                       insn->i_rp->r_pcrel = (insn->i_breg == ZIP_PC);
4199
+                       immv += symv;
4200
+                       if (insn->i_breg == ZIP_PC) {
4201
+                               immv +=(int)(-fragP->fr_address
4202
+                                               -insn->i_rp->r_fr_offset-sizeof(uint32_t));
4203
+                               immv >>= 2;
4204
+                               if ((sym_known)&&(this_segment)) {
4205
+                                       // Tested--this works
4206
+                                       insn->i_rp->r_type = BFD_RELOC_NONE;
4207
+                               } else {
4208
+#ifdef ZIP_DEBUG
4209
+                                       fprintf(stderr, "ZIP_MOV_PCREL relocation needed for %s, pcrel = %d\n", S_GET_NAME(sym), insn->i_rp->r_pcrel);
4210
+#endif
4211
+                                       insn->i_rp->r_type = BFD_RELOC_ZIP_MOV_PCREL;
4212
+                               }
4213
+
4214
+
4215
+//                     } else if((zip_param_got)&&(insn->i_breg == ZIP_GBL)) {
4216
+//                             immv = symv;
4217
+//                             insn->i_rp->r_type = BFD_RELOC_ZIP_MOV_GOTREL;
4218
+//                             as_bad("MOV x(GOT),Ry not yet implemented");
4219
+                       } else {
4220
+                               // Do we really want to assume this is an
4221
+                               // address?
4222
+                               insn->i_rp->r_type = BFD_RELOC_ZIP_MOV_OFFSET;
4223
+                       }
4224
+               } else if ((zip_param_use_machine)&&(pzipm)
4225
+                               &&(insn->i_breg<ZIP_CC)&&(insn->i_areg<ZIP_CC)
4226
+                               &&(ZIPC_ALWAYS == insn->i_cnd)
4227
+                               &&(pzipm->r[insn->i_breg].m_known==MACH_VKNOWN)
4228
+                               &&(fits_within(4,pzipm->r[insn->i_breg].m_value
4229
+                                       +immv))) {
4230
+                       // MOV Rb,Ra
4231
+                       // turn this into an LDI instruction, rather than a
4232
+                       // move instruction
4233
+                       insn->i_op = ZIPO_LDI;
4234
+                       insn->i_imm += pzipm->r[insn->i_breg].m_value;
4235
+                       insn->i_breg = ZIP_RNONE;
4236
+
4237
+                       insn->i_code = LDIOP(insn->i_imm, insn->i_areg);
4238
+                       insn->i_naux = 0;
4239
+               }
4240
+               /*
4241
+               // Handle offsets greater than 13 bits --- up to 32 bits
4242
+               // Only works if we have no symbol in question, and when the
4243
+               // target isn't the PC register (or CC for that matter).
4244
+               else if ((!fits_within(13,insn->i_imm))
4245
+                               &&(insn->i_areg < ZIP_CC)
4246
+                               &&(insn->i_breg < ZIP_CC)) {
4247
+                       // Alternate instruction sequence:
4248
+                       //      but .... these make conditional insns from
4249
+                       //              unconditional!!
4250
+                       //      MOV.always A,Rx -> LDI A,Rx
4251
+                       //      MOV.always A(Ry),Rx -> LDI A,Rx, ADD Ry,Rx
4252
+                       // this works for conditional moves, since ADD.C
4253
+                       // doesn't set conditions
4254
+                       //      MOV.C A(Ry),Rx -> LDI.C A,Rx, ADD.C Ry,Rx
4255
+
4256
+                       return;
4257
+               }
4258
+               */
4259
+
4260
+               if (insn->i_op == ZIPO_MOV) { // If we haven't changed insns,
4261
+                       gas_assert(fits_within(13, insn->i_imm));
4262
+                       insn->i_code = SMPLMOV(insn->i_cnd, immv, insn->i_breg,
4263
+                                       insn->i_areg);
4264
+                       //
4265
+                       // Now for the extra two register bits only present
4266
+                       // in move instructions
4267
+                       //
4268
+                       insn->i_code |= (insn->i_areg&0x10)?0x40000:0;
4269
+                       insn->i_code |= (insn->i_breg&0x10)?0x02000:0;
4270
+               }
4271
+#ifdef ZIP_DEBUG
4272
+               fprintf(stderr, "MOV Instruction assembled into %08x\n", insn->i_code);
4273
+#endif
4274
+               break;
4275
+       case ZIPO_NEG:
4276
+               insn->i_naux = 1;
4277
+               if (insn->i_rp)
4278
+                       as_bad("NEG cannot handle symbols");
4279
+               gas_assert(fits_within(13, -1+insn->i_imm));
4280
+               insn->i_code = SMPLMOV(insn->i_cnd,
4281
+                       (-1+immv), insn->i_breg, insn->i_areg);
4282
+               insn->i_code &= 0xfffbdfff;
4283
+               insn->i_aux[0] = IMMOP(ZIPO_XOR, insn->i_cnd, -1,
4284
+                       insn->i_areg);
4285
+               // printf("NEG Instruction assembled into %08x:%08x\n",
4286
+                       // insn->i_code, insn->i_aux[0]);
4287
+               break;
4288
+       case ZIPO_BREAK: case ZIPO_LOCK: case ZIPO_SIM: case ZIPO_NOOP:
4289
+               if (insn->i_cnd != ZIPC_ALWAYS)
4290
+                       as_bad("NOOP/BREAK/LOCK/SIM instructions cannot handle conditions\n");
4291
+               insn->i_code = NOOPGROUP(insn->i_op, insn->i_imm);
4292
+               insn->i_naux = 0;
4293
+               break;
4294
+       case    ZIPO_SDUMP: case ZIPO_NDUMP: case ZIPO_SEXIT: case ZIPO_NEXIT:
4295
+       case    ZIPO_SOUT:  case ZIPO_NOUT:
4296
+               // These instructions *should*ve been turned into NOOP and SIM
4297
+               // instructions by now.  Getting here with them is therefore
4298
+               // an error.
4299
+               gas_assert(0);
4300
+       case ZIPO_SEXTB: {
4301
+               insn->i_naux = 1;
4302
+               insn->i_code   = IMMOP(ZIPO_LSL, insn->i_cnd, 24, insn->i_areg);
4303
+               insn->i_aux[0] = IMMOP(ZIPO_ASR, insn->i_cnd, 24, insn->i_areg);
4304
+               } break;
4305
+       case ZIPO_SEXTH: {
4306
+               insn->i_naux = 1;
4307
+               insn->i_code   = IMMOP(ZIPO_LSL, insn->i_cnd, 16, insn->i_areg);
4308
+               insn->i_aux[0] = IMMOP(ZIPO_ASR, insn->i_cnd, 16, insn->i_areg);
4309
+               } break;
4310
+       case ZIPO_JSR:
4311
+               if ((zip_param_cis)&&(insn->i_cnd == ZIPC_ALWAYS)
4312
+                               &&(insn->i_rp)) {
4313
+                       insn->i_op = ZIPO_LJSR;
4314
+                       zip_assemble_insn_words(fragP, seg, insn, relax_state, stretch, pzipm);
4315
+                       insn->i_op = ZIPO_JSR;
4316
+               } else if ((zip_param_cis)&&(insn->i_cnd == ZIPC_ALWAYS)
4317
+                               &&(insn->i_breg != ZIP_RNONE)
4318
+                               &&(insn->i_imm == 0)) {
4319
+                       // JSR (Register)
4320
+                       insn->i_naux = 0;
4321
+                       insn->i_code = 0x80008000
4322
+                               | (ZIPV_MOV<<24)
4323
+                               | 0x00f90000    // MOV OpB = PC+1
4324
+                               | 0x0f880       // MOV into PC
4325
+                               | ((insn->i_breg&0x0f)<<3)
4326
+                               | (ZIPV_MOV << 8); // The LW instruction
4327
+
4328
+                       gas_assert(!insn->i_rp);
4329
+               } else if ((!insn->i_rp)&&(insn->i_breg != ZIP_RNONE)) {
4330
+                       gas_assert(fits_within(13,immv));
4331
+                       // JSR offset+register, implemented as two moves
4332
+                       insn->i_naux = 1;
4333
+                       insn->i_code = SMPLMOV(insn->i_cnd, 1, ZIP_PC, ZIP_LR);
4334
+                       insn->i_aux[0] = SMPLMOV(insn->i_cnd, immv, insn->i_breg, ZIP_PC);
4335
+                       insn->i_aux[1] = NOOP_OPCODE;
4336
+               } else {
4337
+                       if (insn->i_rp)
4338
+                               immv += (int)(symv
4339
+                                       - fragP->fr_address
4340
+                                       - (insn->i_rp->r_fr_offset+sizeof(uint32_t)));
4341
+                       if ((zip_param_small)||((sym_known)&&(fits_within(18,immv-4)))) {
4342
+                               // MOV.C 1(PC),R0
4343
+                               // BRA.C _somewhere_
4344
+                               insn->i_naux = 1;
4345
+                               insn->i_code = SMPLMOV(insn->i_cnd, 1, ZIP_PC,
4346
+                                       ZIP_LR);
4347
+                               // Bias the branch by -4, since we're one word
4348
+                               // into this instruction
4349
+                               insn->i_aux[0] = IMMOP(ZIPO_ADD, insn->i_cnd,
4350
+                                       immv-4, ZIP_PC);
4351
+                               insn->i_aux[1] = NOOP_OPCODE;
4352
+                               insn->i_rp->r_pcrel = TRUE;
4353
+                               insn->i_rp->r_type = BFD_RELOC_NONE;
4354
+                       } else {
4355
+                               // If all else fails, call for a long JSR
4356
+                               insn->i_op = ZIPO_LJSR;
4357
+                               zip_assemble_insn_words(fragP, seg, insn,
4358
+                                       relax_state, stretch, pzipm);
4359
+                               insn->i_op = ZIPO_JSR;
4360
+                       }
4361
+               } break;
4362
+       case ZIPO_LJSR:
4363
+               if (insn->i_rp)
4364
+                       immv += (int)(symv
4365
+                               - fragP->fr_address
4366
+                               - (insn->i_rp->r_fr_offset+sizeof(uint32_t)));
4367
+               if (insn->i_rp) {
4368
+                       insn->i_rp->r_pcrel = FALSE;
4369
+                       insn->i_rp->r_type = BFD_RELOC_ZIP_VALUE;
4370
+               } insn->i_breg = ZIP_RNONE;
4371
+               if (insn->i_cnd == ZIPC_ALWAYS) {
4372
+                       if (zip_param_cis) {
4373
+                               insn->i_naux = 1;
4374
+                               insn->i_code = 0x80008000
4375
+                                       | (ZIPV_MOV<<24)
4376
+                                       | 0x00fa0000    // MOV OpB = PC+2
4377
+                                       | 0x0f8f8       // (LW) into PC
4378
+                                       | (ZIPV_LW << 8); // The LW instruction
4379
+                               insn->i_aux[0] = 0; // To be filled in with address value
4380
+                       } else { // If unconditional
4381
+                               // MOV 1(PC),R0
4382
+                               // LW (PC),PC
4383
+                               // _somewhere_
4384
+                               insn->i_naux = 2;
4385
+                               insn->i_code = SMPLMOV(insn->i_cnd, 2, ZIP_PC,
4386
+                                       ZIP_LR);
4387
+                               insn->i_aux[0] = DBLREGOP(ZIPO_LW,ZIPC_ALWAYS,
4388
+                                       0,ZIP_PC,ZIP_PC); // Load into PC register
4389
+                               insn->i_aux[1] = 0;
4390
+                       }
4391
+               } else {
4392
+                       // If conditional, naux = 3
4393
+                       // BRA.!cnd (for whatever condition) +3
4394
+                       // MOV 4(PC),R0
4395
+                       // LW (PC),PC
4396
+                       // address
4397
+                       insn->i_naux = 3;
4398
+                       insn->i_aux[2] = 0;
4399
+                       if (insn->i_cnd != ZIPC_V) {
4400
+                               ZIP_CONDITION cnd =
4401
+                                       zip_negate_condition(insn->i_cnd);
4402
+                               insn->i_code = IMMOP(ZIPO_ADD, cnd, 12, ZIP_PC);
4403
+                               insn->i_aux[0] = SMPLMOV(ZIPC_ALWAYS, 2, ZIP_PC,
4404
+                                       ZIP_LR);
4405
+                               insn->i_aux[1] = DBLREGOP(ZIPO_LW, ZIPC_ALWAYS,
4406
+                                       0,ZIP_PC,ZIP_PC); // Load into PC register
4407
+                       } else {
4408
+                               insn->i_code = SMPLMOV(ZIPC_V, 3, ZIP_PC,
4409
+                                       ZIP_LR);
4410
+                               insn->i_aux[0] = DBLREGOP(ZIPO_LW, ZIPC_V,
4411
+                                       0,ZIP_PC,ZIP_PC); // Load into PC register
4412
+                               insn->i_aux[1] = IMMOP(ZIPO_ADD, ZIPC_ALWAYS, 4, ZIP_PC);
4413
+                       }
4414
+               } if (!insn->i_rp)
4415
+                       insn->i_aux[insn->i_naux-1] = immv;
4416
+               break;
4417
+       default:
4418
+               if (insn->i_rp) {
4419
+                       insn->i_rp->r_pcrel = FALSE;
4420
+                       immv += symv;
4421
+                       if (insn->i_breg == ZIP_PC) {
4422
+                               immv+=(int)(-fragP->fr_address
4423
+                                               -insn->i_rp->r_fr_offset-sizeof(uint32_t));
4424
+                               insn->i_rp->r_pcrel= TRUE;
4425
+                               insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_PCREL;
4426
+                               if ((sym_known)&&(this_segment))
4427
+                                       insn->i_rp->r_type = BFD_RELOC_NONE;
4428
+//                     } else if((zip_param_got)&&(insn->i_breg == ZIP_GBL)) {
4429
+//                             as_bad("<OP> x(GOT),Ry not yet implemented");
4430
+//                             immv += symv;
4431
+//                             insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_GOTREL;
4432
+                       } else {
4433
+                               // Do we really want to assume this is an
4434
+                               // address?
4435
+                               immv += symv;
4436
+                               insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_OFFSET;
4437
+                       }
4438
+               } if (insn->i_breg != ZIP_RNONE) {
4439
+                       if (insn->i_breg == ZIP_PC)
4440
+                               immv >>= 2;
4441
+                       if (!fits_within(14, insn->i_imm)) {
4442
+                               fprintf(stderr, "ERR: (%d) 0x%08x does not fit within 18 bits!\n", insn->i_imm, insn->i_imm);
4443
+                               gas_assert(fits_within(14, insn->i_imm));
4444
+                       }
4445
+                       insn->i_code = DBLREGOP(insn->i_op, insn->i_cnd,
4446
+                               immv, insn->i_breg, insn->i_areg);
4447
+                       if (insn->i_rp) {
4448
+                               if (insn->i_breg == ZIP_PC) {
4449
+                                       insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_PCREL;
4450
+                                       insn->i_rp->r_pcrel = TRUE;
4451
+//                             } else if((zip_param_got)&&(insn->i_breg == ZIP_GBL)) {
4452
+//                                     insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_GOTREL;
4453
+                               } else
4454
+                                       insn->i_rp->r_type = BFD_RELOC_ZIP_OPB_OFFSET;
4455
+                       }
4456
+               } else {
4457
+                       if (!fits_within(18, insn->i_imm)) {
4458
+                               fprintf(stderr, "ERR: (%d) 0x%08x does not fit within 18 bits!\n", insn->i_imm, insn->i_imm);
4459
+                               gas_assert(fits_within(18, insn->i_imm));
4460
+                       }
4461
+                       insn->i_code = IMMOP(insn->i_op, insn->i_cnd,
4462
+                               immv, insn->i_areg);
4463
+                       if (insn->i_rp)
4464
+                               insn->i_rp->r_type  = BFD_RELOC_ZIP_OPB_IMM;
4465
+               }
4466
+#ifdef ZIP_DEBUG
4467
+               fprintf(stderr, "Instruction assembled into %08x%s\n", insn->i_code,
4468
+                       (insn->i_rp)?" w/ Symbol":"");
4469
+#endif
4470
+               break;
4471
+       }
4472
+}
4473
+
4474
+void
4475
+md_assemble(char *line) {
4476
+       const char *linep;
4477
+       char    *p;
4478
+
4479
+       linep = (char *)zip_skip_white_spaces(line);
4480
+       if ((strncasecmp(linep, "nstr", 4)==0)
4481
+               ||(strncasecmp(linep, "sstr", 4)==0)) {
4482
+               uint32_t        base;
4483
+               const char      *sbeg;
4484
+
4485
+               if ((linep[0] =='n')||(linep[0] == 'N'))
4486
+                       base = 0x0400 + NOOP_OPCODE;
4487
+               else
4488
+                       base = 0x0400 + SIM_OPCODE;
4489
+
4490
+               sbeg = strchr(line, '\"');
4491
+               if (!sbeg)
4492
+                       as_bad("String instruction with no quotes found");
4493
+               sbeg++;
4494
+               while(*sbeg != '\"') {
4495
+                       unsigned v = *sbeg++;
4496
+                       if (v == '\\') {
4497
+                               switch(*sbeg++) {
4498
+                               case 'a':       v = '\a'; break;
4499
+                               case 'b':       v = '\b'; break;
4500
+                               case 'f':       v = '\f'; break;
4501
+                               case 'n':       v = '\n'; break;
4502
+                               case 'r':       v = '\r'; break;
4503
+                               case 't':       v = '\t'; break;
4504
+                               case '\\':      v = '\\'; break;
4505
+                               case '\"':      v = '\"'; break;
4506
+                               case '\'':      v = '\''; break;
4507
+                               default: sbeg--;
4508
+                               }
4509
+                       }
4510
+                       p = frag_more(sizeof(uint32_t));
4511
+                       md_number_to_chars(p,base+(v&0x0ff),sizeof(uint32_t));
4512
+               }
4513
+
4514
+               return;
4515
+       }
4516
+
4517
+
4518
+       // Decode an instruction from op_str
4519
+       //      Determine the opcode
4520
+       //              any conditions
4521
+       //              the result register
4522
+       //              any immediate
4523
+       //              any "B" register
4524
+       ZIPIS   insnv, *insn = &insnv;
4525
+       const char *error = zip_parse(line, insn);
4526
+
4527
+#ifdef ZIP_DEBUG
4528
+       fprintf(stderr, "ZIP-ASSEMBLE %s\n", line);
4529
+#endif
4530
+
4531
+       if (error) {
4532
+               as_bad("%s \'%s\'", error, line);
4533
+               return;
4534
+       }
4535
+
4536
+       zip_assemble_insn_words(frag_now, now_seg, insn, 0, 0, &zipm);
4537
+       if (zip_param_use_machine)
4538
+               zip_advance_machine(&zipm, insn);
4539
+#ifdef ZIP_DEBUG
4540
+       zip_debug_machine(&zipm);
4541
+#endif
4542
+
4543
+       // Then, if the instruction is valid we ...
4544
+       //      for branches ...
4545
+       //        symbolS *symp = reloc->reloc_expression.X_add_symbol;
4546
+       //        offsetT offset = reloc->reloc_expression.X_add_number;
4547
+       //        char *f;
4548
+       //        f = frag_var(?, 4, 4, BRANCH_SUBTYPE, symp, offset, NULL);
4549
+       //        md_number_to_chars(f, insn->insn_code, 4); // ???
4550
+       //
4551
+       //
4552
+       if ((!insn->i_rp)&&(cis_mergable)&&(insn->i_naux == 0)
4553
+                       &&(frag_now_fix_octets()>=4)) {
4554
+               // ZIPI lcode = md_number_from_chars(p, 4);
4555
+               unsigned int    last_iword;
4556
+               char    *buf;
4557
+
4558
+               buf = &frag_now->fr_literal[frag_now_fix_octets() - 4];
4559
+               last_iword = (buf[3]&0x0ff)|((buf[2]&0x0ff)<<8)
4560
+                       |((buf[1]&0x0ff)<<16)|((buf[0]&0x0ff)<<24);
4561
+               if ((buf >= frag_now->fr_literal)
4562
+                               &&(zip_can_merge(last_iword,insn->i_code))) {
4563
+                       p = buf;
4564
+                       insn->i_code =zip_insn_merge(last_iword, insn->i_code);
4565
+                       md_number_to_chars(p, insn->i_code, sizeof(uint32_t));
4566
+               } else {
4567
+                       p = frag_more(sizeof(uint32_t)*(1+insn->i_naux));
4568
+                       md_number_to_chars(p, insn->i_code, sizeof(uint32_t));
4569
+               }
4570
+       } else {
4571
+               int     i;
4572
+               ZIPRELOC        *rp = insn->i_rp;
4573
+
4574
+               if ((insn->i_naux == 0)||(NULL == insn->i_rp)) {
4575
+                       // If we have no need of any symbols, we come here.
4576
+                       // If we have no need of any extra 4-byte instructions,
4577
+                       // we come here.
4578
+                       p = frag_more(sizeof(uint32_t)*(1+insn->i_naux));
4579
+
4580
+                       if (insn->i_rp) {
4581
+                               // Generate a fixup for when we finally
4582
+                               // know where this symbol links to
4583
+                               insn->i_rp->r_fr_offset =
4584
+                                       (p - frag_now->fr_literal);
4585
+                               insn->i_rp->r_fix = fix_new(frag_now,
4586
+                                       insn->i_rp->r_fr_offset, // where w/in frag?
4587
+                                       4,              // 1,2, or 4 usually ... ??
4588
+                                       insn->i_rp->r_sym, // Add symbol,
4589
+                                       insn->i_imm, // Fixed/known offset to the symbol
4590
+                                       insn->i_rp->r_pcrel, // T if PC-Relative reloc
4591
+                                       insn->i_rp->r_type); // Reloc type
4592
+                               insn->i_rp = NULL;
4593
+                       }
4594
+               } else {
4595
+                       // First, grow our fragment so we know we have the
4596
+                       // size we'll need.
4597
+                       frag_grow(sizeof(uint32_t)*(1+insn->i_naux));
4598
+
4599
+                       // Then p, the place where we'd get more from, is
4600
+                       // where our instruction will be installed.  We know
4601
+                       // there's room for it there now.
4602
+                       p = frag_more(0);
4603
+                       // Record where in the frag our relaxable instruction
4604
+                       // will be installed
4605
+                       insn->i_rp->r_fr_offset = ( p - frag_now->fr_literal );
4606
+                       // Now tell the assembler about what we've done.
4607
+                       // This'll close off the frag as well, so this is the
4608
+                       // last we'll see of this frag--even though frag_now
4609
+                       // may yet point to it (or not) for a while.
4610
+                       frag_var(rs_machine_dependent, // Relaxation type
4611
+                               sizeof(uint32_t)*(1+insn->i_naux),
4612
+                               sizeof(uint32_t)*(1+insn->i_naux),
4613
+                               rs_machine_dependent,   // Subtype
4614
+                               insn->i_rp->r_sym,      // Symbol
4615
+                               insn->i_imm,    // Offset (to be added to symbol)
4616
+                               (char *)zip_copy_insn(insn));   // Opcode
4617
+
4618
+               }
4619
+               md_number_to_chars(p, insn->i_code, sizeof(uint32_t));
4620
+               for(i=0; i< insn->i_naux; i++)
4621
+                       md_number_to_chars(&p[sizeof(uint32_t)*(1+i)], insn->i_aux[i], sizeof(uint32_t));
4622
+
4623
+               if (rp) {
4624
+                       cis_mergable = FALSE;
4625
+               } else {
4626
+                       cis_mergable = (zip_param_cis)&&(insn->i_naux == 0);
4627
+               }
4628
+       }
4629
+#ifdef ZIP_DEBUG
4630
+       zip_dump_insn(insn);
4631
+#endif
4632
+}
4633
+
4634
+/* Turn a string in input_line_pointer into a floating point constant
4635
+ * of type type, and store the appropriate bytes in *LITP.  The number of
4636
+ * LIITTLENUMS emitted is stored in *SIZEP.  An error message is returned, or
4637
+ * NULL on OK.
4638
+ */
4639
+const char     *
4640
+md_atof(int type, char *litP, int *sizeP) {
4641
+       int     prec;
4642
+       LITTLENUM_TYPE  words[4];
4643
+       char    *t;
4644
+       int     i;
4645
+
4646
+       switch(type) {
4647
+       case 'f':
4648
+               prec = 2; break;
4649
+       case 'd':
4650
+               prec = 4; break;
4651
+       default:
4652
+               *sizeP = 0;
4653
+               return _("Unsupported floating point format");
4654
+       }
4655
+
4656
+       t = atof_ieee(input_line_pointer, type, words);
4657
+       if (t)
4658
+               input_line_pointer = t;
4659
+
4660
+       *sizeP = prec * 2;
4661
+
4662
+       for(i=prec-1; i>= 0; i--) {
4663
+               md_number_to_chars(litP, (valueT)words[i], 2);
4664
+               litP += 2;
4665
+       }
4666
+
4667
+       return NULL;
4668
+}
4669
+#define        AS_BAD_FIX(FXP,STR) as_bad_where(FXP->fx_file,FXP->fx_line,_(STR))
4670
+
4671
+/* Apply a fixup to the object file
4672
+ *
4673
+ * This function will only be called once all of the details of the fixup are
4674
+ * known, before the object file heads to the linker (if at all).
4675
+ */
4676
+void
4677
+md_apply_fix(fixS *fixP, valueT *val, segT seg ATTRIBUTE_UNUSED)
4678
+{
4679
+       unsigned int    iword, mask, final_fix;
4680
+
4681
+       final_fix = (fixP->fx_addsy == NULL) ? TRUE : FALSE;
4682
+
4683
+       bfd_byte *buf = (bfd_byte *)&fixP->fx_frag->fr_literal[fixP->fx_where];
4684
+       iword = (buf[3]&0x0ff)|((buf[2]&0x0ff)<<8)
4685
+                       |((buf[1]&0x0ff)<<16)|((buf[0]&0x0ff)<<24);
4686
+       (*val) &= 0x0ffffffff;
4687
+
4688
+#ifdef ZIP_DEBUG
4689
+       fprintf(stderr, "MD-APPLY-FIX: FRAG=%08x@%08x+%08x(%d), IWORD = %08x Val=%08x (RTYP=%d->%s)%s%s, ADDEND=%08lx\n",
4690
+               ((unsigned)((unsigned long)fixP->fx_frag->fr_literal)),
4691
+               ((unsigned)((unsigned long)fixP->fx_frag->fr_address)),
4692
+               ((unsigned)((unsigned long)fixP->fx_where)),
4693
+               ((unsigned)((unsigned long)fixP->fx_size)),
4694
+               iword, (unsigned)(*val), fixP->fx_r_type,
4695
+               bfd_get_reloc_code_name(fixP->fx_r_type),
4696
+               (fixP->fx_pcrel)?" PC-Rel ":" std ",
4697
+               (fixP->fx_addsy)?"":"(Null Sym)",
4698
+               fixP->fx_offset);
4699
+#endif
4700
+       switch(fixP->fx_r_type) {
4701
+       case BFD_RELOC_NONE:
4702
+               fixP->fx_done = final_fix;
4703
+               break;
4704
+       case BFD_RELOC_ZIP_OPB_IMM:
4705
+               // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_OPB_IMM\n");
4706
+               mask = 0x3ffff; iword = (iword &(~mask))|((*val)&mask);
4707
+               (*val) &= 0x03ffff;
4708
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4709
+               fixP->fx_done = final_fix;
4710
+               break;
4711
+       case BFD_RELOC_ZIP_OPB_PCREL:
4712
+               {
4713
+               uint32_t        oval;
4714
+               oval = *val;
4715
+               oval = (*val>>2);
4716
+               oval &= 0x03fff;
4717
+               mask = 0x3fff; iword = (iword &(~mask))|((oval)&mask);
4718
+               *val = oval;
4719
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4720
+               fixP->fx_done = final_fix;
4721
+               } break;
4722
+       case BFD_RELOC_ZIP_OPB_OFFSET:
4723
+//     case BFD_RELOC_ZIP_OPB_GOTREL:
4724
+       case BFD_RELOC_14:
4725
+               // if (fixP->fx_r_type == BFD_RELOC_ZIP_OPB_OFFSET)
4726
+                       // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_OPB_OFFSET\n");
4727
+               // else if (fixP->fx_r_type == BFD_RELOC_ZIP_OPB_PCREL)
4728
+                       // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_OPB_PCREL\n");
4729
+               // else
4730
+                       // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_OPB_GOTREL\n");
4731
+               mask = 0x3fff; iword = (iword &(~mask))|((*val)&mask);
4732
+               (*val) &= 0x03fff;
4733
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4734
+               fixP->fx_done = final_fix;
4735
+               break;
4736
+       case BFD_RELOC_ZIP_MOV_PCREL:
4737
+               (*val) &= 0x07fff; (*val)>>=2;
4738
+               mask = 0x1fff; iword = (iword &(~mask))|((*val)&mask);
4739
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4740
+               fixP->fx_done = final_fix;
4741
+               break;
4742
+       case BFD_RELOC_ZIP_MOV_OFFSET:
4743
+       // case BFD_RELOC_ZIP_MOV_GOTREL:
4744
+#ifdef ZIP_DEBUG
4745
+               if (fixP->fx_r_type == BFD_RELOC_ZIP_MOV_OFFSET)
4746
+                       fprintf(stderr, "\tMD-APPLY-FIX: BFD_RELOC_ZIP_MOV_OFFSET\n");
4747
+               //else if (fixP->fx_r_type == BFD_RELOC_ZIP_MOV_PCREL)
4748
+               //      fprintf(stderr, "\tMD-APPLY-FIX: BFD_RELOC_ZIP_MOV_PCREL\n");
4749
+               // else
4750
+               //      fprintf(stderr, "\tMD-APPLY-FIX: BFD_RELOC_ZIP_MOV_GOTREL\n");
4751
+               fprintf(stderr, "Final-fix = %d\n", final_fix);
4752
+#endif
4753
+               mask = 0x1fff; iword = (iword &(~mask))|((*val)&mask);
4754
+               (*val) &= 0x01fff;
4755
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4756
+               fixP->fx_done = final_fix;
4757
+               break;
4758
+       case BFD_RELOC_ZIP_LDI:
4759
+               // If the value were known at build time, we wouldn't need
4760
+               // to drop the lower two address bits.  However, since we're
4761
+               // doing a fixup, we know val must reference an address,
4762
+               // hence we shift down two bits.
4763
+               // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_LDI\n");
4764
+               iword |= (*val)&0x03fffff;
4765
+               (*val) &= 0x03fffff;
4766
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4767
+               fixP->fx_done = final_fix;
4768
+               break;
4769
+       case BFD_RELOC_ZIP_LLO:
4770
+               // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_LLO\n");
4771
+               iword |= (*val)&0x0ffff;
4772
+               (*val) &= 0x0ffff;
4773
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4774
+               fixP->fx_done = final_fix;
4775
+               break;
4776
+       case BFD_RELOC_ZIP_BREV:
4777
+               // (*val) &= 0x0fffe0000;
4778
+               iword &= (~0x1ffff);
4779
+               iword |= zip_brev(*val)&0x01ffff;
4780
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4781
+               fixP->fx_done = final_fix;
4782
+               break;
4783
+#ifdef USE_R_ZIP_LHI
4784
+       case BFD_RELOC_ZIP_LHI:
4785
+               // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_LHI\n");
4786
+               iword |= ((*val)>>16)&0x0ffff;
4787
+               (*val) &= 0x0ffff0000;
4788
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4789
+               fixP->fx_done = final_fix;
4790
+               break;
4791
+#endif
4792
+       case BFD_RELOC_32:
4793
+       case BFD_RELOC_ZIP_VALUE:
4794
+               // printf("\tMD-APPLY-FIX: BFD_RELOC_ZIP_VALUE/32\n");
4795
+               iword = (*val);
4796
+               (*val) &= 0x0ffffffff;
4797
+               md_number_to_chars((char *)buf, iword, sizeof(uint32_t));
4798
+               fixP->fx_done = final_fix;
4799
+               break;
4800
+       case BFD_RELOC_16:
4801
+               iword = (*val)&0x0ffff;
4802
+               (*val) &= 0x0ffff;
4803
+               md_number_to_chars((char *)buf, iword, sizeof(uint16_t));
4804
+               fixP->fx_done = final_fix;
4805
+               break;
4806
+       case BFD_RELOC_8:
4807
+               iword = buf[0] & 0x0ff;
4808
+               iword |= (*val)&0x0ff; (*val) &= 0x0ff;
4809
+               md_number_to_chars((char *)buf, iword, sizeof(uint8_t));
4810
+               fixP->fx_done = final_fix;
4811
+               break;
4812
+       default:
4813
+               fprintf(stderr, "RELOC #\%d not supported\n", fixP->fx_r_type);
4814
+               // abort();
4815
+               break;
4816
+       }
4817
+}
4818
+
4819
+/* Generate a machine-dependent relocation. */
4820
+arelent *
4821
+tc_gen_reloc(asection *section ATTRIBUTE_UNUSED, fixS *fixP)
4822
+{
4823
+#ifdef ZIP_DEBUG
4824
+       fprintf(stderr, "Call to TC-GEN-RELOC(%s,FIX,%s,+%ld);\n", segment_name(section),
4825
+                       S_GET_NAME(fixP->fx_addsy),fixP->fx_offset);
4826
+#endif
4827
+
4828
+       arelent *relP;
4829
+
4830
+       relP = xmalloc(sizeof(arelent));
4831
+       gas_assert(relP != 0);
4832
+       relP->sym_ptr_ptr  = (asymbol **)xmalloc(sizeof(asymbol *));
4833
+       *relP->sym_ptr_ptr = symbol_get_bfdsym(fixP->fx_addsy);
4834
+       relP->address      = (fixP->fx_frag->fr_address + fixP->fx_where);
4835
+       // The addend value is added to the symbols value after the value is
4836
+       // is resolved.  It is useful for PC relative addressing, as well as
4837
+       // instructions giving offsets to symbols, such as LDI .x+50,R0.
4838
+       relP->addend = fixP->fx_offset;
4839
+       if (fixP->fx_r_type == BFD_RELOC_ZIP_OPB_PCREL)
4840
+               relP->addend -= 4;
4841
+#ifdef ZIP_DEBUG
4842
+       fprintf(stderr, "ADDEND = %08lx\n", relP->addend);
4843
+#endif
4844
+       relP->howto = bfd_reloc_type_lookup(stdoutput, fixP->fx_r_type);
4845
+       if (! relP->howto) {
4846
+               const char *name;
4847
+               name = S_GET_NAME(fixP->fx_addsy);
4848
+               if (name == NULL)
4849
+                       name = _("<unknown>");
4850
+               as_fatal( _("Cannot generate relocation type for symbol %s, code %s"),
4851
+                       name, bfd_get_reloc_code_name(fixP->fx_r_type));
4852
+       }
4853
+#ifdef ZIP_DEBUG
4854
+       else {
4855
+               const char *name;
4856
+               name = S_GET_NAME(fixP->fx_addsy);
4857
+               if (name == NULL)
4858
+                       name = _("<unknown>");
4859
+               fprintf(stderr, "GENERATING-RELOC(%20s, %4d=0x%04x) for %s\n",
4860
+                       bfd_get_reloc_code_name(fixP->fx_r_type),
4861
+                       fixP->fx_r_type, fixP->fx_r_type, name);
4862
+       }
4863
+#endif
4864
+       return relP;
4865
+}
4866
+
4867
+// Size is estimated in host bytes (octets)
4868
+int
4869
+zip_estimate_size_before_relax(fragS *fragP, segT seg) {
4870
+       ZIPIS   *insn = (ZIPIS *)(fragP->fr_opcode);
4871
+       offsetT last_fix = fragP->fr_fix;
4872
+
4873
+       zip_assemble_insn_words(fragP, seg, insn, 1, 0, NULL);
4874
+
4875
+       // Goal is to estimate the total size of the fragment before any
4876
+       // relaxations.  We need to return the difference between that
4877
+       // new estimate of total size and the current value of fragP->fr_fix.
4878
+#ifdef ZIP_DEBUG
4879
+       fprintf(stderr, "(%s): SZ-ESTIMATE %3ld + %d*(1+%d) - %3ld = %3ld\n",
4880
+               S_GET_NAME(insn->i_rp->r_sym),
4881
+               insn->i_rp->r_fr_offset, OCTETS_PER_BYTE, insn->i_naux,
4882
+               fragP->fr_fix,
4883
+               insn->i_rp->r_fr_offset + (1+insn->i_naux)*sizeof(uint32_t) - fragP->fr_fix);
4884
+#endif
4885
+       // zip_dump_insn(insn);
4886
+       fragP->fr_fix =  insn->i_rp->r_fr_offset + (1+insn->i_naux) * sizeof(uint32_t);
4887
+       return fragP->fr_fix - last_fix;
4888
+}
4889
+
4890
+#define        RELAX_STATE(FRAG)       (FRAG->fr_subtype)
4891
+long
4892
+zip_relax_frag(segT seg, fragS *fragP, long stretch)
4893
+{
4894
+       ZIPIS   *insn = (ZIPIS *)(fragP->fr_opcode);
4895
+       char    *p =&fragP->fr_literal[insn->i_rp->r_fr_offset];
4896
+       long    growth;
4897
+       int     i, old_naux = insn->i_naux;
4898
+
4899
+#ifdef ZIP_DEBUG
4900
+       fprintf(stderr, "--- FIX --- @%08x/%08x, Sym %s (zip_relax_frag), stretch = %ld/offset = %08lx, addr=%08x\n",
4901
+                       (int)((long)(fragP->fr_literal)),
4902
+                       (unsigned)fragP->fr_address,
4903
+                       (insn->i_rp->r_sym)?  S_GET_NAME(insn->i_rp->r_sym)
4904
+                               :"(Null)",
4905
+                       stretch, insn->i_rp->r_fr_offset,
4906
+                       insn->i_imm);
4907
+       // zip_dump_insn(insn);
4908
+#endif
4909
+
4910
+       {
4911
+               fragS   *lclfP;
4912
+               for(lclfP = fragP; lclfP; lclfP = lclfP->fr_next)
4913
+                       gas_assert(lclfP->fr_type < 256);
4914
+       }
4915
+
4916
+       // We need to rebuild the instruction since we could relax it
4917
+       // multiple times
4918
+       zip_assemble_insn_words(fragP, seg, insn, 1, stretch, NULL);
4919
+       {
4920
+               fragS   *lclfP;
4921
+               for(lclfP = fragP; lclfP; lclfP = lclfP->fr_next)
4922
+                       gas_assert(lclfP->fr_type < 256);
4923
+       }
4924
+
4925
+       md_number_to_chars(p, insn->i_code, sizeof(uint32_t));
4926
+       {
4927
+               fragS   *lclfP;
4928
+               for(lclfP = fragP; lclfP; lclfP = lclfP->fr_next)
4929
+                       gas_assert(lclfP->fr_type < 256);
4930
+       }
4931
+
4932
+       for(i=0; i< insn->i_naux; i++)
4933
+               md_number_to_chars(&p[sizeof(uint32_t)*(1+i)], insn->i_aux[i],
4934
+                               sizeof(uint32_t));
4935
+
4936
+       {
4937
+               fragS   *lclfP;
4938
+               for(lclfP = fragP; lclfP; lclfP = lclfP->fr_next)
4939
+                       gas_assert(lclfP->fr_type < 256);
4940
+       }
4941
+
4942
+       // The change in size of this fragment
4943
+       growth = (insn->i_naux - old_naux) * sizeof(uint32_t);
4944
+#ifdef ZIP_DEBUG
4945
+       fprintf(stderr, "GROWING BY %3ld bytes (insn->i_naux = %d->%d, fr_fix was %ld)\n",
4946
+               growth, old_naux, insn->i_naux, fragP->fr_fix);
4947
+       gas_assert(fragP->fr_fix >= 0);
4948
+       gas_assert(fragP->fr_fix + growth>= 0);
4949
+#endif
4950
+       {
4951
+               fragS   *lclfP;
4952
+               for(lclfP = fragP; lclfP; lclfP = lclfP->fr_next)
4953
+                       gas_assert(lclfP->fr_type < 256);
4954
+       }
4955
+
4956
+       return growth;
4957
+}
4958
+
4959
+void
4960
+zip_convert_frag(bfd *headers ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED,
4961
+               fragS *fragP ATTRIBUTE_UNUSED)
4962
+{
4963
+       ZIPIS   *insn = (ZIPIS *)fragP->fr_opcode;
4964
+       // char *p = fragP->fr_literal+ insn->i_rp->r_fr_offset;
4965
+
4966
+#ifdef ZIP_DEBUG
4967
+       fprintf(stderr, "CVT-FRAG: ADDR = %08lx, FIX = %3ld, VAR = %3ld\n",
4968
+               fragP->fr_address, fragP->fr_fix, fragP->fr_var);
4969
+
4970
+       zip_dump_insn(insn);
4971
+#endif
4972
+
4973
+       if ((insn->i_rp)&&(insn->i_rp->r_type != BFD_RELOC_NONE)
4974
+                       &&(!insn->i_rp->r_fix)) {
4975
+               if (insn->i_op == ZIPO_LDI) {
4976
+                       if (insn->i_naux == 1) {
4977
+                               // BREV extension would go here
4978
+                               //
4979
+                               fix_new(fragP,
4980
+                                       insn->i_rp->r_fr_offset, // where w/in frag?
4981
+                                       4,              // 1,2, or 4 usually ... ??
4982
+                                       insn->i_rp->r_sym, // Add symbol,
4983
+                                       insn->i_imm,// Fixed/known offset to the symbol
4984
+                                       insn->i_rp->r_pcrel, // T if PC-Relative reloc
4985
+                                       BFD_RELOC_ZIP_BREV); // Reloc type
4986
+                               fix_new(fragP,
4987
+                                       (insn->i_rp->r_fr_offset+sizeof(uint32_t)), // where w/in frag?
4988
+                                       4,              // 1,2, or 4 usually ... ??
4989
+                                       insn->i_rp->r_sym, // Add symbol,
4990
+                                       insn->i_imm,// Fixed/known offset to the symbol
4991
+                                       insn->i_rp->r_pcrel, // T if PC-Relative reloc
4992
+                                       BFD_RELOC_ZIP_LLO); // Reloc type
4993
+                       } else {
4994
+                               insn->i_rp->r_fix = fix_new(fragP,
4995
+                                       (insn->i_rp->r_fr_offset), // where w/in frag?
4996
+                                       4,              // 1,2, or 4 usually ... ??
4997
+                                       insn->i_rp->r_sym, // Add symbol,
4998
+                                       insn->i_imm, // Fixed/known offset to the symbol
4999
+                                       insn->i_rp->r_pcrel, // T if PC-Relative reloc
5000
+                                       BFD_RELOC_ZIP_LDI); // Reloc type
5001
+                       }
5002
+               } else if ((insn->i_op == ZIPO_BRA)&&(insn->i_naux >= 1)) {
5003
+#ifdef ZIP_DEBUG
5004
+                       fprintf(stderr, "--- CVT-FRAG --- Creating a BRA fixup\n");
5005
+#endif
5006
+                       fix_new(fragP,
5007
+                               insn->i_rp->r_fr_offset +insn->i_naux*sizeof(uint32_t),
5008
+                               4,              // 1,2, or 4 usually ... ??
5009
+                               insn->i_rp->r_sym, // Add symbol,
5010
+                               insn->i_imm, // Fixed/known offset to the symbol
5011
+                               insn->i_rp->r_pcrel, // T if PC-Relative reloc
5012
+                               BFD_RELOC_ZIP_VALUE); // Reloc type
5013
+               } else if (insn->i_rp->r_type == BFD_RELOC_ZIP_VALUE) {
5014
+                               // Use the CIS LW (PC),PC method
5015
+                               fix_new(fragP,
5016
+                               insn->i_rp->r_fr_offset
5017
+                                       + insn->i_naux*sizeof(uint32_t),
5018
+                               4,              // 1,2, or 4 usually ... ??
5019
+                               insn->i_rp->r_sym, // Add symbol,
5020
+                               insn->i_imm, // Fixed/known offset to the symbol
5021
+                               insn->i_rp->r_pcrel, // T if PC-Relative reloc
5022
+                               BFD_RELOC_ZIP_VALUE); // Reloc type
5023
+               } else {
5024
+#ifdef ZIP_DEBUG
5025
+                       fprintf(stderr, "--- CVT-FRAG --- Creating a more generic fixup (%d)\n",
5026
+                               insn->i_rp->r_type);
5027
+#endif
5028
+                       fix_new(fragP,
5029
+                               // where w/in frag?
5030
+                               insn->i_rp->r_fr_offset+insn->i_naux * sizeof(uint32_t),
5031
+                               4,      // 1,2, or 4 usually ... ??
5032
+                               insn->i_rp->r_sym, // Add symbol,
5033
+                               insn->i_imm, // Fixed/known offset to the symbol
5034
+                               insn->i_rp->r_pcrel, // T if PC-Relative reloc
5035
+                               insn->i_rp->r_type); // Reloc type
5036
+               }
5037
+       }
5038
+}
5039
diff -Naur '--exclude=*.swp' binutils-2.27/gas/config/tc-zip.h binutils-2.27-zip/gas/config/tc-zip.h
5040
--- binutils-2.27/gas/config/tc-zip.h   1969-12-31 19:00:00.000000000 -0500
5041
+++ binutils-2.27-zip/gas/config/tc-zip.h       2017-03-03 09:35:34.527310651 -0500
5042
@@ -0,0 +1,191 @@
5043
+////////////////////////////////////////////////////////////////////////////////
5044
+//
5045
+// Filename:   tc-zip.h
5046
+//
5047
+// Project:    Zip CPU backend for GNU Binutils
5048
+//
5049
+// Purpose:
5050
+//
5051
+// Creator:    Dan Gisselquist, Ph.D.
5052
+//             Gisselquist Technology, LLC
5053
+//
5054
+////////////////////////////////////////////////////////////////////////////////
5055
+//
5056
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
5057
+//
5058
+// This program is free software (firmware): you can redistribute it and/or
5059
+// modify it under the terms of  the GNU General Public License as published
5060
+// by the Free Software Foundation, either version 3 of the License, or (at
5061
+// your option) any later version.
5062
+//
5063
+// This program is distributed in the hope that it will be useful, but WITHOUT
5064
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
5065
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
5066
+// for more details.
5067
+//
5068
+// You should have received a copy of the GNU General Public License along
5069
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
5070
+// target there if the PDF file isn't present.)  If not, see
5071
+// <http://www.gnu.org/licenses/> for a copy.
5072
+//
5073
+// License:    GPL, v3, as defined and found on www.gnu.org,
5074
+//             http://www.gnu.org/licenses/gpl.html
5075
+//
5076
+//
5077
+////////////////////////////////////////////////////////////////////////////////
5078
+#ifndef        TC_ZIPCPU
5079
+#define        TC_ZIPCPU
5080
+
5081
+#define        TC_ZIP  1
5082
+
5083
+/* This macro, when defined as zero, means our target in little endian like a
5084
+ * PC.  A 1 would mean it was big endian.  Since the Zip CPU is big endian, we
5085
+ * set this to one here..
5086
+ */
5087
+#define        TARGET_BYTES_BIG_ENDIAN 1
5088
+
5089
+/* If WORKING_DOT_WORD is defined, GAS will not do broken word processing
5090
+ * (*note Broken Words ...).  Otherwise, you should set 'md_short_jump_size'
5091
+ * to the size of a short jump (a jump that is just long enough to jump
5092
+ * around a long jmp) and 'md_long_jump_size' to the size of a long jump
5093
+ * (a jump that can go anywhere in the function).  You should define
5094
+ * md_create_short_jump to create a short jump around a long jump, and define
5095
+ * md_create_long_jump to creat a long jump.  Here, we'll just skip these
5096
+ * and so we define WORKING_DOT_WORD.
5097
+ */
5098
+#define        WORKING_DOT_WORD
5099
+
5100
+/* TC_ADDRESS_BYTES ... Define this macro to specify the number of bytes used
5101
+ * to store an address.  Used to implement dc.a.  The target must have a reloc
5102
+ * for this size.
5103
+ */
5104
+#define        TC_ADDRESS_BYTES        zip_address_bytes
5105
+
5106
+/* TC_PREDICATE_START_CHAR ... I can't find this in the documentation, but I'm
5107
+ * guessing if a line begins with this character, the line beginning will be
5108
+ * taken care of specially.
5109
+ */
5110
+#define        TC_PREDICATE_START_CHAR '['
5111
+#define        TC_PREDICATE_END_CHAR   ']'
5112
+
5113
+
5114
+/* md_cons_align ... You may define this macro to do any special alignment
5115
+ * before a data allocation pseudo-op.
5116
+ *
5117
+ */
5118
+#define        md_cons_align(N)        zip_cons_align(N)
5119
+extern void    zip_cons_align(int);
5120
+
5121
+#define        md_flush_pending_output zip_flush_pending_output
5122
+extern void    zip_flush_pending_output(void);
5123
+
5124
+
5125
+/* This macro is the BFD target name to use when creating the output
5126
+* file.  This will normally depend upon the OBJ_FMT macro. */
5127
+#define TARGET_FORMAT "elf32-zip"
5128
+#define        TARGET_ARCH     bfd_arch_zip
5129
+
5130
+#define md_estimate_size_before_relax  zip_estimate_size_before_relax
5131
+#define        md_relax_frag                   zip_relax_frag
5132
+#define md_convert_frag                        zip_convert_frag
5133
+extern long zip_relax_frag(segT, fragS *, long);
5134
+extern int  zip_estimate_size_before_relax(fragS *, segT);
5135
+extern void zip_convert_frag(bfd *, segT, fragS *);
5136
+extern int     zip_address_bytes(void);
5137
+
5138
+/* These macros must be defined, but it will be a fatal assembler error if we
5139
+* ever hit them. */
5140
+// #define md_estimate_size_before_relax(A, B) (as_fatal (_("estimate size\n")),0)
5141
+#define md_pcrel_from(FIX) (((FIX)->fx_where+(FIX)->fx_frag->fr_address+4)>>OCTETS_PER_BYTE_POWER)
5142
+
5143
+// What do we need to define here to align on 32-bit boundaries?
5144
+#define        md_section_align(SEGMENT, SIZE) (SIZE)
5145
+
5146
+// Check label is called right after any label (lbl: ) is found in the
5147
+// assembly of the program.  We need to make certain this is called, so that
5148
+// in VLIW mode we don't try to merge an instruction pair into a new
5149
+// instruction sequence where the label calls for jumping into the middle
5150
+// of that sequence.
5151
+//
5152
+#define        tc_check_label  zip_check_label
5153
+extern void    zip_check_label(symbolS *);
5154
+
5155
+
5156
+extern void    md_assemble(char *op_str);
5157
+extern void    md_end(void);
5158
+extern void    md_begin(void);
5159
+// extern      symbolS *md_undefined_symbol(char *name);
5160
+// extern      void md_operand(expressionS *name);
5161
+
5162
+#if (TARGET_BYTES_BIG_ENDIAN==0)
5163
+#define        md_number_to_chars      number_to_chars_littleendian
5164
+#else
5165
+#define        md_number_to_chars      number_to_chars_bigendian
5166
+#endif
5167
+
5168
+
5169
+#define        GLOBAL_OFFSET_TABLE_NAME        "_GLOBAL_OFFSET_TABLE_"
5170
+
5171
+//     typedef uint32_t ZIPI, ZIPA;
5172
+//     typedef int     ZIPIMM;
5173
+
5174
+// LR = Link Register, R0
5175
+// FP = Frame Pointer, R12
5176
+// SP = Stack Pointer, R13
5177
+// CC = Condition Codes, R14
5178
+// PC = Program Counter, R15
5179
+typedef        enum {
5180
+       ZIP_LR=0, ZIP_R1, ZIP_R2, ZIP_R3, ZIP_R4, ZIP_R5, ZIP_R6, ZIP_R7,
5181
+       ZIP_R8, ZIP_R9, ZIP_R10, ZIP_R11, ZIP_FP,
5182
+               ZIP_SP, ZIP_CC, ZIP_PC,
5183
+       ZIP_uLR, ZIP_uR1, ZIP_uR2, ZIP_uR3, ZIP_uR4, ZIP_uR5, ZIP_uR6, ZIP_uR7,
5184
+       ZIP_uR8, ZIP_uR9, ZIP_uR10, ZIP_uR11, ZIP_uFP,
5185
+               ZIP_uSP, ZIP_uCC, ZIP_uPC,
5186
+       ZIP_RNONE=48
5187
+} ZIP_REG;
5188
+
5189
+#define        ZIP_USER_REGS   16
5190
+
5191
+typedef        enum {
5192
+       ZIPC_ALWAYS, ZIPC_Z,  ZIPC_LT,  ZIPC_C,
5193
+       ZIPC_V,      ZIPC_NZ, ZIPC_GE, ZIPC_NC
5194
+} ZIP_CONDITION;
5195
+
5196
+typedef        enum {
5197
+       // 16 ALU instructions
5198
+       ZIPO_SUB=0, ZIPO_AND, ZIPO_ADD, ZIPO_OR,        //  5'h000xx
5199
+       ZIPO_XOR, ZIPO_LSR, ZIPO_LSL, ZIPO_ASR,         //  5'h001xx
5200
+       ZIPO_BREV, ZIPO_LDILO, ZIPO_MPYUHI, ZIPO_MPYSHI,//  5'h010xx
5201
+       ZIPO_MPY, ZIPO_MOV, ZIPO_DIVU, ZIPO_DIVS,       //  5'h011xx
5202
+//
5203
+       ZIPO_CMP, ZIPO_TST,                             //  5'h1000x
5204
+       ZIPO_LW, ZIPO_SW, ZIPO_LH, ZIPO_SH, ZIPO_LB, ZIPO_SB,   //  5'h10xxw
5205
+       ZIPO_LDI, ZIPO_LDIn,                            //  5'h1100x
5206
+       ZIPO_FPADD=0x1a, ZIPO_FPSUB,                    //  5'h1101x
5207
+       ZIPO_FPMPY, ZIPO_FPDIV,                         //  5'h1110x
5208
+       ZIPO_FPI2F, ZIPO_FPF2I,                         //  5'h1111x
5209
+       // Pseudo-ops
5210
+       ZIPO_BREAK, ZIPO_LOCK, ZIPO_SIM, ZIPO_NOOP,
5211
+       ZIPO_TRAP, ZIPO_CLR,
5212
+       //
5213
+       ZIPO_BRA,  ZIPO_BLT,  ZIPO_BZ, ZIPO_BC,
5214
+       ZIPO_BV,   ZIPO_BGE,  ZIPO_BNZ, ZIPO_BNC,
5215
+       //
5216
+       ZIPO_HALT, ZIPO_WAIT, ZIPO_RTU, ZIPO_BUSY,
5217
+       ZIPO_STEP, ZIPO_JMP,  ZIPO_NOT, ZIPO_NEG,
5218
+       //
5219
+       ZIPO_SDUMP, ZIPO_NDUMP,
5220
+       ZIPO_SOUT,  ZIPO_NOUT,
5221
+       ZIPO_SEXIT, ZIPO_NEXIT,
5222
+       ZIPO_SEXTB, ZIPO_SEXTH,
5223
+       ZIPO_JSR,   ZIPO_LJSR, ZIPO_LJMP
5224
+} ZIP_OPCODE;
5225
+
5226
+typedef        enum {
5227
+       // 8 instructions
5228
+       ZIPV_SUB=0, ZIPV_AND, ZIPV_ADD, ZIPV_CMP,       // 3'h0xx
5229
+       ZIPV_LW, ZIPV_SW, ZIPV_LDI, ZIPV_MOV,           // 3'h1xx
5230
+} ZIP_VLIWCODE;
5231
+
5232
+#endif
5233
+
5234
diff -Naur '--exclude=*.swp' binutils-2.27/gas/configure.tgt binutils-2.27-zip/gas/configure.tgt
5235
--- binutils-2.27/gas/configure.tgt     2016-08-03 03:36:51.000000000 -0400
5236
+++ binutils-2.27-zip/gas/configure.tgt 2016-12-31 17:44:37.270167826 -0500
5237
@@ -112,6 +112,7 @@
5238
   x86_64*)             cpu_type=i386 arch=x86_64;;
5239
   xgate)               cpu_type=xgate ;;
5240
   xtensa*)             cpu_type=xtensa arch=xtensa ;;
5241
+  zip*)                        cpu_type=zip endian=big ;;
5242
   *)                   cpu_type=${cpu} ;;
5243
 esac
5244
 
5245
@@ -472,6 +473,8 @@
5246
 
5247
   z8k-*-coff | z8k-*-sim)              fmt=coff ;;
5248
 
5249
+  zip*)                                        fmt=elf ;;
5250
+
5251
   *-*-aout | *-*-scout)                        fmt=aout ;;
5252
   *-*-cloudabi*)                       fmt=elf ;;
5253
   *-*-dragonfly*)                      fmt=elf em=dragonfly ;;
5254
diff -Naur '--exclude=*.swp' binutils-2.27/gas/Makefile.am binutils-2.27-zip/gas/Makefile.am
5255
--- binutils-2.27/gas/Makefile.am       2016-08-03 03:36:51.000000000 -0400
5256
+++ binutils-2.27-zip/gas/Makefile.am   2016-12-31 17:45:17.941851449 -0500
5257
@@ -200,6 +200,7 @@
5258
        config/tc-xtensa.c \
5259
        config/tc-z80.c \
5260
        config/tc-z8k.c \
5261
+       config/tc-zip.c \
5262
        config/xtensa-relax.c
5263
 
5264
 TARGET_CPU_HFILES = \
5265
@@ -273,6 +274,7 @@
5266
        config/tc-xtensa.h \
5267
        config/tc-z80.h \
5268
        config/tc-z8k.h \
5269
+       config/tc-zip.h \
5270
        config/xtensa-relax.h
5271
 
5272
 # OBJ files in config
5273
diff -Naur '--exclude=*.swp' binutils-2.27/gas/Makefile.in binutils-2.27-zip/gas/Makefile.in
5274
--- binutils-2.27/gas/Makefile.in       2016-08-03 04:16:28.000000000 -0400
5275
+++ binutils-2.27-zip/gas/Makefile.in   2016-12-31 17:49:43.603837948 -0500
5276
@@ -494,6 +494,7 @@
5277
        config/tc-xtensa.c \
5278
        config/tc-z80.c \
5279
        config/tc-z8k.c \
5280
+       config/tc-zip.c \
5281
        config/xtensa-relax.c
5282
 
5283
 TARGET_CPU_HFILES = \
5284
@@ -567,6 +568,7 @@
5285
        config/tc-xtensa.h \
5286
        config/tc-z80.h \
5287
        config/tc-z8k.h \
5288
+       config/tc-zip.h \
5289
        config/xtensa-relax.h
5290
 
5291
 
5292
@@ -922,6 +924,7 @@
5293
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-xtensa.Po@am__quote@
5294
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-z80.Po@am__quote@
5295
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-z8k.Po@am__quote@
5296
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-zip.Po@am__quote@
5297
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/te-vms.Po@am__quote@
5298
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/write.Po@am__quote@
5299
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-relax.Po@am__quote@
5300
@@ -1941,6 +1944,20 @@
5301
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
5302
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-z8k.obj `if test -f 'config/tc-z8k.c'; then $(CYGPATH_W) 'config/tc-z8k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-z8k.c'; fi`
5303
 
5304
+tc-zip.o: config/tc-zip.c
5305
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-zip.o -MD -MP -MF $(DEPDIR)/tc-zip.Tpo -c -o tc-zip.o `test -f 'config/tc-zip.c' || echo '$(srcdir)/'`config/tc-zip.c
5306
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-zip.Tpo $(DEPDIR)/tc-zip.Po
5307
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='config/tc-zip.c' object='tc-zip.o' libtool=no @AMDEPBACKSLASH@
5308
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
5309
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-zip.o `test -f 'config/tc-zip.c' || echo '$(srcdir)/'`config/tc-zip.c
5310
+
5311
+tc-zip.obj: config/tc-zip.c
5312
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-zip.obj -MD -MP -MF $(DEPDIR)/tc-zip.Tpo -c -o tc-zip.obj `if test -f 'config/tc-zip.c'; then $(CYGPATH_W) 'config/tc-zip.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-zip.c'; fi`
5313
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/tc-zip.Tpo $(DEPDIR)/tc-zip.Po
5314
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='config/tc-zip.c' object='tc-zip.obj' libtool=no @AMDEPBACKSLASH@
5315
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
5316
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-zip.obj `if test -f 'config/tc-zip.c'; then $(CYGPATH_W) 'config/tc-zip.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-zip.c'; fi`
5317
+
5318
 xtensa-relax.o: config/xtensa-relax.c
5319
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa-relax.o -MD -MP -MF $(DEPDIR)/xtensa-relax.Tpo -c -o xtensa-relax.o `test -f 'config/xtensa-relax.c' || echo '$(srcdir)/'`config/xtensa-relax.c
5320
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/xtensa-relax.Tpo $(DEPDIR)/xtensa-relax.Po
5321
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip.exp binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp
5322
--- binutils-2.27/gas/testsuite/gas/zip/zip.exp 1969-12-31 19:00:00.000000000 -0500
5323
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp     2017-01-12 22:12:40.839206088 -0500
5324
@@ -0,0 +1,17 @@
5325
+# ZipCPU assembler testsuite
5326
+
5327
+if [istarget zip*] {
5328
+  run_dump_test "zip_insn_add"
5329
+  run_dump_test "zip_insn_bratest"
5330
+  run_dump_test "zip_insn_ctest"
5331
+  run_dump_test "zip_insn_lditest"
5332
+  run_dump_test "zip_insn_prologue"
5333
+  run_dump_test "zip_insn_prologuev"
5334
+  run_dump_test "zip_insn_specials"
5335
+  run_dump_test "zip_insn_optest"
5336
+  run_dump_test "zip_insn_mov"
5337
+  run_dump_test "zip_insn_vliw"
5338
+  # run_dump_test "zip_insn_fpu"
5339
+  # run_dump_test "zip_insn_jsr"
5340
+  # run_dump_test "zip_insn_jsrv"
5341
+}
5342
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d
5343
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.d  1969-12-31 19:00:00.000000000 -0500
5344
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d      2017-01-12 22:01:30.790982203 -0500
5345
@@ -0,0 +1,41 @@
5346
+#as: -novliw
5347
+#objdump: -dr
5348
+#name: Generic OpB instruction test
5349
+
5350
+.*: +file format elf32-zip
5351
+
5352
+
5353
+Disassembly of section .text:
5354
+
5355
+00000000 <add_insn_test>:
5356
+   0:  00 83 e0 00     ADD +\$-8192,R0
5357
+   4:  00 84 a0 00     ADD +\$-8192\+R2,R0
5358
+   8:  08 82 00 00     ADD +\$-131072,R1
5359
+   c:  00 80 1f ff     ADD +\$8191,R0
5360
+  10:  00 84 a0 01     ADD +\$-8191\+R2,R0
5361
+  14:  08 81 ff ff     ADD +\$131071,R1
5362
+  18:  18 80 00 01     ADD +\$1,R3
5363
+  1c:  18 85 00 01     ADD +\$1\+R4,R3
5364
+  20:  30 87 c0 01     ADD +\$4\+PC,R6
5365
+  24:  30 87 c0 01     ADD +\$4\+PC,R6
5366
+  28:  30 87 c0 01     ADD +\$4\+PC,R6
5367
+  2c:  30 87 c0 01     ADD +\$4\+PC,R6
5368
+  30:  50 88 00 04     ADD.Z +\$4,R10
5369
+  34:  50 a8 00 04     ADD.NZ +.4,R10
5370
+  38:  50 90 00 04     ADD.LT +.4,R10
5371
+  3c:  50 b0 00 04     ADD.GE +.4,R10
5372
+  40:  50 98 00 04     ADD.C +.4,R10
5373
+  44:  50 b8 00 04     ADD.NC +.4,R10
5374
+  48:  50 a0 00 04     ADD.V +.4,R10
5375
+  4c:  50 88 00 04     ADD.Z +.4,R10
5376
+  50:  58 a8 00 04     ADD.NZ +.4,R11
5377
+  54:  60 90 00 04     ADD.LT +.4,R12
5378
+  58:  68 b0 00 04     ADD.GE +.4,SP
5379
+  5c:  70 98 00 04     ADD.C +.4,CC
5380
+  60:  78 b8 00 04     BNC +@0x00000068.*$
5381
+  64:  68 a0 00 04     ADD.V +.4,SP
5382
+  68:  70 80 00 04     ADD +.4,CC
5383
+  6c:  78 80 00 04     BRA +@0x00000074.*$
5384
+  70:  78 89 ff ff     BZ +@0x00020073.*$
5385
+  74:  78 aa 00 00     BNZ +@0xfffe0078.*$
5386
+
5387
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s
5388
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.s  1969-12-31 19:00:00.000000000 -0500
5389
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s      2017-01-10 12:00:50.870044337 -0500
5390
@@ -0,0 +1,33 @@
5391
+       .text
5392
+
5393
+add_insn_test:
5394
+       add     -8192,R0
5395
+       add     -8192+R2,R0
5396
+       add     -131072,R1
5397
+       add     8191,R0
5398
+       add     -8191+R2,R0
5399
+       add     131071,R1
5400
+       add     1,R3
5401
+       add     1(R4),R3
5402
+       add     5+pc,R6
5403
+       add     5+r15,R6
5404
+       add     5+spc,R6
5405
+       add     5+sr15,R6
5406
+       add.z   4,R10
5407
+       add.nz  4,R10
5408
+       add.lt  4,R10
5409
+       add.ge  4,R10
5410
+       add.c   4,R10
5411
+       add.nc  4,R10
5412
+       add.v   4,R10
5413
+       [z]  add        4,R10
5414
+       [nz] add        4,R11
5415
+       [lt] add        4,R12
5416
+       [ge] add        4,R13
5417
+       [c]  add        4,R14
5418
+       [nc] add        4,R15
5419
+       [v]  add        4,sp
5420
+       add     4,cc
5421
+       add     4,pc
5422
+       add.z   131071,pc
5423
+       add.nz  -131072,pc
5424
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d
5425
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.d      1969-12-31 19:00:00.000000000 -0500
5426
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d  2017-01-10 10:46:16.957469423 -0500
5427
@@ -0,0 +1,22 @@
5428
+#as:
5429
+#objdump: -dr
5430
+#name: Local branch (BRA) and conditional branch testing
5431
+
5432
+.*: +file format elf32-zip
5433
+
5434
+
5435
+Disassembly of section .text:
5436
+
5437
+00000000 <bra_insn_test>:
5438
+   0:  78 80 00 20     BRA        \$32
5439
+   4:  78 88 00 1c     BZ         @0x00000024  // .. <bra_target>
5440
+   8:  78 a8 00 18     BNZ        @0x00000024  // .. <bra_target>
5441
+   c:  78 98 00 14     BC         @0x00000024  // .. <bra_target>
5442
+  10:  78 b8 00 10     BNC        @0x00000024  // .. <bra_target>
5443
+  14:  78 90 00 0c     BLT        @0x00000024  // .. <bra_target>
5444
+  18:  78 b0 00 08     BGE        @0x00000024  // .. <bra_target>
5445
+  1c:  78 a0 00 04     BV         @0x00000024  // .. <bra_target>
5446
+  20:  06 7f ff ff     LDI        \$-1,R0
5447
+
5448
+00000024 <bra_target>:
5449
+  24:  7f c0 00 00     NOOP
5450
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s
5451
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.s      1969-12-31 19:00:00.000000000 -0500
5452
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s  2017-01-09 10:28:54.983992877 -0500
5453
@@ -0,0 +1,14 @@
5454
+       .text
5455
+
5456
+bra_insn_test:
5457
+       bra     bra_target
5458
+       bz      bra_target
5459
+       bnz     bra_target
5460
+       bc      bra_target
5461
+       bnc     bra_target
5462
+       blt     bra_target
5463
+       bge     bra_target
5464
+       bv      bra_target
5465
+       ldi -1,r0
5466
+bra_target:
5467
+       noop
5468
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d
5469
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.d        1969-12-31 19:00:00.000000000 -0500
5470
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d    2017-01-16 11:02:02.344009430 -0500
5471
@@ -0,0 +1,39 @@
5472
+#as:
5473
+#objdump: -dr
5474
+#name: Conditional predicate test(s)
5475
+
5476
+.*: +file format elf32-zip
5477
+
5478
+
5479
+Disassembly of section .text:
5480
+
5481
+00000000 <conditional_tests>:
5482
+   0:  00 80 00 01     ADD +\$1,R0
5483
+   4:  00 88 00 01     ADD.Z +\$1,R0
5484
+   8:  00 88 00 01     ADD.Z +\$1,R0
5485
+   c:  00 a8 00 01     ADD.NZ +\$1,R0
5486
+  10:  00 a8 00 01     ADD.NZ +\$1,R0
5487
+  14:  00 b0 00 01     ADD.GE +\$1,R0
5488
+  18:  00 b0 00 01     ADD.GE +\$1,R0
5489
+  1c:  00 90 00 01     ADD.LT +\$1,R0
5490
+  20:  00 90 00 01     ADD.LT +\$1,R0
5491
+  24:  00 a0 00 01     ADD.V +\$1,R0
5492
+  28:  00 98 00 01     ADD.C +\$1,R0
5493
+  2c:  00 98 00 01     ADD.C +\$1,R0
5494
+  30:  00 b8 00 01     ADD.NC +\$1,R0
5495
+  34:  00 b8 00 01     ADD.NC +\$1,R0
5496
+  38:  00 80 00 01     ADD +\$1,R0
5497
+  3c:  00 88 00 01     ADD.Z +\$1,R0
5498
+  40:  28 8b ff e0     ADD.Z +\$-32,R5
5499
+  44:  00 88 00 01     ADD.Z +\$1,R0
5500
+  48:  00 a8 00 01     ADD.NZ +\$1,R0
5501
+  4c:  00 a8 00 01     ADD.NZ +\$1,R0
5502
+  50:  00 b0 00 01     ADD.GE +\$1,R0
5503
+  54:  00 b0 00 01     ADD.GE +\$1,R0
5504
+  58:  00 90 00 01     ADD.LT +\$1,R0
5505
+  5c:  00 90 00 01     ADD.LT +\$1,R0
5506
+  60:  00 a0 00 01     ADD.V  +\$1,R0
5507
+  64:  00 98 00 01     ADD.C  +\$1,R0
5508
+  68:  00 98 00 01     ADD.C  +\$1,R0
5509
+  6c:  00 b8 00 01     ADD.NC +\$1,R0
5510
+  70:  00 b8 00 01     ADD.NC +\$1,R0
5511
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s
5512
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.s        1969-12-31 19:00:00.000000000 -0500
5513
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s    2017-01-16 10:55:53.054697861 -0500
5514
@@ -0,0 +1,34 @@
5515
+       .text
5516
+
5517
+conditional_tests:
5518
+       add     1,R0
5519
+       add.z   1,R0
5520
+       add.eq  1,R0
5521
+       add.nz  1,R0
5522
+       add.ne  1,R0
5523
+       add.ge  1,R0
5524
+       add.gte 1,R0
5525
+       add.lt  1,R0
5526
+       add.n   1,R0
5527
+       add.v   1,R0
5528
+       add.c   1,R0
5529
+       add.ltu 1,R0
5530
+       add.nc  1,R0
5531
+       add.geu 1,R0
5532
+       ;
5533
+       add     1,R0
5534
+       [z]     add     1,R0
5535
+       [z]     add     -32,R5
5536
+       [EQ]    add     1,R0
5537
+       [nz]    add     1,R0
5538
+       [ne]    add     1,R0
5539
+       [ge]    add     1,R0
5540
+       [gte]   add     1,R0
5541
+       [lt]    add     1,R0
5542
+       [n]     add     1,R0
5543
+       [v]     add     1,R0
5544
+       [c]     add     1,R0
5545
+       [ltu]   add     1,R0
5546
+       [nc]    add     1,R0
5547
+       [geu]   add     1,R0
5548
+
5549
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d
5550
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.d      1969-12-31 19:00:00.000000000 -0500
5551
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d  2017-01-10 11:31:45.633275455 -0500
5552
@@ -0,0 +1,24 @@
5553
+#as: -nozipm
5554
+#objdump: -dr
5555
+#name: Load-Immediate test
5556
+
5557
+.*: +file format elf32-zip
5558
+
5559
+
5560
+Disassembly of section .text:
5561
+
5562
+00000000 <ldi_insn_test>:
5563
+   0:  06 00 00 00     CLR +R0
5564
+   4:  0a 08 00 00     CLR.Z +\$0,R1
5565
+   8:  16 00 20 00     LDI +\$8192,R2
5566
+   c:  1a 08 00 00     LDI.Z +0x00002000,R3.*
5567
+  10:  1a 48 20 00
5568
+  14:  22 29 ff ff     LDI.NZ +0xffffe000,R4.*
5569
+  18:  22 68 e0 00
5570
+  1c:  2a 03 fe 00     BREV +\$-512,R5
5571
+  20:  32 00 01 ff     LDI +0xff800001,R6.*
5572
+  24:  32 40 00 01
5573
+  28:  3a 00 01 ff     BREV +\$511,R7
5574
+  2c:  42 03 fe ff     BREV +\$-257,R8
5575
+  30:  4a 01 fe ff     LDI +0xff7ffffe,R9.*
5576
+  34:  4a 40 ff fe
5577
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s
5578
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.s      1969-12-31 19:00:00.000000000 -0500
5579
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s  2017-01-09 10:28:37.472119620 -0500
5580
@@ -0,0 +1,13 @@
5581
+       .text
5582
+
5583
+ldi_insn_test:
5584
+       ldi     0,R0
5585
+       ldi.z   0,r1
5586
+       ldi     8192,r2
5587
+       ldi.z   8192,r3
5588
+       ldi.nz  -8192,r4
5589
+       ldi     8388607,r5
5590
+       ldi     -8388607,r6
5591
+       ldi     -8388608,r7
5592
+       ldi     -8388609,r8
5593
+       ldi     -8388610,r9
5594
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d
5595
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.d  1969-12-31 19:00:00.000000000 -0500
5596
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d      2017-01-12 22:09:54.925246052 -0500
5597
@@ -0,0 +1,86 @@
5598
+#as: -novliw -nozipm
5599
+#objdump: -dr
5600
+#name: Mov instruction special test
5601
+
5602
+.*: +file format elf32-zip
5603
+
5604
+
5605
+Disassembly of section .text:
5606
+
5607
+00000000 <mov_insn_test>:
5608
+   0:  0b 40 10 00     MOV +\$-4096\+R0,R1
5609
+   4:  1b 40 90 01     MOV +\$-4095\+R2,R3
5610
+   8:  2b 41 0f ff     MOV +\$4095\+R4,R5
5611
+   c:  3b 41 80 00     MOV +R6,R7
5612
+
5613
+00000010 <mov_to_user>:
5614
+  10:  0b 44 10 00     MOV +\$-4096\+R0,uR1
5615
+  14:  1b 44 90 01     MOV +\$-4095\+R2,uR3
5616
+  18:  2b 45 0f ff     MOV +\$4095\+R4,uR5
5617
+  1c:  3b 45 80 00     MOV +R6,uR7
5618
+
5619
+00000020 <mov_from_user>:
5620
+  20:  0b 40 30 00     MOV +\$-4096\+uR0,R1
5621
+  24:  1b 40 b0 01     MOV +\$-4095\+uR2,R3
5622
+  28:  2b 41 2f ff     MOV +\$4095\+uR4,R5
5623
+  2c:  3b 41 a0 00     MOV +uR6,R7
5624
+
5625
+00000030 <mov_user_to_user>:
5626
+  30:  0b 44 30 00     MOV +\$-4096\+uR0,uR1
5627
+  34:  1b 44 b0 01     MOV +\$-4095\+uR2,uR3
5628
+  38:  2b 45 2f ff     MOV +\$4095\+uR4,uR5
5629
+  3c:  3b 45 a0 00     MOV +uR6,uR7
5630
+
5631
+00000040 <move_from_upc>:
5632
+  40:  0b 47 f0 00     MOV +\$-4096\+uPC,uR1
5633
+  44:  1b 47 f0 01     MOV +\$-4095\+uPC,uR3
5634
+  48:  2b 47 ef ff     MOV +\$4095\+uPC,uR5
5635
+  4c:  3b 47 e0 00     MOV +uPC,uR7
5636
+
5637
+00000050 <move_from_usp>:
5638
+  50:  0b 47 70 00     MOV +\$-4096\+uSP,uR1
5639
+  54:  1b 47 70 01     MOV +\$-4095\+uSP,uR3
5640
+  58:  2b 47 6f ff     MOV +\$4095\+uSP,uR5
5641
+  5c:  3b 47 60 00     MOV +uSP,uR7
5642
+
5643
+00000060 <move_from_ucc>:
5644
+  60:  0b 47 b0 00     MOV +\$-4096\+uCC,uR1
5645
+  64:  1b 47 b0 01     MOV +\$-4095\+uCC,uR3
5646
+  68:  2b 47 af ff     MOV +\$4095\+uCC,uR5
5647
+  6c:  3b 47 a0 00     MOV +uCC,uR7
5648
+
5649
+00000070 <move_to_upc>:
5650
+  70:  7b 44 10 00     MOV +\$-4096\+R0,uPC
5651
+  74:  7b 44 90 01     MOV +\$-4095\+R2,uPC
5652
+  78:  7b 45 0f ff     MOV +\$4095\+R4,uPC
5653
+  7c:  7b 45 80 00     MOV +R6,uPC
5654
+
5655
+00000080 <move_to_usp>:
5656
+  80:  6b 44 10 00     MOV +\$-4096\+R0,uSP
5657
+  84:  6b 44 90 01     MOV +\$-4095\+R2,uSP
5658
+  88:  6b 45 0f ff     MOV +\$4095\+R4,uSP
5659
+  8c:  6b 45 80 00     MOV +R6,uSP
5660
+
5661
+00000090 <move_to_ucc>:
5662
+  90:  73 44 10 00     MOV +\$-4096\+R0,uCC
5663
+  94:  73 44 90 01     MOV +\$-4095\+R2,uCC
5664
+  98:  73 45 0f ff     MOV +\$4095\+R4,uCC
5665
+  9c:  73 45 80 00     MOV +R6,uCC
5666
+
5667
+000000a0 <move_to_pc>:
5668
+  a0:  7b 40 10 00     JMP +\$-4096\+R0
5669
+  a4:  7b 40 90 01     JMP +\$-4095\+R2
5670
+  a8:  7b 41 0f ff     JMP +\$4095\+R4
5671
+  ac:  7b 41 80 00     JMP +R6
5672
+
5673
+000000b0 <move_to_sp>:
5674
+  b0:  6b 40 10 00     MOV +\$-4096\+R0,SP
5675
+  b4:  6b 40 90 01     MOV +\$-4095\+R2,SP
5676
+  b8:  6b 41 0f ff     MOV +\$4095\+R4,SP
5677
+  bc:  6b 41 80 00     MOV +R6,SP
5678
+
5679
+000000c0 <move_to_cc>:
5680
+  c0:  73 40 10 00     MOV +\$-4096\+R0,CC
5681
+  c4:  73 40 90 01     MOV +\$-4095\+R2,CC
5682
+  c8:  73 41 0f ff     MOV +\$4095\+R4,CC
5683
+  cc:  73 41 80 00     MOV +R6,CC
5684
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s
5685
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.s  1969-12-31 19:00:00.000000000 -0500
5686
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s      2017-01-12 16:45:17.027962005 -0500
5687
@@ -0,0 +1,93 @@
5688
+       .text
5689
+
5690
+mov_insn_test:
5691
+       mov     -4096+R0,R1
5692
+       mov     -4095+R2,R3
5693
+       mov     4095+R4,R5
5694
+       mov     R6,R7
5695
+       ;
5696
+mov_to_user:
5697
+       ;
5698
+       mov     -4096+R0,uR1
5699
+       mov     -4095+R2,uR3
5700
+       mov     4095+R4,uR5
5701
+       mov     R6,uR7
5702
+       ;
5703
+mov_from_user:
5704
+       ;
5705
+       mov     -4096+uR0,R1
5706
+       mov     -4095+uR2,R3
5707
+       mov     4095+uR4,R5
5708
+       mov     uR6,R7
5709
+       ;
5710
+mov_user_to_user:
5711
+       ;
5712
+       mov     -4096+uR0,uR1
5713
+       mov     -4095+uR2,uR3
5714
+       mov     4095+uR4,uR5
5715
+       mov     uR6,uR7
5716
+       ;
5717
+       ;
5718
+move_from_upc:
5719
+       ;
5720
+       mov     -4096+upc,uR1
5721
+       mov     -4095+upc,uR3
5722
+       mov     4095+upc,uR5
5723
+       mov     upc,uR7
5724
+       ;
5725
+move_from_usp:
5726
+       ;
5727
+       mov     -4096+usp,uR1
5728
+       mov     -4095+usp,uR3
5729
+       mov     4095+usp,uR5
5730
+       mov     usp,uR7
5731
+       ;
5732
+move_from_ucc:
5733
+       ;
5734
+       mov     -4096+ucc,uR1
5735
+       mov     -4095+ucc,uR3
5736
+       mov     4095+ucc,uR5
5737
+       mov     ucc,uR7
5738
+       ;
5739
+move_to_upc:
5740
+       ;
5741
+       mov     -4096+r0,upc
5742
+       mov     -4095+r2,upc
5743
+       mov     4095+r4,upc
5744
+       mov     r6,upc
5745
+       ;
5746
+move_to_usp:
5747
+       ;
5748
+       mov     -4096+r0,usp
5749
+       mov     -4095+r2,usp
5750
+       mov     4095+r4,usp
5751
+       mov     r6,usp
5752
+       ;
5753
+move_to_ucc:
5754
+       ;
5755
+       mov     -4096+r0,ucc
5756
+       mov     -4095+r2,ucc
5757
+       mov     4095+r4,ucc
5758
+       mov     r6,ucc
5759
+       ;
5760
+move_to_pc:
5761
+       ;
5762
+       mov     -4096+r0,pc
5763
+       mov     -4095+r2,pc
5764
+       mov     4095+r4,pc
5765
+       mov     r6,pc
5766
+       ;
5767
+move_to_sp:
5768
+       ;
5769
+       mov     -4096+r0,sp
5770
+       mov     -4095+r2,sp
5771
+       mov     4095+r4,sp
5772
+       mov     r6,sp
5773
+       ;
5774
+move_to_cc:
5775
+       ;
5776
+       mov     -4096+r0,cc
5777
+       mov     -4095+r2,cc
5778
+       mov     4095+r4,cc
5779
+       mov     r6,cc
5780
+       ;
5781
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d
5782
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.d       1969-12-31 19:00:00.000000000 -0500
5783
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d   2017-01-12 22:12:11.497444662 -0500
5784
@@ -0,0 +1,98 @@
5785
+#as: -novliw -nozipm
5786
+#objdump: -dr
5787
+#name: OpCode generation test
5788
+
5789
+.*: +file format elf32-zip
5790
+
5791
+
5792
+Disassembly of section .text:
5793
+
5794
+00000000 <optest>:
5795
+   0:  00 00 00 04     SUB +\$4,R0
5796
+   4:  08 40 00 04     AND +\$4,R1
5797
+   8:  10 80 00 04     ADD +\$4,R2
5798
+   c:  19 00 00 04     XOR +\$4,R3
5799
+  10:  20 c0 00 04     OR +\$4,R4
5800
+  14:  29 40 00 04     LSR +\$4,R5
5801
+  18:  31 80 00 04     LSL +\$4,R6
5802
+  1c:  39 c0 00 04     ASR +\$4,R7
5803
+  20:  02 40 00 03     LDILO +\$3,R0
5804
+  24:  0a 00 00 02     BREV +\$2,R1
5805
+  28:  12 80 00 03     MPYUHI +\$3,R2
5806
+  2c:  1a c0 00 03     MPYSHI +\$3,R3
5807
+  30:  23 00 00 03     MPY +\$3,R4
5808
+  34:  2b 80 00 07     DIVU +\$7,R5
5809
+  38:  33 c0 00 09     DIVS +\$9,R6
5810
+  3c:  04 00 00 05     CMP +\$5,R0
5811
+  40:  0c 40 00 05     TST +\$5,R1
5812
+  44:  1c 43 ff ff     TST +\$-1,R3
5813
+  48:  24 43 ff ff     TST +\$-1,R4
5814
+  4c:  14 40 00 04     TST +\$4,R2
5815
+  50:  0d 84 00 04     LB +4\(R0\),R1
5816
+  54:  15 c4 40 04     SB +R2,\$4\(R1\)
5817
+  58:  1d 04 80 04     LH +4\(R2\),R3
5818
+  5c:  25 44 c0 04     SH +R4,\$4\(R3\)
5819
+  60:  2c 85 00 04     LW +4\(R4\),R5
5820
+  64:  34 c5 40 04     SW +R6,\$4\(R5\)
5821
+  68:  17 80 00 07     FPI2F +\$7,R2
5822
+  6c:  17 84 40 03     FPI2F +\$3\+R1,R2
5823
+  70:  16 84 c0 00     FPADD +R3,R2
5824
+  74:  27 05 c0 00     FPMPY +R7,R4
5825
+  78:  4f 45 80 00     FPDIV +R6,R9
5826
+  7c:  57 c6 00 00     FPF2I +R8,R10
5827
+  80:  00 07 00 07     SUB +\$7\+R12,R0
5828
+  84:  08 47 00 07     AND +\$7\+R12,R1
5829
+  88:  10 87 00 07     ADD +\$7\+R12,R2
5830
+  8c:  19 07 00 07     XOR +\$7\+R12,R3
5831
+  90:  20 c7 00 07     OR +\$7\+R12,R4
5832
+  94:  29 47 00 07     LSR +\$7\+R12,R5
5833
+  98:  31 87 00 07     LSL +\$7\+R12,R6
5834
+  9c:  39 c7 00 07     ASR +\$7\+R12,R7
5835
+  a0:  00 07 3f fd     SUB +\$-3\+R12,R0
5836
+  a4:  08 47 3f fd     AND +\$-3\+R12,R1
5837
+  a8:  10 87 3f fd     ADD +\$-3\+R12,R2
5838
+  ac:  19 07 3f fd     XOR +\$-3\+R12,R3
5839
+  b0:  20 c7 3f fd     OR +\$-3\+R12,R4
5840
+  b4:  29 47 3f fd     LSR +\$-3\+R12,R5
5841
+  b8:  31 87 3f fd     LSL +\$-3\+R12,R6
5842
+  bc:  39 c7 3f fd     ASR +\$-3\+R12,R7
5843
+  c0:  02 47 01 66     LDILO +\$358\+R12,R0
5844
+  c4:  0a 04 7e 9a     BREV +\$-358\+R1,R1
5845
+  c8:  12 84 7e 9a     MPYUHI +\$-358\+R1,R2
5846
+  cc:  1a c4 7e 9a     MPYSHI +\$-358\+R1,R3
5847
+  d0:  23 04 7e 9a     MPY +\$-358\+R1,R4
5848
+  d4:  2b 84 7e 9a     DIVU +\$-358\+R1,R5
5849
+  d8:  33 c4 7e 9a     DIVS +\$-358\+R1,R6
5850
+  dc:  04 04 bf ed     CMP +\$-19\+R2,R0
5851
+  e0:  0c 44 bf ed     TST +\$-19\+R2,R1
5852
+  e4:  0d 80 01 04     LB +\(\$260\),R1
5853
+  e8:  15 c0 01 06     SB +R2,\(\$262\)
5854
+  ec:  1d 00 01 10     LH +\(\$272\),R3
5855
+  f0:  25 40 01 12     SH +R4,\(\$274\)
5856
+  f4:  2c 80 01 19     LW +\(\$281\),R5
5857
+  f8:  34 c0 01 ab     SW +R6,\(\$427\)
5858
+  fc:  00 02 00 00     SUB +\$-131072,R0
5859
+ 100:  00 02 00 00     SUB +\$-131072,R0
5860
+ 104:  08 42 00 00     AND +\$-131072,R1
5861
+ 108:  10 82 00 00     ADD +\$-131072,R2
5862
+ 10c:  19 02 00 00     XOR +\$-131072,R3
5863
+ 110:  20 c2 00 00     OR +\$-131072,R4
5864
+ 114:  29 42 00 00     LSR +\$-131072,R5
5865
+ 118:  31 82 00 00     LSL +\$-131072,R6
5866
+ 11c:  39 c2 00 00     ASR +\$-131072,R7
5867
+ 120:  02 40 14 85     LDILO +\$5253,R0
5868
+ 124:  0a 02 00 00     BREV +\$-131072,R1
5869
+ 128:  12 82 00 00     MPYUHI +\$-131072,R2
5870
+ 12c:  1a c2 00 00     MPYSHI +\$-131072,R3
5871
+ 130:  23 02 00 00     MPY +\$-131072,R4
5872
+ 134:  2b 82 00 00     DIVU +\$-131072,R5
5873
+ 138:  33 c2 00 00     DIVS +\$-131072,R6
5874
+ 13c:  04 02 00 00     CMP +\$-131072,R0
5875
+ 140:  0c 42 00 00     TST +\$-131072,R1
5876
+ 144:  0d 82 00 00     LB +\(\$-131072\),R1
5877
+ 148:  15 c2 00 00     SB +R2,\(\$-131072\)
5878
+ 14c:  1d 02 00 00     LH +\(\$-131072\),R3
5879
+ 150:  25 42 00 00     SH +R4,\(\$-131072\)
5880
+ 154:  2c 82 00 00     LW +\(\$-131072\),R5
5881
+ 158:  34 c2 00 00     SW +R6,\(\$-131072\)
5882
+ 15c:  17 82 00 00     FPI2F +\$-131072,R2
5883
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s
5884
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.s       1969-12-31 19:00:00.000000000 -0500
5885
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s   2017-01-12 16:28:47.212542071 -0500
5886
@@ -0,0 +1,119 @@
5887
+       .text
5888
+
5889
+optest:
5890
+       sub     4,R0
5891
+       and     4,R1
5892
+       add     4,R2
5893
+       xor     4,R3
5894
+       or      4,R4
5895
+       lsr     4,R5
5896
+       lsl     4,R6
5897
+       asr     4,R7
5898
+       ;
5899
+       ldilo   3,R0
5900
+       brev    2,R1
5901
+       mpyuhi  3,R2
5902
+       mpyshi  3,R3
5903
+       mpy     3,R4
5904
+       divu    7,R5
5905
+       divs    9,r6
5906
+       ; mov   R1,R2
5907
+
5908
+       ;
5909
+       cmp     5,R0
5910
+       test    5,R1
5911
+       test    R3
5912
+       tst     R4
5913
+       tst     4,R2
5914
+       ;
5915
+       lb      4(r0),r1
5916
+       sb      r2,4(r1)
5917
+       lh      4(r2),r3
5918
+       sh      r4,4(r3)
5919
+       lw      4(r4),r5
5920
+       sw      r6,4(r5)
5921
+       ; ldi
5922
+       fpi2f   7,r2
5923
+       fpi2f   3(r1),r2
5924
+       fpadd   r3,r2
5925
+       ; fpmpy r7,r4
5926
+       fpmul   r7,r4
5927
+       fpdiv   r6,r9
5928
+       fpf2i   r8,r10
5929
+       ;
5930
+       ;
5931
+; Now repeat, with Reg + Imm
5932
+       sub     7(r12),R0
5933
+       and     7(r12),R1
5934
+       add     7(r12),R2
5935
+       xor     7(r12),R3
5936
+       or      7(r12),R4
5937
+       lsr     7(r12),R5
5938
+       lsl     7(r12),R6
5939
+       asr     7(r12),R7
5940
+       ;
5941
+       sub     -3+r12,R0
5942
+       and     -3+r12,R1
5943
+       add     -3+r12,R2
5944
+       xor     -3+r12,R3
5945
+       or      -3+r12,R4
5946
+       lsr     -3+r12,R5
5947
+       lsl     -3+r12,R6
5948
+       asr     -3+r12,R7
5949
+       ;
5950
+       ldilo   358+r12,R0
5951
+       brev    -358+r1,R1
5952
+       mpyuhi  -358+r1,R2
5953
+       mpyshi  -358+r1,R3
5954
+       mpy     -358+r1,R4
5955
+       divu    -358+r1,R5
5956
+       divs    -358+r1,r6
5957
+       ; mov   R1,R2
5958
+
5959
+       ;
5960
+       cmp     -19+r2,R0
5961
+       test    -19+r2,R1
5962
+       ;
5963
+       lb      0x104,r1
5964
+       sb      r2,0x106
5965
+       lh      0x110,r3
5966
+       sh      r4,0x112
5967
+       lw      0x119,r5
5968
+       sw      r6,0x1ab
5969
+       ; ldi
5970
+       ; floating point --- already done
5971
+
5972
+
5973
+; Ops with the minimum integer
5974
+       sub     -0x20000,R0
5975
+       sub     -131072,R0
5976
+       and     -131072,R1
5977
+       add     -131072,R2
5978
+       xor     -0x20000,R3
5979
+       or      -131072,R4
5980
+       lsr     -131072,R5
5981
+       lsl     -131072,R6
5982
+       asr     -131072,R7
5983
+       ;
5984
+       ldilo   0x21485,R0
5985
+       brev    -0x20000,R1
5986
+       mpyuhi  -0x20000,R2
5987
+       mpyshi  -0x20000,R3
5988
+       mpy     -0x20000,R4
5989
+       divu    -0x20000,R5
5990
+       divs    -0x20000,r6
5991
+       ; mov   R1,R2
5992
+
5993
+       ;
5994
+       cmp     -0x20000,R0
5995
+       test    -0x20000,R1
5996
+       ;
5997
+       lb      -0x20000,r1
5998
+       sb      r2,-0x20000
5999
+       lh      -0x20000,r3
6000
+       sh      r4,-0x20000
6001
+       lw      -0x20000,r5
6002
+       sw      r6,-0x20000
6003
+       ; ldi
6004
+       fpi2f   -0x20000,r2
6005
+       ;
6006
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d
6007
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.d     1969-12-31 19:00:00.000000000 -0500
6008
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d 2017-01-10 11:09:36.301473902 -0500
6009
@@ -0,0 +1,32 @@
6010
+#as: -novliw
6011
+#objdump: -dr
6012
+#name: Prologue test - Non-thumb
6013
+
6014
+.*: +file format elf32-zip
6015
+
6016
+
6017
+Disassembly of section .text:
6018
+
6019
+00000000 <some_function>:
6020
+   0:  68 00 00 30     SUB +\$48,SP
6021
+   4:  04 c7 40 00     SW +R0,\(SP\)
6022
+   8:  2c c7 40 04     SW +R5,\$4\(SP\)
6023
+   c:  34 c7 40 08     SW +R6,\$8\(SP\)
6024
+  10:  3c c7 40 0c     SW +R7,\$12\(SP\)
6025
+  14:  44 c7 40 10     SW +R8,\$16\(SP\)
6026
+  18:  4c c7 40 14     SW +R9,\$20\(SP\)
6027
+  1c:  54 c7 40 18     SW +R10,\$24\(SP\)
6028
+  20:  5c c7 40 1c     SW +R11,\$28\(SP\)
6029
+  24:  64 c7 40 20     SW +R12,\$32\(SP\)
6030
+  28:  38 84 80 00     ADD +R2,R7
6031
+  2c:  04 87 40 00     LW +\(SP\),R0
6032
+  30:  04 87 40 04     LW +4\(SP\),R0
6033
+  34:  04 87 40 08     LW +8\(SP\),R0
6034
+  38:  04 87 40 0c     LW +12\(SP\),R0
6035
+  3c:  04 87 40 10     LW +16\(SP\),R0
6036
+  40:  04 87 40 14     LW +20\(SP\),R0
6037
+  44:  04 87 40 18     LW +24\(SP\),R0
6038
+  48:  04 87 40 1c     LW +28\(SP\),R0
6039
+  4c:  04 87 40 20     LW +32\(SP\),R0
6040
+  50:  68 80 00 30     ADD +\$48,SP
6041
+  54:  7b 40 00 00     RTN +
6042
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s
6043
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.s     1969-12-31 19:00:00.000000000 -0500
6044
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s 2017-01-09 07:25:40.495644200 -0500
6045
@@ -0,0 +1,24 @@
6046
+some_function:
6047
+       SUB     48,SP
6048
+       SW      R0,(SP)
6049
+       SW      R5,4(SP)
6050
+       SW      R6,8(SP)
6051
+       SW      R7,12(SP)
6052
+       SW      R8,16(SP)
6053
+       SW      R9,20(SP)
6054
+       SW      R10,24(SP)
6055
+       SW      R11,28(SP)
6056
+       SW      R12,32(SP)
6057
+       ADD     R2,R7
6058
+       LW      (SP),R0
6059
+       LW      4(SP),R0
6060
+       LW      8(SP),R0
6061
+       LW      12(SP),R0
6062
+       LW      16(SP),R0
6063
+       LW      20(SP),R0
6064
+       LW      24(SP),R0
6065
+       LW      28(SP),R0
6066
+       LW      32(SP),R0
6067
+       ADD     48,SP
6068
+       RETN
6069
+
6070
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d
6071
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.d    1969-12-31 19:00:00.000000000 -0500
6072
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d        2017-01-12 21:58:59.513900839 -0500
6073
@@ -0,0 +1,21 @@
6074
+#as: -nozipm -vliw
6075
+#objdump: -dr
6076
+#name: Prologue test - thumb
6077
+
6078
+.*: +file format elf32-zip
6079
+
6080
+
6081
+Disassembly of section .text:
6082
+
6083
+00000000 <some_function>:
6084
+   0:  e8 30 85 00     SUB +\$48,SP +| SW +R0,\(SP\)
6085
+   4:  ad 04 b5 08     SW +R5,\$4\(SP\) +| SW +R6,$8\(SP\)
6086
+   8:  bd 0c c5 10     SW +R7,\$12\(SP\) +| SW +R8,$16\(SP\)
6087
+   c:  cd 14 d5 18     SW +R9,\$20\(SP\) +| SW +R10,$24\(SP\)
6088
+  10:  dd 1c e5 20     SW +R11,\$28\(SP\) +| SW +R12,$32\(SP\)
6089
+  14:  ba 90 84 00     ADD +R2,R7 +| LW +\(SP\),R0
6090
+  18:  84 04 84 08     LW +4\(SP\),R0 +| LW +8\(SP\),R0
6091
+  1c:  84 0c 84 10     LW +12\(SP\),R0 +| LW +16\(SP\),R0
6092
+  20:  84 14 84 18     LW +20\(SP\),R0 +| LW +24\(SP\),R0
6093
+  24:  84 1c 84 20     LW +28\(SP\),R0 +| LW +32\(SP\),R0
6094
+  28:  ea 30 ff 80     ADD +\$48,SP +| MOV +R0,PC
6095
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s
6096
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.s    1969-12-31 19:00:00.000000000 -0500
6097
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s        2017-01-10 11:29:18.612449601 -0500
6098
@@ -0,0 +1,24 @@
6099
+some_function:
6100
+       SUB     48,SP
6101
+       SW      R0,(SP)
6102
+       SW      R5,4(SP)
6103
+       SW      R6,8(SP)
6104
+       SW      R7,12(SP)
6105
+       SW      R8,16(SP)
6106
+       SW      R9,20(SP)
6107
+       SW      R10,24(SP)
6108
+       SW      R11,28(SP)
6109
+       SW      R12,32(SP)
6110
+       ADD     R2,R7
6111
+       LW      (SP),R0
6112
+       LW      4(SP),R0
6113
+       LW      8(SP),R0
6114
+       LW      12(SP),R0
6115
+       LW      16(SP),R0
6116
+       LW      20(SP),R0
6117
+       LW      24(SP),R0
6118
+       LW      28(SP),R0
6119
+       LW      32(SP),R0
6120
+       ADD     48,SP
6121
+       RETN
6122
+
6123
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d
6124
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.d     1969-12-31 19:00:00.000000000 -0500
6125
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d 2017-01-24 08:03:32.892847657 -0500
6126
@@ -0,0 +1,41 @@
6127
+#as:
6128
+#objdump: -dr
6129
+#name: Special instruction(s) test
6130
+
6131
+.*: +file format elf32-zip
6132
+
6133
+
6134
+Disassembly of section .text:
6135
+
6136
+00000000 <specials_test>:
6137
+   0:  7f 00 00 00     BRK
6138
+   4:  7f 00 00 11     BRK        \$17
6139
+   8:  7f c0 00 00     NOOP
6140
+   c:  7f c0 02 ff     NDUMP *$
6141
+  10:  7f c0 02 07     NDUMP      R7
6142
+  14:  7f c0 02 03     NDUMP      R3
6143
+  18:  7f c0 02 14     NDUMP      uR4
6144
+  1c:  7f c0 01 00     NEXIT
6145
+  20:  7f c0 01 00     NEXIT
6146
+  24:  7f c0 01 fc     NEXIT      \$-4
6147
+  28:  7f c0 01 f0     NEXIT      \$-16
6148
+  2c:  7f c0 03 07     NEXIT      R7
6149
+  30:  7f c4 00 23     NSIM       \$262179
6150
+  34:  7f 80 00 00     SIM +$
6151
+  38:  7f 80 02 ff     SDUMP *$
6152
+  3c:  7f 80 02 07     SDUMP      R7
6153
+  40:  7f 80 02 03     SDUMP      R3
6154
+  44:  7f 80 02 14     SDUMP      uR4
6155
+  48:  7f 80 01 17     SEXIT      \$23
6156
+  4c:  7f 80 01 e9     SEXIT      \$-23
6157
+  50:  7f 80 01 00     SEXIT
6158
+  54:  7f 80 03 0f     SEXIT      PC
6159
+  58:  7f 80 03 0e     SEXIT      CC
6160
+  5c:  7f 84 00 23     SIM        \$262179
6161
+  60:  7f 87 0f 23     SIM        \$462627
6162
+  64:  7f 80 04 61     SOUT       \$97
6163
+  68:  7f c0 04 62     NOUT       \$98
6164
+  6c:  7f 80 02 22     SOUT       R2
6165
+  70:  7f c0 02 27     NOUT       R7
6166
+  74:  7f 80 02 33     SOUT       uR3
6167
+  78:  7f c0 02 38     NOUT       uR8
6168
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s
6169
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.s     1969-12-31 19:00:00.000000000 -0500
6170
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s 2017-01-19 07:18:13.405003668 -0500
6171
@@ -0,0 +1,35 @@
6172
+       .text
6173
+
6174
+specials_test:
6175
+       break
6176
+       break   17
6177
+       noop
6178
+       ndump
6179
+       ndump   R7
6180
+       ndump   sR3
6181
+       ndump   uR4
6182
+       nexit
6183
+       nexit   0
6184
+       nexit   -4
6185
+       nexit   240
6186
+       nexit   R7
6187
+       noop    0x40023
6188
+       snoop
6189
+       sdump
6190
+       sdump   R7
6191
+       sdump   sR3
6192
+       sdump   uR4
6193
+       sexit   23
6194
+       sexit   -23
6195
+       sexit   0
6196
+       sexit   PC
6197
+       sexit   CC
6198
+       snoop   0x40023
6199
+       sim     0x70f23
6200
+       sout    'a'
6201
+       nout    'b'
6202
+       sout    R2
6203
+       nout    R7
6204
+       sout    uR3
6205
+       nout    uR8
6206
+
6207
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d
6208
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.d 1969-12-31 19:00:00.000000000 -0500
6209
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d     2017-01-12 21:50:28.719237156 -0500
6210
@@ -0,0 +1,77 @@
6211
+#as: -vliw
6212
+#objdump: -dr
6213
+#name: Thumb instruction set test
6214
+
6215
+.*: +file format elf32-zip
6216
+
6217
+
6218
+Disassembly of section .text:
6219
+
6220
+00000000 <vliw_merge_test>:
6221
+   0:  82 01 8a 01     ADD +\$1,R0 +| ADD +$1,R1
6222
+   4:  10 88 00 01     ADD.Z +\$1,R2
6223
+   8:  18 a8 00 01     ADD.NZ +\$1,R3
6224
+   c:  20 a0 00 01     ADD.V +\$1,R4
6225
+  10:  00 80 00 7f     ADD +\$127,R0
6226
+  14:  00 80 00 80     ADD +\$128,R0
6227
+  18:  00 80 00 81     ADD +\$129,R0
6228
+  1c:  82 3e 82 3f     ADD +\$62,R0 +| ADD +\$63,R0 *
6229
+  20:  00 80 00 40     ADD +\$64,R0
6230
+  24:  00 80 00 41     ADD +\$65,R0
6231
+  28:  82 88 82 89     ADD +R1,R0 +| ADD +\$1+R1,R0 *
6232
+  2c:  82 89 82 8a     ADD +\$1\+R1,R0 +| ADD +\$2\+R1,R0 *
6233
+  30:  82 8a 82 8a     ADD +\$2\+R1,R0 +| ADD +\$2\+R1,R0 *
6234
+  34:  00 84 40 03     ADD +\$3\+R1,R0
6235
+  38:  00 84 40 04     ADD +\$4\+R1,R0
6236
+  3c:  00 84 40 05     ADD +\$5\+R1,R0
6237
+  40:  00 84 7f fb     ADD +\$-5\+R1,R0
6238
+  44:  82 8c 82 8d     ADD +\$-4\+R1,R0 +| ADD +$-3+R1,R0 *
6239
+  48:  82 8e 82 8f     ADD +\$-2\+R1,R0 +| ADD +$-1+R1,R0 *
6240
+  4c:  82 88 84 88     ADD +R1,R0 +| LW +(R1),R0 *
6241
+  50:  94 89 9c 8a     LW  +1\(R1\),R2 +| LW +2(R1),R3 *
6242
+  54:  24 84 40 03     LW  +3\(R1\),R4
6243
+  58:  2c 84 40 04     LW  +4\(R1\),R5
6244
+  5c:  84 00 94 01     LW  +\(SP\),R0 +| LW +1\(SP\),R2 *
6245
+  60:  9c 02 a4 03     LW  +2\(SP\),R3 +| LW +3\(SP\),R4 *
6246
+  64:  ac 04 b4 3d     LW +4\(SP\),R5 +| LW +61\(SP\),R6 *
6247
+  68:  bc 3e c4 3f     LW +62\(SP\),R7 +| LW +63\(SP\),R8 *
6248
+  6c:  4c 87 40 40     LW +64\(SP\),R9
6249
+  70:  54 87 40 41     LW +65\(SP\),R10
6250
+  74:  54 c7 7f bf     SW +R10,\$-65\(SP\)
6251
+  78:  cd 40 c5 41     SW +R9,\$-64\(SP\) +| SW +R8,$-63\(SP\) *
6252
+  7c:  bd 42 b5 43     SW +R7,\$-62\(SP\) +| SW +R6,$-61\(SP\) *
6253
+  80:  b5 44 87 f8     SW +R6,\$-60\(SP\) +| MOV +PC,R0 *
6254
+  84:  8f f9 97 fa     MOV +\$4\+PC,R1 +| MOV +$8\+PC,R2 *
6255
+  88:  97 fa 9f fb     MOV +\$8\+PC,R2 +| MOV +$12\+PC,R3 *
6256
+  8c:  23 43 c0 04     MOV +0x000000a0,R4.*$
6257
+  90:  2b 43 c0 05     MOV +0x000000a8,R5.*$
6258
+  94:  33 43 df fb     MOV +0x00000084,R6.*$
6259
+  98:  bf fc c7 fd     MOV +\$-16\+PC,R7 +| MOV +$-12\+PC,R8 *
6260
+  9c:  cf fe 87 ff     MOV +\$-8\+PC,R9 +| MOV +$-4\+PC,R0 *
6261
+  a0:  13 43 c0 00     MOV +0x000000a4,R2.*$
6262
+
6263
+000000a4 <vliw_ldi_test>:
6264
+  a4:  86 00 8e 40     CLR +R0 +| LDI +\$64,R1
6265
+  a8:  16 00 00 7f     LDI +\$127,R2
6266
+  ac:  1e 00 00 80     LDI +\$128,R3
6267
+  b0:  26 00 00 81     LDI +\$129,R4
6268
+  b4:  2e 00 00 82     LDI +\$130,R5
6269
+  b8:  36 7f ff 7e     LDI +\$-130,R6
6270
+  bc:  3e 7f ff 7f     LDI +\$-129,R7
6271
+  c0:  c6 80 ce 81     LDI +\$-128,R8 +| LDI +\$-127,R9
6272
+  c4:  d6 82 de 83     LDI +\$-126,R10 +| LDI +\$-125,R11
6273
+
6274
+000000c8 <vliw_op_test>:
6275
+  c8:  88 80 99 90     SUB +R0,R1 +| AND +R2,R3 *$
6276
+  cc:  aa a0 bb b0     ADD +R4,R5 +| CMP +R6,uR7 *$
6277
+  d0:  c4 b8 cd d0     LW +\(R7\),R8 +| SW +R9,\$-48\(SP\) *$
6278
+  d4:  de 7c 9f 89     LDI +\$124,R11 +| MOV +$1+R1,R3 *$
6279
+  d8:  c8 05 88 80     SUB +\$5,R9 +| SUB +R0,R1 *$
6280
+  dc:  99 90 aa a0     AND +R2,R3 +| ADD +R4,R5 *$
6281
+  e0:  bb b0 c4 b8     CMP +R6,uR7 +| LW +(R7),R8 *$
6282
+  e4:  cd d0 de 7c     SW +R9,\$-48\(SP\) +| LDI +\$124,R11 *$
6283
+  e8:  9f 89 c8 0e     MOV +\$1\+R1,R3 +| SUB +\$14,R9 *$
6284
+  ec:  99 11 aa 13     AND +\$17,R3 +| ADD +\$19,R5 *$
6285
+  f0:  bb 3f c4 18     CMP +\$63\+R7,R7 +| LW         24\(SP\),R8 *$
6286
+  f4:  cd 1c de 7c     SW +R9,\$28\(SP\) +| LDI +\$124,R11 *$
6287
+  f8:  1b 40 40 01     MOV +\$1\+R1,R3
6288
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s
6289
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.s 1969-12-31 19:00:00.000000000 -0500
6290
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s     2017-01-12 16:55:54.690241718 -0500
6291
@@ -0,0 +1,110 @@
6292
+       .text
6293
+
6294
+vliw_merge_test:
6295
+       ; Simple: are merges enabled?
6296
+       add     1,R0
6297
+       add     1,R1
6298
+       ; These should not merge with any neighbor
6299
+       add.z   1,R2
6300
+       add.nz  1,R3
6301
+       add.v   1,R4
6302
+       add     127,R0
6303
+       add     128,R0
6304
+       add     129,R0
6305
+       add     62,R0
6306
+       add     63,R0
6307
+       add     64,R0
6308
+       add     65,R0
6309
+       add     0(R1),R0
6310
+       add     1(R1),R0
6311
+       add     1(R1),R0
6312
+       add     2(R1),R0
6313
+       add     2(R1),R0
6314
+       add     2(R1),R0
6315
+       add     3(R1),R0
6316
+       add     4(R1),R0
6317
+       add     5(R1),R0
6318
+       add     -5(R1),R0
6319
+       add     -4(R1),R0
6320
+       add     -3(R1),R0
6321
+       add     -2(R1),R0
6322
+       add     -1(R1),R0
6323
+       add     0(R1),R0
6324
+       lw      (r1),r0
6325
+       lw      1(r1),r2
6326
+       lw      2(r1),r3
6327
+       lw      3(r1),r4
6328
+       lw      4(r1),r5
6329
+       lw      (sp),r0
6330
+       lw      1(sp),r2
6331
+       lw      2(sp),r3
6332
+       lw      3(sp),r4
6333
+       lw      4(sp),r5
6334
+       lw      61(sp),r6
6335
+       lw      62(sp),r7
6336
+       lw      63(sp),r8
6337
+       lw      64(sp),r9
6338
+       lw      65(sp),r10
6339
+       sw      r10,-65(sp)
6340
+       sw      r9,-64(sp)
6341
+       sw      r8,-63(sp)
6342
+       sw      r7,-62(sp)
6343
+       sw      r6,-61(sp)
6344
+       sw      r6,-60(sp)
6345
+       mov     (PC),R0
6346
+       mov     1(PC),R1
6347
+       mov     2(PC),R2
6348
+       mov     2(PC),R2
6349
+       mov     3(PC),R3
6350
+       mov     4(PC),R4
6351
+       mov     5(PC),R5
6352
+       mov     -5(PC),R6
6353
+       mov     -4(PC),R7
6354
+       mov     -3(PC),R8
6355
+       mov     -2(PC),R9
6356
+       mov     -1(PC),R0
6357
+       mov     0(PC),R2
6358
+       # LDI's
6359
+vliw_ldi_test:
6360
+       LDI     0,R0
6361
+       LDI     64,R1
6362
+       LDI     127,R2
6363
+       LDI     128,R3
6364
+       LDI     129,R4
6365
+       LDI     130,R5
6366
+       LDI     -130,R6
6367
+       LDI     -129,R7
6368
+       LDI     -128,R8
6369
+       LDI     -127,R9
6370
+       LDI     -126,R10
6371
+       LDI     -125,R11
6372
+vliw_op_test:
6373
+       sub     r0,r1
6374
+       and     r2,r3
6375
+       add     r4,r5
6376
+       cmp     r6,r7
6377
+       lw      (r7),r8
6378
+       sw      r9,(r10)
6379
+       ldi     124,r11
6380
+       mov     1+r1,r3
6381
+       # and with a touch of offset
6382
+       sub     5,r9
6383
+       sub     r0,r1
6384
+       and     r2,r3
6385
+       add     r4,r5
6386
+       cmp     r6,r7
6387
+       lw      (r7),r8
6388
+       sw      r9,(r10)
6389
+       ldi     124,r11
6390
+       mov     1+r1,r3
6391
+       # And now, so that they all have immediates instead of register
6392
+       sub     14,r9
6393
+       and     17,r3
6394
+       add     19,r5
6395
+       cmp     63,r7
6396
+       lw      24(sp),r8
6397
+       sw      r9,28(sp)
6398
+       ldi     124,r11
6399
+       mov     1+r1,r3
6400
+
6401
+
6402
diff -Naur '--exclude=*.swp' binutils-2.27/gas/write.c binutils-2.27-zip/gas/write.c
6403
--- binutils-2.27/gas/write.c   2016-08-03 03:36:51.000000000 -0400
6404
+++ binutils-2.27-zip/gas/write.c       2016-12-31 17:51:52.470985149 -0500
6405
@@ -2676,7 +2676,7 @@
6406
 
6407
              case rs_org:
6408
                {
6409
-                 addressT target = offset;
6410
+                 addressT target = offset * OCTETS_PER_BYTE;
6411
                  addressT after;
6412
 
6413
                  if (symbolP)
6414
diff -Naur '--exclude=*.swp' binutils-2.27/include/dis-asm.h binutils-2.27-zip/include/dis-asm.h
6415
--- binutils-2.27/include/dis-asm.h     2016-08-03 03:36:53.000000000 -0400
6416
+++ binutils-2.27-zip/include/dis-asm.h 2016-12-31 17:52:29.022758231 -0500
6417
@@ -318,10 +318,12 @@
6418
 extern int print_insn_rl78_g10         (bfd_vma, disassemble_info *);
6419
 extern int print_insn_rl78_g13         (bfd_vma, disassemble_info *);
6420
 extern int print_insn_rl78_g14         (bfd_vma, disassemble_info *);
6421
+extern int print_insn_zip              (bfd_vma, disassemble_info *);
6422
 
6423
 extern disassembler_ftype arc_get_disassembler (bfd *);
6424
 extern disassembler_ftype cris_get_disassembler (bfd *);
6425
 extern disassembler_ftype rl78_get_disassembler (bfd *);
6426
+extern disassembler_ftype zip_get_disassembler (bfd *);
6427
 
6428
 extern void print_aarch64_disassembler_options (FILE *);
6429
 extern void print_i386_disassembler_options (FILE *);
6430
diff -Naur '--exclude=*.swp' binutils-2.27/include/elf/common.h binutils-2.27-zip/include/elf/common.h
6431
--- binutils-2.27/include/elf/common.h  2016-08-03 03:36:53.000000000 -0400
6432
+++ binutils-2.27-zip/include/elf/common.h      2016-12-31 17:53:58.942198950 -0500
6433
@@ -411,6 +411,9 @@
6434
 /* Old constant that might be in use by some software. */
6435
 #define EM_OPENRISC            EM_OR1K
6436
 
6437
+/* ZipCPU vs instruction set -- Use this until we get an official number */
6438
+#define EM_ZIP                 0xdad1
6439
+
6440
 /* See the above comment before you add a new EM_* value here.  */
6441
 
6442
 /* Values for e_version.  */
6443
diff -Naur '--exclude=*.swp' binutils-2.27/include/elf/zip.h binutils-2.27-zip/include/elf/zip.h
6444
--- binutils-2.27/include/elf/zip.h     1969-12-31 19:00:00.000000000 -0500
6445
+++ binutils-2.27-zip/include/elf/zip.h 2017-01-18 18:19:33.764898333 -0500
6446
@@ -0,0 +1,58 @@
6447
+////////////////////////////////////////////////////////////////////////////////
6448
+//
6449
+// Filename:   zip.h
6450
+//
6451
+// Project:    Zip CPU backend for GNU Binutils
6452
+//
6453
+// Purpose:
6454
+//
6455
+// Creator:    Dan Gisselquist, Ph.D.
6456
+//             Gisselquist Technology, LLC
6457
+//
6458
+////////////////////////////////////////////////////////////////////////////////
6459
+//
6460
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
6461
+//
6462
+// This program is free software (firmware): you can redistribute it and/or
6463
+// modify it under the terms of  the GNU General Public License as published
6464
+// by the Free Software Foundation, either version 3 of the License, or (at
6465
+// your option) any later version.
6466
+//
6467
+// This program is distributed in the hope that it will be useful, but WITHOUT
6468
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
6469
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
6470
+// for more details.
6471
+//
6472
+// You should have received a copy of the GNU General Public License along
6473
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
6474
+// target there if the PDF file isn't present.)  If not, see
6475
+// <http://www.gnu.org/licenses/> for a copy.
6476
+//
6477
+// License:    GPL, v3, as defined and found on www.gnu.org,
6478
+//             http://www.gnu.org/licenses/gpl.html
6479
+//
6480
+//
6481
+////////////////////////////////////////////////////////////////////////////////
6482
+#ifndef        _ELF_ZIP_H
6483
+#define        _ELF_ZIP_H
6484
+
6485
+#include "elf/reloc-macros.h"
6486
+
6487
+/* Relocations.  */
6488
+START_RELOC_NUMBERS(elf_zip_reloc_type)
6489
+  RELOC_NUMBER (R_ZIP_NONE,        0)
6490
+  RELOC_NUMBER (R_ZIP_VALUE,       1)
6491
+  RELOC_NUMBER (R_ZIP_BREV,        2)
6492
+  RELOC_NUMBER (R_ZIP_LLO,         3)
6493
+  RELOC_NUMBER (R_ZIP_LDI,         4)
6494
+  RELOC_NUMBER (R_ZIP_BRANCH,      5)
6495
+  RELOC_NUMBER (R_ZIP_OPB_IMM,     6)
6496
+  RELOC_NUMBER (R_ZIP_OPB_OFFSET,  7)
6497
+  RELOC_NUMBER (R_ZIP_OPB_PCREL,   8)
6498
+  RELOC_NUMBER (R_ZIP_MOV_OFFSET,  9)
6499
+  RELOC_NUMBER (R_ZIP_MOV_PCREL,  10)
6500
+  // RELOC_NUMBER (R_ZIP_OPB_GOTREL, 11)
6501
+  // RELOC_NUMBER (R_ZIP_MOV_GOTREL, 12)
6502
+END_RELOC_NUMBERS(R_ZIP_max)
6503
+
6504
+#endif /* _ELF_ZIP_H */
6505
diff -Naur '--exclude=*.swp' binutils-2.27/ld/configure.tgt binutils-2.27-zip/ld/configure.tgt
6506
--- binutils-2.27/ld/configure.tgt      2016-08-03 03:36:54.000000000 -0400
6507
+++ binutils-2.27-zip/ld/configure.tgt  2016-12-31 17:55:04.013793303 -0500
6508
@@ -816,6 +816,8 @@
6509
                        ;;
6510
 z8k-*-coff)            targ_emul=z8002; targ_extra_emuls=z8001
6511
                        ;;
6512
+zip*)                  targ_emul=elf32zip;
6513
+                       ;;
6514
 *-*-ieee*)             targ_emul=vanilla
6515
                        ;;
6516
 *-tandem-none)         targ_emul=st2000
6517
diff -Naur '--exclude=*.swp' binutils-2.27/ld/emulparams/elf32zip.sh binutils-2.27-zip/ld/emulparams/elf32zip.sh
6518
--- binutils-2.27/ld/emulparams/elf32zip.sh     1969-12-31 19:00:00.000000000 -0500
6519
+++ binutils-2.27-zip/ld/emulparams/elf32zip.sh 2017-01-05 08:22:45.000000000 -0500
6520
@@ -0,0 +1,50 @@
6521
+################################################################################
6522
+#
6523
+# Filename:    elf32zip.sh
6524
+#
6525
+# Project:     Zip CPU backend for GNU Binutils
6526
+#
6527
+# Purpose:     This is a simple shell script providing some variables used
6528
+#              later and elsewhere by the ZipCPU linker.  Some things to note
6529
+#      are: 1) the TEXT_START_ADDR is set for the Basys-3 board I am using and
6530
+#      will likely need to change as your platform changes, 2) there currently
6531
+#      aren't any "pages" since the ZipCPU doesn't yet support a memory
6532
+#      management unit, 3) the ENTRY point only works if a separate loader
6533
+#      is loading the ZipCPU into RAM.  In all other cases, place your startup
6534
+#      code directly at the top of the .start segment, and set the ZipCPU
6535
+#      to run from there.  It'll start then at the first address loaded in
6536
+#      memory.
6537
+#
6538
+# Creator:     Dan Gisselquist, Ph.D.
6539
+#              Gisselquist Technology, LLC
6540
+#
6541
+################################################################################
6542
+#
6543
+# Copyright (C) 2016, Gisselquist Technology, LLC
6544
+#
6545
+# This program is free software (firmware): you can redistribute it and/or
6546
+# modify it under the terms of  the GNU General Public License as published
6547
+# by the Free Software Foundation, either version 3 of the License, or (at
6548
+# your option) any later version.
6549
+#
6550
+# This program is distributed in the hope that it will be useful, but WITHOUT
6551
+# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
6552
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
6553
+# for more details.
6554
+#
6555
+# License:     GPL, v3, as defined and found on www.gnu.org,
6556
+#              http://www.gnu.org/licenses/gpl.html
6557
+#
6558
+#
6559
+################################################################################
6560
+
6561
+SCRIPT_NAME=elf
6562
+TEMPLATE_NAME=elf32
6563
+ARCH=zip
6564
+OUTPUT_FORMAT="elf32-zip"
6565
+ENTRY="_start"
6566
+TEXT_START_ADDR="0x08000"
6567
+MAXPAGESIZE=0x01000
6568
+COMMONPAGESIZE=0x1000
6569
+EMBEDDED=yes
6570
+
6571
diff -Naur '--exclude=*.swp' binutils-2.27/ld/Makefile.am binutils-2.27-zip/ld/Makefile.am
6572
--- binutils-2.27/ld/Makefile.am        2016-08-03 03:36:54.000000000 -0400
6573
+++ binutils-2.27-zip/ld/Makefile.am    2016-12-31 17:57:39.684819835 -0500
6574
@@ -286,6 +286,7 @@
6575
        eelf32xc16xs.c \
6576
        eelf32xstormy16.c \
6577
        eelf32xtensa.c \
6578
+       eelf32zip.c \
6579
        eelf_i386.c \
6580
        eelf_i386_be.c \
6581
        eelf_i386_chaos.c \
6582
@@ -1309,6 +1310,9 @@
6583
   $(BFDDIR)/elf-bfd.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/xtensa.h \
6584
   $(srcdir)/scripttempl/elfxtensa.sc ${GEN_DEPENDS}
6585
 
6586
+eelf32zip.c: $(srcdir)/emulparams/elf32zip.sh $(ELF_DEPS) \
6587
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
6588
+
6589
 eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
6590
   $(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
6591
 
6592
diff -Naur '--exclude=*.swp' binutils-2.27/ld/Makefile.in binutils-2.27-zip/ld/Makefile.in
6593
--- binutils-2.27/ld/Makefile.in        2016-08-03 03:36:54.000000000 -0400
6594
+++ binutils-2.27-zip/ld/Makefile.in    2016-12-31 17:59:30.788122513 -0500
6595
@@ -654,6 +654,7 @@
6596
        eelf32xc16xs.c \
6597
        eelf32xstormy16.c \
6598
        eelf32xtensa.c \
6599
+       eelf32zip.c \
6600
        eelf_i386.c \
6601
        eelf_i386_be.c \
6602
        eelf_i386_chaos.c \
6603
@@ -1314,6 +1315,7 @@
6604
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Po@am__quote@
6605
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Po@am__quote@
6606
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@
6607
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32zip.Po@am__quote@
6608
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Po@am__quote@
6609
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Po@am__quote@
6610
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Po@am__quote@
6611
@@ -2897,6 +2899,9 @@
6612
   $(BFDDIR)/elf-bfd.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/xtensa.h \
6613
   $(srcdir)/scripttempl/elfxtensa.sc ${GEN_DEPENDS}
6614
 
6615
+eelf32zip.c: $(srcdir)/emulparams/elf32zip.sh $(ELF_DEPS) \
6616
+  $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
6617
+
6618
 eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
6619
   $(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
6620
 
6621
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/configure binutils-2.27-zip/opcodes/configure
6622
--- binutils-2.27/opcodes/configure     2016-08-03 04:33:39.000000000 -0400
6623
+++ binutils-2.27-zip/opcodes/configure 2017-01-05 08:50:32.000000000 -0500
6624
@@ -12685,7 +12685,7 @@
6625
        bfd_xtensa_arch)        ta="$ta xtensa-dis.lo" ;;
6626
        bfd_z80_arch)           ta="$ta z80-dis.lo" ;;
6627
        bfd_z8k_arch)           ta="$ta z8k-dis.lo" ;;
6628
-
6629
+       bfd_zip_arch)           ta="$ta zip-dis.lo zip-opc.lo" ;;
6630
        "")                     ;;
6631
        *)              as_fn_error "*** unknown target architecture $arch" "$LINENO" 5 ;;
6632
        esac
6633
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/configure.ac binutils-2.27-zip/opcodes/configure.ac
6634
--- binutils-2.27/opcodes/configure.ac  2016-08-03 03:36:54.000000000 -0400
6635
+++ binutils-2.27-zip/opcodes/configure.ac      2017-01-05 08:49:53.000000000 -0500
6636
@@ -353,7 +353,7 @@
6637
        bfd_xtensa_arch)        ta="$ta xtensa-dis.lo" ;;
6638
        bfd_z80_arch)           ta="$ta z80-dis.lo" ;;
6639
        bfd_z8k_arch)           ta="$ta z8k-dis.lo" ;;
6640
-
6641
+       bfd_zip_arch)           ta="$ta zip-dis.lo zip-opc.lo" ;;
6642
        "")                     ;;
6643
        *)              AC_MSG_ERROR(*** unknown target architecture $arch) ;;
6644
        esac
6645
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/disassemble.c binutils-2.27-zip/opcodes/disassemble.c
6646
--- binutils-2.27/opcodes/disassemble.c 2016-08-03 03:36:54.000000000 -0400
6647
+++ binutils-2.27-zip/opcodes/disassemble.c     2016-12-31 18:02:03.139162969 -0500
6648
@@ -98,6 +98,7 @@
6649
 #define ARCH_xtensa
6650
 #define ARCH_z80
6651
 #define ARCH_z8k
6652
+#define ARCH_zip
6653
 #define INCLUDE_SHMEDIA
6654
 #endif
6655
 
6656
@@ -495,6 +496,11 @@
6657
        disassemble = print_insn_z8002;
6658
       break;
6659
 #endif
6660
+#ifdef ARCH_zip
6661
+    case bfd_arch_zip:
6662
+       disassemble = zip_get_disassembler(abfd);
6663
+       break;
6664
+#endif
6665
 #ifdef ARCH_vax
6666
     case bfd_arch_vax:
6667
       disassemble = print_insn_vax;
6668
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/Makefile.am binutils-2.27-zip/opcodes/Makefile.am
6669
--- binutils-2.27/opcodes/Makefile.am   2016-08-03 03:36:54.000000000 -0400
6670
+++ binutils-2.27-zip/opcodes/Makefile.am       2017-01-05 08:28:32.000000000 -0500
6671
@@ -86,7 +86,9 @@
6672
        w65-opc.h \
6673
        xc16x-desc.h xc16x-opc.h \
6674
        xstormy16-desc.h xstormy16-opc.h \
6675
-       z8k-opc.h
6676
+       z8k-opc.h \
6677
+       zip-opc.h \
6678
+       zip-dis.h
6679
 
6680
 # C source files that correspond to .o's ending up in libopcodes
6681
 # for all machines.
6682
@@ -269,7 +271,9 @@
6683
        xgate-dis.c \
6684
        xgate-opc.c \
6685
        z80-dis.c \
6686
-       z8k-dis.c
6687
+       z8k-dis.c \
6688
+       zip-dis.c \
6689
+       zip-opc.c
6690
 
6691
 # C source files that correspond to .o's ending up in libopcodes.
6692
 LIBOPCODES_CFILES = \
6693
@@ -346,7 +350,6 @@
6694
        touch stamp-lib
6695
 
6696
 libopcodes.a: stamp-lib ; @true
6697
-
6698
 POTFILES = $(HFILES) $(CFILES)
6699
 po/POTFILES.in: @MAINT@ Makefile
6700
        for f in $(POTFILES); do echo $$f; done | LC_ALL=C sort > tmp \
6701
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/Makefile.in binutils-2.27-zip/opcodes/Makefile.in
6702
--- binutils-2.27/opcodes/Makefile.in   2016-08-03 03:36:54.000000000 -0400
6703
+++ binutils-2.27-zip/opcodes/Makefile.in       2017-01-05 08:28:04.000000000 -0500
6704
@@ -386,7 +386,9 @@
6705
        w65-opc.h \
6706
        xc16x-desc.h xc16x-opc.h \
6707
        xstormy16-desc.h xstormy16-opc.h \
6708
-       z8k-opc.h
6709
+       z8k-opc.h \
6710
+       zip-opc.h \
6711
+       zip-dis.h
6712
 
6713
 
6714
 # C source files that correspond to .o's ending up in libopcodes
6715
@@ -570,7 +572,9 @@
6716
        xgate-dis.c \
6717
        xgate-opc.c \
6718
        z80-dis.c \
6719
-       z8k-dis.c
6720
+       z8k-dis.c \
6721
+       zip-dis.c \
6722
+       zip-opc.c
6723
 
6724
 
6725
 # C source files that correspond to .o's ending up in libopcodes.
6726
@@ -974,6 +978,8 @@
6727
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xtensa-dis.Plo@am__quote@
6728
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/z80-dis.Plo@am__quote@
6729
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/z8k-dis.Plo@am__quote@
6730
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zip-dis.Plo@am__quote@
6731
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/zip-opc.Plo@am__quote@
6732
 
6733
 .c.o:
6734
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
6735
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-dis.c binutils-2.27-zip/opcodes/zip-dis.c
6736
--- binutils-2.27/opcodes/zip-dis.c     1969-12-31 19:00:00.000000000 -0500
6737
+++ binutils-2.27-zip/opcodes/zip-dis.c 2017-03-03 09:34:03.983308793 -0500
6738
@@ -0,0 +1,474 @@
6739
+////////////////////////////////////////////////////////////////////////////////
6740
+//
6741
+// Filename:   zip-dis.c
6742
+//
6743
+// Project:    Zip CPU backend for GNU Binutils
6744
+//
6745
+// Purpose:
6746
+//
6747
+// Creator:    Dan Gisselquist, Ph.D.
6748
+//             Gisselquist Technology, LLC
6749
+//
6750
+////////////////////////////////////////////////////////////////////////////////
6751
+//
6752
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
6753
+//
6754
+// This program is free software (firmware): you can redistribute it and/or
6755
+// modify it under the terms of  the GNU General Public License as published
6756
+// by the Free Software Foundation, either version 3 of the License, or (at
6757
+// your option) any later version.
6758
+//
6759
+// This program is distributed in the hope that it will be useful, but WITHOUT
6760
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
6761
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
6762
+// for more details.
6763
+//
6764
+// You should have received a copy of the GNU General Public License along
6765
+// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
6766
+// target there if the PDF file isn't present.)  If not, see
6767
+// <http://www.gnu.org/licenses/> for a copy.
6768
+//
6769
+// License:    GPL, v3, as defined and found on www.gnu.org,
6770
+//             http://www.gnu.org/licenses/gpl.html
6771
+//
6772
+//
6773
+////////////////////////////////////////////////////////////////////////////////
6774
+#include "config.h"
6775
+
6776
+#include <stdio.h>
6777
+#include <stdint.h>
6778
+#include <ctype.h>
6779
+#include <strings.h>
6780
+#include <string.h>
6781
+#include <assert.h>
6782
+
6783
+#include "zip-opc.h"
6784
+#include "zip-dis.h"
6785
+
6786
+static inline  int
6787
+TWOWORD_LOAD(uint32_t one, uint32_t two) {
6788
+       // BREV followed by LODILO
6789
+       if (((one&0x87c40000)==0x02000000)&&((two&0x87c40000)==0x02400000)
6790
+               // Must be to the same register too, and on the same condition
6791
+               &&(((one^two)&0xf8380000)==0))
6792
+               return 1;
6793
+       return 0;
6794
+}
6795
+
6796
+static inline  int
6797
+OFFSET_PC_MOV(uint32_t ins) {
6798
+       // 0.xxxx.01101.ccc.0.1111.0.iiiiiiiiiiiii
6799
+       // 0xxx.x011.01cc.c011.110i.iiii.iiii.iiii
6800
+       //
6801
+       return ((ins & 0x87c7e000)==0x0343c000);
6802
+}
6803
+
6804
+static inline  int
6805
+TWOWORD_LJMP(uint32_t iword) {
6806
+       // LJMP a long jump instruction, for which the address of the target
6807
+       // is found in the next word
6808
+       if (iword==0x7c87c000)
6809
+               return 1;
6810
+       // Now, the CIS form ... an
6811
+       // Unconditional LJMP in the second half word
6812
+       if ((iword&0x80007fff)==0x80007cf8)
6813
+               return 1;
6814
+       return 0;
6815
+}
6816
+
6817
+
6818
+static inline  int
6819
+TWOWORD_JSR(uint32_t iword, uint32_t nxtword) {
6820
+       // First word moves the return address to R0
6821
+       if (iword != 0x0343c001)
6822
+               return 0;
6823
+       // Second word is a BRA statement to ... anywhere
6824
+       // 0.1111.00010.ccc.0.iiiiiiiiiiiiiiiiii
6825
+       // 0111.1000.10cc.c0ii.iiii.iiii.iiii.iiii
6826
+       if ((nxtword&0xffc40000) == 0x78800000)
6827
+               return 1;
6828
+       return 0;
6829
+}
6830
+
6831
+static inline  int
6832
+THREEWORD_LJSR(uint32_t iword, uint32_t nxtword) {
6833
+       // First word moves the return address to R0
6834
+       if (iword!=0x0343c002)
6835
+               return 0;
6836
+       // Second word is an LJMP statement
6837
+       if (nxtword==0x7c87c000)
6838
+               return 1;
6839
+       return 0;
6840
+}
6841
+
6842
+static inline  int
6843
+TWOWORD_CIS_JSR(uint32_t iword) {
6844
+       // MOV 2(PC) | LOD (PC),PC
6845
+       //
6846
+       // 1.0000.111.1.1111.010
6847
+       //                      1.1111.100.1.1111.000
6848
+       if (iword == 0x87fafcf8)
6849
+               return 1;
6850
+       return 0;
6851
+}
6852
+
6853
+static inline  int
6854
+CIS_JSR(uint32_t iword __attribute__((unused)) ) {
6855
+       if (TWOWORD_CIS_JSR(iword))
6856
+               return 1;
6857
+       // MOV 1(PC) | MOV Rx,PC
6858
+       //
6859
+       // 1.0000.111.1.1111.001
6860
+       //                      1.1111.111.1.xxxx.000
6861
+       if ((iword&0xffffff87) == 0x87f9ff80)
6862
+               return 1;
6863
+       return 0;
6864
+}
6865
+
6866
+static inline  int
6867
+POSSIBLE_TWOWORD_BEGINNING(uint32_t iword) {
6868
+       // Unconditional LJMP
6869
+       if (TWOWORD_LJMP(iword))
6870
+               return 1;
6871
+       // MOV 1(PC),PC
6872
+       if (iword == 0x0343c001)
6873
+               return 1;
6874
+       // MOV 2(PC),PC
6875
+       if (iword == 0x0343c002)
6876
+               return 1;
6877
+       if (TWOWORD_CIS_JSR(iword))
6878
+               return 1;
6879
+       // The conditional LJMP is three words, which we don't handle ...
6880
+       // Any BREV command could be the beginning of a twoword instruction
6881
+       //
6882
+       // Of course, the point here is to determine whether we should (or need
6883
+       // to) read a second word from our read-memory function.  Reading a
6884
+       // second word, given that the first is a BREV, isn't a problem since a
6885
+       // program can't end on/with a BREV instruction.
6886
+       //
6887
+       // BREV #,Rx
6888
+       if ((iword&0x87c40000)==0x02000000)
6889
+               return 1;
6890
+       return 0;
6891
+}
6892
+
6893
+static uint32_t
6894
+zip_bitreverse(uint32_t v) {
6895
+       uint32_t r=0, b;
6896
+       for(b=0; b<32; b++, v>>=1)
6897
+               r = (r<<1)|(v&1);
6898
+       return r;
6899
+}
6900
+
6901
+static inline  uint32_t
6902
+TWOWORD_VALUE(uint32_t one, uint32_t two) {
6903
+       return ((two&0x0ffff)|(zip_bitreverse(one&0x0ffff)));
6904
+}
6905
+
6906
+static long
6907
+zip_sbits(const long val, const int bits) {
6908
+       long    r;
6909
+
6910
+       r = val & ((1l<<bits)-1);
6911
+       if (r & (1l << (bits-1)))
6912
+               r |= (-1l << bits);
6913
+       return r;
6914
+}
6915
+
6916
+static unsigned long
6917
+zip_ubits(const long val, const int bits) {
6918
+       unsigned long r = val & ((1l<<bits)-1);
6919
+       return r;
6920
+}
6921
+
6922
+static int
6923
+zip_getbits(const ZIPI ins, const int which)
6924
+{
6925
+       if (which & 0x40000000) {
6926
+               return zip_sbits(ins>>(which & 0x03f), (which>>8)&0x03f);
6927
+       } else { // if (which &0x03f)
6928
+               return zip_ubits(ins>>(which & 0x03f), (which>>8)&0x03f)
6929
+                       + ((which>>16)&0x0ff);
6930
+       }
6931
+}
6932
+
6933
+static void
6934
+zipi_to_halfstring(const uint32_t addr, const ZIPI ins, const ZIPI nxtword, char *line, const ZOPCODE *listp, uint32_t *refaddr)
6935
+{
6936
+       *refaddr = 0;
6937
+
6938
+       if ((TWOWORD_LOAD(ins,nxtword))&&(listp==zip_oplist)) {
6939
+               int cv = zip_getbits(ins, ZIP_BITFIELD(3,19)); // The condition
6940
+               int dv = zip_getbits(ins, ZIP_REGFIELD(27)); // The destination
6941
+
6942
+               *refaddr = TWOWORD_VALUE(ins,nxtword);
6943
+
6944
+               sprintf(line, "%s%s", "LDI", zip_ccstr[cv]);
6945
+               sprintf(line, "%-11s", line);
6946
+               sprintf(line, "%s0x%08x", line, *refaddr);
6947
+               sprintf(&line[strlen(line)], ",%s", zip_regstr[dv]);
6948
+
6949
+               return;
6950
+       } else if (TWOWORD_JSR(ins, nxtword)) {
6951
+               int cv = zip_getbits(nxtword, ZIP_BITFIELD(3,19));
6952
+               int iv = zip_sbits(nxtword, 18);
6953
+
6954
+               *refaddr = iv + addr + 8;
6955
+               sprintf(line, "%s%s", "JSR", zip_ccstr[cv]);
6956
+               sprintf(line, "%-11s", line);
6957
+               sprintf(line, "%s0x%08x", line, *refaddr);
6958
+
6959
+               return;
6960
+       } else if (TWOWORD_CIS_JSR(ins)) {
6961
+               *refaddr = nxtword;
6962
+               sprintf(line, "%-11s", "JSR");
6963
+               sprintf(line, "%s0x%08x", line, *refaddr);
6964
+               return;
6965
+       } else if (CIS_JSR(ins)) {
6966
+               int ra = zip_getbits(ins, ZIP_REGFIELD(3));
6967
+               sprintf(line, "%-11s%s", "JSR", zip_regstr[ra]);
6968
+               return;
6969
+       } else if (OFFSET_PC_MOV(ins)) {
6970
+               int     cv = zip_getbits(ins, ZIP_BITFIELD(3,19));
6971
+               int     dv = zip_getbits(ins, ZIP_REGFIELD(27));
6972
+               int     iv = zip_sbits(ins, 13);
6973
+               uint32_t        ref;
6974
+
6975
+               ref = (iv<<2) + addr + 4;
6976
+
6977
+               sprintf(line, "%s%s", "MOV", zip_ccstr[cv]);
6978
+               sprintf(line, "%-11s", line);
6979
+               sprintf(line, "%s0x%08x", line, ref);
6980
+               sprintf(line, "%s,%s", line, zip_regstr[dv]);
6981
+
6982
+               *refaddr = ref;
6983
+               return;
6984
+       }
6985
+
6986
+       int     i;
6987
+       for(i=0; i<nzip_oplist; i++) {
6988
+               if (((~zip_oplist[i].s_mask)&zip_oplist[i].s_val)!=0) {
6989
+                       printf("Instruction %d, %s, fails consistency check\n",
6990
+                               i, zip_oplist[i].s_opstr);
6991
+                       printf("%08x & %08x = %08x != %08x\n",
6992
+                               zip_oplist[i].s_mask,
6993
+                               zip_oplist[i].s_val,
6994
+                               (~zip_oplist[i].s_mask)&zip_oplist[i].s_val,
6995
+                               0);
6996
+                       assert(((~zip_oplist[i].s_mask)&zip_oplist[i].s_val)==0);
6997
+               }
6998
+       } line[0] = '\0';
6999
+       for(i=0; (listp[i].s_mask != 0); i++) {
7000
+               // printf("%2d: %6s %08x & %08x == %08x\n",
7001
+                       // i, zip_oplist[i].s_opstr, ins,
7002
+                       // zip_oplist[i].s_mask, zip_oplist[i].s_val);
7003
+               if ((ins & listp[i].s_mask) == listp[i].s_val) {
7004
+                       // Write the opcode onto our line
7005
+                       sprintf(line, "%s", listp[i].s_opstr);
7006
+                       if (listp[i].s_cf != ZIP_OPUNUSED) {
7007
+                               int bv = zip_getbits(ins, listp[i].s_cf);
7008
+                               strcat(line, zip_ccstr[bv]);
7009
+                       } sprintf(line, "%-11s", line); // Pad it to 11 chars
7010
+
7011
+                       int     ra = -1, rb = -1, rr = -1, imv = 0;
7012
+
7013
+                       if (listp[i].s_result != ZIP_OPUNUSED)
7014
+                               rr = zip_getbits(ins, listp[i].s_result);
7015
+                       if (listp[i].s_ra != ZIP_OPUNUSED)
7016
+                               ra = zip_getbits(ins, listp[i].s_ra);
7017
+                       if (listp[i].s_rb != ZIP_OPUNUSED)
7018
+                               rb = zip_getbits(ins, listp[i].s_rb);
7019
+                       if (listp[i].s_i != ZIP_OPUNUSED)
7020
+                               imv = zip_getbits(ins, listp[i].s_i);
7021
+
7022
+                       if ((listp[i].s_rb != ZIP_OPUNUSED)&&(rb == 15))
7023
+                               imv <<= 2;
7024
+
7025
+                       // Treat stores special
7026
+                       if ((strncasecmp("SW",listp[i].s_opstr, 2)==0)
7027
+                               ||(strncasecmp("SH",listp[i].s_opstr, 2)==0)
7028
+                               ||(strncasecmp("SB",listp[i].s_opstr, 2)==0)) {
7029
+                               strcat(line, zip_regstr[ra]);
7030
+                               strcat(line, ",");
7031
+
7032
+                               if (listp[i].s_i != ZIP_OPUNUSED) {
7033
+                                       if (listp[i].s_rb == ZIP_OPUNUSED)
7034
+                                               sprintf(&line[strlen(line)],
7035
+                                                       "($%d)", imv);
7036
+                                       else if (imv != 0)
7037
+                                               sprintf(&line[strlen(line)],
7038
+                                                       "$%d", imv);
7039
+                               } if (listp[i].s_rb != ZIP_OPUNUSED) {
7040
+                                       sprintf(&line[strlen(line)],
7041
+                                               "(%s)", zip_regstr[rb]);
7042
+                               }
7043
+                       // Treat long jumps special
7044
+                       } else if (strncasecmp("LJMP",listp[i].s_opstr, 3)==0) {
7045
+                               sprintf(&line[strlen(line)], "@0x%08x", nxtword);
7046
+                               *refaddr = nxtword;
7047
+                       // Treat relative jumps (branches) specially as well
7048
+                       } else if ((toupper(listp[i].s_opstr[0]=='B'))
7049
+                               &&(strcasecmp(listp[i].s_opstr,"BUSY")!=0)
7050
+                               &&(strcasecmp(listp[i].s_opstr,"BREV")!=0)
7051
+                               &&(strcasecmp(listp[i].s_opstr,"BRK")!=0)
7052
+                               &&(addr != 0)) {
7053
+                               // Branch instruction: starts with B and isn't
7054
+                               // BREV (bit reverse), BRK (break), or
7055
+                               // BUSY
7056
+                               uint32_t target = addr;
7057
+
7058
+                               target += zip_getbits(ins, listp[i].s_i)+4;
7059
+                               sprintf(&line[strlen(line)], "@0x%08x", target);
7060
+                               *refaddr = target;
7061
+                       } else {
7062
+                               int memop = 0;
7063
+                               if (('L'==toupper(listp[i].s_opstr[0]))
7064
+                                       &&(('W'==toupper(listp[i].s_opstr[1]))
7065
+                                        ||('H'==toupper(listp[i].s_opstr[1]))
7066
+                                        ||('B'==toupper(listp[i].s_opstr[1])))
7067
+                                       &&(!listp[i].s_opstr[2]))
7068
+                                       memop = 1;
7069
+
7070
+                               if (listp[i].s_i != ZIP_OPUNUSED) {
7071
+                                       if((memop)&&(listp[i].s_rb == ZIP_OPUNUSED))
7072
+                                               sprintf(&line[strlen(line)],
7073
+                                                       "($%d)", imv);
7074
+                                       else if((memop)&&(imv != 0))
7075
+                                               sprintf(&line[strlen(line)],
7076
+                                                       "%d", imv);
7077
+                                       else if((!memop)&&((imv != 0)||(listp[i].s_rb == ZIP_OPUNUSED)))
7078
+                                               sprintf(&line[strlen(line)],
7079
+                                                       "$%d%s", imv,
7080
+                                                       (listp[i].s_rb!=ZIP_OPUNUSED)?"+":"");
7081
+                               } if (listp[i].s_rb != ZIP_OPUNUSED) {
7082
+                                       if (memop)
7083
+                                               sprintf(&line[strlen(line)],
7084
+                                                       "(%s)", zip_regstr[rb]);
7085
+                                       else
7086
+                                               strcat(line, zip_regstr[rb]);
7087
+                               } if(((listp[i].s_i != ZIP_OPUNUSED)||(listp[i].s_rb != ZIP_OPUNUSED))
7088
+                                       &&((listp[i].s_ra != ZIP_OPUNUSED)||(listp[i].s_result != ZIP_OPUNUSED)))
7089
+                                       strcat(line, ",");
7090
+
7091
+                               if (listp[i].s_ra != ZIP_OPUNUSED) {
7092
+                                       strcat(line, zip_regstr[ra]);
7093
+                               } else if (listp[i].s_result != ZIP_OPUNUSED) {
7094
+                                       strcat(line, zip_regstr[rr]);
7095
+                               }
7096
+                       }
7097
+                       break;
7098
+               }
7099
+       } if (line[0] == '\0') {
7100
+               sprintf(line, "ILL %08x", ins);
7101
+       }
7102
+}
7103
+
7104
+static void
7105
+zipi_to_double_string(const uint32_t addr, const ZIPI ins, const ZIPI nxtword, char *la, char *lb, uint32_t *refaddr) {
7106
+       zipi_to_halfstring(addr, ins, nxtword, la, zip_oplist, refaddr);
7107
+       if (lb) {
7108
+               if ((ins & 0x80000000)&&(!CIS_JSR(ins))) {
7109
+                       zipi_to_halfstring(addr, ins, nxtword,
7110
+                                       lb, zip_opbottomlist, refaddr);
7111
+                       *refaddr = 0;
7112
+               } else lb[0] = '\0';
7113
+       }
7114
+}
7115
+
7116
+static int
7117
+print_zip_insn(bfd_vma vma, disassemble_info *info)
7118
+{
7119
+       ZIPI    iword, nxtword;
7120
+       char    astr[80], bstr[80];
7121
+       unsigned char ibytes[12];
7122
+       uint32_t        refaddr = 0;
7123
+
7124
+       // Deal with misalignment ...
7125
+       if ((vma & 3)!=0) {
7126
+               int     consumed = 0;
7127
+
7128
+               // Consume up to four bytes, after a zero (possibly multiple),
7129
+               // though, align ourselves
7130
+               (*info->read_memory_func)(vma, ibytes, 4, info);
7131
+               while((consumed<4)&&(ibytes[consumed]!=0))
7132
+                       consumed++;
7133
+               while((consumed<4)&&(ibytes[consumed]==0))
7134
+                       consumed++;
7135
+               if (consumed <= 1)
7136
+                       consumed = 1;
7137
+               return consumed;
7138
+       }
7139
+
7140
+       // Always read the first word
7141
+       (*info->read_memory_func)(vma, ibytes, 4, info);
7142
+       iword  = (ibytes[0]<<24)|(ibytes[1]<<16)|(ibytes[2]<<8)|(ibytes[3]);
7143
+       // Only if we know we have a second do we read the second
7144
+       if ((POSSIBLE_TWOWORD_BEGINNING(iword))
7145
+               // We also test for reading past the end of the buffer
7146
+               &&((*info->read_memory_func)(vma, ibytes, 8, info) ==0)) {
7147
+               nxtword= (ibytes[4]<<24)|(ibytes[5]<<16)|(ibytes[6]<<8)|(ibytes[7]);
7148
+       } else {
7149
+               const int NOOP_CODE = 0x76000000;
7150
+               nxtword = NOOP_CODE;
7151
+       }
7152
+
7153
+       bstr[0] = '\0';
7154
+
7155
+       if (THREEWORD_LJSR(iword,nxtword)) {
7156
+               sprintf(astr, "%-11s", "LJSR");
7157
+               if ((*info->read_memory_func)(vma, ibytes, 12, info) ==0)
7158
+                       refaddr = (ibytes[8]<<24)|(ibytes[9]<<16)|(ibytes[10]<<8)|(ibytes[11]);
7159
+               sprintf(&astr[strlen(astr)], "@0x%08x", refaddr);
7160
+       } else if (TWOWORD_CIS_JSR(iword)) {
7161
+               refaddr = nxtword;
7162
+               sprintf(astr, "%-11s0x%08x", "JSR", refaddr);
7163
+       } else
7164
+               zipi_to_double_string(vma, iword, nxtword, astr, bstr,&refaddr);
7165
+
7166
+       if (bstr[0])
7167
+               sprintf(astr, "%-25s | %s", astr,bstr);
7168
+
7169
+       // Remove any trailing spaces
7170
+       unsigned ln = strlen(astr);
7171
+       while((ln > 0)&&(isspace(astr[ln-1])))
7172
+               astr[--ln] = '\0';
7173
+
7174
+       (*info->fprintf_func)(info->stream, "%s", astr);
7175
+
7176
+       if ((info->print_address_func)&&(refaddr != 0)) {
7177
+               if (ln < 25)
7178
+                       (*info->fprintf_func)(info->stream, "%*s", 25-ln, "");
7179
+
7180
+               (*info->fprintf_func)(info->stream, " // ");
7181
+               (*info->print_address_func)(refaddr, info);
7182
+       }
7183
+
7184
+       // Normal LOD (PC),PC = 0x7c87c000
7185
+       //      1'b0, 4'hf, 5'h12, 3'h0, 1'b1, 4'hf, 14'h00
7186
+       //      0111 1100 1000 0111 1100 0000 0000 0000
7187
+       // or CIS  x | LOD (PC),PC
7188
+       //      1'b1, 4'hx 5'hx 1'b0 2'bx 5'hx 4'hf 5'h12 1'b1 4'hf
7189
+       //      1xxx xxxx xx0x xxxx xx11 1110 0101 1111
7190
+       //      0x80203fff mask, val = 0x80003e5f
7191
+       if (THREEWORD_LJSR(iword,nxtword))
7192
+               return 12;
7193
+       if (TWOWORD_LJMP(iword))
7194
+               return 8;
7195
+       // Two word load: Destination registers and conditional execution bits
7196
+       // must match as well.
7197
+       if (TWOWORD_LOAD(iword,nxtword))
7198
+               return 8;
7199
+       if (TWOWORD_JSR(iword,nxtword))
7200
+               return 8;
7201
+       if (TWOWORD_CIS_JSR(iword))
7202
+               return 8;
7203
+       return 4;
7204
+}
7205
+
7206
+
7207
+disassembler_ftype
7208
+zip_get_disassembler(bfd *abfd ATTRIBUTE_UNUSED)
7209
+{
7210
+       return print_zip_insn;
7211
+}
7212
+
7213
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-dis.h binutils-2.27-zip/opcodes/zip-dis.h
7214
--- binutils-2.27/opcodes/zip-dis.h     1969-12-31 19:00:00.000000000 -0500
7215
+++ binutils-2.27-zip/opcodes/zip-dis.h 2016-12-31 18:10:03.512012534 -0500
7216
@@ -0,0 +1,45 @@
7217
+////////////////////////////////////////////////////////////////////////////////
7218
+//
7219
+// Filename:   zip-dis.h
7220
+//
7221
+// Project:    Zip CPU backend for GNU Binutils
7222
+//
7223
+// Purpose:
7224
+//
7225
+// Creator:    Dan Gisselquist, Ph.D.
7226
+//             Gisselquist Technology, LLC
7227
+//
7228
+////////////////////////////////////////////////////////////////////////////////
7229
+//
7230
+// Copyright (C) 2016, Gisselquist Technology, LLC
7231
+//
7232
+// This program is free software (firmware): you can redistribute it and/or
7233
+// modify it under the terms of  the GNU General Public License as published
7234
+// by the Free Software Foundation, either version 3 of the License, or (at
7235
+// your option) any later version.
7236
+//
7237
+// This program is distributed in the hope that it will be useful, but WITHOUT
7238
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
7239
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
7240
+// for more details.
7241
+//
7242
+// You should have received a copy of the GNU General Public License along
7243
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
7244
+// target there if the PDF file isn't present.)  If not, see
7245
+// <http://www.gnu.org/licenses/> for a copy.
7246
+//
7247
+// License:    GPL, v3, as defined and found on www.gnu.org,
7248
+//             http://www.gnu.org/licenses/gpl.html
7249
+//
7250
+//
7251
+////////////////////////////////////////////////////////////////////////////////
7252
+#ifndef        ZIP_DIS_H
7253
+#define        ZIP_DIS_H
7254
+
7255
+#include "config.h"
7256
+#include "dis-asm.h"
7257
+
7258
+extern disassembler_ftype
7259
+zip_get_disassembler(bfd *abfd);
7260
+
7261
+#endif
7262
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-opc.c binutils-2.27-zip/opcodes/zip-opc.c
7263
--- binutils-2.27/opcodes/zip-opc.c     1969-12-31 19:00:00.000000000 -0500
7264
+++ binutils-2.27-zip/opcodes/zip-opc.c 2017-03-06 14:00:55.404955681 -0500
7265
@@ -0,0 +1,362 @@
7266
+////////////////////////////////////////////////////////////////////////////////
7267
+//
7268
+// Filename:   zip-opc.c
7269
+//
7270
+// Project:    Zip CPU backend for GNU Binutils
7271
+//
7272
+// Purpose:
7273
+//
7274
+// Creator:    Dan Gisselquist, Ph.D.
7275
+//             Gisselquist Technology, LLC
7276
+//
7277
+////////////////////////////////////////////////////////////////////////////////
7278
+//
7279
+// Copyright (C) 2015-2017, Gisselquist Technology, LLC
7280
+//
7281
+// This program is free software (firmware): you can redistribute it and/or
7282
+// modify it under the terms of  the GNU General Public License as published
7283
+// by the Free Software Foundation, either version 3 of the License, or (at
7284
+// your option) any later version.
7285
+//
7286
+// This program is distributed in the hope that it will be useful, but WITHOUT
7287
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
7288
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
7289
+// for more details.
7290
+//
7291
+// You should have received a copy of the GNU General Public License along
7292
+// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
7293
+// target there if the PDF file isn't present.)  If not, see
7294
+// <http://www.gnu.org/licenses/> for a copy.
7295
+//
7296
+// License:    GPL, v3, as defined and found on www.gnu.org,
7297
+//             http://www.gnu.org/licenses/gpl.html
7298
+//
7299
+//
7300
+////////////////////////////////////////////////////////////////////////////////
7301
+#include "zip-opc.h"
7302
+
7303
+const  char    *zip_regstr[49] = {
7304
+       "R0", "R1", "R2", "R3",
7305
+       "R4", "R5", "R6", "R7",
7306
+       "R8", "R9", "R10","R11",
7307
+       "R12","SP", "CC", "PC",
7308
+       "uR0", "uR1", "uR2", "uR3",
7309
+       "uR4", "uR5", "uR6", "uR7",
7310
+       "uR8", "uR9", "uR10", "uR11",
7311
+       "uR12", "uSP", "uCC", "uPC",
7312
+       "sR0", "sR1", "sR2", "sR3",
7313
+       "sR4", "sR5", "sR6", "sR7",
7314
+       "sR8", "sR9", "sR10","sR11",
7315
+       "sR12","sSP", "sCC", "sPC", "rILL"
7316
+};
7317
+
7318
+const  char    *zip_ccstr[8] = {
7319
+       "",  ".Z",  ".LT", ".C",
7320
+       ".V",".NZ", ".GE", ".NC"
7321
+};
7322
+
7323
+static const ZOPCODE   zip_oplist_raw[] = {
7324
+       // Special case instructions.  These are general instructions, but with
7325
+       // special opcodes
7326
+       // Conditional branches
7327
+       //      0.1111.0111.ccc.0.111.10iiiii--
7328
+       //      0111 1011 11cc c011 110i iiii iiii iiii
7329
+       { "BUSY", 0xffc7fffc, 0x7883fffc, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7330
+       { "BZ",  0xfffc0000, 0x78880000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7331
+       { "BLT", 0xfffc0000, 0x78900000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7332
+       { "BC",  0xfffc0000, 0x78980000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7333
+       { "BV",  0xfffc0000, 0x78a00000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7334
+       { "BNZ",  0xfffc0000, 0x78a80000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7335
+       { "BGE",  0xfffc0000, 0x78b00000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7336
+       { "BNC",  0xfffc0000, 0x78b80000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_OPUNUSED },
7337
+       { "BRA",  0xffc40000, 0x78800000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7338
+       // Changes/updates to CC, based upon LDI
7339
+       { "TRAP", 0xfffffff0, 0x76000000, ZIP_OPUNUSED,ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7340
+       { "TRAP", 0xff800000, 0x76000000, ZIP_OPUNUSED,ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7341
+       // BREV based traps
7342
+       { "TRAP", 0xffc7ffff, 0x72000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7343
+       // LDILO based traps
7344
+       { "TRAP",0xffc4ffff, 0x72400000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7345
+       { "TRAP",0xffc40000, 0x72400000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7346
+       // CLR -- a LDI of zero
7347
+       //      0.rrrr.1100.iiiiiii--
7348
+       //      0rrr r110 0...
7349
+       { "CLR",  0x87ffffff, 0x06000000, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7350
+       // BREV based clears
7351
+       { "CLR", 0x87c7ffff, 0x02000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7352
+       // HALT
7353
+       //      0.1110.00011.ccc.0.0000000000010
7354
+       //      0111.0000.11cc.c000.0000.0000.0000.0010
7355
+       { "HALT", 0xffc7ffff, 0x70c00010, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7356
+       // The "wait" instruction is identical, with the only difference being
7357
+       // the interrrupt context of the processor.  Well, almost.  To
7358
+       // facilitate waits from supervisor mode, the wait instruction
7359
+       // explicitly forces the CPU into user mode.
7360
+       { "WAIT", 0xffc7ffff, 0x70c00030, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7361
+       // 1.0011.11000.000.0000...... 5f ? A carefully chosen illegal insn ??
7362
+       // "INT", 0xff10007f, 0x9e00005f, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19),
7363
+       // Return to user space
7364
+       { "RTU", 0xffc7ffff, 0x70c00020, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7365
+       // The return instruction: JMP R0 (possibly conditional) = MOV R0,PC
7366
+       { "RTN", 0xffc7ffff, 0x7b400000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7367
+       // JMP (possibly a conditional jump, if not covered by branches above)
7368
+       // 0.1111.01101.ccc.a.rrrr.biiiiiiiiiiiiiiii
7369
+       // 0111.1011.01cc.c0rr.rrbi.iiii.iiii.iiii              MOV x,PC
7370
+       { "JMP",  0xffc40000, 0x7b400000, ZIP_OPUNUSED,ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(13,0), ZIP_BITFIELD(3,19) },
7371
+       // 0.1111.1100.ii.iiii.iiii.iiii.iiii.iiii.iiii
7372
+       // 0111.1110.0iii.iiii.iiii.iiii.iiii.iiii              LDI x,PC
7373
+       { "JMPI", 0xff800000, 0x7e000000, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(23,0), ZIP_OPUNUSED },
7374
+       // 0.1111.10010.000.1.1111.000000000000000
7375
+       // 0111.1100.1000.0111.11ii.iiii.iiii.iiii              LOD (PC),PC
7376
+       { "LJMP", 0xffffffff, 0x7c87c000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7377
+       // NOT : XOR w/ -1
7378
+       //      0.rrrr.00100.ccc.0111.11111111111
7379
+       //      0rrr.r001.00cc.c011.f.f.f.f
7380
+       // { "NOT", 0x87c7ffff, 0x0103ffff, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7381
+       // General instructions
7382
+       // 0rrr.rooo.oocc.cxrr.rrii.iiii.iiii.iiii
7383
+       { "SUB", 0x87c40000, 0x00000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7384
+       { "SUB", 0x87c40000, 0x00040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7385
+       //
7386
+       { "AND", 0x87c40000, 0x00400000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7387
+       { "AND", 0x87c40000, 0x00440000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7388
+       //
7389
+       { "ADD", 0x87c40000, 0x00800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7390
+       { "ADD", 0x87c40000, 0x00840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7391
+       //
7392
+       { "OR", 0x87c40000, 0x00c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7393
+       { "OR", 0x87c40000, 0x00c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7394
+       //
7395
+       { "XOR", 0x87c40000, 0x01000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7396
+       { "XOR", 0x87c40000, 0x01040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7397
+       //
7398
+       { "LSR", 0x87c40000, 0x01400000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7399
+       { "LSR", 0x87c40000, 0x01440000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7400
+       //
7401
+       { "LSL", 0x87c40000, 0x01800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7402
+       { "LSL", 0x87c40000, 0x01840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7403
+       //
7404
+       { "ASR", 0x87c40000, 0x01c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7405
+       { "ASR", 0x87c40000, 0x01c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7406
+       //
7407
+       { "BREV",0x87c40000, 0x02000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7408
+       { "BREV",0x87c40000, 0x02040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7409
+       //
7410
+       { "LDILO",0x87c40000, 0x02400000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7411
+       { "LDILO",0x87c40000, 0x02440000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7412
+       //
7413
+       //
7414
+       { "MPYUHI", 0x87c40000, 0x02800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7415
+       { "MPYUHI", 0x87c40000, 0x02840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7416
+       //
7417
+       { "MPYSHI", 0x87c40000, 0x02c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7418
+       { "MPYSHI", 0x87c40000, 0x02c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7419
+       //
7420
+       { "MPY", 0x87c40000, 0x03000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7421
+       { "MPY", 0x87c40000, 0x03040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7422
+       //
7423
+       { "MOV", 0x87c42000, 0x03400000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(13,0), ZIP_BITFIELD(3,19) },
7424
+       { "MOV", 0x87c42000, 0x03440000, ZIP_URGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(13,0), ZIP_BITFIELD(3,19) },
7425
+       { "MOV", 0x87c42000, 0x03402000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_URGFIELD(14), ZIP_IMMFIELD(13,0), ZIP_BITFIELD(3,19) },
7426
+       { "MOV", 0x87c42000, 0x03442000, ZIP_URGFIELD(27), ZIP_OPUNUSED, ZIP_URGFIELD(14), ZIP_IMMFIELD(13,0), ZIP_BITFIELD(3,19) },
7427
+       //
7428
+       { "DIVU", 0x87c40000, 0x03800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7429
+       { "DIVU", 0x87c40000, 0x03840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7430
+       //
7431
+       { "DIVS", 0x87c40000, 0x03c00000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7432
+       { "DIVS", 0x87c40000, 0x03c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7433
+       //
7434
+       { "CMP", 0x87c40000, 0x04000000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7435
+       { "CMP", 0x87c40000, 0x04040000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7436
+       { "TST", 0x87c40000, 0x04400000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7437
+       { "TST", 0x87c40000, 0x04440000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7438
+       //
7439
+       { "LW", 0x87c40000, 0x04800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7440
+       { "LW", 0x87c40000, 0x04840000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7441
+       //
7442
+       { "SW", 0x87c40000, 0x04c00000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7443
+       { "SW", 0x87c40000, 0x04c40000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7444
+       //
7445
+       { "LH", 0x87c40000, 0x05000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7446
+       { "LH", 0x87c40000, 0x05040000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7447
+       //
7448
+       { "SH", 0x87c40000, 0x05400000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7449
+       { "SH", 0x87c40000, 0x05440000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7450
+       //
7451
+       { "LB", 0x87c40000, 0x05800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7452
+       { "LB", 0x87c40000, 0x05840000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7453
+       //
7454
+       { "SB", 0x87c40000, 0x05c00000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7455
+       { "SB", 0x87c40000, 0x05c40000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7456
+       //
7457
+       // 0rrr.r101.1
7458
+       { "LDI",  0x87800000, 0x06000000, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(23,0), ZIP_OPUNUSED },
7459
+       // 0111.x111.00.xxxxxxxx
7460
+       { "BREAK", 0xf7ffffff, 0x77000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7461
+       { "BREAK", 0xf7c00000, 0x77000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(22,0), ZIP_OPUNUSED },
7462
+       { "LOCK",  0xf7ffffff, 0x77400000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7463
+       { "LOCK",  0xf7c00000, 0x77400000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(22,0), ZIP_OPUNUSED },
7464
+       // 0.111x.00000.xxx.xxx.xxxx.xxxx.xxxx.xxxx
7465
+       // 0111.x111.11.xxx.xxx.xxxx.xxxx.xxxx.xxxx
7466
+       // SNOOP = SIM w/ no argument(s)
7467
+       { "SIM",  0xf7ffffff, 0x77800000, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7468
+       { "SEXIT",0xf7ffffff, 0x77800100, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7469
+       { "SEXIT",0xf7fffff0, 0x77800310, ZIP_OPUNUSED, ZIP_URGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7470
+       { "SEXIT",0xf7ffffe0, 0x77800300, ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7471
+       { "SEXIT",0xf7ffff00, 0x77800100, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD( 8,0), ZIP_OPUNUSED },
7472
+       { "SDUMP",0xf7ffffff, 0x778002ff, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7473
+       { "SDUMP",0xf7fffff0, 0x77800200, ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7474
+       { "SDUMP",0xf7fffff0, 0x77800210, ZIP_OPUNUSED, ZIP_URGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7475
+       { "SOUT", 0xf7fffff0, 0x77800230, ZIP_OPUNUSED, ZIP_URGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7476
+       { "SOUT", 0xf7ffffe0, 0x77800220, ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7477
+       { "SOUT", 0xf7ffff00, 0x77800400, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD( 8,0), ZIP_OPUNUSED },
7478
+       { "SDUMP",0xf7ffff00, 0x77800200, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD( 8,0), ZIP_OPUNUSED },
7479
+       { "SIM",  0xf7c00000, 0x77800000, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD(22,0), ZIP_OPUNUSED },
7480
+       { "NOOP", 0xf7ffffff, 0x77c00000, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7481
+       { "NEXIT",0xf7ffffff, 0x77c00100, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7482
+       { "NEXIT",0xf7ffff00, 0x77c00100, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD( 8,0), ZIP_OPUNUSED },
7483
+       { "NEXIT",0xf7fffff0, 0x77c00310, ZIP_OPUNUSED, ZIP_URGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7484
+       { "NEXIT",0xf7ffffe0, 0x77c00300, ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7485
+       { "NDUMP",0xf7ffffff, 0x77c002ff, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7486
+       { "NDUMP",0xf7fffff0, 0x77c00200, ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7487
+       { "NDUMP",0xf7fffff0, 0x77c00210, ZIP_OPUNUSED, ZIP_URGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7488
+
7489
+       { "NOUT", 0xf7fffff0, 0x77c00230, ZIP_OPUNUSED, ZIP_URGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7490
+       { "NOUT", 0xf7ffffe0, 0x77c00220, ZIP_OPUNUSED, ZIP_REGFIELD(0), ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7491
+       { "NOUT", 0xf7ffff00, 0x77c00400, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD( 8,0), ZIP_OPUNUSED },
7492
+       { "NDUMP",0xf7ffff00, 0x77c00200, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_OPUNUSED,       ZIP_OPUNUSED },
7493
+       { "NSIM", 0xf7c00000, 0x77c00000, ZIP_OPUNUSED, ZIP_OPUNUSED,    ZIP_OPUNUSED, ZIP_IMMFIELD(22,0), ZIP_OPUNUSED },
7494
+       //
7495
+       //
7496
+       // 0rrr.r11f.ffcc.cxrr.rrii.iiii.iiii.iiii
7497
+       { "FPADD",0x87c43fff, 0x06840000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7498
+       { "FPSUB",0x87c43fff, 0x06c40000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7499
+       { "FPMPY",0x87c43fff, 0x07040000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7500
+       { "FPDIV",0x87c43fff, 0x07440000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(14), ZIP_OPUNUSED, ZIP_BITFIELD(3,19) },
7501
+       { "FPI2F",0x87c40000, 0x07800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(18,0), ZIP_BITFIELD(3,19) },
7502
+       { "FPI2F",0x87c40000, 0x07840000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7503
+       { "FPF2I",0x87c40000, 0x07c40000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(14), ZIP_IMMFIELD(14,0), ZIP_BITFIELD(3,19) },
7504
+       //
7505
+       //
7506
+       //
7507
+       //
7508
+       //
7509
+       //      16-bit instructions, high side
7510
+       //
7511
+       //
7512
+       //      1.1111.00010.xcc.0iiii.xxxx.xxxxx.xxxxx
7513
+       //      1111.1000.10xc.c0ii.iixx.xxxx.xxxx.xxxx
7514
+       // Mask, val, result, Ra, Rb, I, condition (no conditions for OP_UNDER_TEST)
7515
+       // BRA: 1.1111.011.0.sssssss
7516
+       { "BRA", 0xff800000, 0xf9000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7517
+       // CLR: 1.rrrr.110.00000000
7518
+       { "CLR", 0x87ff0000, 0x86000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7519
+       // RTN: 1.1111.111.0.0000.000, MOV R0,Pc
7520
+       { "RTN", 0xffff0000, 0xff800000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7521
+       // JMP: 1.1111.111.0.rrrrsss
7522
+       { "JMP", 0xff800000, 0xff000000, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7523
+       // LJSR: 1.000_0.011_.0.111_1.001 ?.1111.110.1.1111.000
7524
+       // { "LJSR",0xffffffff, 0x83797ef8, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7525
+       //
7526
+       // 1.rrrr.000.0.sssssss
7527
+       // 1rrr.r000.0sss.ssss
7528
+       { "SUB", 0x87800000, 0x80000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7529
+       // 1.rrrr.000.1.rrrrsss
7530
+       { "SUB", 0x87800000, 0x80800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7531
+       //
7532
+       // 1.rrrr.001.0.sssssss
7533
+       // 1.rrrr.001.1.rrrrsss
7534
+       { "AND", 0x87800000, 0x81000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7535
+       { "AND", 0x87800000, 0x81800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7536
+       //
7537
+       // 1.rrrr.010.0.sssssss
7538
+       // 1.rrrr.010.1.rrrrsss
7539
+       { "ADD", 0x87800000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7540
+       { "ADD", 0x87800000, 0x82800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7541
+       //
7542
+       // 1.rrrr.011.a.rrrrsss
7543
+       { "CMP", 0x87800000, 0x83000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7544
+       { "CMP", 0x87800000, 0x83800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7545
+       //
7546
+       // 1.rrrr.100.0.sssssss
7547
+       // 1.rrrr.100.1.rrrrsss
7548
+       { "LW", 0x87800000, 0x84000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7549
+       { "LW", 0x87800000, 0x84800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7550
+       // 1.rrrr.101.ssssssss
7551
+       { "SW", 0x87800000, 0x85000000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
7552
+       // 1.rrrr.110.0.sssssss
7553
+       { "SW", 0x87800000, 0x85800000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7554
+       // 1.rrrr.110.iiiiiiii
7555
+       { "LDI", 0x87000000, 0x86000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(8,16), ZIP_OPUNUSED },
7556
+       // 1.rrrr.111.1.sssssss
7557
+       { "MOV", 0x87800000, 0x87800000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
7558
+       //
7559
+       // 1.rrrr.111.1.rrrrsss
7560
+       // Illegal instruction !!
7561
+       { "ILLV", 0x80000000, 0x80000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(32,16), ZIP_OPUNUSED },
7562
+       // Global illegal instruction
7563
+       { "ILL", 0x00000000, 0x00000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(32,0), ZIP_OPUNUSED }
7564
+};
7565
+
7566
+static const ZOPCODE   zip_opbottomlist_raw[] = {
7567
+       //
7568
+       //
7569
+       //
7570
+       //      16-bit instructions, low side ... treat these as special
7571
+       //
7572
+       //
7573
+       // Mask, val, result, Ra, Rb, I, condition (no conditions for OP_UNDER_TEST)
7574
+       // BRA: 1.xxx_xxxx_xxxx_xxxx_?.111_1.011.0.sssssss
7575
+       { "BRA", 0x80007f80, 0x80007900, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7576
+       // CLR: 1.xxx_xxxx_xxxx_xxxx_?.rrr_r.101.0000_0000
7577
+       { "CLR", 0x800007ff, 0x80000600, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7578
+       // RTN: 1.1111.111.0.0000.000, MOV R0,Pc
7579
+       { "RTN", 0x80007fff, 0x80007f80, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
7580
+       // JMP: 1.1111.111.0.rrrrsss
7581
+       { "JMP", 0x80007f80, 0x80007f00, ZIP_REGFIELD(11),ZIP_OPUNUSED, ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7582
+       // LJMP: 1.xxx_xxxx_xxxx_xxxx_?.111_1.100._1.111_1.000
7583
+       { "LJMP", 0x80007fff, 0x80007cf8, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7584
+       //
7585
+       // 1.rrrr.000.0.sssssss
7586
+       { "SUB", 0x80000780, 0x80000000, ZIP_REGFIELD(11), ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7587
+       // 1.rrrr.000.1.rrrrsss
7588
+       { "SUB", 0x80000780, 0x80000080, ZIP_REGFIELD(11), ZIP_REGFIELD(11), ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7589
+       //
7590
+       // 1.rrrr.001.0.sssssss
7591
+       // 1.rrrr.001.1.rrrrsss
7592
+       { "AND", 0x80000780, 0x80000100, ZIP_REGFIELD(11), ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7593
+       { "AND", 0x80000780, 0x80000180, ZIP_REGFIELD(11), ZIP_REGFIELD(11), ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7594
+       //
7595
+       // 1.rrrr.010.0.sssssss
7596
+       // 1.rrrr.010.1.rrrrsss
7597
+       { "ADD", 0x80000780, 0x80000200, ZIP_REGFIELD(11), ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7598
+       { "ADD", 0x80000780, 0x80000280, ZIP_REGFIELD(11), ZIP_REGFIELD(11), ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7599
+       //
7600
+       // 1.rrrr.011.a.rrrrsss
7601
+       { "CMP", 0x80000780, 0x80000300, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7602
+       { "CMP", 0x80000780, 0x80000380, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7603
+       //
7604
+       // 1.rrrr.100.0.sssssss
7605
+       // 1.rrrr.100.1.rrrrsss
7606
+       { "LW", 0x80000780, 0x80000400, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_SP, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7607
+       { "LW", 0x80000780, 0x80000480, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7608
+       // 1.rrrr.101.ssssssss
7609
+       { "SW", 0x80000780, 0x80000500, ZIP_OPUNUSED, ZIP_REGFIELD(11), ZIP_SP, ZIP_IMMFIELD(7,0), ZIP_OPUNUSED },
7610
+       { "SW", 0x80000780, 0x80000580, ZIP_OPUNUSED, ZIP_REGFIELD(11), ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7611
+       // 1.rrr_r.110.ssssssss
7612
+       { "LDI", 0x80000700, 0x80000600, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(8,0), ZIP_OPUNUSED },
7613
+       // 1.rrr_r.111_.x.rrr_rsss
7614
+       { "MOV", 0x80000780, 0x80000780, ZIP_REGFIELD(11), ZIP_OPUNUSED, ZIP_REGFIELD(3), ZIP_IMMFIELD(3,0), ZIP_OPUNUSED },
7615
+       //
7616
+       //
7617
+       // Illegal instruction !!
7618
+       { "ILLV",       0x80000000, 0x80000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(15,0), ZIP_OPUNUSED },
7619
+       { "ILL",        0x00000000, 0x00000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(15,0), ZIP_OPUNUSED }
7620
+};
7621
+
7622
+const ZOPCODE  *zip_oplist = zip_oplist_raw,
7623
+               *zip_opbottomlist = zip_opbottomlist_raw;
7624
+
7625
+const int      nzip_oplist = (sizeof(zip_oplist_raw)/sizeof(ZOPCODE));
7626
+const int      nzip_opbottom = (sizeof(zip_opbottomlist_raw)/sizeof(ZOPCODE));
7627
+
7628
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-opc.h binutils-2.27-zip/opcodes/zip-opc.h
7629
--- binutils-2.27/opcodes/zip-opc.h     1969-12-31 19:00:00.000000000 -0500
7630
+++ binutils-2.27-zip/opcodes/zip-opc.h 2017-02-10 17:48:01.761470841 -0500
7631
@@ -0,0 +1,77 @@
7632
+////////////////////////////////////////////////////////////////////////////////
7633
+//
7634
+// Filename:   zip-opc.h
7635
+//
7636
+// Project:    Zip CPU backend for GNU Binutils
7637
+//
7638
+// Purpose:
7639
+//
7640
+// Creator:    Dan Gisselquist, Ph.D.
7641
+//             Gisselquist Technology, LLC
7642
+//
7643
+////////////////////////////////////////////////////////////////////////////////
7644
+//
7645
+// Copyright (C) 2016, Gisselquist Technology, LLC
7646
+//
7647
+// This program is free software (firmware): you can redistribute it and/or
7648
+// modify it under the terms of  the GNU General Public License as published
7649
+// by the Free Software Foundation, either version 3 of the License, or (at
7650
+// your option) any later version.
7651
+//
7652
+// This program is distributed in the hope that it will be useful, but WITHOUT
7653
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
7654
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
7655
+// for more details.
7656
+//
7657
+// You should have received a copy of the GNU General Public License along
7658
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
7659
+// target there if the PDF file isn't present.)  If not, see
7660
+// <http://www.gnu.org/licenses/> for a copy.
7661
+//
7662
+// License:    GPL, v3, as defined and found on www.gnu.org,
7663
+//             http://www.gnu.org/licenses/gpl.html
7664
+//
7665
+//
7666
+////////////////////////////////////////////////////////////////////////////////
7667
+#ifndef        ZIP_OPC_H
7668
+#define        ZIP_OPC_H
7669
+
7670
+#include <stdint.h>
7671
+
7672
+// MACROS used in the instruction definition list.
7673
+#define        ZIP_OPUNUSED    -1
7674
+#define        ZIP_BITFIELD(LN,MN)     (((LN&0x0ff)<<8)+(MN&0x0ff)) // A generic bitfield
7675
+#define        ZIP_REGFIELD(MN)        (0x00000400 +(MN&0x0ff)) // Normal register field
7676
+#define        ZIP_URGFIELD(MN)        (0x0100400 +(MN&0x0ff)) // User register field
7677
+#define        ZIP_IMMFIELD(LN,MN)     (0x40000000 + (((LN&0x0ff)<<8)+(MN&0x0ff))) // Sgn extnd
7678
+#define        ZIP_SP  0xd0000
7679
+
7680
+typedef        uint32_t        ZIPI;   // A Zip CPU instruction
7681
+
7682
+typedef        struct {
7683
+       char    s_opstr[8];     // OPCode name
7684
+       ZIPI    s_mask,         // Bits that must match 4 this pattern to match
7685
+               s_val;          // What those masked bits must be
7686
+       //
7687
+       // The following describe not the value, but the bits where there
7688
+       // respective vaules will be found within the instruction.  For example,
7689
+       // an instruction with no immediate will have an s_i value of -1
7690
+       // (ZIP_OPUNUSED), whereas an instruction with an immediate value of -1
7691
+       // might have an s_i value of ZIP_BITFIELD(14,0), or 0x0400.  The
7692
+       // opcode itself will tell you what the value is--not this structure
7693
+       // describing the opcode.
7694
+       //
7695
+       int     s_result,       // Register where the result will be placed
7696
+               s_ra,           // A register, often the result
7697
+               s_rb,           // B register, source operand (if used)
7698
+               s_i,            // Immediate value, added to B if B is used
7699
+               s_cf;           // Condition flags.
7700
+} ZOPCODE;
7701
+
7702
+extern const   char    *zip_regstr[49], *zip_ccstr[8];
7703
+
7704
+extern const ZOPCODE   *zip_oplist, *zip_opbottomlist;
7705
+extern const int       nzip_oplist, nzip_opbottom;
7706
+
7707
+
7708
+#endif

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