OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Blame information for rev 130

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Line No. Rev Author Line
1 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/config.sub gcc-5.3.0-zip/config.sub
2
--- gcc-5.3.0-original/config.sub       2015-01-02 04:30:21.000000000 -0500
3
+++ gcc-5.3.0-zip/config.sub    2016-01-30 12:27:56.023073747 -0500
4
@@ -316,7 +316,7 @@
5
        | visium \
6
        | we32k \
7
        | x86 | xc16x | xstormy16 | xtensa \
8
-       | z8k | z80)
9
+       | z8k | z80 | zip)
10
                basic_machine=$basic_machine-unknown
11
                ;;
12
        c54x)
13
@@ -1547,6 +1547,9 @@
14
 # system, and we'll never get to this point.
15
 
16
 case $basic_machine in
17
+       zip-*)
18
+               os=-elf
19
+               ;;
20
        score-*)
21
                os=-elf
22
                ;;
23
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure gcc-5.3.0-zip/configure
24
--- gcc-5.3.0-original/configure        2015-05-03 13:29:57.000000000 -0400
25
+++ gcc-5.3.0-zip/configure     2016-01-30 16:19:48.264867231 -0500
26
@@ -3927,6 +3927,8 @@
27
   vax-*-*)
28
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
29
     ;;
30
+  zip*)
31
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
32
 esac
33
 
34
 # If we aren't building newlib, then don't build libgloss, since libgloss
35
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure.ac gcc-5.3.0-zip/configure.ac
36
--- gcc-5.3.0-original/configure.ac     2015-05-03 13:29:57.000000000 -0400
37
+++ gcc-5.3.0-zip/configure.ac  2016-02-12 10:47:23.847194843 -0500
38
@@ -1274,6 +1274,10 @@
39
   vax-*-*)
40
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
41
     ;;
42
+  zip*)
43
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
44
+    unsupported_languages="$unsupported_languages fortran java"
45
+    ;;
46
 esac
47
 
48
 # If we aren't building newlib, then don't build libgloss, since libgloss
49 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cfgexpand.c gcc-5.3.0-zip/gcc/cfgexpand.c
50
--- gcc-5.3.0-original/gcc/cfgexpand.c  2015-07-23 06:39:26.000000000 -0400
51
+++ gcc-5.3.0-zip/gcc/cfgexpand.c       2016-04-01 06:40:17.288326711 -0400
52
@@ -108,6 +108,14 @@
53
 #include "tree-chkp.h"
54
 #include "rtl-chkp.h"
55
 
56
+#ifdef DO_ZIP_DEBUGS
57
+#include <stdio.h>
58
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
59
+extern void    zip_debug_rtx(const_rtx);
60
+#else
61
+#define        ZIP_DEBUG_LINE(STR,RTX)
62
+#endif
63
+
64
 /* Some systems use __main in a way incompatible with its use in gcc, in these
65
    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
66
    give the same symbol without quotes for an alternative entry point.  You
67 111 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
68
--- gcc-5.3.0-original/gcc/cgraphbuild.c        2015-01-09 15:18:42.000000000 -0500
69
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c     2016-03-24 22:13:24.815287808 -0400
70
@@ -62,6 +62,13 @@
71
 #include "ipa-prop.h"
72
 #include "ipa-inline.h"
73
 
74
+#ifdef DO_ZIP_DEBUGS
75
+extern void zip_debug_rtx(const_rtx);
76
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
77
+#else
78
+#define        ZIP_DEBUG_LINE(STR,RTX)
79
+#endif
80
+
81
 /* Context of record_reference.  */
82
 struct record_reference_ctx
83
 {
84 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
85
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c       1969-12-31 19:00:00.000000000 -0500
86
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c    2016-02-14 00:54:31.821055716 -0500
87
@@ -0,0 +1,52 @@
88
+////////////////////////////////////////////////////////////////////////////////
89
+//
90
+// Filename:   common/config/zip/zip-common.c
91
+//
92
+// Project:    Zip CPU backend for the GNU Compiler Collection
93
+//
94
+// Purpose:    To eliminate the frame register automatically.
95
+//
96
+// Creator:    Dan Gisselquist, Ph.D.
97
+//             Gisselquist Technology, LLC
98
+//
99
+////////////////////////////////////////////////////////////////////////////////
100
+//
101
+// Copyright (C) 2016, Gisselquist Technology, LLC
102
+//
103
+// This program is free software (firmware): you can redistribute it and/or
104
+// modify it under the terms of  the GNU General Public License as published
105
+// by the Free Software Foundation, either version 3 of the License, or (at
106
+// your option) any later version.
107
+//
108
+// This program is distributed in the hope that it will be useful, but WITHOUT
109
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
110
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
111
+// for more details.
112
+//
113
+// You should have received a copy of the GNU General Public License along
114
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
115
+// target there if the PDF file isn't present.)  If not, see
116
+// <http://www.gnu.org/licenses/> for a copy.
117
+//
118
+// License:    GPL, v3, as defined and found on www.gnu.org,
119
+//             http://www.gnu.org/licenses/gpl.html
120
+//
121
+//
122
+////////////////////////////////////////////////////////////////////////////////
123
+#include "config.h"
124
+#include "system.h"
125
+#include "coretypes.h"
126
+#include "tm.h"
127
+#include "common/common-target.h"
128
+#include "common/common-target-def.h"
129
+
130
+static const struct default_options zip_option_optimization_table[] =
131
+  {
132
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
133
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
134
+  };
135
+
136
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
137
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
138
+
139
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
140
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
141 127 dgisselq
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-04-21 20:04:11.745606740 -0400
142 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
143
@@ -21,7 +21,7 @@
144
 #ifndef GCC_AARCH64_LINUX_H
145
 #define GCC_AARCH64_LINUX_H
146
 
147
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
148
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
149
 
150
 #undef  ASAN_CC1_SPEC
151
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
152
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
153 127 dgisselq
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-04-21 20:04:11.761606648 -0400
154 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
155
@@ -23,8 +23,8 @@
156
 #define EXTRA_SPECS \
157
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
158
 
159
-#define GLIBC_DYNAMIC_LINKER   "/tools/lib/ld-linux.so.2"
160
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
161
+#define GLIBC_DYNAMIC_LINKER   "/lib/ld-linux.so.2"
162
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
163
 #if DEFAULT_LIBC == LIBC_UCLIBC
164
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
165
 #elif DEFAULT_LIBC == LIBC_GLIBC
166
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
167 127 dgisselq
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-04-21 20:04:11.761606648 -0400
168 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
169
@@ -68,8 +68,8 @@
170
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
171
 
172
 #undef  GLIBC_DYNAMIC_LINKER
173
-#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/tools/lib/ld-linux.so.3"
174
-#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/tools/lib/ld-linux-armhf.so.3"
175
+#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/lib/ld-linux.so.3"
176
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
177
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
178
 
179
 #define GLIBC_DYNAMIC_LINKER \
180
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
181 127 dgisselq
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-04-21 20:04:11.761606648 -0400
182 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
183
@@ -62,7 +62,7 @@
184
 
185
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
186
 
187
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
188
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
189
 
190
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
191
    %{static:-Bstatic} \
192
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
193 127 dgisselq
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-04-21 20:04:11.761606648 -0400
194 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
195
@@ -45,7 +45,7 @@
196
   %{shared:-G -Bdynamic} \
197
   %{!shared: %{!static: \
198
    %{rdynamic:-export-dynamic} \
199
-   -dynamic-linker /tools/lib/ld-uClibc.so.0} \
200
+   -dynamic-linker /lib/ld-uClibc.so.0} \
201
    %{static}} -init __init -fini __fini"
202
 
203
 #undef TARGET_SUPPORTS_SYNC_CALLS
204
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
205 127 dgisselq
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-04-21 20:04:11.761606648 -0400
206 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
207
@@ -102,7 +102,7 @@
208
 #undef CRIS_DEFAULT_CPU_VERSION
209
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
210
 
211
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
212
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
213
 
214
 #undef CRIS_LINK_SUBTARGET_SPEC
215
 #define CRIS_LINK_SUBTARGET_SPEC \
216
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
217 127 dgisselq
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-04-21 20:04:11.761606648 -0400
218 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
219
@@ -129,9 +129,9 @@
220
 #endif
221
 
222
 #if FBSD_MAJOR < 6
223
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
224
+#define FBSD_DYNAMIC_LINKER "/usr/libexec/ld-elf.so.1"
225
 #else
226
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
227
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
228
 #endif
229
 
230
 /* NOTE: The freebsd-spec.h header is included also for various
231
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
232 127 dgisselq
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-04-21 20:04:11.761606648 -0400
233 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
234
@@ -34,7 +34,7 @@
235
 #define ENDFILE_SPEC \
236
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
237
 
238
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
239
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
240
 
241
 #undef LINK_SPEC
242
 #define LINK_SPEC "\
243
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
244 127 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-04-21 20:04:11.761606648 -0400
245 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
246
@@ -22,7 +22,7 @@
247
 #define GNU_USER_LINK_EMULATION "elf_i386"
248
 
249
 #undef GNU_USER_DYNAMIC_LINKER
250
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so"
251
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
252
 
253
 #undef STARTFILE_SPEC
254
 #if defined HAVE_LD_PIE
255
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
256 127 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-04-21 20:04:11.761606648 -0400
257 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
258
@@ -22,6 +22,6 @@
259
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
260
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
261
 
262
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
263
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld-kfreebsd-x86-64.so.1"
264
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
265
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
266
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
267
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
268
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
269 127 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-04-21 20:04:11.761606648 -0400
270 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
271
@@ -19,4 +19,4 @@
272
 <http://www.gnu.org/licenses/>.  */
273
 
274
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
275
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
276
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
277
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
278 127 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-04-21 20:04:11.761606648 -0400
279 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
280
@@ -27,6 +27,6 @@
281
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
282
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
283
 
284
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
285
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux-x86-64.so.2"
286
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
287
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
288
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
289
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
290
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
291 127 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-04-21 20:04:11.761606648 -0400
292 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
293
@@ -20,4 +20,4 @@
294
 <http://www.gnu.org/licenses/>.  */
295
 
296
 #define GNU_USER_LINK_EMULATION "elf_i386"
297
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
298
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
299
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
300 127 dgisselq
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-04-21 20:04:11.761606648 -0400
301 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
302
@@ -55,7 +55,7 @@
303
 /* Define this for shared library support because it isn't in the main
304
    linux.h file.  */
305
 
306
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-ia64.so.2"
307
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
308
 
309
 #undef LINK_SPEC
310
 #define LINK_SPEC "\
311
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
312 127 dgisselq
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-04-21 20:04:11.761606648 -0400
313 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
314
@@ -32,4 +32,4 @@
315
 
316
 
317
 #undef GNU_USER_DYNAMIC_LINKER
318
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
319
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
320
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
321 127 dgisselq
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-04-21 20:04:11.761606648 -0400
322 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
323
@@ -31,5 +31,4 @@
324
   while (0)
325
 
326
 #undef GNU_USER_DYNAMIC_LINKER
327
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
328
-
329
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
330
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
331 127 dgisselq
--- gcc-5.3.0-original/gcc/config/linux.h       2016-04-21 20:04:11.761606648 -0400
332 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
333
@@ -73,10 +73,10 @@
334
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
335
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
336
    supporting both 32-bit and 64-bit compilation.  */
337
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
338
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
339
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
340
-#define UCLIBC_DYNAMIC_LINKERX32 "/tools/lib/ldx32-uClibc.so.0"
341
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
342
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
343
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
344
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
345
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
346
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
347
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
348
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
349 127 dgisselq
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-04-21 20:04:11.761606648 -0400
350 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
351
@@ -67,7 +67,7 @@
352
    %{shared:-shared} \
353
    %{symbolic:-Bsymbolic} \
354
    %{rdynamic:-export-dynamic} \
355
-   -dynamic-linker /tools/lib/ld-linux.so.2"
356
+   -dynamic-linker /lib/ld-linux.so.2"
357
 
358
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
359
 
360
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
361 127 dgisselq
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-04-21 20:04:11.761606648 -0400
362 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
363
@@ -71,7 +71,7 @@
364
    When the -shared link option is used a final link is not being
365
    done.  */
366
 
367
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
368
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
369
 
370
 #undef LINK_SPEC
371
 #define LINK_SPEC "-m m68kelf %{shared} \
372
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
373 127 dgisselq
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-04-21 20:04:11.761606648 -0400
374 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
375
@@ -28,7 +28,7 @@
376
 #undef TLS_NEEDS_GOT
377
 #define TLS_NEEDS_GOT 1
378
 
379
-#define DYNAMIC_LINKER "/tools/lib/ld.so.1"
380
+#define DYNAMIC_LINKER "/lib/ld.so.1"
381
 #undef  SUBTARGET_EXTRA_SPECS
382
 #define SUBTARGET_EXTRA_SPECS \
383
   { "dynamic_linker", DYNAMIC_LINKER }
384
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
385 127 dgisselq
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-04-21 20:04:11.761606648 -0400
386 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
387
@@ -22,20 +22,20 @@
388
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
389
 
390
 #define GLIBC_DYNAMIC_LINKER32 \
391
-  "%{mnan=2008:/tools/lib/ld-linux-mipsn8.so.1;:/tools/lib/ld.so.1}"
392
+  "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}"
393
 #define GLIBC_DYNAMIC_LINKER64 \
394
-  "%{mnan=2008:/tools/lib64/ld-linux-mipsn8.so.1;:/tools/lib64/ld.so.1}"
395
+  "%{mnan=2008:/lib64/ld-linux-mipsn8.so.1;:/lib64/ld.so.1}"
396
 #define GLIBC_DYNAMIC_LINKERN32 \
397
-  "%{mnan=2008:/tools/lib32/ld-linux-mipsn8.so.1;:/tools/lib32/ld.so.1}"
398
+  "%{mnan=2008:/lib32/ld-linux-mipsn8.so.1;:/lib32/ld.so.1}"
399
 
400
 #undef UCLIBC_DYNAMIC_LINKER32
401
 #define UCLIBC_DYNAMIC_LINKER32 \
402
-  "%{mnan=2008:/tools/lib/ld-uClibc-mipsn8.so.0;:/tools/lib/ld-uClibc.so.0}"
403
+  "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}"
404
 #undef UCLIBC_DYNAMIC_LINKER64
405
 #define UCLIBC_DYNAMIC_LINKER64 \
406
-  "%{mnan=2008:/tools/lib/ld64-uClibc-mipsn8.so.0;:/tools/lib/ld64-uClibc.so.0}"
407
+  "%{mnan=2008:/lib/ld64-uClibc-mipsn8.so.0;:/lib/ld64-uClibc.so.0}"
408
 #define UCLIBC_DYNAMIC_LINKERN32 \
409
-  "%{mnan=2008:/tools/lib32/ld-uClibc-mipsn8.so.0;:/tools/lib32/ld-uClibc.so.0}"
410
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
411
 
412
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
413
 #define GNU_USER_DYNAMIC_LINKERN32 \
414
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
415 127 dgisselq
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-04-21 20:04:11.761606648 -0400
416 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
417
@@ -32,7 +32,7 @@
418
 #undef  ASM_SPEC
419
 #define ASM_SPEC ""
420
 
421
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
422
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
423
 
424
 #undef  LINK_SPEC
425
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
426
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
427 127 dgisselq
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-04-21 20:04:11.761606648 -0400
428 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
429
@@ -37,7 +37,7 @@
430
 /* Define this for shared library support because it isn't in the main
431
    linux.h file.  */
432
 
433
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
434
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
435
 
436
 #undef LINK_SPEC
437
 #define LINK_SPEC "\
438
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
439 127 dgisselq
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-04-21 20:04:11.761606648 -0400
440 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
441
@@ -357,14 +357,14 @@
442
 #undef LINK_OS_DEFAULT_SPEC
443
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
444
 
445
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
446
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
447
 #ifdef LINUX64_DEFAULT_ABI_ELFv2
448
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/tools/lib64/ld64.so.1;:/tools/lib64/ld64.so.2}"
449
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"
450
 #else
451
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/tools/lib64/ld64.so.2;:/tools/lib64/ld64.so.1}"
452
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"
453
 #endif
454
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
455
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
456
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
457
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
458
 #if DEFAULT_LIBC == LIBC_UCLIBC
459
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
460
 #elif DEFAULT_LIBC == LIBC_GLIBC
461
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
462 127 dgisselq
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-04-21 20:04:11.761606648 -0400
463 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
464
@@ -757,8 +757,8 @@
465
 
466
 #define LINK_START_LINUX_SPEC ""
467
 
468
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
469
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
470
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
471
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
472
 #if DEFAULT_LIBC == LIBC_UCLIBC
473
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
474
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
475
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
476 127 dgisselq
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-04-21 20:04:11.761606648 -0400
477 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
478
@@ -60,8 +60,8 @@
479
 #define MULTILIB_DEFAULTS { "m31" }
480
 #endif
481
 
482
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
483
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64.so.1"
484
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
485
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
486
 
487
 #undef  LINK_SPEC
488
 #define LINK_SPEC \
489
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
490 127 dgisselq
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-04-21 20:04:11.761606648 -0400
491 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
492
@@ -43,7 +43,7 @@
493
 
494
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
495
 
496
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
497
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
498
 
499
 #undef SUBTARGET_LINK_EMUL_SUFFIX
500
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
501
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
502 127 dgisselq
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-04-21 20:04:11.761606648 -0400
503 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
504
@@ -84,8 +84,8 @@
505
    When the -shared link option is used a final link is not being
506
    done.  */
507
 
508
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
509
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux.so.2"
510
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
511
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
512
 
513
 #ifdef SPARC_BI_ARCH
514
 
515
@@ -193,7 +193,7 @@
516
 #else /* !SPARC_BI_ARCH */
517
 
518
 #undef LINK_SPEC
519
-#define LINK_SPEC "-m elf64_sparc -Y P,%R/tools/lib64 %{shared:-shared} \
520
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
521
   %{!shared: \
522
     %{!static: \
523
       %{rdynamic:-export-dynamic} \
524
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
525 127 dgisselq
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-04-21 20:04:11.761606648 -0400
526 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
527
@@ -83,7 +83,7 @@
528
    When the -shared link option is used a final link is not being
529
    done.  */
530
 
531
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
532
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
533
 
534
 #undef  LINK_SPEC
535
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
536
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
537 127 dgisselq
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-04-21 20:04:11.761606648 -0400
538 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
539
@@ -41,7 +41,7 @@
540
   %{!shared: \
541
     %{!static: \
542
       %{rdynamic:-export-dynamic} \
543
-      -dynamic-linker /tools/lib/ld.so.1} \
544
+      -dynamic-linker /lib/ld.so.1} \
545
     %{static:-static}}"
546
 
547
 #undef  WCHAR_TYPE
548
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
549 127 dgisselq
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-04-21 20:04:11.761606648 -0400
550 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
551
@@ -44,7 +44,7 @@
552
   %{mlongcalls:--longcalls} \
553
   %{mno-longcalls:--no-longcalls}"
554
 
555
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
556
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
557
 
558
 #undef LINK_SPEC
559
 #define LINK_SPEC \
560
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/netbsd.h gcc-5.3.0-zip/gcc/config/zip/netbsd.h
561
--- gcc-5.3.0-original/gcc/config/zip/netbsd.h  1969-12-31 19:00:00.000000000 -0500
562
+++ gcc-5.3.0-zip/gcc/config/zip/netbsd.h       2016-01-30 15:04:14.796899050 -0500
563
@@ -0,0 +1,82 @@
564
+////////////////////////////////////////////////////////////////////////////////
565
+//
566
+// Filename:   netbsd.h
567
+//
568
+// Project:    Zip CPU backend for the GNU Compiler Collection
569
+//
570
+// Purpose:
571
+//
572
+// Creator:    Dan Gisselquist, Ph.D.
573
+//             Gisselquist Technology, LLC
574
+//
575
+////////////////////////////////////////////////////////////////////////////////
576
+//
577
+// Copyright (C) 2016, Gisselquist Technology, LLC
578
+//
579
+// This program is free software (firmware): you can redistribute it and/or
580
+// modify it under the terms of  the GNU General Public License as published
581
+// by the Free Software Foundation, either version 3 of the License, or (at
582
+// your option) any later version.
583
+//
584
+// This program is distributed in the hope that it will be useful, but WITHOUT
585
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
586
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
587
+// for more details.
588
+//
589
+// You should have received a copy of the GNU General Public License along
590
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
591
+// target there if the PDF file isn't present.)  If not, see
592
+// <http://www.gnu.org/licenses/> for a copy.
593
+//
594
+// License:    GPL, v3, as defined and found on www.gnu.org,
595
+//             http://www.gnu.org/licenses/gpl.html
596
+//
597
+//
598
+////////////////////////////////////////////////////////////////////////////////
599
+#ifndef        ZIP_NETBSD_H
600
+#define        ZIP_NETBSD_H
601
+
602
+/* Define default target values. */
603
+
604
+#undef MACHINE_TYPE
605
+#define        MACHINE_TYPE    "NetBSD/Zip ELF"
606
+
607
+#undef TARGET_OS_CPP_BUILTINS
608
+#define        TARGET_OS_CPP_BUILTINS()        \
609
+       do { NETBSD_OS_CPP_BUILTINS_ELF();              \
610
+       builtin_define("__ZIPCPU__");                   \
611
+       builtin_assert("cpu=zip");                      \
612
+       builtin_assert("machine=zip");                  \
613
+       } while(0);
614
+
615
+#undef CPP_SPEC
616
+#define        CPP_SPEC        NETBSD_CPP_SPEC
617
+
618
+#undef STARTFILE_SPEC
619
+#define        STARTFILE_SPEC  NETBSD_STARTFILE_SPEC
620
+
621
+#undef ENDFILE_SPEC
622
+#define        ENDFILE_SPEC    NETBSD_ENDFILE_SPEC
623
+
624
+#undef LIB_SPEC
625
+#define        LIB_SPEC        NETBSD_LIB_SPEC
626
+
627
+#undef TARGET_VERSION
628
+#define        TARGET_VERSION  fprintf(stderr, " (%s)", MACHINE_TYPE);
629
+
630
+/* Make gcc agree with <machine/ansi.h> */
631
+
632
+#undef WCHAR_TYPE
633
+#define        WCHAR_TYPE      "int"
634
+
635
+#undef WCHAR_TYPE_SIZE
636
+#define        WCHAR_TYPE_SIZE 32
637
+
638
+#undef WINT_TYPE
639
+#define        WINT_TYPE       "int"
640
+
641
+/* Clean up after the generic Zip/ELF configuration. */
642
+#undef MD_EXEC_PREFIX
643
+#undef MD_STARTFILE_PREFIX
644
+
645
+#endif /* ZIP_NETBSD_H */
646
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/t-zip gcc-5.3.0-zip/gcc/config/zip/t-zip
647
--- gcc-5.3.0-original/gcc/config/zip/t-zip     1969-12-31 19:00:00.000000000 -0500
648
+++ gcc-5.3.0-zip/gcc/config/zip/t-zip  2016-02-04 19:00:59.939652587 -0500
649
@@ -0,0 +1,47 @@
650
+################################################################################
651
+##
652
+## Filename:   t-zip
653
+##
654
+## Project:    Zip CPU backend for the GNU Compiler Collection
655
+##
656
+## Purpose:
657
+##
658
+## Creator:    Dan Gisselquist, Ph.D.
659
+##             Gisselquist Technology, LLC
660
+##
661
+################################################################################
662
+##
663
+## Copyright (C) 2016, Gisselquist Technology, LLC
664
+##
665
+## This program is free software (firmware): you can redistribute it and/or
666
+## modify it under the terms of  the GNU General Public License as published
667
+## by the Free Software Foundation, either version 3 of the License, or (at
668
+## your option) any later version.
669
+##
670
+## This program is distributed in the hope that it will be useful, but WITHOUT
671
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
672
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
673
+## for more details.
674
+##
675
+## You should have received a copy of the GNU General Public License along
676
+## with this program.  (It's in the $(ROOT)/doc directory, run make with no
677
+## target there if the PDF file isn't present.)  If not, see
678
+## <http://www.gnu.org/licenses/> for a copy.
679
+##
680
+## License:    GPL, v3, as defined and found on www.gnu.org,
681
+##             http://www.gnu.org/licenses/gpl.html
682
+##
683
+##
684
+################################################################################
685
+
686
+FPBIT = fp-bit.c
687
+DPBIT = dp-bit.c
688
+
689
+# dp-bit.c: $(srcdir)/config/fp-bit.c
690
+       # cat $(srcdir)/config/fp-bit.c > dp-bit.c
691
+#
692
+# fp-bit.c: $(srcdir)/config/fp-bit.c
693
+       # echo '#define FLOAT" > fp-bit.c
694
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
695
+
696
+
697
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
698
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
699 127 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-04-21 16:52:37.544818916 -0400
700
@@ -0,0 +1,2174 @@
701 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
702
+//
703
+// Filename:   zip.c
704
+//
705
+// Project:    Zip CPU backend for the GNU Compiler Collection
706
+//
707
+// Purpose:
708
+//
709
+// Creator:    Dan Gisselquist, Ph.D.
710
+//             Gisselquist Technology, LLC
711
+//
712
+////////////////////////////////////////////////////////////////////////////////
713
+//
714
+// Copyright (C) 2016, Gisselquist Technology, LLC
715
+//
716
+// This program is free software (firmware): you can redistribute it and/or
717
+// modify it under the terms of  the GNU General Public License as published
718
+// by the Free Software Foundation, either version 3 of the License, or (at
719
+// your option) any later version.
720
+//
721
+// This program is distributed in the hope that it will be useful, but WITHOUT
722
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
723
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
724
+// for more details.
725
+//
726
+// You should have received a copy of the GNU General Public License along
727
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
728
+// target there if the PDF file isn't present.)  If not, see
729
+// <http://www.gnu.org/licenses/> for a copy.
730
+//
731
+// License:    GPL, v3, as defined and found on www.gnu.org,
732
+//             http://www.gnu.org/licenses/gpl.html
733
+//
734
+//
735
+////////////////////////////////////////////////////////////////////////////////
736
+#include "config.h"
737
+#include "system.h"
738
+#include "coretypes.h"
739
+#include "tm.h"
740
+#include "rtl.h"
741
+#include "dominance.h"
742
+#include "cfg.h"
743
+#include "cfgrtl.h"
744
+#include "cfganal.h"
745
+#include "lcm.h"
746
+#include "cfgbuild.h"
747
+#include "cfgcleanup.h"
748
+#include "predict.h"
749
+#include "basic-block.h"
750
+#include "df.h"
751
+#include "hashtab.h"
752
+#include "hash-set.h"
753
+#include "machmode.h"
754
+#include "symtab.h"
755
+#include "rtlhash.h"
756
+#include "tree.h"
757
+#include "regs.h"
758
+#include "hard-reg-set.h"
759
+#include "real.h"
760
+#include "insn-config.h"
761
+#include "conditions.h"
762
+#include "output.h"
763
+#include "insn-attr.h"
764
+#include "flags.h"
765
+#include "expr.h"
766
+#include "function.h"
767
+#include "recog.h"
768
+#include "toplev.h"
769
+#include "ggc.h"
770
+#include "builtins.h"
771
+#include "calls.h"
772
+#include "langhooks.h"
773
+#include "optabs.h"
774
+#include "explow.h"
775
+#include "emit-rtl.h"
776 122 dgisselq
+#include "ifcvt.h"
777 102 dgisselq
+
778
+// #include "tmp_p.h"
779
+#include "target.h"
780
+#include "target-def.h"
781
+// #include "tm-constrs.h"
782 122 dgisselq
+#include "tm-preds.h"
783 102 dgisselq
+
784
+#include "diagnostic.h"
785
+// #include "integrate.h"
786
+
787
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
788
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
789
+static bool    zip_return_in_memory(const_tree, const_tree);
790
+static bool    zip_frame_pointer_required(void);
791
+
792
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
793
+               const_tree type, bool named);
794
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
795
+
796
+static void    zip_asm_trampoline_template(FILE *);
797
+static void    zip_trampoline_init(rtx, tree, rtx);
798
+static void    zip_init_builtins(void);
799
+static tree zip_builtin_decl(unsigned, bool);
800
+// static void zip_asm_output_anchor(rtx x);
801
+       void    zip_asm_output_def(FILE *s, const char *n, const char *v);
802
+static rtx     zip_expand_builtin(tree exp, rtx target, rtx subtarget,
803
+                       enum machine_mode tmode, int    ignore);
804
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
805
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
806
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
807
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
808
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
809 122 dgisselq
+static          HOST_WIDE_INT  zip_min_opb_imm = -0x20000;
810
+static          HOST_WIDE_INT  zip_max_opb_imm =  0x1ffff;
811 102 dgisselq
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x20000;
812
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1ffff;
813
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
814
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
815
+static int     zip_sched_issue_rate(void) { return 1; }
816
+static bool    zip_legitimate_address_p(machine_mode, rtx, bool);
817
+static bool    zip_legitimate_move_operand_p(machine_mode, rtx, bool);
818
+       void    zip_debug_rtx_pfx(const char *, const_rtx x);
819
+       void    zip_debug_rtx(const_rtx x);
820
+static void    zip_override_options(void);
821
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
822
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
823 111 dgisselq
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
824 117 dgisselq
+static bool    zip_cannot_modify_jumps_p(void);
825 122 dgisselq
+#ifdef HAVE_cc0
826
+       void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
827
+#error "We're not supposed to have CC0 anymore"
828
+#else
829
+static bool    zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
830
+#endif
831 102 dgisselq
+
832
+
833 103 dgisselq
+#define        ALL_DEBUG_OFF   false
834 102 dgisselq
+#define        ALL_DEBUG_ON    false
835
+
836
+enum ZIP_BUILTIN_ID_CODE {
837
+       ZIP_BUILTIN_RTU,
838
+       ZIP_BUILTIN_HALT,
839
+       ZIP_BUILTIN_IDLE,
840
+       ZIP_BUILTIN_SYSCALL,
841
+       ZIP_BUILTIN_SAVE_CONTEXT,
842
+       ZIP_BUILTIN_RESTORE_CONTEXT,
843
+       ZIP_BUILTIN_BITREV,
844
+       ZIP_BUILTIN_CC,
845 117 dgisselq
+       ZIP_BUILTIN_UCC,
846 102 dgisselq
+       ZIP_BUILTIN_MAX
847
+};
848
+
849
+static GTY (()) tree   zip_builtins[(int)ZIP_BUILTIN_MAX];
850
+static enum insn_code  zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
851
+
852
+
853
+#include "gt-zip.h"
854
+
855
+/* The Global 'targetm' Variable. */
856
+struct gcc_target      targetm = TARGET_INITIALIZER;
857
+
858
+
859
+enum   reg_class zip_reg_class(int);
860
+
861
+#define        LOSE_AND_RETURN(msgid, x)               \
862
+       do {                                    \
863
+               zip_operand_lossage(msgid, x);  \
864
+               return;                         \
865
+       } while(0)
866
+
867
+/* Per-function machine data. */
868
+struct GTY(()) machine_function
869
+{
870
+       /* number of pretented arguments for varargs */
871
+       int     pretend_size;
872
+
873
+       /* Number of bytes saved on the stack for local variables. */
874
+       int     local_vars_size;
875
+
876
+       /* Number of bytes saved on stack for register save area */
877
+       int     saved_reg_size;
878
+       int     save_ret;
879
+
880
+       int     sp_fp_offset;
881
+       bool    fp_needed;
882
+       int     size_for_adjusting_sp;
883
+};
884
+
885
+/* Allocate a chunk of memory for per-function machine-dependent data. */
886
+
887
+static struct machine_function *
888
+zip_init_machine_status(void) {
889
+       return ggc_cleared_alloc<machine_function>();
890
+}
891
+
892
+static void
893
+zip_override_options(void)
894
+{
895
+       init_machine_status = zip_init_machine_status;
896
+}
897
+
898
+enum   reg_class
899
+zip_reg_class(int regno)
900
+{
901
+       if (is_ZIP_GENERAL_REG(regno)) {
902
+               return GENERAL_REGS;
903
+       } else if (is_ZIP_REG(regno)) {
904
+               return ALL_REGS;
905
+       } return NO_REGS;
906
+}
907
+
908
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
909
+static bool
910
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
911
+       const   HOST_WIDE_INT size = int_size_in_bytes(type);
912
+       return (size == -1)||(size > UNITS_PER_WORD);
913
+}
914
+
915
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
916
+ * insn.  Formatted output isn't easily implemented, since we use output operand
917
+ * lossage to output the actual message and handle the categorization of the
918
+ * error.  */
919
+
920
+static void
921
+zip_operand_lossage(const char *msgid, rtx op) {
922
+       fprintf(stderr, "Operand lossage??\n");
923
+       debug_rtx(op);
924
+       zip_debug_rtx(op);
925
+       output_operand_lossage("%s", msgid);
926
+}
927
+
928
+/* The PRINT_OPERAND_ADDRESS worker.   */
929
+void
930
+zip_print_operand_address(FILE *file, rtx x) {
931
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
932
+
933
+       if (dbg) zip_debug_rtx(x);
934
+       switch(GET_CODE(x)) {
935
+               case REG:
936 127 dgisselq
+                       gcc_assert(is_ZIP_REG(REGNO(x)));
937 102 dgisselq
+                       fprintf(file, "(%s)", reg_names[REGNO(x)]);
938
+                       break;
939
+               case SYMBOL_REF:
940
+                       fprintf(file, "%s", XSTR(x,0));
941
+                       break;
942
+               case LABEL_REF:
943
+                       x = LABEL_REF_LABEL(x);
944
+               case CODE_LABEL:
945
+                       { char buf[256];
946
+                       ASM_GENERATE_INTERNAL_LABEL(buf, "L", CODE_LABEL_NUMBER(x));
947
+#ifdef ASM_OUTPUT_LABEL_REF
948
+                       ASM_OUTPUT_LABEL_REF(file, buf);
949
+#else
950
+                       assemble_name(file, buf);
951
+#endif
952
+                       }
953
+                       break;
954
+               case PLUS:
955 111 dgisselq
+                       if (!REG_P(XEXP(x, 0))) {
956
+                               fprintf(stderr, "Unsupported address construct\n");
957
+                               zip_debug_rtx(x);
958 102 dgisselq
+                               abort();
959 127 dgisselq
+                       } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0))));
960
+                       if (CONST_INT_P(XEXP(x, 1))) {
961 102 dgisselq
+                               if (INTVAL(XEXP(x,1))!=0) {
962
+                                       fprintf(file, "%ld(%s)",
963
+                                       INTVAL(XEXP(x, 1)),
964
+                                       reg_names[REGNO(XEXP(x, 0))]);
965
+                               } else {
966
+                                       fprintf(file, "(%s)",
967
+                                       reg_names[REGNO(XEXP(x, 0))]);
968
+                               }
969
+                       } else if (GET_CODE(XEXP(x,1)) == SYMBOL_REF) {
970
+                               fprintf(file, "%s(%s)", XSTR(x,0),
971
+                                       reg_names[REGNO(XEXP(x, 0))]);
972
+                       } else if ((GET_CODE(XEXP(x, 1)) == MINUS)
973
+                               && (GET_CODE(XEXP(XEXP(x, 1), 0))==SYMBOL_REF)
974
+                               && (GET_CODE(XEXP(XEXP(x, 1), 1))==SYMBOL_REF)) {
975
+                               fprintf(file, "%s-%s(%s)",
976
+                                       XSTR(XEXP(XEXP(x, 1),0),0),
977
+                                       XSTR(XEXP(XEXP(x, 1),1),0),
978
+                                       reg_names[REGNO(XEXP(x, 0))]);
979
+                       } else
980
+                               fprintf(file, "#INVALID(%s)",
981
+                                       reg_names[REGNO(XEXP(x, 0))]);
982
+                       /*
983
+                       else if (GET_CODE(XEXP(addr, 1)) == LABEL)
984
+                               fprintf(file, "%s(%s)",
985
+                                       GET_CODE(XEXP(addr, 1)),
986
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
987
+                       else if ((GET_CODE(XEXP(addr, 1)) == MINUS)
988
+                               && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 0))==LABEL)
989
+                               && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 1))==LABEL)) {
990
+                               fprintf(file, "%s-%s(%s)",
991
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
992
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
993
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
994
+                       }
995
+                       */
996
+                       break;
997
+               // We don't support direct memory addressing within our
998
+               // instruction set, even though the instructions themselves
999
+               // would support direct memory addressing of the lower 18 bits
1000
+               // of memory space.
1001
+               case MEM:
1002
+                       if (dbg) zip_debug_rtx(x);
1003
+                       zip_print_operand_address(file, XEXP(x, 0));
1004
+                       break;
1005 111 dgisselq
+               case CONST_INT:
1006
+                       fprintf(file, "%ld",INTVAL(x));
1007
+                       break;
1008 102 dgisselq
+               default:
1009 111 dgisselq
+                       fprintf(stderr, "Unknown address format\n");
1010
+                       zip_debug_rtx(x);
1011 102 dgisselq
+                       abort(); break;
1012
+                       // output_addr_const(file, x);
1013
+               break;
1014
+       }
1015
+}
1016
+
1017
+/* The PRINT_OPERAND worker. */
1018
+
1019
+void
1020
+zip_print_operand(FILE *file, rtx x, int code)
1021
+{
1022
+       rtx operand = x;
1023
+       int     rgoff = 0;
1024
+
1025
+       // fprintf(file, "Print Operand!\n");
1026
+
1027
+       /* New code entries should just be added to the switch below.  If
1028
+        * handling is finished, just return.  If handling was just a
1029
+        * modification of the operand, the modified operand should be put in
1030
+        * "operand", and then do a break to let default handling
1031
+        * (zero-modifier) output the operand.
1032
+        */
1033
+       switch(code) {
1034
+               case 0:
1035
+                       /* No code, print as usual. */
1036
+                       break;
1037
+               case 'L':
1038
+                       /* Lower of two registers, print one up */
1039
+                       rgoff = 1;
1040
+                       break;
1041
+               case 'R':
1042
+               case 'H':
1043
+                       /* Higher of a register pair, print normal */
1044
+                       break;
1045
+
1046
+               default:
1047
+                       LOSE_AND_RETURN("invalid operand modifier letter", x);
1048
+       }
1049
+
1050
+       /* Print an operand as without a modifier letter. */
1051
+       switch (GET_CODE(operand)) {
1052
+       case REG:
1053
+               if (REGNO(operand)+rgoff >= FIRST_PSEUDO_REGISTER)
1054
+                       internal_error("internal error: bad register: %d", REGNO(operand));
1055
+               fprintf(file, "%s", reg_names[REGNO(operand)+rgoff]);
1056
+               return;
1057
+       case SCRATCH:
1058
+               LOSE_AND_RETURN("Need a scratch register", x);
1059
+               return;
1060
+
1061
+       case CODE_LABEL:
1062
+       case LABEL_REF:
1063
+       case SYMBOL_REF:
1064
+       case PLUS:
1065
+               PRINT_OPERAND_ADDRESS(file, operand);
1066
+               return;
1067
+       case MEM:
1068
+               PRINT_OPERAND_ADDRESS(file, XEXP(operand, 0));
1069
+               return;
1070
+
1071
+       default:
1072
+               /* No need to handle all strange variants, let
1073
+                * output_addr_const do it for us.
1074
+                */
1075
+               if (CONSTANT_P(operand)) {
1076
+                       output_addr_const(file, operand);
1077
+                       return;
1078
+               }
1079
+
1080
+               LOSE_AND_RETURN("unexpected operand", x);
1081
+       }
1082
+}
1083
+
1084
+static bool
1085
+zip_frame_pointer_required(void)
1086
+{
1087
+       // This should really depend upon whether we have variable sized
1088
+       // arguments in our frame or not.  Once this fails, let's look
1089
+       // at what the problem was and then whether or not we can detect
1090
+       // it.
1091
+       //
1092
+       // Use a GCC global to determine our answer
1093 103 dgisselq
+       if (cfun->calls_alloca)
1094
+               return true;
1095 102 dgisselq
+       return (frame_pointer_needed);
1096
+/*
1097
+*/
1098
+}
1099
+
1100
+/* Determine whether or not a register needs to be saved on the stack or not.
1101
+ */
1102
+static bool
1103
+zip_save_reg(int regno) {
1104
+       if (regno == 0)
1105
+               return ((!crtl->is_leaf)
1106
+                       ||((df_regs_ever_live_p(0))&&(!call_used_regs[0])));
1107
+       else if ((regno == zip_GOT)&&(!ZIP_PIC))
1108
+               return  ((df_regs_ever_live_p(regno))
1109
+                               &&(!call_used_regs[regno]));
1110
+       else if (regno == zip_FP)
1111
+               return((zip_frame_pointer_required())||((df_regs_ever_live_p(regno))
1112
+                               &&(!call_used_regs[regno])));
1113
+       else if (regno < zip_FP)
1114
+               return  ((df_regs_ever_live_p(regno))
1115
+                               &&(!call_used_regs[regno]));
1116
+       return false;
1117
+}
1118
+
1119
+/* Compute the size of the local area and the size to be adjusted by the
1120
+ * prologue and epilogue.
1121
+ *
1122
+ * Here's what we are looking at (top is the current, bottom is the last ...)
1123
+ *
1124
+ *     Stack Pointer ->
1125 124 dgisselq
+ *                     Outgoing arguments
1126 102 dgisselq
+ *                     Local variables (could be variable size)
1127
+ *     Frame Pointer ->        (= Stack Pointer + sp_fp_offset)
1128
+ *                     Saved return address, if saved
1129
+ *                     Other Saved registers
1130
+ *                     Saved frame pointer (if used)
1131
+ *                     Saved R12, if used
1132
+ *                     (Stack pointer is not saved)
1133
+ *     Original stack pointer ->       (= Stack_Pointer +size_for_adjusting_sp)
1134
+ *                     Called arguments (not passed in registers)
1135
+ *                     Return arguments (not R1, args.pretend_args_size)
1136
+ *             (Prior function's stack frame ... )
1137
+ *
1138
+ */
1139
+static void
1140
+zip_compute_frame(void) {
1141
+       int     regno;
1142
+       int     args_size;
1143 124 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1144 102 dgisselq
+
1145 124 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME\n");
1146 102 dgisselq
+       // gcc_assert(crtl);
1147
+       gcc_assert(cfun);
1148
+       gcc_assert(cfun->machine);
1149
+
1150
+       args_size=(ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
1151
+
1152
+       if(crtl->args.pretend_args_size > 0) {
1153
+               args_size += crtl->args.pretend_args_size;
1154
+               // printf("%s pretend_args_size : %d\n", current_function_name(),
1155
+                       // crtl->args.pretend_args_size);
1156
+               cfun->machine->pretend_size = crtl->args.pretend_args_size;
1157
+       }
1158
+
1159
+       cfun->machine->local_vars_size = get_frame_size();
1160
+
1161
+       // Save callee-saved registers.
1162
+       cfun->machine->saved_reg_size = 0;
1163
+       for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1164
+               if (zip_save_reg(regno))
1165
+                       cfun->machine->saved_reg_size ++;
1166
+       }
1167
+
1168
+       cfun->machine->fp_needed = (zip_frame_pointer_required());
1169
+
1170
+       if ((cfun->machine->fp_needed)&&
1171
+                       (!df_regs_ever_live_p(zip_FP))) {
1172
+               cfun->machine->saved_reg_size ++;
1173
+       }
1174
+
1175
+       cfun->machine->sp_fp_offset = args_size + cfun->machine->local_vars_size;
1176
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
1177
+                       + cfun->machine->saved_reg_size
1178
+                       + args_size;
1179 124 dgisselq
+       if(dbg) {
1180
+               fprintf(stderr, "\tFRAME-POINTR: %s\n",
1181
+                       cfun->machine->fp_needed?"Yes":"No");
1182
+               fprintf(stderr, "\tARGS-SIZE   : %d\n",
1183
+                       args_size);
1184
+               fprintf(stderr, "\tLOCALS-SIZE : %d\n",
1185
+                       cfun->machine->local_vars_size);
1186
+               fprintf(stderr, "\tREGISTERS   : %d\n",
1187
+                       cfun->machine->saved_reg_size);
1188
+               fprintf(stderr, "\tSP_FP_OFFSET: %d\n",
1189
+                       cfun->machine->sp_fp_offset);
1190
+               fprintf(stderr, "\tSP-ADJUSTMNT: %d\n",
1191
+                       cfun->machine->size_for_adjusting_sp);
1192
+       }
1193 102 dgisselq
+}
1194
+
1195
+void
1196
+zip_expand_prologue(void) {
1197
+       rtx     insn;
1198
+
1199
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1200
+       zip_compute_frame();
1201
+
1202 124 dgisselq
+       if (dbg)  fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
1203 127 dgisselq
+       if (dbg)  fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
1204
+                       cfun->machine->sp_fp_offset);
1205 102 dgisselq
+       if (cfun->machine->size_for_adjusting_sp != 0) {
1206
+               insn = emit_insn(gen_subsi3(stack_pointer_rtx,
1207
+                               stack_pointer_rtx,
1208
+                       gen_int_mode(cfun->machine->size_for_adjusting_sp,
1209
+                               SImode)));
1210
+                       // cfun->machine->sp_fp_offset
1211
+
1212
+               RTX_FRAME_RELATED_P(insn) = 1;
1213
+       }
1214
+
1215
+       {
1216
+               int offset = 0, regno;
1217
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1218
+                       if (zip_save_reg(regno)) {
1219 127 dgisselq
+                               if (dbg) fprintf(stderr,
1220
+                                       "PROLOGUE: Saving R%d in %d+%d(SP)\n",
1221
+                                       regno, cfun->machine->sp_fp_offset,
1222
+                                       offset);
1223 124 dgisselq
+                               insn=emit_insn(gen_movsi_sto_off(
1224
+                                       stack_pointer_rtx,
1225
+                                       GEN_INT(cfun->machine->sp_fp_offset
1226
+                                               +offset++),
1227 102 dgisselq
+                                       gen_rtx_REG(SImode, regno)));
1228
+                               RTX_FRAME_RELATED_P(insn) = 1;
1229
+                       }
1230
+               }
1231 103 dgisselq
+               if (dbg)  fprintf(stderr, "%d registers saved%s\n", offset,
1232
+                       (crtl->saves_all_registers)?", should be all of them":", less than all");
1233 102 dgisselq
+       }
1234
+
1235
+       if (cfun->machine->fp_needed) {
1236
+               if (dbg) zip_debug_rtx(stack_pointer_rtx);
1237
+               if (dbg) zip_debug_rtx(frame_pointer_rtx);
1238
+               insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
1239 124 dgisselq
+                               stack_pointer_rtx,
1240
+                               GEN_INT(cfun->machine->sp_fp_offset)));
1241 102 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1242 103 dgisselq
+               if (dbg)  fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
1243 102 dgisselq
+       }
1244
+}
1245
+
1246
+bool
1247
+zip_use_return_insn(void)
1248
+{
1249
+       if ((!reload_completed)||(cfun->machine->fp_needed)
1250
+                       ||(get_frame_size()!=0)) {
1251
+               // If R0 ever gets pushed to the stack, then we cannot
1252
+               // use a master return from anywhere.  We need to clean up the
1253
+               // stack first.
1254
+               if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
1255
+                                               &&(!call_used_regs[0]))) {
1256
+                       return false;
1257
+               }
1258
+       }
1259
+       zip_compute_frame();
1260
+       return (cfun->machine->size_for_adjusting_sp == 0);
1261
+}
1262
+
1263
+/* As per the notes in M68k.c, quote the function epilogue should not depend
1264
+ * upon the current stack pointer.  It should use the frame poitner only,
1265
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
1266
+ * take advantage of it to omit stack adjustments before returning ...
1267
+ *
1268
+ * Let's see if we can use their approach here.
1269
+ *
1270
+ * We can't.  Consider our choices:
1271
+ *     LOD (FP),R0
1272
+ *     LOD 1(FP),R4
1273
+ *     LOD 2(FP),R5
1274
+ *     LOD 3(FP),R6
1275
+ *     LOD 4(FP),FP
1276
+ *     ... Then what is the stack pointer?
1277
+ * or
1278
+ *     LOD (FP),R0
1279
+ *     LOD 1(FP),R4
1280
+ *     LOD 2(FP),R5
1281
+ *     LOD 3(FP),R6
1282
+ *     MOV FP,SP
1283
+ *     LOD 4(SP),FP
1284
+ *     ... Which suffers unnecessary pipeline stalls, and certainly doesn't
1285
+ *     exploit our pipeline memory function
1286
+ * or
1287
+ *     MOV FP,SP
1288
+ *     LOD (SP),R0
1289
+ *     LOD 1(SP),R4
1290
+ *     LOD 2(SP),R5
1291
+ *     LOD 3(SP),R6
1292
+ *     LOD 4(SP),FP
1293
+ * Which will be our choice.  Note that we do use the stack pointer, eventually.
1294
+ *
1295
+ */
1296
+void
1297
+zip_expand_epilogue(void) {
1298
+       int     regno, offset;
1299
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1300
+
1301
+       zip_compute_frame();
1302
+
1303
+       if (dbg) fprintf(stderr, "EPILOG::\n");
1304
+       if (cfun->machine->fp_needed) {
1305 124 dgisselq
+               // This is done special--if you can't trust the stack pointer
1306
+               // enough so that you must have a frame pointer, then you can't
1307
+               // trust its offset enough to restore from it.  Hence, we start
1308
+               // by moving the frame pointer to the stack pointer to recover
1309
+               // the stack pointer back to a usable value.
1310 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
1311
+               emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
1312
+       }
1313
+
1314
+       if (cfun->machine->saved_reg_size != 0) {
1315 124 dgisselq
+               if (cfun->machine->fp_needed)
1316
+                       offset = 0;
1317
+               else
1318
+                       offset = cfun->machine->sp_fp_offset;
1319 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
1320
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1321
+                       if (zip_save_reg(regno)) {
1322
+                               if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d\n", regno);
1323 124 dgisselq
+                               emit_insn(gen_movsi_lod_off(
1324 102 dgisselq
+                                               gen_rtx_REG(SImode, regno),
1325 124 dgisselq
+                                               stack_pointer_rtx,
1326
+                                               GEN_INT(offset++)));
1327 102 dgisselq
+                       }
1328
+               }
1329
+       }
1330
+
1331 124 dgisselq
+       if (cfun->machine->fp_needed) {
1332
+               // Restore the stack pointer back to the original, the
1333
+               // difference being the difference from the frame pointer
1334
+               // to the original stack
1335
+               emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
1336
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
1337
+                               -cfun->machine->sp_fp_offset)));
1338
+       } else {
1339
+               // else now the difference is between the stack pointer and
1340
+               // the original stack pointer.
1341 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
1342
+                               cfun->machine->size_for_adjusting_sp);
1343
+               emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
1344 124 dgisselq
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
1345 102 dgisselq
+       }
1346
+       if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
1347
+
1348
+       emit_jump_insn(ret_rtx);
1349
+}
1350
+
1351
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
1352
+ *
1353
+ * We currently only support calculating the return address for the current
1354
+ * frame.
1355
+ */
1356
+
1357
+/*
1358
+rtx
1359
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
1360
+{
1361
+       if (count)
1362
+               return NULL_RTX;
1363
+
1364
+       zip_compute_frame();
1365
+
1366
+       // saved return address for current function is at fp - 1
1367
+       if (cfun->machine->save_ret)
1368
+               return gen_rtx_MEM(Pmode, plus_constant(frame_pointer_rtx,
1369
+                               -UNITS_PER_WORD));
1370
+       return get_hard_reg_initial_val(Pmode, RETURN_ADDRESS_REGNUM);
1371
+}
1372
+*/
1373
+
1374
+/* Implements the macro INITIAL_ELIMINATION_OFFSET,
1375
+ * return the OFFSET.
1376
+ */
1377
+int
1378
+zip_initial_elimination_offset(int from, int to) {
1379
+       int     ret = 0;
1380
+       zip_compute_frame();
1381
+
1382
+       if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
1383
+               ret = cfun->machine->sp_fp_offset;
1384 117 dgisselq
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
1385
+               ret = cfun->machine->sp_fp_offset;
1386 102 dgisselq
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
1387 117 dgisselq
+               // ret = cfun->machine->local_vars_size;
1388
+               ret = 0;
1389 102 dgisselq
+       } else {
1390
+               abort();
1391
+       }
1392
+
1393
+       return ret;
1394
+}
1395
+
1396
+/*
1397
+ * Code taken from m68k ...
1398
+ */
1399
+static bool
1400
+zip_can_eliminate(int from, int to)
1401
+{
1402
+       // fprintf(stderr, "CAN_ELIMINATE::QUERYING(%d,%d)\n", from, to);
1403
+       if ((from == zip_FP)&&(to == zip_SP))
1404
+               return !cfun->machine->fp_needed;
1405
+       return true;
1406
+}
1407
+
1408
+/*
1409
+static void
1410
+zip_basic_check(void)
1411
+{
1412
+       gcc_assert(mode_base_align[SImode]==4);
1413
+       if ((BITS_PER_UNIT != 32)
1414
+                       ||(GET_MODE_SIZE(SImode)!=1)
1415
+                       ||(GET_MODE_SIZE(DImode)!=1)
1416
+                       ||(HARD_REGNO_NREGS(0,SImode)!=1)) {
1417
+               printf("SIZEOF(SIMode) == %d\n", GET_MODE_SIZE(SImode));
1418
+               printf("BITS_PER_UNIT  == %d\n", BITS_PER_UNIT);
1419
+               gcc_assert(BITS_PER_UNIT==32);
1420
+               gcc_assert(GET_MODE_SIZE(SImode)==1);
1421
+               gcc_assert(HARD_REGNO_NREGS(0,SImode)==1);
1422
+       }
1423
+}
1424
+*/
1425
+
1426
+#define        zip_basic_check()
1427
+
1428
+/* Compute the number of word sized regiters needed to hold a function
1429
+ * argument of mode INT_MODE and tree type TYPE.
1430
+ */
1431
+int
1432
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
1433
+       int     size;
1434
+
1435
+       zip_basic_check();
1436
+
1437
+       if (targetm.calls.must_pass_in_stack(mode, type))
1438
+               return 0;
1439
+
1440
+       if ((type)&&(mode == BLKmode))
1441
+               size = int_size_in_bytes(type);
1442
+       else
1443
+               size = GET_MODE_SIZE(mode);
1444
+
1445
+       return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
1446
+}
1447
+
1448
+/* pushed in function prologue */
1449
+/*
1450
+static int
1451
+zip_arg_partial_bytes(CUMULATIVE_ARGS *cum, enum machine_mode mode,
1452
+               tree type, bool name ATTRIBUTE_UNUSED) {
1453
+       int     words;
1454
+       unsigned int    regs = zip_num_arg_regs(mode, type);
1455
+
1456
+       if (*cum >= ZIP_LAST_ARG_REGNO + 1)
1457
+               words = 0;
1458
+       else if ((*cum + regs) > ZIP_LAST_ARG_REGNO + 1)
1459
+               words = (*cum + regs) - ZIP_LAST_ARG_REGNO + 1;
1460
+       else
1461
+               words = 0;
1462
+
1463
+       return words * UNITS_PER_WORD;
1464
+}
1465
+*/
1466
+
1467
+static void
1468
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
1469
+               const_tree type, bool named ATTRIBUTE_UNUSED) {
1470
+       CUMULATIVE_ARGS *cum;
1471
+       int     nreg;
1472
+
1473
+       zip_basic_check();
1474
+
1475
+       cum = get_cumulative_args(ca);
1476
+       nreg = zip_num_arg_regs(mode, type);
1477
+       if (((*cum)+nreg) > NUM_ARG_REGS)
1478
+               (*cum) = NUM_ARG_REGS;
1479
+       else
1480
+               (*cum) += nreg;
1481
+}
1482
+
1483
+static rtx
1484
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
1485
+               const_tree type ATTRIBUTE_UNUSED, bool named) {
1486
+       CUMULATIVE_ARGS *cum;
1487
+
1488
+       zip_basic_check();
1489
+
1490
+
1491
+       if (!named)
1492
+               return NULL_RTX;
1493
+       //if (targetm.calls.must_pass_in_stack(mode, type))
1494
+               //return NULL_RTX;
1495
+       cum = get_cumulative_args(ca);
1496
+
1497
+       if ((*cum) >= NUM_ARG_REGS)
1498
+               return NULL_RTX;
1499
+       return
1500
+               gen_rtx_REG(mode, (*cum)+1);
1501
+}
1502
+
1503 122 dgisselq
+#ifdef HAVE_cc0
1504 102 dgisselq
+/* NOTICE_UPDATE_CC sends us here
1505
+ */
1506
+void
1507
+zip_update_cc_notice(rtx exp, rtx_insn *insn)
1508
+{
1509 122 dgisselq
+#error "The CC0 code was supposed to be removed"
1510 102 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1511
+       enum    attr_ccresult  ccr;
1512
+       enum    attr_conditional  conditionally_executed;
1513
+
1514
+       // The default is that nothing has changed.
1515
+       // cc_status = cc_status_prev;
1516
+       rtx     src, dest;
1517
+
1518
+       if (dbg) fprintf(stderr, "CC-NOTICE ...\n");
1519
+       if (dbg) zip_debug_rtx_pfx("CC :", exp);
1520
+       if (dbg) debug_rtx(exp);
1521
+
1522
+       ccr = get_attr_ccresult(insn);
1523
+       if (ccr == CCRESULT_UNKNOWN) {
1524
+               CC_STATUS_INIT;
1525
+               if (dbg) fprintf(stderr, "\tINIT-CC\n");
1526
+               return;
1527
+       }
1528
+
1529
+       if ((GET_CODE(exp) == PARALLEL)&&(GET_CODE(XVECEXP(exp, 0, 0))==SET)) {
1530
+               // This works up and until we add cc0 parallel instructions
1531
+               // to our instruction set.
1532
+               dest = SET_DEST(XVECEXP(exp, 0, 0));
1533
+               src  = SET_SRC (XVECEXP(exp, 0, 0));
1534
+       } else if (GET_CODE(exp) == SET) {
1535
+               dest = SET_DEST(exp);
1536
+               src  = SET_SRC (exp);
1537
+       } else {
1538
+               // First, do nothing if we haven't touched the condition codes.
1539
+               // Condition codes can only be changed as a result of a set
1540
+               // expression ...?
1541
+               if (dbg) fprintf(stderr, "Non-set expression, doesn\'t touch condition codes\n");
1542
+               return;
1543
+       }
1544
+
1545 111 dgisselq
+
1546
+       if (ccr == CCRESULT_UNCHANGED) {
1547
+               if (dbg) fprintf(stderr, "\tUnchanged CC\n");
1548
+
1549
+               // We can't just run away here ... even though the CC result
1550
+               // hasn't changed, GCC's ability to recognize it as a valid
1551
+               // result has changed.  In other words, if we just 'set' a
1552
+               // value contained within either value1 or value2, then we'll
1553
+               // need to update those values so that they are no longer looked
1554
+               // upon as potentially containing the current CC values.
1555
+
1556
+               if (dest) {
1557
+                       if (dest == cc0_rtx)
1558
+                               CC_STATUS_INIT;
1559
+                       else if ((REG_P(dest))&&(dest != pc_rtx)) {
1560
+                               // An example here might be a load instruction
1561
+                               if (reg_mentioned_p(dest, cc_status.value1))
1562
+                                       cc_status.value1 = NULL_RTX;
1563
+                               if (reg_mentioned_p(dest, cc_status.value2))
1564
+                                       cc_status.value2 = NULL_RTX;
1565
+                       }
1566
+               }
1567
+               return;
1568
+       }
1569
+
1570 102 dgisselq
+       // Gotta wait on this test, until we know whether or not the
1571
+       // conditionally executed instruction was designed to set the
1572
+       // CC0 register.
1573
+       conditionally_executed = get_attr_conditional(insn);
1574
+       if ((conditionally_executed == CONDITIONAL_YES)&&(dest != cc0_rtx)) {
1575
+               // cc_status is unchanged
1576 111 dgisselq
+               // However, GCC's vision of it may have changed
1577
+               //
1578
+               // Initialize CC_STATUS
1579 102 dgisselq
+               if (dbg) fprintf(stderr, "\tCC -- unchanged (conditional exec)\n");
1580 111 dgisselq
+               CC_STATUS_INIT;
1581 102 dgisselq
+               return;
1582 111 dgisselq
+       } else if (GET_CODE(src)==IF_THEN_ELSE) {
1583
+               // Same thing as above
1584
+               CC_STATUS_INIT;
1585
+               return;
1586 102 dgisselq
+       }
1587
+
1588
+       if (ccr == CCRESULT_VALIDZN)
1589
+               cc_status.flags = CC_NO_OVERFLOW;
1590
+       else
1591
+               cc_status.flags = 0;
1592
+       cc_status.value1 = dest;
1593
+       if (dest == cc0_rtx)
1594
+               cc_status.value2 = src;
1595
+       else if((REG_P(dest))&&(!reg_mentioned_p(dest, src)))
1596
+               cc_status.value2 = src;
1597
+       else if((SUBREG_P(dest))&&(!reg_mentioned_p(XEXP(dest,0), src)))
1598
+               cc_status.value2 = src;
1599
+       else
1600
+               cc_status.value2 = 0;
1601
+       if (dbg) fprintf(stderr, "\tCC -- Set flags for\n");
1602
+       if (dbg) zip_debug_rtx_pfx("V1: ", dest);
1603
+       if ((dbg)&&(cc_status.value2)) zip_debug_rtx_pfx("V2: ", src);
1604
+       else if (dbg)   fprintf(stderr, "V2: (No SRC)\n");
1605
+       if ((dbg)&&(REG_P(dest))) fprintf(stderr, "src refers to dest ?? %s\n",
1606
+               refers_to_regno_p(REGNO(dest),REGNO(dest),src,NULL)?"Yes":"No");
1607
+       if ((dbg)&&(REG_P(dest))) fprintf(stderr, "Occurrs %d times\n",
1608
+               count_occurrences(dest,src,0));
1609
+       if ((dbg)&&(REG_P(dest))) fprintf(stderr, "%s mentioned\n",
1610
+               reg_mentioned_p(dest,src)?"Is":"Is not");
1611
+       if ((dbg)&&(REG_P(dest))) fprintf(stderr, "%s referenced\n",
1612
+               reg_referenced_p(dest,src)?"Is":"Is not");
1613
+
1614
+//
1615
+// These results are only used in final.c, where they are used to remove
1616
+// compare instructions if the optimizer is on.  If I produce nothing, no
1617
+// compare instructions will be removed.  If I produce something, a smart
1618
+// decision may be made to remove compare instructions.
1619
+//
1620
+// cc_status will be compared  with subsequent
1621
+//     (set (cc0) (something)) (i.e. compare only) instructions
1622
+//
1623
+//     (set (cc0) (compare (x) (y)))
1624
+//     dst = cc0 -- the destination of the set is ignored, save that it must be
1625
+//             cc0
1626
+//     src1 = (compare (x) (y))
1627
+//     if (src1 == compare)&&(y == (const_int 0))
1628
+//             src2 = (x)
1629
+//     else
1630
+//             src2 = null
1631
+//
1632
+//     Four conditions:
1633
+//     1. if (val1)&&(src1 == val1)
1634
+//             This would be true if I had seen a (set (val1) (src1)) insn
1635
+//             If I have seen a (set (val1) (src1))
1636
+//                     or equivalently a (set (val1) (compare (x) (y)))
1637
+//     or
1638
+//     2. if (val2)&&(src1 == val2)
1639
+//             This would be true if I had seen a (set (val1) (src1)) insn,
1640
+//             and only if val2 was still valid.
1641
+//     or
1642
+//     3. if (src2)&&(value1)&&(src2 == value1)
1643
+//             This would be true if we are comparing against zero, and the
1644
+//             number we are comparing against zero is value 1
1645
+//     or
1646
+//     4. if (src2)&&(value2)&&(src2 == value2)
1647
+//             ... or value2.  This is the common ZipCPU case.
1648
+//
1649
+//             then delete the compare.
1650
+//
1651
+}
1652 122 dgisselq
+#else
1653 102 dgisselq
+
1654 122 dgisselq
+void   zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
1655
+               bool preserve_op0)
1656
+{
1657
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1658 102 dgisselq
+
1659 122 dgisselq
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
1660
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
1661
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
1662
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
1663
+
1664
+       if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
1665
+               rtx tem = *op0;
1666
+               *op0 = *op1;
1667
+               *op1 = tem;
1668
+               *code = (int)swap_condition((enum rtx_code)*code);
1669
+       }
1670
+
1671
+       if ((*code == LE)||(*code == LEU)||(*code == GTU)) {
1672
+               int offset = 1; // (*code == GTU) ? 1 : -1;
1673
+               bool    swap = false;
1674
+
1675
+               if (CONST_INT_P(*op1)) {
1676
+                       *op1 = GEN_INT(INTVAL(*op1)+offset);
1677
+                       swap = true;
1678
+               } else if (REG_P(*op1)) {
1679
+                       *op1 = plus_constant(SImode, *op1, offset, true);
1680
+                       swap = true;
1681
+               } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
1682
+                       *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
1683
+                               INTVAL(XEXP(*op1,1))+offset);
1684
+                       swap = true;
1685
+               } if (swap) {
1686
+                       if (*code == LE)
1687
+                               (*code)= LT;
1688
+                       else if (*code == LEU)
1689
+                               (*code)= LTU;
1690
+                       else // (*code == GTU)
1691
+                               (*code) = GEU;
1692
+               }
1693
+       }
1694
+}
1695
+
1696
+static bool
1697
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
1698
+       *a = zip_CC;
1699
+       *b = INVALID_REGNUM;
1700
+       return true;
1701
+}
1702
+
1703
+#endif
1704
+
1705
+
1706 102 dgisselq
+/* totally buggy - we can't return pointers to nested functions */
1707
+static void
1708
+zip_asm_trampoline_template(FILE *f) {
1709
+       // Whereas at one time I thought I wouldn't need it, now I know I
1710
+       // need this trampoline function, although it is for a completely
1711
+       // different purpose than the one I was familiar with.
1712
+       fprintf(f, "\tldihi 0,r1\n");
1713
+       fprintf(f, "\tldilo 0,r1\n");
1714
+       fprintf(f, "\tjmp r1\n");
1715
+}
1716
+
1717
+/* Worker function for TARGET_TRAMPOLINE_INIT. */
1718
+static void
1719
+zip_trampoline_init(rtx m_tramp ATTRIBUTE_UNUSED,
1720
+       tree fndecl ATTRIBUTE_UNUSED,
1721
+       rtx chain_value ATTRIBUTE_UNUSED) {
1722
+// #warning "This needs to be filled out"
1723
+       abort();
1724
+}
1725
+
1726
+static tree
1727
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
1728
+       tree type)
1729
+{
1730
+       tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
1731
+       zip_basic_check();
1732
+
1733
+       if(t) {
1734
+               zip_builtins[code] = t;
1735
+               zip_builtins_icode[code] = icode;
1736
+       }
1737
+
1738
+       return t;
1739
+
1740
+}
1741
+
1742
+void   zip_init_builtins(void) {
1743
+       zip_basic_check();
1744
+
1745
+  tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
1746
+#ifdef HAVE_zip_rtu
1747
+  def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
1748
+#endif
1749
+#ifdef HAVE_zip_halt
1750
+  def_builtin("zip_halt",  CODE_FOR_zip_halt,  ZIP_BUILTIN_HALT, void_ftype_void);
1751
+#endif
1752
+#ifdef HAVE_zip_idle
1753
+  def_builtin("zip_idle", CODE_FOR_zip_idle, ZIP_BUILTIN_IDLE, void_ftype_void);
1754
+#endif
1755
+
1756
+#ifdef HAVE_zip_syscall
1757
+// Support int SYSCALL(callID, int a, int b, int c);
1758
+  def_builtin("zip_syscall", CODE_FOR_zip_syscall, ZIP_BUILTIN_SYSCALL,
1759
+                       build_function_type_list(void_type_node, NULL_TREE));
1760
+#endif
1761
+
1762
+#ifdef HAVE_zip_save_context
1763
+  def_builtin("zip_save_context", CODE_FOR_zip_save_context, ZIP_BUILTIN_SAVE_CONTEXT,
1764
+               build_function_type_list(void_type_node, ptr_type_node, 0));
1765
+#endif
1766
+
1767
+#ifdef HAVE_zip_restore_context
1768
+  def_builtin("zip_restore_context", CODE_FOR_zip_restore_context, ZIP_BUILTIN_RESTORE_CONTEXT,
1769
+       build_function_type_list(void_type_node, ptr_type_node, 0));
1770
+#endif
1771
+
1772
+#ifdef HAVE_zip_bitrev
1773
+  def_builtin("zip_bitrev", CODE_FOR_zip_bitrev, ZIP_BUILTIN_BITREV,
1774
+       build_function_type_list(unsigned_type_node, unsigned_type_node,
1775
+               NULL_TREE));
1776
+#endif
1777
+
1778
+#ifdef HAVE_zip_cc
1779
+  def_builtin("zip_cc", CODE_FOR_zip_cc, ZIP_BUILTIN_CC,
1780
+       build_function_type_list(unsigned_type_node, NULL_TREE));
1781
+#endif
1782
+
1783 117 dgisselq
+#ifdef HAVE_zip_ucc
1784
+  def_builtin("zip_ucc", CODE_FOR_zip_ucc, ZIP_BUILTIN_UCC,
1785
+       build_function_type_list(unsigned_type_node, NULL_TREE));
1786
+#endif
1787
+
1788 102 dgisselq
+}
1789
+
1790
+static tree
1791
+zip_builtin_decl(unsigned zip_builtin_code, bool initialize_p ATTRIBUTE_UNUSED)
1792
+{
1793
+  if (zip_builtin_code >= ZIP_BUILTIN_MAX)
1794
+    return error_mark_node;
1795
+
1796
+  return zip_builtins[zip_builtin_code];
1797
+}
1798
+
1799
+static rtx
1800
+zip_expand_builtin(tree exp, rtx target,
1801
+               rtx subtarget ATTRIBUTE_UNUSED,
1802
+               machine_mode tmode ATTRIBUTE_UNUSED,
1803
+               int     ignore ATTRIBUTE_UNUSED) {
1804
+
1805
+       tree    fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
1806
+       bool    nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
1807
+       enum    ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
1808
+       enum    insn_code icode = zip_builtins_icode[code];
1809
+       rtx     pat, op[5];
1810
+       call_expr_arg_iterator  iter;
1811
+       tree    arg;
1812
+
1813
+       if ((code == ZIP_BUILTIN_SAVE_CONTEXT)
1814
+                       ||(code == ZIP_BUILTIN_RESTORE_CONTEXT)) {
1815
+               arg = first_call_expr_arg(exp, &iter);
1816
+               if (arg == error_mark_node)
1817
+                       return NULL_RTX;
1818
+               op[0] = expand_normal(arg);
1819
+               if (GET_CODE(op[0]) != REG)
1820
+                       op[0] = force_reg(Pmode, op[0]);
1821
+               pat = GEN_FCN(icode)(op[0]);
1822
+       } else if (code == ZIP_BUILTIN_BITREV) {
1823
+               arg = first_call_expr_arg(exp, &iter);
1824
+               if (arg == error_mark_node) {
1825
+                       return NULL_RTX;
1826
+               }
1827
+               op[0] = expand_normal(arg);
1828
+               if (!target)
1829
+                       target = gen_reg_rtx(SImode);
1830
+               pat = GEN_FCN(icode)(target, op[0]);
1831 117 dgisselq
+       } else if ((code == ZIP_BUILTIN_CC)||(code == ZIP_BUILTIN_UCC)) {
1832 102 dgisselq
+               if (!target)
1833
+                       target = gen_reg_rtx(SImode);
1834
+               pat = GEN_FCN(icode)(target);
1835
+       } else // RTU, HALT, IDLE
1836
+               pat = GEN_FCN(icode)();
1837
+       if (!pat)
1838
+               return NULL_RTX;
1839
+       emit_insn(pat);
1840
+       return (nonvoid ? target : const0_rtx);
1841
+}
1842
+
1843
+static bool
1844
+zip_scalar_mode_supported_p(enum machine_mode mode) {
1845
+       zip_basic_check();
1846
+
1847
+       return ((mode)==SImode)||((mode)==DImode); // ||((mode)==SFmode);
1848
+}
1849
+
1850
+static bool
1851
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode) {
1852
+       return ((mode)==SFmode)||((mode)==DFmode);
1853
+}
1854
+
1855
+static int
1856
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
1857
+       enum machine_mode mode ATTRIBUTE_UNUSED,
1858
+       addr_space_t as ATTRIBUTE_UNUSED, bool spd ATTRIBUTE_UNUSED) {
1859
+       return 1;
1860
+}
1861
+
1862
+static bool
1863
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
1864
+       addr_space_t as ATTRIBUTE_UNUSED) {
1865
+       return false;
1866
+}
1867
+
1868
+/*
1869
+static void
1870
+zip_asm_output_anchor(rtx x) {
1871
+       printf("ANCHOR: OP(%d)\n", GET_CODE(x));
1872
+}
1873
+*/
1874
+
1875
+static void
1876
+zip_debug_print(const char *pfx, int lvl, const char *str) {
1877
+       int     i;
1878
+       i = lvl;
1879
+       if ((true)||(lvl == 0))
1880
+               fprintf(stderr, "%s", pfx);
1881
+       else
1882
+               i += strlen(pfx);
1883
+       while(i-->0)
1884
+               fprintf(stderr, "  ");
1885
+       fprintf(stderr, "%s\n", str);
1886
+}
1887
+
1888
+static void
1889
+zip_debug_print_m(const char *pfx, int lvl, const char *str, enum machine_mode m) {
1890
+       int     i;
1891
+
1892
+       i = lvl;
1893
+       if ((true)||(lvl == 0))
1894
+               fprintf(stderr, "%s", pfx);
1895
+       else
1896
+               i = lvl+strlen(pfx);
1897
+       while(i-->0)
1898
+               fprintf(stderr, "  ");
1899
+       switch(m) {
1900
+               case VOIDmode:
1901
+                       fprintf(stderr, "%s:V\n", str);
1902
+                       break;
1903
+               case BLKmode:
1904
+                       fprintf(stderr, "%s:BLK\n", str);
1905
+                       break;
1906
+               case BImode:
1907
+                       fprintf(stderr, "%s:BI\n", str);
1908
+                       break;
1909
+#ifdef HAVE_QImode
1910
+               case QImode:
1911
+                       fprintf(stderr, "%s:QI\n", str);
1912
+                       break;
1913
+#endif
1914
+#ifdef HAVE_HImode
1915
+               case HImode:
1916
+                       fprintf(stderr, "%s:HI\n", str);
1917
+                       break;
1918
+#endif
1919
+               case SImode:
1920
+                       fprintf(stderr, "%s:SI\n", str);
1921
+                       break;
1922 122 dgisselq
+               case CCmode:
1923
+                       fprintf(stderr, "%s:CC\n", str);
1924
+                       break;
1925 102 dgisselq
+               case DImode:
1926
+                       fprintf(stderr, "%s:DI\n", str);
1927
+                       break;
1928
+               default:
1929
+                       fprintf(stderr, "%s:?\n", str);
1930
+       }
1931
+}
1932
+
1933
+static void
1934
+zip_debug_rtx_1(const char *pfx, const_rtx x, int lvl) {
1935
+       if (x == NULL_RTX) {
1936
+               zip_debug_print(pfx, lvl, "(NULL-RTX)");
1937
+               return;
1938
+       } else if (GET_CODE(x) > NUM_RTX_CODE) {
1939
+               char    buf[64];
1940
+               sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
1941
+               zip_debug_print(pfx, lvl, buf);
1942 117 dgisselq
+               gcc_assert(0 && "Bad RTX Code");
1943 102 dgisselq
+               return;
1944
+       } switch(GET_CODE(x)) { // rtl.def
1945 122 dgisselq
+       case PARALLEL:
1946
+               zip_debug_print(pfx, lvl, "(PARALLEL");
1947
+               for(int j=0; j<XVECLEN(x,0);j++)
1948
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
1949
+               zip_debug_print(pfx, lvl, ")");
1950
+               debug_rtx(x);
1951
+               break;
1952 102 dgisselq
+       case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
1953 122 dgisselq
+       case SEQUENCE:
1954
+               zip_debug_print(pfx, lvl, "(SEQUENCE");
1955
+               for(int j=0; j<XVECLEN(x,0);j++)
1956
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
1957
+               zip_debug_print(pfx, lvl, ")");
1958
+               debug_rtx(x);
1959
+               break;
1960 102 dgisselq
+       case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
1961
+       case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
1962
+       case INSN:
1963
+               zip_debug_print(pfx, lvl, "(INSN");
1964
+               /*
1965
+               { const rtx_insn *tmp_rtx;
1966
+               for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
1967
+                       zip_debug_rtx_1(tmp_rtx, lvl+1);
1968
+               }}
1969
+               */
1970
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
1971
+               zip_debug_print(pfx, lvl, ")");
1972 117 dgisselq
+               debug_rtx(x);
1973 102 dgisselq
+               break;
1974
+       case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
1975 111 dgisselq
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
1976
+               zip_debug_print(pfx, lvl, ")");
1977
+               /*
1978 102 dgisselq
+               if (JUMP_LABEL(x)) {
1979 111 dgisselq
+                       if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
1980
+                               char    buf[64];
1981
+                               sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
1982
+                               zip_debug_print(pfx, lvl+1, buf);
1983
+                       } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
1984
+                               char    buf[64];
1985
+                               sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
1986
+                               zip_debug_print(pfx, lvl+1, buf);
1987
+                       } else
1988
+                       zip_debug_print(pfx, lvl+1, "(w/Label))");
1989 102 dgisselq
+               } else
1990 111 dgisselq
+                       zip_debug_print(pfx, lvl+1, "(NO label))");
1991
+               debug_rtx(x);
1992
+               */
1993 102 dgisselq
+               break;
1994
+       case CALL:
1995
+               zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
1996
+               zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
1997
+               zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
1998
+               zip_debug_print(pfx, lvl, ")");
1999
+               break;
2000
+       case CALL_INSN: zip_debug_print(pfx, lvl, "(CALL-INSN");
2001
+               debug_rtx(x);
2002
+               break;
2003
+       case BARRIER: zip_debug_print(pfx, lvl, "(BARRIER)"); break;
2004
+       case RETURN: zip_debug_print(pfx, lvl, "(RETURN)"); break;
2005
+       case NOTE:
2006
+               {       char buf[128];
2007
+                       sprintf(buf, "(NOTE %s)", GET_REG_NOTE_NAME(GET_MODE(x)));
2008
+                       zip_debug_print(pfx, lvl, buf);
2009
+               }break;
2010
+       case COND_EXEC: zip_debug_print(pfx, lvl, "(COND_EXEC)");
2011
+               debug_rtx(x);
2012
+               break;
2013
+       case ASM_INPUT: zip_debug_print(pfx, lvl, "(ASM INPUT)"); break;
2014
+       case ASM_OPERANDS: zip_debug_print(pfx, lvl, "(ASM OPERANDS)"); break;
2015
+       case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
2016
+       case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
2017
+       case CODE_LABEL:
2018
+               {
2019
+                       char    buf[64];
2020 111 dgisselq
+                       sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
2021 102 dgisselq
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
2022
+               } break;
2023
+       case SET:
2024
+               zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
2025 117 dgisselq
+               zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
2026
+               zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
2027 102 dgisselq
+               zip_debug_print(pfx, lvl, ")");
2028 117 dgisselq
+               debug_rtx(x);
2029 102 dgisselq
+               break;
2030 122 dgisselq
+       case REG: {
2031 127 dgisselq
+               char buf[25], mstr[4];
2032
+               mstr[0] = '\0';
2033
+               if (GET_MODE(x) == SImode)
2034
+                       strcpy(mstr, ":SI");
2035
+               else if (GET_MODE(x) == DImode)
2036
+                       strcpy(mstr, ":DI");
2037
+               else if (GET_MODE(x) == VOIDmode)
2038
+                       strcpy(mstr, ":V");
2039 102 dgisselq
+               if (REGNO(x) == zip_PC)
2040 127 dgisselq
+                       sprintf(buf, "(PC%s)", mstr);
2041 102 dgisselq
+               else if (REGNO(x) == zip_CC)
2042 127 dgisselq
+                       sprintf(buf, "(CC%s)", mstr);
2043 102 dgisselq
+               else if (REGNO(x) == zip_SP)
2044 127 dgisselq
+                       sprintf(buf, "(SP%s)", mstr);
2045 102 dgisselq
+               else if (REGNO(x) == zip_FP)
2046 127 dgisselq
+                       sprintf(buf, "(REG%s FP)", mstr);
2047 102 dgisselq
+               else if (REGNO(x) == zip_GOT)
2048 127 dgisselq
+                       sprintf(buf, "(REG%s GBL)", mstr);
2049 102 dgisselq
+               else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
2050 127 dgisselq
+                       sprintf(buf, "(REG%s RTN-VL)", mstr);
2051 102 dgisselq
+               else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
2052 127 dgisselq
+                       sprintf(buf, "(REG%s RTN-AD)", mstr);
2053 122 dgisselq
+               else
2054 127 dgisselq
+                       sprintf(buf, "(REG%s %d)", mstr, REGNO(x));
2055
+               if (mstr[0])
2056
+                       zip_debug_print(pfx, lvl, buf);
2057
+               else
2058
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
2059 102 dgisselq
+               } break;
2060
+       case IF_THEN_ELSE: // 51
2061
+               zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
2062
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2063
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2064
+               zip_debug_rtx_1(pfx, XEXP(x,2),lvl+1);
2065
+               zip_debug_print(pfx, lvl, ")");
2066
+               break;
2067
+       case PC:
2068
+               zip_debug_print(pfx, lvl, "(PC)");
2069
+               break;
2070
+       case CC0:
2071
+               zip_debug_print(pfx, lvl, "(CC0)");
2072
+               break;
2073
+       case COMPARE:
2074 127 dgisselq
+               zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x));
2075 102 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2076
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2077
+               zip_debug_print(pfx, lvl, ")");
2078
+               break;
2079 111 dgisselq
+       case CONST:
2080
+               zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
2081
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2082
+               zip_debug_print(pfx, lvl, ")");
2083
+               break;
2084 102 dgisselq
+       case CONST_INT:
2085
+               { char buf[25];
2086
+               if (GET_MODE(x)==SImode)
2087 111 dgisselq
+                       sprintf(buf, "(CONST_INT:SI %ld)", INTVAL(x));
2088 102 dgisselq
+               else if (GET_MODE(x)==VOIDmode)
2089 111 dgisselq
+                       sprintf(buf, "(CONST_INT:V %ld)", INTVAL(x));
2090 102 dgisselq
+               else
2091 111 dgisselq
+                       sprintf(buf, "(CONST_INT:? %ld)", INTVAL(x));
2092 102 dgisselq
+               zip_debug_print(pfx, lvl, buf);
2093
+               } break;
2094
+       case LABEL_REF:
2095 122 dgisselq
+               { char buf[256];
2096 111 dgisselq
+               sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
2097
+               zip_debug_print(pfx, lvl, buf);
2098
+               }
2099 102 dgisselq
+               break;
2100
+       case SYMBOL_REF:
2101
+               {
2102
+                       char buf[64];
2103
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
2104
+                       // fprintf(file, "%s", XSTR(x,0));
2105
+                       zip_debug_print(pfx, lvl, buf);
2106
+               }
2107
+               break;
2108
+       case MEM:
2109
+               zip_debug_print_m(pfx, lvl, "(MEM", GET_MODE(x));
2110
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2111
+               zip_debug_print(pfx, lvl, ")");
2112
+               break;
2113
+       /*
2114
+       case VALUE:
2115
+               {
2116
+                       char buf[64];
2117
+                       sprintf(buf, "(VALUE: %d)", INTVAL(XEXP,0));
2118
+                       zip_debug_print_m(pfx, lvl, "buf", GET_MODE(x));
2119
+               }
2120
+               break;
2121
+       */
2122
+       case PLUS:
2123
+               zip_debug_print_m(pfx, lvl, "(PLUS", GET_MODE(x));
2124
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2125
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2126
+               zip_debug_print(pfx, lvl, ")");
2127
+               break;
2128
+       case MINUS:
2129
+               zip_debug_print_m(pfx, lvl, "(MINUS", GET_MODE(x));
2130
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2131
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2132
+               zip_debug_print(pfx, lvl, ")");
2133
+               break;
2134
+       case AND:
2135
+               zip_debug_print_m(pfx, lvl, "(AND", GET_MODE(x));
2136
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2137
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2138
+               zip_debug_print(pfx, lvl, ")");
2139
+               break;
2140
+       case IOR:
2141
+               zip_debug_print_m(pfx, lvl, "(OR", GET_MODE(x));
2142
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2143
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2144
+               zip_debug_print(pfx, lvl, ")");
2145
+               break;
2146
+       case XOR:
2147
+               zip_debug_print_m(pfx, lvl, "(XOR", GET_MODE(x));
2148
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2149
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2150
+               zip_debug_print(pfx, lvl, ")");
2151
+               break;
2152
+       case MULT:
2153
+               zip_debug_print_m(pfx, lvl, "(MULT", GET_MODE(x));
2154
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2155
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2156
+               zip_debug_print(pfx, lvl, ")");
2157
+               break;
2158
+       case EQ:        //
2159
+               zip_debug_print_m(pfx, lvl, "(EQ", GET_MODE(x));
2160
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2161
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2162
+               zip_debug_print(pfx, lvl, ")");
2163
+               break;
2164
+       case NE:        //
2165
+               zip_debug_print_m(pfx, lvl, "(NE", GET_MODE(x));
2166
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2167
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2168
+               zip_debug_print(pfx, lvl, ")");
2169
+               break;
2170
+       case GE:        //
2171
+               zip_debug_print_m(pfx, lvl, "(GE", GET_MODE(x));
2172
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2173
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2174
+               zip_debug_print(pfx, lvl, ")");
2175
+               break;
2176
+       case GT:        //
2177
+               zip_debug_print_m(pfx, lvl, "(GT", GET_MODE(x));
2178
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2179
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2180
+               zip_debug_print(pfx, lvl, ")");
2181
+               break;
2182
+       case LE:        //
2183
+               zip_debug_print_m(pfx, lvl, "(LE", GET_MODE(x));
2184
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2185
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2186
+               zip_debug_print(pfx, lvl, ")");
2187
+               break;
2188
+       case LT:        //
2189
+               zip_debug_print_m(pfx, lvl, "(LT", GET_MODE(x));
2190
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2191
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2192
+               zip_debug_print(pfx, lvl, ")");
2193
+               break;
2194
+       case GEU:       //
2195
+               zip_debug_print_m(pfx, lvl, "(GEU", GET_MODE(x));
2196
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2197
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2198
+               zip_debug_print(pfx, lvl, ")");
2199
+               break;
2200
+       case GTU:       //
2201
+               zip_debug_print_m(pfx, lvl, "(GTU", GET_MODE(x));
2202
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2203
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2204
+               zip_debug_print(pfx, lvl, ")");
2205
+               break;
2206
+       case LEU:       //
2207
+               zip_debug_print_m(pfx, lvl, "(LEU", GET_MODE(x));
2208
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2209
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2210
+               zip_debug_print(pfx, lvl, ")");
2211
+               break;
2212
+       case LTU:       //
2213
+               zip_debug_print_m(pfx, lvl, "(LTU", GET_MODE(x));
2214
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2215
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2216
+               zip_debug_print(pfx, lvl, ")");
2217
+               break;
2218
+       case SCRATCH:   //
2219
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
2220
+               break;
2221
+       case SUBREG:
2222
+               { char buf[25];
2223 111 dgisselq
+               if (REG_P(XEXP(x,0))) {
2224
+                       sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
2225
+                               SUBREG_BYTE(x));
2226
+                       zip_debug_print(pfx, lvl, buf);
2227
+               } else if (MEM_P(XEXP(x,0))) {
2228
+                       sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
2229
+                       zip_debug_print(pfx, lvl, buf);
2230
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2231
+                       zip_debug_print(pfx, lvl, ")");
2232
+               } else {
2233
+                       sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
2234
+                       zip_debug_print(pfx, lvl, buf);
2235
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2236
+                       zip_debug_print(pfx, lvl, ")");
2237
+               }}
2238
+               break;
2239 127 dgisselq
+       case ASHIFT:
2240
+               zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x));
2241
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2242
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2243
+               zip_debug_print(pfx, lvl, ")");
2244
+               break;
2245
+       case ASHIFTRT:
2246
+               zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x));
2247
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2248
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2249
+               zip_debug_print(pfx, lvl, ")");
2250
+               break;
2251
+       case LSHIFTRT:
2252
+               zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
2253
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2254
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2255
+               zip_debug_print(pfx, lvl, ")");
2256
+               break;
2257 102 dgisselq
+       default:
2258 111 dgisselq
+               { char buf[128];
2259 102 dgisselq
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
2260
+               zip_debug_print(pfx, lvl, buf);
2261
+               debug_rtx(x);
2262
+               } break;
2263
+       }
2264
+}
2265
+
2266
+void
2267
+zip_debug_rtx_pfx(const char *pfx, const_rtx x) {
2268
+       zip_debug_rtx_1(pfx, x, 0);
2269
+}
2270
+
2271
+void
2272
+zip_debug_rtx(const_rtx x) {
2273
+       zip_debug_rtx_pfx("", x);
2274
+}
2275
+
2276
+void
2277
+zip_debug_insn(rtx_insn *insn ATTRIBUTE_UNUSED) {
2278
+}
2279
+
2280
+void
2281
+zip_debug_bb(basic_block bb) {
2282
+       rtx_insn        *insn;
2283
+
2284
+       fprintf(stderr, "************ BASIC-BLOCK ***************\n");
2285
+       FOR_BB_INSNS(bb, insn)
2286
+       {
2287
+               zip_debug_rtx(insn);
2288
+       }
2289
+}
2290
+
2291
+
2292
+static bool
2293 122 dgisselq
+zip_legitimate_opb(rtx x, bool strict)
2294 102 dgisselq
+{
2295 103 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2296 102 dgisselq
+
2297 111 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
2298 102 dgisselq
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
2299
+
2300
+       if (NULL_RTX == x)
2301
+               return false;
2302 122 dgisselq
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
2303
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
2304 102 dgisselq
+               return false;
2305 122 dgisselq
+       } else if ((strict)&&(REG_P(x))) {
2306
+               if (REGNO(x)<zip_CC) {
2307
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
2308
+                       return true;
2309
+               } else return false;
2310
+       } else if (register_operand(x, GET_MODE(x))) {
2311
+               // This also handles subregs
2312
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
2313
+               return true;
2314 111 dgisselq
+       } else if ((CONST_INT_P(x))
2315
+               &&(INTVAL(x) >= zip_min_opb_imm)
2316
+               &&(INTVAL(x) <= zip_max_opb_imm)) {
2317 122 dgisselq
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", zip_min_opb_imm, INTVAL(x), zip_max_opb_imm);
2318 111 dgisselq
+               return true;
2319 122 dgisselq
+       // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
2320
+               // return true;
2321 102 dgisselq
+       } else if (GET_CODE(x) == PLUS) {
2322
+               // Is it a valid register?
2323 122 dgisselq
+               if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) {
2324 111 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
2325 102 dgisselq
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
2326
+                       return false;
2327 122 dgisselq
+               } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
2328 102 dgisselq
+                       return false;
2329
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
2330
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
2331
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
2332 111 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
2333 103 dgisselq
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
2334
+                               // gcc_unreachable();
2335 102 dgisselq
+                       return true;
2336
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
2337 122 dgisselq
+                       ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL)
2338 102 dgisselq
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
2339
+                       // While we can technically support this, the problem
2340
+                       // is that the symbol address could be anywhere, and we
2341
+                       // have no way of recovering if it's outside of our
2342
+                       // 14 allowable bits.
2343 111 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
2344 102 dgisselq
+                       return false;
2345
+               }
2346
+       }
2347
+
2348 111 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
2349 102 dgisselq
+       if (dbg) zip_debug_rtx(x);
2350
+       return false;
2351
+}
2352
+
2353
+static bool
2354
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
2355
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2356
+
2357
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
2358
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
2359
+
2360 122 dgisselq
+       if (!zip_legitimate_opb(x, strict))
2361 102 dgisselq
+               return false;
2362 122 dgisselq
+       else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) {
2363
+               if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset)
2364
+                       ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) {
2365 124 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %ld\n", INTVAL(XEXP(x,1)));
2366 102 dgisselq
+                       return false;
2367
+               }
2368
+       }
2369
+
2370 122 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n");
2371 102 dgisselq
+       if (dbg) zip_debug_rtx(x);
2372 122 dgisselq
+       return true;
2373 102 dgisselq
+}
2374
+
2375
+int
2376
+zip_pd_mov_operand(rtx op)
2377
+{
2378
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2379
+
2380
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
2381
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
2382
+}
2383
+
2384
+int
2385 111 dgisselq
+zip_pd_mvimm_operand(rtx op)
2386
+{
2387
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2388
+
2389
+       if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
2390
+       if (!CONST_INT_P(op))
2391
+               return false;
2392
+       if (INTVAL(op) > zip_max_mov_offset)
2393
+               return false;
2394
+       if (INTVAL(op) < zip_min_mov_offset)
2395
+               return false;
2396
+       return true;
2397
+}
2398
+
2399
+int
2400
+zip_pd_imm_operand(rtx op)
2401
+{
2402
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2403
+
2404
+       if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
2405
+       if (!CONST_INT_P(op))
2406
+               return false;
2407
+       if (INTVAL(op) > zip_max_anchor_offset)
2408
+               return false;
2409
+       if (INTVAL(op) < zip_min_anchor_offset)
2410
+               return false;
2411
+       return true;
2412
+}
2413
+
2414
+int
2415 102 dgisselq
+zip_address_operand(rtx op)
2416
+{
2417
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2418
+
2419
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
2420 111 dgisselq
+       if ((REG_P(op))&&(REGNO(op)==zip_CC))
2421
+               return false;
2422
+       else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
2423
+                       &&(REGNO(XEXP(op,0))==zip_CC))
2424
+               return false;
2425
+       else
2426
+               return zip_legitimate_opb(op, !can_create_pseudo_p());
2427 102 dgisselq
+}
2428
+
2429
+int
2430 111 dgisselq
+zip_pd_opb_operand(rtx op)
2431 102 dgisselq
+{
2432
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2433
+
2434 111 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
2435 122 dgisselq
+       return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
2436 102 dgisselq
+}
2437
+
2438
+int
2439
+zip_ct_address_operand(rtx op)
2440
+{
2441
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2442
+
2443
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
2444 111 dgisselq
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
2445 102 dgisselq
+}
2446
+
2447
+int
2448
+zip_const_address_operand(rtx x) {
2449
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2450
+
2451
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
2452
+       if (dbg) zip_debug_rtx(x);
2453 127 dgisselq
+       if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
2454
+               fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
2455 102 dgisselq
+               return false;
2456 127 dgisselq
+       }
2457 102 dgisselq
+       if ((GET_CODE(x) == LABEL_REF)
2458
+                       ||(GET_CODE(x) == CODE_LABEL)
2459
+                       ||(GET_CODE(x) == SYMBOL_REF)) {
2460 127 dgisselq
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n");
2461 102 dgisselq
+               return true;
2462
+       } else if (CONST_INT_P(x)) {
2463 127 dgisselq
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n");
2464 102 dgisselq
+               return true;
2465
+       } else if (GET_CODE(x) == PLUS) {
2466
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
2467
+               return ((zip_const_address_operand(XEXP(x,0)))
2468
+                       &&(CONST_INT_P(XEXP(x,1))));
2469
+       } else if (GET_CODE(x) == MINUS) {
2470
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(MINUS)\n");
2471
+               return ((zip_const_address_operand(XEXP(x,0)))
2472
+                       &&(zip_const_address_operand(XEXP(x,1))));
2473
+       }
2474
+
2475
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> No\n");
2476
+       if (dbg) zip_debug_rtx(x);
2477
+       return false;
2478
+}
2479
+
2480
+int
2481
+zip_ct_const_address_operand(rtx x) {
2482
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2483
+
2484
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
2485
+       return zip_const_address_operand(x);
2486
+}
2487
+
2488
+int
2489
+zip_pd_const_address_operand(rtx x) {
2490
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2491
+
2492
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
2493
+       return zip_const_address_operand(x);
2494
+}
2495
+
2496
+
2497
+static bool
2498
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
2499
+{
2500
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2501
+
2502
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
2503
+       if (dbg) zip_debug_rtx(x);
2504
+
2505
+       // Only insist the register be a valid register if strict is true
2506 111 dgisselq
+       if (zip_legitimate_opb(x, strict))
2507 102 dgisselq
+               return true;
2508 111 dgisselq
+       // else if (zip_const_address_operand(x))
2509
+               // return true;
2510 102 dgisselq
+
2511
+       return false;
2512
+}
2513
+
2514 111 dgisselq
+static rtx
2515
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
2516
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2517
+
2518
+       if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
2519
+       if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
2520
+               return x;
2521
+
2522
+       if (GET_CODE(x)==PLUS) {
2523
+               if (!REG_P(XEXP(x,0)))
2524
+                       XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
2525
+               if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
2526
+                       &&(!CONST_INT_P(XEXP(x,1))))
2527
+                       x = force_reg(GET_MODE(x),x);
2528
+       } else if (MEM_P(x))
2529
+               x = force_reg(GET_MODE(x),x);
2530
+
2531
+       if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
2532
+       return x;
2533
+}
2534
+
2535 102 dgisselq
+void
2536
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
2537
+{
2538
+       assemble_name(stream, name);
2539
+       fprintf(stream, "\t.equ ");
2540
+       assemble_name(stream, value);
2541
+       fputc('\n', stream);
2542
+}
2543
+
2544 111 dgisselq
+#define        USE_SUBREG
2545
+#ifdef USE_SUBREG
2546
+#define        SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
2547
+#define        SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
2548
+#else
2549
+#define        SREG_P(RTX)     false
2550
+#define        SMEM_P(RTX)     false
2551
+#endif
2552 102 dgisselq
+
2553
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
2554 103 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2555 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
2556
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
2557
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
2558
+       switch(GET_CODE(condition)) {
2559
+       case EQ:        return "LDI\t0,%0\n\tLDILO.Z\t1,%0";
2560
+       case NE:        return "LDI\t0,%0\n\tLDILO.NZ\t1,%0";
2561
+       case LT:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0";
2562
+       case GT:        return "LDI\t0,%0\n\tLDILO.GT\t1,%0";
2563
+       case LE:        return "LDI\t1,%0\n\tLDILO.GT\t0,%0";
2564
+       case GE:        return "LDI\t0,%0\n\tLDILO.GE\t1,%0";
2565
+       case LTU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0";
2566
+       case GTU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0";
2567
+       case LEU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0";
2568
+       case GEU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0";
2569
+       default:
2570
+               zip_debug_rtx(condition);
2571
+               internal_error("CSTORE Unsupported condition");
2572
+               return NULL;
2573
+       }
2574
+}
2575
+
2576 127 dgisselq
+/*
2577 102 dgisselq
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
2578
+       static char     result[64] = "";
2579
+       switch(condition) {
2580
+               //
2581
+               // Result already exists in the iffalse register
2582
+               // Can't change it.  Therefore, on the
2583
+               // condition ... move true register to the
2584
+               // destination
2585
+               //
2586
+               case EQ:        sprintf(result, "%s.Z\t%%%d,%%0", op, opno); break;
2587
+               case NE:        sprintf(result, "%s.NZ\t%%%d,%%0", op, opno); break;
2588
+               case LT:        sprintf(result, "%s.LT\t%%%d,%%0", op, opno); break;
2589
+               case GT:        sprintf(result, "%s.GT\t%%%d,%%0", op, opno); break;
2590
+               // .LE doesn't exist on Zip CPU--turn this into two instructions
2591
+               case LE:        sprintf(result, "%s.LT\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
2592
+               case GE:        sprintf(result, "%s.GE\t%%%d,%%0", op, opno); break;
2593
+               case LTU:       sprintf(result, "%s.C\t%%%d,%%0", op, opno); break;
2594
+               //
2595
+               // .GTU doesn't exist on the Zip CPU either. We also note that
2596
+               // .C will never be set on an equal condition.  Therefore, we
2597
+               // turn this into a XOR.NZ 2,CC, which will set the .C condition
2598
+               // as long as .Z wasn't true.  We then undo this when we're
2599
+               // done.  This is possible since none of these instructions
2600
+               // (LDI/MOV/Lod conditional, nor Xor conditional) will ever set
2601
+               // the condition codes.
2602
+               //
2603
+               // This is obviously not very optimal.  Avoid this by all means
2604
+               // if you can
2605
+               case GTU:       sprintf(result, "XOR.NZ\t2,CC\n%s.C\t%%%d,%%0\n\tXOR.NZ\t2,CC", op, opno); break;
2606
+               // .LEU doesn't exist on Zip CPU either--turn this into another
2607
+               // two instructions
2608
+               case LEU:       sprintf(result, "%s.C\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
2609
+               //
2610
+               // .GEU doesn't exist on Zip CPU.  Implementing it her is
2611
+               // painful.  We can change the condition codes to make it so,
2612
+               // but the instruction requires the condition codes not be
2613
+               // changed.  Hence, we must change them back if we do so.
2614
+               //
2615
+               // .C will be set on less than but not equal.  Hence !.C will
2616
+               // be true on greater than or equal.
2617
+               case GEU:       sprintf(result, "XOR\t2,CC\n%s.C\t%%%d,%%0\n\tXOR\t2,CC", op, opno); break;
2618
+               default:
2619
+                       internal_error("MOVSICC(BINARY) Unsupported condition");
2620
+                       return NULL;
2621
+       } return result;
2622
+}
2623 127 dgisselq
+*/
2624 102 dgisselq
+
2625 127 dgisselq
+bool
2626
+zip_supported_condition(int c) {
2627
+       switch(c) {
2628
+       case NE: case LT: case EQ: case GT: case GE: case LTU:
2629
+               return true;
2630
+               break;
2631
+       default:
2632
+               break;
2633
+       } return false;
2634 102 dgisselq
+}
2635
+
2636 127 dgisselq
+bool
2637
+zip_signed_comparison(int c) {
2638
+       switch(c) {
2639
+       case NE: case LT: case EQ: case GT: case GE:
2640
+               return true;
2641
+       default:
2642
+               break;
2643
+       } return false;
2644
+}
2645
+
2646
+void
2647
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
2648 103 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2649 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
2650
+       if (dbg) zip_debug_rtx_pfx("DST", dst);
2651
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
2652
+       if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
2653
+       if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
2654 127 dgisselq
+
2655
+       // Start with the condition
2656
+       rtx     cmpa = XEXP(condition,0), cmpb=XEXP(condition,1);
2657
+       enum rtx_code   cmpcode = GET_CODE(condition);
2658
+
2659
+       //; Do we need to swap or adjust the condition?
2660
+       if (zip_supported_condition((int)cmpcode)) {
2661
+               // Keep everything as is
2662
+       } else if ((zip_supported_condition(reverse_condition(cmpcode)))
2663
+                       &&(!MEM_P(iffalse))) {
2664
+               rtx tem = iffalse;
2665
+               iffalse = iftrue;
2666
+               iftrue = tem;
2667
+
2668
+               cmpcode = reverse_condition(cmpcode);
2669
+       } else if ((zip_supported_condition((int)swap_condition(cmpcode)))
2670
+               &&((REG_P(cmpb))||(can_create_pseudo_p()))) {
2671
+               rtx tem = cmpa;
2672
+               cmpa = cmpb;
2673
+               cmpa = tem;
2674
+               cmpcode = swap_condition(cmpcode);
2675
+
2676
+               if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode))
2677
+                       &&(REG_P(XEXP(cmpa,0)))
2678
+                       &&(CONST_INT_P(XEXP(cmpa,1)))
2679
+                       &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) {
2680
+
2681
+                       // If we were doing CMP x(Rb),Ra
2682
+                       // and we just changed it to CMP Ra,x(Rb)
2683
+                       // adjust it to CMP -x(Ra),Rb
2684
+                       cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1)));
2685
+                       cmpa = XEXP(cmpa,0);
2686
+               } else if (!REG_P(cmpa)) {
2687
+                       // Otherwise, if we had anything else in Rb other than
2688
+                       // a register ... such as a constant, then load it into
2689
+                       // a register before comparing it.  So
2690
+                       //      CMP x,Ra
2691
+                       // became
2692
+                       //      CMP Ra,x
2693
+                       // now becomes
2694
+                       //      LDI x,Rt
2695
+                       //      CMP Ra,Rt
2696
+                       // (We already tested for can_create_pseudo_p() above..)
2697
+                       tem = gen_reg_rtx(SImode);
2698
+                       emit_move_insn(tem, cmpa);
2699
+                       cmpa = tem;
2700 102 dgisselq
+               }
2701 127 dgisselq
+       } else {
2702
+               // Here's our last chance.
2703
+               // This will adjust for less than equal types of stuff
2704
+               int     cod = (int)cmpcode;
2705
+               zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false);
2706
+               cmpcode = (enum rtx_code)cod;
2707 102 dgisselq
+       }
2708
+
2709 127 dgisselq
+       gcc_assert(zip_supported_condition((int)cmpcode));
2710
+
2711
+       //; Always do the default move
2712
+       emit_move_insn(dst, iffalse);
2713
+
2714
+       rtx     cc_rtx = gen_rtx_REG(CCmode, zip_CC);
2715
+
2716
+       //; Now let's get our comparison right
2717
+       emit_insn(gen_rtx_SET(VOIDmode, cc_rtx,
2718
+               gen_rtx_COMPARE(CCmode, cmpa, cmpb)));
2719
+
2720
+       //; Finally, let's load the value on true
2721
+       emit_insn(gen_movsicc_bare(dst,
2722
+                       gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX),
2723
+                       iftrue, dst));
2724 102 dgisselq
+}
2725
+
2726
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
2727
+       // We know upon entry that REG_P(dst) must be true
2728
+       if (!REG_P(dst))
2729
+               internal_error("%s","ADDSICC into something other than register");
2730
+       if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
2731
+               switch (GET_CODE(condition)) {
2732
+               case EQ: return "ADD.Z\t%3,%0";
2733
+               case NE: return "ADD.NZ\t%3,%0";
2734
+               case LT: return "ADD.LT\t%3,%0";
2735
+               case GT: return "ADD.GT\t%3,%0";
2736
+               case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
2737
+               case GE: return "ADD.GE\t%3,%0";
2738
+               case LTU: return "ADD.C\t%3,%0";
2739
+               case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
2740
+               case GEU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tXOR\t2,CC";
2741
+               // Can do a GEU comparison, and then undo on the Zero condition
2742
+               case GTU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tSUB.Z\t%3,%0\n\tXOR\t2,CC";
2743
+               default:
2744
+                       internal_error("%s", "Zip/No usable addsi expansion");
2745
+                       break;
2746
+               }
2747
+       } else {
2748
+               // MOV A+REG,REG
2749
+               switch (GET_CODE(condition)) {
2750
+               case EQ: return "MOV.Z\t%3+%2,%0";
2751
+               case NE: return "MOV.NZ\t%3+%2,%0";
2752
+               case LT: return "MOV.LT\t%3+%2,%0";
2753
+               case GT: return "MOV.GT\t%3+%2,%0";
2754
+               case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
2755
+               case GE: return "MOV.GE\t%3+%2,%0";
2756
+               case LTU: return "MOV.C\t%3+%2,%0";
2757
+               case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
2758
+               case GEU: return "XOR\t2,CC\n\tMOV.C\t%3+%2,%0\n\tXOR\t2,CC";
2759
+               // Can do a GEU comparison, and then undo on the Zero condition
2760
+               // EXCEPT: with a move instruction, what's there to undo?  We
2761
+               // just clobbered our register!
2762
+               // case GTU: return "XOR\t2,CC\n\tMOV.C\t%3,%0\n\tSUB.Z\t%3,%0XOR\t2,CC";
2763
+               default:
2764
+                       internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
2765
+                       break;
2766
+               }
2767
+       }
2768
+
2769
+       return "BREAK";
2770
+}
2771
+
2772 103 dgisselq
+static int     zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
2773 102 dgisselq
+       int     rv = 14;
2774
+       if ((mode == DImode)||(mode == DFmode))
2775
+               rv += 2;
2776
+       return rv;
2777
+}
2778
+
2779 103 dgisselq
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
2780 117 dgisselq
+static bool    zip_cannot_modify_jumps_p(void) {
2781
+       // Let's try their suggested approach, keeping us from modifying jumps
2782
+       // after reload.  This should also allow our peephole2 optimizations
2783
+       // to adjust things back to what they need to be if necessary.
2784
+       return (reload_completed || reload_in_progress);
2785
+}
2786 122 dgisselq
+
2787
+rtx_insn       *zip_ifcvt_info;
2788
+
2789
+void
2790
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
2791
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2792
+       if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
2793
+       if (*true_expr) switch(GET_CODE(*true_expr)) {
2794
+               case LE:
2795
+               case GTU:
2796
+               case GEU:
2797
+               case LEU:
2798
+                       if (dbg) fprintf(stderr, "TRUE, missing expr\n");
2799
+                       if (dbg) zip_debug_rtx(*true_expr);
2800
+                       *true_expr = NULL_RTX;
2801
+                       break;
2802
+               default: // LT, GT, GTE, LTU, NE, EQ
2803
+                       break;
2804
+       }
2805
+
2806
+       if (*false_expr) switch(GET_CODE(*false_expr)) {
2807
+               case LE:
2808
+               case GTU:
2809
+               case GEU:
2810
+               case LEU:
2811
+                       if (dbg) fprintf(stderr, "FALSE, missing expr\n");
2812
+                       if (dbg) zip_debug_rtx(*false_expr);
2813
+                       *false_expr = NULL_RTX;
2814
+               default:
2815
+                       break;
2816
+       }
2817
+       if ((dbg)&&((!*true_expr)||(!*false_expr)))
2818
+               fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n");
2819
+}
2820
+
2821
+void
2822
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
2823
+/*
2824
+       fprintf(stderr, "IFCVT -- CANCEL\n");
2825
+       zip_ifcvt_info = NULL;
2826
+*/
2827
+}
2828
+
2829
+void
2830
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
2831
+/*
2832
+rtx_insn *insn;
2833
+FOR_BB_INSNS(ceinfo->test_bb, insn)
2834
+       fprintf(stderr, "IFCVT -- FINAL\n");
2835
+       zip_debug_rtx_pfx("FINAL-TEST-BB", insn);
2836
+       zip_ifcvt_info = NULL;
2837
+*/
2838
+}
2839
+
2840
+void
2841
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
2842
+/*
2843
+       zip_ifcvt_info = NULL;
2844
+       rtx_insn *insn, *ifinsn = NULL;
2845
+       FOR_BB_INSNS(ceinfo->test_bb, insn) {
2846
+               rtx     p;
2847
+               p = single_set(insn);
2848
+               if (!p) continue;
2849
+               if (SET_DEST(p)==pc_rtx) {
2850
+                       ifinsn = insn;
2851
+               }
2852
+               if (!REG_P(SET_DEST(p)))
2853
+                       continue;
2854
+               if (GET_MODE(SET_DEST(p))!=CCmode)
2855
+                       continue;
2856
+               if (REGNO(SET_DEST(p))!=zip_CC)
2857
+                       continue;
2858
+               zip_ifcvt_info = insn;
2859
+       }
2860
+
2861
+       if (zip_ifcvt_info)
2862
+               zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info);
2863
+       if (ifinsn)
2864
+               zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
2865
+*/
2866
+}
2867
+
2868 127 dgisselq
+int    zip_insn_sets_cc(rtx_insn *insn) {
2869
+       return (get_attr_ccresult(insn)==CCRESULT_SET);
2870
+}
2871
+
2872
+int    zip_is_conditional(rtx_insn *insn) {
2873
+       return (get_attr_conditional(insn)==CONDITIONAL_YES);
2874
+}
2875 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
2876
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
2877 127 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-04-21 16:49:43.785679680 -0400
2878
@@ -0,0 +1,4058 @@
2879 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
2880
+//
2881
+// Filename:   gcc/config/zip/zip.h
2882
+//
2883
+// Project:    Zip CPU backend for the GNU Compiler Collection
2884
+//
2885
+// Purpose:
2886
+//
2887
+// Creator:    Dan Gisselquist, Ph.D.
2888
+//             Gisselquist Technology, LLC
2889
+//
2890
+////////////////////////////////////////////////////////////////////////////////
2891
+//
2892
+// Copyright (C) 2016, Gisselquist Technology, LLC
2893
+//
2894
+// This program is free software (firmware): you can redistribute it and/or
2895
+// modify it under the terms of  the GNU General Public License as published
2896
+// by the Free Software Foundation, either version 3 of the License, or (at
2897
+// your option) any later version.
2898
+//
2899
+// This program is distributed in the hope that it will be useful, but WITHOUT
2900
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
2901
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
2902
+// for more details.
2903
+//
2904
+// You should have received a copy of the GNU General Public License along
2905
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
2906
+// target there if the PDF file isn't present.)  If not, see
2907
+// <http://www.gnu.org/licenses/> for a copy.
2908
+//
2909
+// License:    GPL, v3, as defined and found on www.gnu.org,
2910
+//             http://www.gnu.org/licenses/gpl.html
2911
+//
2912
+//
2913
+////////////////////////////////////////////////////////////////////////////////
2914
+#ifndef        GCC_ZIP_H
2915
+#define        GCC_ZIP_H
2916
+
2917
+
2918
+//
2919
+//
2920 127 dgisselq
+// Zip CPU configuration defines
2921 102 dgisselq
+//
2922
+//
2923
+#define        ZIP_USER        0        // Assume we are in supervisor mode
2924
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
2925
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
2926
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
2927
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
2928
+#define        ZIP_VLIW        1       // Assume we have the VLIW feature
2929
+#define        ZIP_ATOMIC      ((ZIP_PIPELINED)&&(ZIP_VLIW))
2930
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
2931
+#define        ZIP_HAS_DI      1
2932 127 dgisselq
+// Should we use the peephole optimizations?
2933
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
2934 102 dgisselq
+
2935
+// Zip has 16 registers in each user mode.
2936
+//     Register 15 is the program counter (PC)
2937
+//     Register 14 is the condition codes (CC)
2938
+//     Register 13 is the stack pointer   (SP)
2939
+//     Register 12 (may be) the Global Offset Table pointer (GOT)
2940
+//     Register  0 (may be) the return address pointer
2941
+// Registers 16-31 may only be used in supervisor mode.
2942
+#define        is_ZIP_GENERAL_REG(REGNO)       ((REGNO)<13)
2943
+#define        is_ZIP_REG(REGNO)               ((REGNO)<16)
2944
+
2945 103 dgisselq
+// #define     zip_FP_PSEUDO   16
2946
+#define        zip_PC          15
2947
+#define        zip_CC          14
2948
+#define        zip_SP          13
2949
+#define        zip_FP          12
2950
+#define        zip_GOT         11
2951
+#define        zip_AP          10
2952
+#define        zip_R1          1
2953
+#define        zip_R0          0
2954 102 dgisselq
+
2955
+#define        ZIP_FIRST_ARG_REGNO     1
2956
+#define        ZIP_LAST_ARG_REGNO      5
2957 111 dgisselq
+#define        NUM_ARG_REGS            (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
2958
+#define        MAX_PARM_REGS           (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
2959 102 dgisselq
+
2960
+/* The overall framework of an assembler file */
2961
+
2962
+#define        ASM_COMMENT_START       ";"
2963
+#define        ASM_APP_ON              ""
2964
+#define        ASM_APP_OFF             ""
2965
+
2966
+#define        FILE_ASM_OP             "\t.file\n"
2967
+
2968
+/* Output and Generation of Labels */
2969
+#define        GLOBAL_ASM_OP           "\t.global\t"
2970
+
2971
+#undef BITS_PER_UNIT
2972
+#define        BITS_PER_UNIT   (32)
2973
+
2974
+/* Assembler Commands for Alignment */
2975
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
2976 127 dgisselq
+       { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
2977 102 dgisselq
+
2978
+
2979
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
2980
+ * for an instruction operand X. */
2981
+#define        PRINT_OPERAND(STREAM, X, CODE)  zip_print_operand(STREAM, X, CODE)
2982
+#define        PRINT_OPERAND_ADDRESS(STREAM, X) zip_print_operand_address(STREAM, X)
2983
+
2984
+/* Passing arguments in registers */
2985
+#define        FUNCTION_VALUE_REGNO_P(REGNO)   ((REGNO)==zip_R1)
2986
+
2987
+/* Define how to find the value returned by a function.  VALTYPE is the data
2988
+ * type of the value (as a tree).  If the precise function being called is known
2989
+ * FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */
2990
+#define        FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG(TYPE_MODE(VALTYPE), zip_R1)
2991
+
2992
+/* Define how to find the value returned by a library function assuming the
2993
+ * value has mode MODE.
2994
+ */
2995
+#define        LIBCALL_VALUE(MODE)     gen_rtx_REG(MODE, zip_R1)
2996
+
2997
+
2998
+/* STACK AND CALLING */
2999
+
3000
+
3001
+/* Define this macro as a C expression that is nonzero for registers that are
3002
+ * used by the epilogue or the return pattern.  The stack and frame pointer
3003
+ * registers are already assumed to be used as needed.
3004
+ */
3005
+#define        EPILOGUE_USES(R)        (R == RETURN_ADDRESS_REGNUM)
3006
+
3007
+
3008
+/* The best alignment to use in cases where we have a choice. */
3009 127 dgisselq
+#define        FASTEST_ALIGNMENT       BITS_PER_WORD
3010 102 dgisselq
+
3011
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
3012
+ * largest integer machine mode that should actually be used.  All integer
3013
+ * machine modes of this size and smaller can be used for structures and unions
3014
+ * with the appropriate sizes.  If this macro is undefined,
3015
+ * GET_MODE_BITSIZE(DImode) is assumed.
3016
+ *
3017
+ * ZipCPU -- The default looks good enough for us.
3018
+ */
3019
+
3020
+/* Generate Code for Profiling
3021
+ */
3022
+#define        FUNCTION_PROFILER(FILE,LABELNO)         (abort(), 0)
3023
+
3024
+
3025
+/* A C expression which is nonzero if register number NUM is suitable for use
3026
+ * as an index register in operand addresses.
3027
+ */
3028
+#define        REGNO_OK_FOR_INDEX_P(NUM)       0
3029
+
3030
+
3031
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
3032
+ * (an RTX) is a legitimate memory address on the target machine for a memory
3033
+ * operand of mode MODE.
3034
+ */
3035 111 dgisselq
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
3036
+// DRIVER_SELF_SPECS
3037
+// OPTION_DEFAULT_SPECS
3038
+// CPP_SPEC
3039
+// CPLUSPLUS_CPP_SPEC
3040
+// CC1_SPEC
3041
+// CC1PLUS_SPEC
3042
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
3043
+ * to pass to the assembler.  It can also specify how to translate options you
3044
+ * give to GCC into options for GCC to pass to the assembler.  See the file
3045
+ * 'sun3.h' for an example of this.
3046
+ *
3047
+ * Do not define thismacro if it does not need to do anything.
3048
+ */
3049
+// #undef      ASM_SPEC
3050
+// ASM_FINAL_SPEC
3051
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
3052
+
3053
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
3054
+ * to pass to the linker.  It can also specify how to translate options you give
3055
+ * to GCC into options for GCC to pass to the linker.
3056
+ *
3057
+ * Do not define this macro if it does not need to do anything.
3058
+ */
3059
+
3060
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC.  The
3061
+ * difference between the two is that LIB_SPEC is used at the end of the
3062
+ * command given to the linker.
3063
+ *
3064
+ * If this macro is not defined, a default is provided that loads the standard
3065
+ * C library from the usual place.  See 'gcc.c'.
3066
+ */
3067
+#undef LIB_SPEC
3068
+// #define     LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
3069
+#define        LIB_SPEC        ""
3070
+
3071
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
3072
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
3073
+ * line.  This constant is placed both before and after the value of LIB_SPEC.
3074
+ *
3075
+ * If this macro is not defined, the GCC driver provides a default that passes
3076
+ * the string '-lgcc' to the linker.
3077
+ */
3078
+#undef LIBGCC_SPEC
3079
+#define        LIBGCC_SPEC     ""
3080
+
3081
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
3082
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
3083
+ * modified to refer to different versions of 'libgcc.a' depending on the
3084
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
3085
+ * and '-shared-libgcc'.  On targets where these modifications are
3086
+ * inappropriate, define REAL_LIBGCC_SPEC instead.  REAL_LIBGCC_SPEC tells the
3087
+ * driver how to place a reference to 'libgcc' on the link command line, but
3088
+ * unlike LIBGCC_SPEC, it is used unmodified.
3089
+ */
3090
+#define        REAL_LIBGCC_SPEC        ""
3091
+
3092
+// USE_LD_AS_NEEDED
3093
+// LINK_EH_SPEC
3094
+
3095
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
3096
+ * difference between the two is that STARTFILE_SPEC is used at the very
3097
+ * beginning of the command given to the linker.
3098
+ *
3099
+ * If this macro is not defined, a default is provided that loads the standard
3100
+ * C startup file from the usual place.  See 'gcc.c'
3101
+ */
3102
+#undef STARTFILE_SPEC
3103
+#define        STARTFILE_SPEC  ""
3104
+
3105
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
3106
+ * difference between the two is that ENDFILE_SPEC is used at the very end
3107
+ * of the command given to the linker.
3108
+ *
3109
+ * Do not define this macro if it does not do anything.
3110
+ */
3111
+// #undef      ENDFILE_SPEC
3112
+// #define     ENDFILE_SPEC    ""
3113
+
3114
+// THREAD_MODEL_SPEC
3115
+// SYSROOT_SUFFIX_SPEC
3116
+// SYSROOT_HEADERS_SUFFIX_SPEC
3117
+// EXTRA_SPECS
3118
+// LINK_LIBGCC_SPECIAL_1
3119
+// LINK_GCC_C_SEQUENCE_SPEC
3120
+// LINK_COMMAND_SPEC
3121
+// TARGET_ALWAYS_STRIP_DOTDOT
3122
+// MULTILIB_DEFAULTS
3123
+// RELATIVE_PREFIX_NOT_LINKDIR
3124
+// MD_EXEC_PREFIX
3125
+// STANDARD_STARTFILE_PREFIX
3126
+// STANDARD_STARTFILE_PREFIX_1
3127
+// STANDARD_STARTFILE_PREFIX_2
3128
+// MD_STARTFILE_PREFIX
3129
+// MD_STARTFILE_PREFIX_1
3130
+// INIT_ENVIRONMENT
3131
+// LOCAL_INCLUDE_DIR
3132
+#undef LOCAL_INCLUDE_DIR
3133
+
3134
+// NATIVE_SYSTEM_HEADER_COMPONENT
3135
+// INCLUDE_DEFAULTS
3136
+
3137 102 dgisselq
+/* 17.03 Run-time Target Specification */
3138
+
3139
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
3140
+ * code that defines built-in preprocessor macros and assertions for the target
3141
+ * CPU, using the functions builtin_define, builtin_define_std, and
3142
+ * builtin_assert.  When the front end calls this macro it provides a trailing
3143
+ * semicolon, and since it has finished command line option proccessing your
3144
+ * code can use those results freely.
3145
+ *
3146
+ * ZipCPU --- We should probably capture in this macro what capabilities the
3147
+ * command line parameters we've been given indicate that our CPU has.  That
3148
+ * way, code can be adjusted depending upon the CPU's capabilities.
3149
+ */
3150
+#define        TARGET_CPU_CPP_BUILTINS()                       \
3151
+       { builtin_define("__ZIPCPU__");                 \
3152
+       if (ZIP_FPU) builtin_define("__ZIPFPU__");      \
3153
+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \
3154
+       }
3155
+       // If (zip_param_has_fpu)  builtin_define("__ZIPFPU__");
3156
+       // If (zip_param_has_div)  builtin_define("__ZIPDIV__");
3157
+       // If (zip_param_has_mpy)  builtin_define("__ZIPMPY__");
3158
+       // If (zip_param_has_lock) builtin_define("__ZIPLOCK__");
3159
+       // If (zip_param_supervisor) builtin_define("__ZIPUREGS__");
3160
+       // If (we support int64s) builtin_define("___int64_t_defined");
3161
+
3162
+/* TARGET_OS_CPP_BUILTINS() ... Similarly to TARGET_CPU_CPP_BUILTINS but this
3163
+ * macro is optional and is used for the target operating system instead.
3164
+ */
3165
+
3166
+/* Option macros: (we need to define these eventually ... )
3167
+ *
3168
+ *     TARGET_HANDLE_OPTION
3169
+ *     TARGET_HANDLE_C_OPTION
3170
+ *     TARGET_OBJ_CONSTRUCT_STRING_OBJECT
3171
+ *     TARGET_OBJ_DECLARE_UNRESOLVED_CLASS_REFERENCE
3172
+ *     TARGET_OBJ_DECLARE_CLASS_DEFINITION
3173
+ *     TARGET_STRING_OBJECT_REF_TYPE_P
3174
+ *     TARGET_CHECK_STRING_OBJECT_FORMAT_ARG
3175
+ *     TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE(VOID)
3176
+ *     C_COMMON_OVERRIDE_OTPTIONS
3177
+ *     TARGET_OPTION_OPTIMIZATION_TABLE
3178
+ *     TARGET_OPTION_INIT_STRUCT
3179
+ *     TARGET_OPTION_DEFAULT_PARAMS
3180
+ */
3181
+
3182
+/* SWITCHABLE_TARGET
3183
+ *
3184
+ * Zip CPU doesn't need this, so it defaults to zero.  No need to change it
3185
+ * here.
3186
+ */
3187
+
3188
+/* TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(VOID) ... Returns true if the
3189
+ * target supports IEEE 754 floating-point exceptions and rounding modes, false
3190
+ * otherwise.  This is intended to relate to the float and double types, but not
3191
+ * necessarily "long double".  By default, returns true if the adddf3
3192
+ * instruction pattern is available and false otherwise, on the assumption that
3193
+ * hardware floating point supports exceptions and rounding modes but software
3194
+ * floating point does not.
3195
+ *
3196
+ * ZipCPU floating point is barely going to be functional, I doubt it will
3197
+ * support all of these bells and whistles when full functionality is even
3198
+ * achieved.  Therefore, we won't support these modes.  However, we can't just
3199
+ * set this to zero, so let's come back to this.
3200
+ */
3201
+// #warning "Wrong answer encoded to date"
3202 103 dgisselq
+// #undef      TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
3203 102 dgisselq
+// #define     TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0
3204
+
3205
+/* 17.04 Defining data structures for per-function information */
3206
+
3207
+/* INIT_EXPANDERS ... Macro called to initialize any target specific
3208
+ * information.  This macro is called once per function, before generation of
3209
+ * any RTL has begun.  The intention is to allow the initialization of the
3210
+ * function pointer init_machine_status.
3211
+ */
3212
+// #warning "I may need to define this to handle function return addresses ..."
3213
+
3214
+/* 17.05 Storage Layout */
3215
+
3216
+/* Storage Layout */
3217
+#define        BITS_BIG_ENDIAN         0        // MSB has highest number
3218
+#define        BYTES_BIG_ENDIAN        1       // 1 if MSB is lowest number
3219
+#define        WORDS_BIG_ENDIAN        1       // 1 if MSW is lowest number
3220
+#define        FLOAT_WORDS_BIG_ENDIAN  1
3221
+#define        BITS_PER_WORD           32
3222
+// #define     MAX_BITS_PER_WORD       // defaults to BITS_PER_WORD
3223
+#define        UNITS_PER_WORD          1       // Storage units in a word, pwr of 2:1-8
3224
+#define        MIN_UNITS_PER_WORD      1       // Default is UNITS_PER_WORD
3225
+/* POINTER_SIZE ... Width of a pointer in bits.  You must specify a value no
3226
+ * wider than the width of Pmode.  If it is not equal to the width of Pmode,
3227
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
3228
+ * default is BITS_PER_WORD.
3229
+ *
3230
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
3231
+ */
3232
+#define        POINTER_SIZE            32      // Ptr width in bits
3233
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
3234
+ * should be extended from ptr_mode to either Pmode or word_mode.  It is greater
3235
+ * than zero if pointers should be zero-extended, zero if they should be sign
3236
+ * extended, and negative if some other conversion is needed.  In the last case,
3237
+ * the extension is done by the target's ptr_extend instruction.
3238
+ *
3239
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
3240
+ * the same width.
3241
+ *
3242
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
3243
+ * number of bits as SImode.  Therefore, one might wish to convert between the
3244
+ * two.  Hence, we specify how we would do that here.
3245
+ */
3246 127 dgisselq
+#define        POINTERS_EXTEND_UNSIGNED        1
3247 102 dgisselq
+
3248
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
3249
+ * object whose type is type and which has he specified mode and signedness is
3250
+ * to be stored in a register.  This macro is only called when type is a scalar
3251
+ * type.
3252
+ *
3253
+ * On most RISC machines, which only have operations that operate on a full
3254
+ * register, define this macro to set m to word_mode if m is an integer mode
3255
+ * narrower than BITS_PER_WORD.  In most cases, only integer modes should be
3256
+ * widened because wider precision floating-point operations are usually more
3257
+ * expensive than their narrower counterparts.
3258
+ *
3259
+ * For most machines, the macro definition does not change unsigndep.  However,
3260
+ * some machines, have instructions that preferentially handle either signed or
3261
+ * unsigned quantities of certain modes.  For example, on the DEC Alpha, 32-bit
3262
+ * loads from memory and 32-bit add instructions sign-extend the result to
3263
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
3264
+ * is more efficient.
3265
+ *
3266
+ * Do not define this macro if it would never modify m.
3267
+ *
3268
+ * ZipCPU --- We need to always (if possible) promote everything to SImode where
3269
+ * we can handle things.  HImode and QImode just don't make sense on this CPU.
3270
+ */
3271
+#define        PROMOTE_MODE(M,U,T)     if ((GET_MODE_CLASS(M)==MODE_INT)&&(GET_MODE_SIZE(M)<2)) (M)=SImode;
3272
+
3273
+// TARGET_PROMOTE_FUNCTION_MODE
3274
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
3275
+ * stack, in bits.  All stack parameters receive at least this much alignment
3276
+ * regardless of data type.  On most machines, this is the same as the size of
3277
+ * an integer.
3278
+ */
3279
+#define        PARM_BOUNDARY   32
3280
+
3281
+/* STACK_BOUNDARY ... Define this macro to the minimum alignment enforced by
3282
+ * hardware for the stack pointer on this machine.  The definition is a C
3283
+ * expression for the desired alignment (measured in bits).  This value is used
3284
+ * as a default if PREFERRED_STACK_BOUNDARY is not defined.  On most machines,
3285
+ * this should be the same as PARM_BOUNDARY.
3286
+ */
3287
+#define        STACK_BOUNDARY  PARM_BOUNDARY
3288
+
3289
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */
3290 127 dgisselq
+#define        PREFERRED_STACK_BOUNDARY        STACK_BOUNDARY
3291 102 dgisselq
+
3292 127 dgisselq
+/* INCOMING_STACK_BOUNDARY ... Define this macro if the incoming stack boundary
3293
+ * may be different from PREFERRED_STACK_BOUNDARY.  This macro must evaluate
3294
+ * to a value equal to or larger than STACK_BOUNDARY.
3295 102 dgisselq
+ */
3296 127 dgisselq
+#define        INCOMING_STACK_BOUNDARY STACK_BOUNDARY
3297 102 dgisselq
+
3298
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits.
3299
+ */
3300
+#define        FUNCTION_BOUNDARY       32
3301
+
3302
+/* BIGGEST_ALIGNMENT ... Biggest alignment that any data type can require on
3303
+ * this machine, in bits.  Note that this is not the biggest alignment that is
3304
+ * supported, just the biggest alignment that, when violated, may cause a fault.
3305
+ */
3306
+#define BIGGEST_ALIGNMENT      32
3307
+
3308 127 dgisselq
+/* MALLOC_ABI_ALIGNMENT
3309
+ */
3310
+
3311
+/* ATTRIBUTE_ALIGNED_VALUE
3312
+ */
3313
+
3314 102 dgisselq
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be
3315
+ * given to an object that can be referenced in one operation, without
3316
+ * disturbing any nearby object.  Normally, this is BITS_PER_UNIT, but may be
3317
+ * larger on machines that don't have byte or halfword store operations.
3318
+ */
3319
+#define        MINIMUM_ATOMIC_ALIGNMENT        BITS_PER_UNIT
3320
+
3321 127 dgisselq
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
3322
+ * field can require on this machine, in bits.  If defined, this overrides
3323
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
3324
+ * alignment has been set by the __attribute__((aligned(n))) construct.
3325
+ */
3326
+#define        BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT
3327
+
3328
+/* ADJUST_FIELD_ALIGN
3329
+ */
3330
+#define        ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
3331
+
3332
+/* MAX_STACK_ALIGNMENT
3333
+ */
3334
+#define        MAX_STACK_ALIGNMENT     BITS_PER_WORD
3335
+
3336
+/* MAX_OFILE_ALIGNMENT
3337
+ */
3338
+
3339
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
3340
+ * the alignment for a variable in the static store.  TYPE is the data type, and
3341
+ * BASIC-ALIGN is the alignment that the object would ordinarily have.  The
3342
+ * value of this macro is used instead of that alignment to align the object.
3343
+ *
3344
+ * If this macro is not defined, then BASIC-ALIGN is used.
3345
+ *
3346
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is
3347
+ * broken.  So we define it to be our fastest alignment, or 32-bits.
3348
+ */
3349
+#define        DATA_ALIGNMENT(TYPE, ALIGN)     BITS_PER_WORD
3350
+
3351
+
3352
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
3353
+ */
3354
+
3355
+/* CONSTANT_ALIGNMENT(CONST, BASIC-ALIGN) ... If defined, a C expression to
3356
+ * compute the alignment given to a constant that is being placed in memory.
3357
+ * CONST is the constant and BASIC-ALIGN is the alignment that the object
3358
+ * would ordinarily have.  The value of this macro is used instead of that
3359
+ * alignment to align the object.
3360
+ *
3361
+ * If this macro is not defined, then BASIC-ALIGN is used.
3362
+ *
3363
+ * ZipCPU -- in hindsiht, if this macro is not defined then the compiler is
3364
+ * broken.  We'll define it as above.
3365
+ *
3366
+ */
3367
+#define        CONSTANT_ALIGNMENT(EXP, ALIGN)  BITS_PER_WORD
3368
+
3369
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
3370
+ */
3371
+#define        LOCAL_ALIGNMENT(TYP,ALIGN)      BITS_PER_WORD
3372
+
3373
+/* TARGET_VECTOR_ALIGNMENT
3374
+ */
3375
+
3376
+/* STACK_SLOT_ALIGNMENT
3377
+ */
3378
+#define        STACK_SLOT_ALIGNMENT(T,M,B)     BITS_PER_WORD
3379
+
3380
+/* LOCAL_DECL_ALIGNMEN(DECL)
3381
+ */
3382
+#define        LOCAL_DECL_ALIGNMENT(DECL)      BITS_PER_WORD
3383
+
3384
+/* MINIMUM_ALIGNMENT
3385
+ */
3386
+#define        MINIMUM_ALIGNMENT(EXP,MOD,ALIGN)        BITS_PER_WORD
3387
+
3388
+/* EMPTY_FIELD_BOUNDARY
3389
+ * Alignment of field after 'int : 0' in a structure.
3390
+ */
3391
+#define        EMPTY_FIELD_BOUNDARY    BITS_PER_WORD
3392
+
3393
+/* STRUCTURE_SIE_BOUNDARY
3394
+ * ZipCPU -- Every structures size must be a multiple of 32-bits.
3395
+ */
3396
+#define        STRUCTURE_SIZE_BOUNDARY BITS_PER_WORD
3397
+
3398 102 dgisselq
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
3399
+ * fail to work when given unaligned data.  If instructions will merely go
3400
+ * slower in that case, define this macro as 0.
3401 125 dgisselq
+ *
3402
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
3403
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
3404
+ * is easy, then there really are no instructions that will ever fail.
3405 102 dgisselq
+ */
3406 125 dgisselq
+#define        STRICT_ALIGNMENT        0
3407 102 dgisselq
+
3408 127 dgisselq
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
3409
+ * other C compilers handle alignment of bit-fields and the structures that
3410
+ * contain them.
3411
+ *
3412
+ * The behavior is that the type written for a named bit-field (int, short, or
3413
+ * other integer type) imposes an alignment for the entire structure, as if the
3414
+ * structure really did contain an ordinary field of that type.  In addition,
3415
+ * the bit-field is placed within the structure so that it would fit within
3416
+ * such a field, not crossing a boundary for it.
3417
+ *
3418
+ * Thus, no most machines, a named bit-field whose type is written as int would
3419
+ * not cross a four-byte boundary, and would force four-byte alignment for the
3420
+ * whole structure.  (The alignment used may not be four bytes; it is controlled
3421
+ * by other alignment parameters.)
3422
+ *
3423
+ * An unnamed bit-field will not affect the alignment of the containing
3424
+ * structure.
3425
+ *
3426
+ * If the macro is defined, its definition should be a C expression, a non
3427
+ * zero value for the expression enables this behavior.
3428
+ * Look at the fundamental type that is used for a bit-field and use that to
3429
+ * impose alignment on the enclosing structure.  struct s{int a:8}; should
3430
+ * have the same alignment as 'int', not 'char'.
3431
+ */
3432
+#undef PCC_BITFIELD_TYPE_MATTERS
3433
+#define        PCC_BITFIELD_TYPE_MATTERS       0
3434
+
3435 102 dgisselq
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the
3436
+ * largest integer machine mode that should actually be used.  All integer
3437
+ * machine modes of this size or smaller can be used for structures and unions
3438
+ * with the appropriate sizes.  If this macro is undefined,
3439
+ * GET_MODE_BITSIZE(DImode) is assumed.
3440
+ *
3441
+ * ZipCPU ... Get_MOD_BITSIZE(DImode) will be 64, and this is really not the
3442
+ * size on bits of the largest integer machine mode.  However, that's the case
3443
+ * with most DI implementations: A long is two words, spliced together.  We'd
3444
+ * like to support that eventually, but we need to get there.  Hence, let's use
3445
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
3446
+ */
3447
+#if (ZIP_HAS_DI != 0)
3448
+#define        MAX_FIXED_MODE_SIZE     64
3449
+#else
3450
+#define        MAX_FIXED_MODE_SIZE     32
3451
+#endif
3452
+
3453
+
3454
+/* 17.06 Layout of Source Language Data Types */
3455
+
3456
+#undef CHAR_TYPE_SIZE
3457
+#undef SHORT_TYPE_SIZE
3458
+#undef INT_TYPE_SIZE
3459
+#undef LONG_TYPE_SIZE
3460
+#undef LONG_LONG_TYPE_SIZE
3461
+//
3462
+#define        CHAR_TYPE_SIZE  32
3463
+#define        SHORT_TYPE_SIZE 32
3464
+#define        INT_TYPE_SIZE   32
3465
+#define        LONG_TYPE_SIZE  32
3466
+#define        LONG_LONG_TYPE_SIZE     64
3467
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
3468
+#undef FLOAT_TYPE_SIZE
3469
+#undef DOUBLE_TYPE_SIZE
3470
+#undef LONG_DOUBLE_TYPE_SIZE
3471
+#define        FLOAT_TYPE_SIZE         32
3472
+#define        DOUBLE_TYPE_SIZE        FLOAT_TYPE_SIZE // Zip CPU doesn't support dbls
3473
+#define        LONG_DOUBLE_TYPE_SIZE   64      // This'll need to be done via emulation
3474
+// SHORT_FRAC_TYPE_SIZE
3475
+// LONG_FFRACT_TYPE_SIZE
3476
+// LONG_LONG_FRACT_TIME_SIZE
3477
+#undef SHORT_ACCUM_TYPE_SIZE
3478
+#undef ACCUM_TYPE_SIZE
3479
+#undef LONG_ACCUM_TYPE_SIZE
3480
+#define        SHORT_ACCUM_TYPE_SIZE   SHORT_TYPE_SIZE
3481
+#define        ACCUM_TYPE_SIZE         INT_TYPE_SIZE
3482
+#define        LONG_ACCUM_TYPE_SIZE    LONG_TYPE_SIZE
3483
+
3484
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
3485
+ * hook and should be defined if that hook is overriden to be true.  It causes
3486
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
3487
+ * rather than the default __.  A port which uses this macro should also arrange
3488
+ * to use t-gnu-prefix in the libgcc config.host.
3489
+ *
3490
+ * ZipCPU -- I see no reason to define and therefore change this behavior.
3491
+ */
3492
+
3493
+/* TARGET_FLT_EVAL_METHOD ... A C expression for the value for FLT_EVAL_METHOD
3494
+ * in float.h,, assuming, if applicable, that the floating-point control word
3495
+ * is in its default state.  If you do not define this macro the value of
3496
+ * FLT_EVAL_METHOD will be zero.
3497
+ *
3498
+ * ZipCPU --- ???
3499
+ */
3500
+
3501
+/* WIDEST_HARDWARE_FP_SIZE ... A C expression for the size in bits of the widest
3502
+ * floating-point format supported by the hardware.  If you define this macro,
3503
+ * you must specify a value less than or equal to the value of LONG_DOUBLE_...
3504
+ * If you do not define this macro, the value of LONG_DOUBLE_TYPE_SIZE is the
3505
+ * default.
3506
+ *
3507
+ * ZipCPU supports 32-bit IEEE floats--IF THE SUPPORT IS COMPILED IN!  This
3508
+ * really needs to be determined, then, based upon a compile time parameter
3509
+ * where the one compiling the code states whether or not the H/W even has
3510
+ * floating point support.
3511
+ *
3512
+ * For now, we'll assume it does--but once we implement GCC parameters, we'll
3513
+ * need to change this.
3514
+ */
3515
+#undef WIDEST_HARDWARE_FP_SIZE
3516
+// #warning "Definition needs to change if no FPU present"
3517
+#define        WIDEST_HARDWARE_FP_SIZE FLOAT_TYPE_SIZE
3518
+
3519
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
3520
+ * whether the type char should be signed or unsigned by default.  The user
3521
+ * can always override this default with the options -fsigned-char and
3522
+ * -funsigned-char.
3523
+ *
3524
+ * ZipCPU--let's go with the default behavior.
3525
+ */
3526
+#define        DEFAULT_SIGNED_CHAR     1
3527
+
3528
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
3529 103 dgisselq
+ * the compiler should give an enum type only as many bytes as it takes to
3530 102 dgisselq
+ * represent the range of possible values of that type.  It should return
3531
+ * false if all enum types should be allocated like int.
3532
+ *
3533
+ * The default is to return false.  This is what the ZipCPU needs, so we won't
3534
+ * override it.
3535
+ */
3536
+
3537
+/* SIZE_TYPE ... A C expression for a string describing the name of the data
3538
+ * type to use for size values.  The typedef name size_t is defined using the
3539
+ * contents of the string.
3540
+ *
3541
+ * If you don't define this macro, the default is "long unsigned int".  Since
3542
+ * on the ZipCPU this is a 32-bit number, and all ZipCPU values are 32-bits,
3543
+ * the default seems perfect for us.
3544
+ */
3545
+#define        SIZE_TYPE       "unsigned int"
3546
+
3547
+/* SIZETYPE ... GCC defines internal types () for expressions dealing with size.
3548
+ * This macro is a C expression for a string describing the name of the data
3549
+ * type from which the precision of sizetype is extracted.  The string has the
3550
+ * same restrictions as SIZE_TYPE string.  If you don't define this macro, the
3551
+ * default is SIZE_TYPE --- which seems good enough for us.
3552
+ */
3553
+
3554
+/* PTRDIFF_TYPE ... A C expression for a string describing the name of the data
3555 127 dgisselq
+ * type to use for the result of subtracting two pointers.  The typedef name
3556 102 dgisselq
+ * ptrdiff_t is defined using the contents of the string.  See SIZE_TYPE for
3557
+ * more information.
3558
+ *
3559
+ * The default is "long int" which for the ZipCPU is 32-bits---still good enough
3560
+ * for us.
3561
+ */
3562
+#define        PTRDIFF_TYPE    "int"
3563
+
3564
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
3565
+ * type to use for wide characters.  The typedef name wchar_t is defined using
3566
+ * the contents of  the string.  If you don't define this macro, the default is
3567
+ * 'int'--good enough for ZipCPU.
3568
+ */
3569
+
3570
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
3571
+ * wide characters.  This is used in cpp, which cannot make use of WCHAR_TYPE.
3572
+ */
3573
+#undef WCHAR_TYPE_SIZE
3574
+#define        WCHAR_TYPE_SIZE 32
3575
+
3576
+/* WINT_TYPE ... A C expression for a string describing the name of the data
3577
+ * type to use for wide characters passed to printf and returned from getwc.
3578
+ * The typedef name wint_t is defined using the contents of the string.  See
3579
+ *
3580 103 dgisselq
+ * ZipCPU -- If you don't define this macro, the default is "unsigned int"--also
3581
+ * best for us again.
3582 102 dgisselq
+ */
3583
+
3584
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
3585
+ * data type that can represent any value of any standard or extended signed
3586
+ * integer type.  The typedef name intmax_t is defined using the contents of
3587
+ * the string.
3588
+ *
3589
+ * If you don't define this macro, the default is the first of "int", "long int"
3590
+ * or "long long int" that has as much precision as "long long int".
3591
+ */
3592
+
3593
+/* UINTMAX_TYPE ... same as INTMAX_TYPE, but for unsigned
3594
+ */
3595
+
3596
+#undef SIG_ATOMIC_TYPE
3597
+#if (ZIP_ATOMIC != 0)
3598
+#define        SIG_ATOMIC_TYPE "int"
3599
+#else
3600
+#define        SIG_ATOMIC_TYPE NULL    // We have no atomic types, but registers
3601
+#endif
3602
+#undef INT8_TYPE
3603
+#define        INT8_TYPE               NULL    // We have no 8-bit integer type
3604
+#undef INT16_TYPE
3605
+#define        INT16_TYPE              NULL
3606
+#undef INT32_TYPE
3607
+#define        INT32_TYPE              "int"
3608
+#undef UINT8_TYPE
3609
+#define        UINT8_TYPE              NULL
3610
+#undef UINT16_TYPE
3611
+#define        UINT16_TYPE             NULL
3612
+#undef UINT32_TYPE
3613
+#define        UINT32_TYPE             "unsigned int"
3614
+#undef INT_LEAST8_TYPE
3615
+#define        INT_LEAST8_TYPE         "int"
3616
+#undef INT_LEAST16_TYPE
3617
+#define        INT_LEAST16_TYPE        "int"
3618
+#undef INT_LEAST32_TYPE
3619
+#define        INT_LEAST32_TYPE        "int"
3620
+#undef UINT_LEAST8_TYPE
3621
+#define        UINT_LEAST8_TYPE        "unsigned int"
3622
+#undef UINT_LEAST16_TYPE
3623
+#define        UINT_LEAST16_TYPE       "unsigned int"
3624
+#undef UINT_LEAST32_TYPE
3625
+#define        UINT_LEAST32_TYPE       "unsigned int"
3626
+#undef INT_FAST8_TYPE
3627
+#define        INT_FAST8_TYPE          "int"
3628
+#undef INT_FAST16_TYPE
3629
+#define        INT_FAST16_TYPE         "int"
3630
+#undef INT_FAST32_TYPE
3631
+#define        INT_FAST32_TYPE         "int"
3632
+#undef UINT_FAST8_TYPE
3633
+#define        UINT_FAST8_TYPE         "unsigned int"
3634
+#undef UINT_FAST16_TYPE
3635
+#define        UINT_FAST16_TYPE        "unsigned int"
3636
+#undef UINT_FAST32_TYPE
3637
+#define        UINT_FAST32_TYPE        "unsigned int"
3638
+#undef INTPTR_TYPE
3639
+#define        INTPTR_TYPE             "unsigned int"
3640
+#undef UINTPTR_TYPE
3641
+#define        UINTPTR_TYPE            "unsigned int"
3642
+
3643
+#undef INT64_TYPE
3644
+#undef UINT64_TYPE
3645
+#undef INT_LEAST64_TYPE
3646
+#undef UINT_LEAST64_TYPE
3647
+#undef INT_FAST64_TYPE
3648
+#undef UINT_FAST64_TYPE
3649
+
3650
+#if (ZIP_HAS_DI != 0)
3651
+#define        INT64_TYPE              "long int"
3652
+#define        UINT64_TYPE             "long unsigned int"
3653
+#define        INT_LEAST64_TYPE        "long int"
3654
+#define        UINT_LEAST64_TYPE       "long unsigned int"
3655
+#define        INT_FAST64_TYPE         "long int"
3656
+#define        UINT_FAST64_TYPE        "long unsigned int"
3657
+#else
3658
+#define        INT64_TYPE              NULL
3659
+#define        UINT64_TYPE             NULL
3660
+#define        INT_LEAST64_TYPE        NULL
3661
+#define        UINT_LEAST64_TYPE       NULL
3662
+#define        INT_FAST64_TYPE         NULL
3663
+#define        UINT_FAST64_TYPE        NULL
3664
+#endif
3665
+
3666
+#define        TARGET_PTRMEMFUNC_VBI_LOCATION  ptrmemfunc_vbit_in_pfn
3667
+
3668
+
3669
+/* 17.07 Register Usage / Register definitions */
3670
+
3671
+/* FIRST_PSEUDO_REGISTER ... Number of hardware registers known to the compiler.
3672
+ * They receive numbers 0 through FIRST_PSEUDO_REGISTER-1; thus the first
3673
+ * pseudo register's numbrer really is assigned the number
3674
+ * FIRST_PSEUDO_REGISTER.
3675
+ *
3676
+ * ZipCPU---There are 16 registers in the ZipCPU, numbered 0-15 with the CC
3677
+ * and PC register being numbered 14 and 15 respectively.  Therefore, the
3678
+ * compiler can take register number 16 and above and do whatever it wants
3679
+ * with it.
3680
+ */
3681
+#ifdef DEFINE_USER_REGS
3682 103 dgisselq
+#  define      FIRST_PSEUDO_REGISTER   32
3683 102 dgisselq
+#else
3684 103 dgisselq
+#  ifdef       zip_FP_PSEUDO
3685
+#    define    FIRST_PSEUDO_REGISTER   (zip_FP_PSEUDO+1)
3686
+#  else
3687
+#    define    FIRST_PSEUDO_REGISTER   16
3688
+#  endif
3689 102 dgisselq
+#endif
3690
+
3691
+/* FIXED_REGISTERS ... An initializer that says which registers are used for
3692
+ * fixed purposes all throughout the compiled code and are therefore not
3693
+ * available for general allocation.  These would include the stack pointer, the
3694
+ * frame pointer (except on machines where that can be used as a general
3695
+ * register when no frame pointer is needed), the program counter on machines
3696
+ * where that is considered one of the addressable registers, and any other
3697
+ * numbered register with a standard use.
3698
+ *
3699
+ * This information is expressed as a sequence of numbers, separated by commas,
3700
+ * and surrounded by braces.  The nth number is 1 if register n is fixed, 0
3701
+ * otherwise.
3702
+ *
3703
+ * For the Zip CPU, we have three fixed registers that are not available for
3704
+ * general allocation:
3705
+ *
3706
+ *     SP      The stack pointer
3707
+ *     CC      The condition codes and CPU state register
3708
+ *     PC      The program counter
3709
+ *
3710
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset
3711
+ * table pointer) are registers that we hope will not be so fixed.
3712
+ */
3713 127 dgisselq
+#ifdef DEFINE_USER_REGS
3714
+#  define      FIXED_REGISTERS         { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,   1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }
3715 103 dgisselq
+#else
3716 127 dgisselq
+#  ifdef       zip_FP_PSEUDO
3717
+#    define    FIXED_REGISTERS         { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1 }
3718
+#  else
3719
+#    define    FIXED_REGISTERS         { 0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1 }
3720
+#  endif
3721 103 dgisselq
+#endif
3722 102 dgisselq
+
3723
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register
3724
+ * that is clobbered (in general) by function calls as well as for fixed
3725
+ * registers.  This macro therefore identifies the registers that are not
3726
+ * available for general allocation of values that must live across function
3727
+ * calls.
3728
+ *
3729
+ * If a register has 0 in CALL_USED_REGISTERS, the compiler automatically saves
3730
+ * it on function entry and restores it on function exit, if the register is
3731
+ * used within the function.
3732
+ *
3733
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any
3734
+ * register above R5.
3735
+ */
3736 127 dgisselq
+#ifdef DEFINE_USER_REGS
3737
+#  define      CALL_USED_REGISTERS     { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,  1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }
3738 103 dgisselq
+#else
3739 127 dgisselq
+#  ifdef       zip_FP_PSEUDO
3740
+#    define    CALL_USED_REGISTERS     { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1 }
3741
+#  else
3742
+#    define    CALL_USED_REGISTERS     { 0,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1 }
3743
+#  endif
3744 103 dgisselq
+#endif
3745 102 dgisselq
+
3746
+/* CALL_REALLY_USED_REGISTERS ...  optional macro that, if not defined, defaults
3747
+ * to the value of CALL_USED_REGISTERS.
3748
+ */
3749
+
3750
+/* HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) ... A C expression that is nonzero
3751
+ * if it is not permissible to store a value of mode MODE in hard register REGNO
3752
+ * across a call without some part of it being clobbbered.  For most machines,
3753
+ * this macro need not be defined.  It is only required for machines that do
3754 103 dgisselq
+ * not preserve the entire contents of a register across a call.
3755 102 dgisselq
+ *
3756 127 dgisselq
+ * ZipCPU--Always preserves the entire contents of those registers that are
3757
+ * preserved across calls, so this shouldnt need to be defined.
3758 102 dgisselq
+ */
3759 127 dgisselq
+// #define     HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE)      (REGNO==0)
3760 102 dgisselq
+
3761
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally
3762
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and
3763
+ * reg_class_contents, to take into account any dependence of these register
3764
+ * sets on target flags.  The first three of these are of type char[]
3765
+ * (interpreted as Boolean vectors).  global_regs is a const char *[] and
3766
+ * reg_class_contents is a HARD_REG_SET.  Before the macro is called,
3767
+ * fixed_regs, call_used_regs, reg_class_contents, and reg_names have been
3768
+ * initialized from FIXED_REGISTERS, CALL_USED_REGISTERS, REG_CLASS_CONTENTS,
3769
+ * and REGISTER_NAMES, respectively.  global_regs has been cleared, and any
3770
+ * -ffixed-reg, -fcall-used-reg, and -fcall-saved-reg command options have been
3771
+ * applied.
3772
+ *
3773
+ * ZipCPU -- I may need to return and define this depending upon how FP and
3774
+ * GBL register allocation go.  But for now, we'll leave this at its default
3775
+ * value.
3776
+ */
3777
+// #warning "Revisit me after FP and GBL allocation"
3778
+
3779
+/* INCOMING_REGNO(out) ... Define this macro if the target machine has register
3780
+ * windows. ...
3781
+ *
3782
+ * Zip CPU has no register windows.
3783
+ */
3784
+
3785
+/* OUTGOING_REGNO ... same thing.
3786
+ */
3787
+
3788
+/* LOCAL_REGNO ... same thing.
3789
+ */
3790
+
3791
+/* PC_REGNUM ... If the program counter has a register number, define this as
3792
+ * that register number.  Otherwise do not define it.
3793
+ */
3794
+#define        PC_REGNUM       zip_PC
3795
+
3796
+
3797
+/* REG_ALLOC_ORDER ... If defined, an initializer for a vector of integers,
3798
+ * containing the number of hard registers in the order in which GCC should
3799
+ * prefer to use them (from most preferred to least.
3800
+ *
3801 103 dgisselq
+ * If this macro is not defined, registers are used lowest numbered first (all
3802 102 dgisselq
+ * else being equal).
3803
+ *
3804
+ * Since the default is the ZipCPU desired case, we won't define this here.
3805
+ */
3806
+
3807
+/* ADJUST_REG_ALLOC_ORDER ... on most machines it is not necessary to define
3808
+ * this macro, so we won't either.
3809
+ */
3810
+
3811
+/* HONOR_REG_ALLOC_ORDER ...
3812
+ */
3813
+
3814
+/* HONOR_REG_ALLOC_ORDER ... on most machines it is not necessary to define
3815
+ * this macro, so we won't either.
3816
+ */
3817
+
3818
+/* HARD_REGNO_NREGS(REGNO, MODE) ... A C expression for the number of
3819
+ * consecutive hard registers, starting at register number REGNO, required to
3820
+ * hold a value of mode MODE.
3821
+ *
3822
+ * On a machine where all registers are exactly one word, a suitable definition
3823
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
3824
+ *
3825
+ * On ZipCPU, we might do
3826
+ *     ((((MODE)==DImode)||((MODE)==DFmode))?2:1)
3827
+ * but I think the default (above) code should work as well.  Hence, let's stick
3828
+ * with the default, lest someone try to create larger modes (TImode, OImode,
3829
+ * XImode) and expect us to follow them properly some how.
3830
+ *
3831
+ * Okay, now in hind sight, we know that the default doesn't work for our
3832
+ * architecture, since GET_MODE_SIZE(SImode)=4, not 1.  Thus, let's rearrange
3833
+ * this expression to work in bits rather than in bytes and we'll know more
3834
+ * of what we are doing.
3835
+ */
3836
+#undef HARD_REGNO_NREGS
3837
+#define        HARD_REGNO_NREGS(REGNO, MODE)   ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
3838
+               / (UNITS_PER_WORD))
3839
+
3840
+/* HARD_REGNO_NREGS_HAS_PADDING(REGNO,MODE) ... A C expression that is nonzero
3841
+ * if a value of mode MODE, stored in memory, ends with padding that causes it
3842
+ * to take up more space than in registers starting at register number REGNO
3843
+ * (as determined by multiplying GCC's notion of the size of the register when
3844
+ * containing this mode by the number of registers returned by HARD_REGNO_NREGS)
3845
+ * By default this is zero.
3846
+ *
3847
+ * Zip CPU --- The default looks good enough to me.
3848
+ */
3849
+
3850
+/* HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE)
3851
+ *
3852
+ * ZipCPU ---
3853
+ */
3854
+
3855
+/* REGMODE_NATURAL_SIZE(MODE) -- Define this macro if the natural size of
3856
+ * registers that hold values of mode mode is not the word size.  It is a C
3857
+ * expression that should give the natural size in bytes for the specified mode.
3858
+ * It is used by the register allocator to try to optimize its results.
3859
+ *
3860
+ * ZipCPU ---
3861
+ */
3862
+// #define     REGMODE_NATURAL_SIZE(MODE)      (((MODE)==DImode)?2:1)
3863
+
3864
+/* HARD_REGNO_MODE_OK ... A C expression that is nonzero if it is permissible
3865 103 dgisselq
+ * to store a value of mode MODE in a hard register number REGNO (or in several
3866 102 dgisselq
+ * registers starting with that one).  For a machine where all registers are
3867
+ * equivalent, a suitable definition is '1'.  You need not include code to check
3868
+ * for the numbers of fixed registers, because the allocation mechanism
3869
+ * considered them to be always occupied.
3870
+ *
3871
+ * ZipCPU --- As long as you are already avoiding the fixed registers, the
3872
+ * suitable default definition mentioned above should be sufficient.
3873
+ */
3874
+#undef HARD_REGNO_MODE_OK
3875 103 dgisselq
+#define        HARD_REGNO_MODE_OK(R,M) (R<zip_CC)
3876 102 dgisselq
+
3877
+/* HARD_REGNO_RENAME_OK(FROM,TO) ... A C expression that is nonzero if it is
3878
+ * okay to rename a hard register FROM to another hard register TO.  One common
3879
+ * use of this macro is to prevernt renaming of a register to another register
3880
+ * that is not saved by a prologue in an interrupt handler.  The default is
3881
+ * always nonzero.
3882
+ *
3883
+ * ZipCPU --- The default looks good enough to us.
3884
+ */
3885
+#undef HARD_REGNO_RENAME_OK
3886
+#define        HARD_REGNO_RENAME_OK(FROM,TO)   ((is_ZIP_GENERAL_REG(FROM))&&(is_ZIP_GENERAL_REG(TO)))
3887
+
3888
+
3889
+/* MODES_TIABLE_P(M1, M2) ... A C expression that is nonzero if a value of mode
3890
+ * M1 is accessible in mode M2 without copying.
3891
+ *
3892
+ * ZipCPU --- well, that's true for us (although we support scant few modes) ...
3893
+ * so lets' set to one.
3894
+ */
3895
+#define        MODES_TIEABLE_P(M1,M2)  1
3896
+
3897
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
3898
+ * This target hook should return true if it is OK to use a hard register
3899
+ * REGNO has a scratch register in peephole2.  One common use of this macro is
3900
+ * to prevent using of a register that is not saved by a prologue in an
3901
+ * interrupt handler.  The default version of this hook always returns true.
3902
+ *
3903
+ * ZipCPU --- the default works for us as well.  If you are in an interrupt
3904
+ * context, you have an entirely new set of registers (the supervisor set), so
3905
+ * this is a non-issue.
3906
+ */
3907
+
3908
+/* AVOID_CCMODE_COPIES ... define this macro if the compiler should avoid
3909
+ * copies to/from CCmode register(s).  You should only define this macro if
3910
+ * support for copying to/from CCmode is incomplete.
3911
+ *
3912
+ * ZipCPU --- CCmode register copies work like any other, so we'll keep with the
3913
+ * default definition.
3914
+ */
3915
+
3916
+/* STACK_REGS ... Define this if the machine has any stack-like registers.
3917
+ *
3918
+ * Zip CPU has no stack-like registers, as their definition is different from
3919
+ * the ZipCPU stack pointer register.
3920
+ */
3921
+
3922 127 dgisselq
+// #define     ZIP_REG_BYTE_SIZE       1
3923 102 dgisselq
+
3924
+/* 17.08 Register Classes */
3925
+
3926
+/* enum reg_class ... An enumerate type that must be defined with all the
3927
+ * register class names as enumerated values.  NO_REGS must be first.  ALL_REGS
3928
+ * must be the last register class, followed by one more enumerated value,
3929
+ * LIM_REG_CLASSES, which is not a register class but rather tells how many
3930
+ * classes there are.
3931
+ *
3932
+ * ZipCPU --- We'll defined register 0-13 as general registers, 14-15 in
3933
+ * all_regs, and go from there.
3934
+ */
3935
+enum   reg_class {
3936
+       NO_REGS, GENERAL_REGS,
3937
+#ifdef DEFINE_USER_REGS
3938
+       USER_REGS,
3939
+#endif
3940
+       ALL_REGS, LIM_REG_CLASSES
3941
+};
3942
+
3943
+/* N_REG_CLASSES ... the number of distinct register classes, defined as follows
3944
+ */
3945
+#define        N_REG_CLASSES   (int)LIM_REG_CLASSES
3946
+
3947
+/* REG_CLASS_NAMES ... An initializer containing the names of the register
3948
+ * classes as C string constants.  These names are used in writing some of the
3949
+ * debugging dumps.
3950
+ */
3951 127 dgisselq
+#ifdef DEFINE_USER_REGS
3952
+#  define      REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" }
3953
+#else
3954
+#  define      REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "ALL_REGS" }
3955
+#endif
3956 102 dgisselq
+
3957
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register
3958 127 dgisselq
+ * classes, as integers which are bit masks.  The nth integer specifies the
3959 102 dgisselq
+ * contents of class n.  That way the integer mask is interpreted as that
3960
+ * register r is in the class if (mask&(1<<r)) is 1.
3961
+ *
3962
+ * When the machine has more than 32 registers ... that's not us.
3963
+ *
3964
+ * ZipCPU --- This is straight forward, three register classes, etc.
3965
+ */
3966 127 dgisselq
+#ifdef DEFINE_USER_REGS
3967
+#    define    REG_CLASS_CONTENTS { { 0x000000000}, {0x00003fff}, {0x0ffff0000l}, {0x0ffffffffl} }
3968 103 dgisselq
+#else
3969 127 dgisselq
+#  ifdef       zip_FP_PSEUDO
3970
+#    define    REG_CLASS_CONTENTS { { 0x00000}, {0x13fff}, {0x1ffff} }
3971
+#  else
3972
+#    define    REG_CLASS_CONTENTS { { 0x00000}, {0x03fff}, {0x0ffff} }
3973
+#  endif
3974 103 dgisselq
+#endif
3975 102 dgisselq
+
3976
+/* REGNO_REG_CLASS ... A C expression whose value is a register class
3977
+ * containing hard register REGNO.  In general there is more than one such
3978
+ * class;  Choose a class which is minimal, meaning that no smaller class also
3979
+ * contains the register.
3980
+ */
3981
+#undef REGNO_REG_CLASS
3982 103 dgisselq
+#ifdef zip_FP_PSEUDO
3983
+#define        REGNO_REG_CLASS(R)      (is_ZIP_REG(R)?((((R)<=13)||((R)==zip_FP_PSEUDO))?GENERAL_REGS:ALL_REGS):NO_REGS)
3984
+#else
3985 102 dgisselq
+#define        REGNO_REG_CLASS(R)      (is_ZIP_REG(R)?((R<=13)?GENERAL_REGS:ALL_REGS):NO_REGS)
3986 103 dgisselq
+#endif
3987 102 dgisselq
+
3988
+/* BASE_REG_CLASS ... A macro whose definition is the name of the class to which
3989
+ * a valid base register must belong.  A base register is one used in an address
3990
+ * which is the register value plus a displacement.
3991
+ */
3992
+#undef BASE_REG_CLASS
3993
+#define        BASE_REG_CLASS  GENERAL_REGS
3994
+
3995
+/* MODE_BASE_CLASS(MODE) ... This is a variation of the BASE_REG_CLASS macro
3996
+ * which allows the selection of a bse register in a mode dependent manner.  If
3997
+ * mode is VOIDmode then it should return the same value as BASE_REG_CLASS.
3998
+ */
3999
+#undef MODE_BASE_CLASS
4000
+#define        MODE_BASE_CLASS(MODE)   GENERAL_REGS
4001
+
4002
+/* MODE_BASE_REG_REG_CLASS(MODE) ... A C expression whose value is the register
4003
+ * class to which a valid base register must belong in order to be used in a
4004
+ * base plus index register address.  You should define this macro if base plus
4005
+ * index addresses have different requirements than other base register uses.
4006
+ *
4007
+ * Zip CPU does not support the base plus index addressing mode, thus ...
4008
+ */
4009 111 dgisselq
+// #undef      MODE_BASE_REG_REG_CLASS
4010
+// #define     MODE_BASE_REG_REG_CLASS(MODE)   NO_REGS
4011 102 dgisselq
+
4012
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
4013
+ * which a valid index register must belong.  An index register is one used in
4014
+ * an address where its value is either multiplied by a scale factor or added
4015
+ * to another register (as well as added to a displacement).
4016
+ *
4017
+ * ZipCPU -- Has no index registers.
4018
+ */
4019
+#undef INDEX_REG_CLASS
4020
+#define        INDEX_REG_CLASS NO_REGS
4021
+
4022
+/* REGNO_OK_FOR_BASE_P(NUM) ... A C expression which is nonzero if register
4023
+ * number num is suitable for use as a base register in operand addresses.
4024
+ */
4025
+#undef REGNO_OK_FOR_BASE_P
4026 127 dgisselq
+# define REGNO_OK_FOR_BASE_P(NUM)      ((NUM>=FIRST_PSEUDO_REGISTER)||(NUM != zip_CC))
4027 102 dgisselq
+
4028
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
4029
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
4030 111 dgisselq
+ * memory reference in MODE.  You should define this macro if the mode of the
4031 102 dgisselq
+ * memory reference affects whether a register may be used as a base register.
4032
+ *
4033
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
4034
+ */
4035
+
4036
+/* REGNO_MODE_OK_FOR_REG_BASE_P(NUM, MODE) ... base plus index operand
4037
+ * addresses, accessing memory in mode mode.
4038
+ *
4039
+ * Use of this macro is deprecated.
4040
+ */
4041
+
4042 111 dgisselq
+/* REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) ... A C expression which is
4043 102 dgisselq
+ * nonzero if a register number N is suitable for use as a base register in
4044
+ * operand addresses, accessing memory in mode M in address space AS.  This is
4045
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
4046
+ * the context in which the register appears in the memory reference.
4047
+ *
4048
+ * ZipCPU---We aren't specific in how we use our registers.
4049
+ */
4050
+#define        REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) REGNO_OK_FOR_BASE_P(N)
4051
+
4052
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
4053
+ * num is suitable for use as an index register in opernad addressess.  It may
4054
+ * be either a suitable hard register or a pseudo register that has been
4055 111 dgisselq
+ * allocated such as a hard register.
4056 102 dgisselq
+ *
4057
+ * ZipCPU has no index registers, therefore we declare this to be zero.
4058
+ */
4059
+#undef REGNO_OK_FOR_INDEX_P
4060
+#define        REGNO_OK_FOR_INDEX_P(REGNO)     0
4061
+
4062
+/* TARGET_PREFERRED_RENAME_CLASS(RCLASS) ... A target hook that places
4063
+ * additional preference on the register class to use when it is necessary to
4064
+ * rename a register in class RCLASS to another class, or perhaps NO_REGS, if no
4065
+ * preferred register class is found or hook preferred_rename_class is not
4066
+ * implemented.  SOmething returning a more restrictive class makes better code.
4067
+ * For example, on ARM, thumb-2 instructions using LO_REGS may be smaller than
4068
+ * instructions using GENERIC_REGS.  By returning LO_REGS from
4069
+ * preferred_rename_class, code size can be reduced.
4070
+ */
4071
+// #undef TARGET_PREFERRED_RENAME_CLASS
4072
+// #define     TARGET_PREFERRED_RENAME_CLASS(RCLASS)   RCLASS
4073
+
4074
+/* TARGET_PREFERRED_RELOAD_CLASS(X,RC) ... A target hook that places additional
4075
+ * restri tions on the register class to use when it is necessary to copy value
4076
+ * X into a register in class RC.  The value is a register class; rehaps RC, or
4077
+ * perhaps a smaller class.
4078
+ *
4079
+ * The default fversion of this hook always returns value of RC argument, which
4080
+ * sounds quite appropriate for the ZipCPU.
4081
+ */
4082
+
4083
+/* PREFERRED_RELOAD_CLASS(X,CLASS) ... A C expression that places additional
4084
+ * restrictions on the register class to use when it is necessary to copy
4085
+ * value X into a register in class CLASS.  On many machines, the following
4086
+ * definition is safe: PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
4087
+ * Sometimes returning a more restrictive class makes better code.  For example,
4088
+ * on the 68k, when x is an integer constant that is in range for a moveq
4089
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
4090 111 dgisselq
+ * includes the data registers.  Requiring a data register guarantees that a
4091 102 dgisselq
+ * 'moveq' will be used.
4092
+ *
4093
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS.  For
4094
+ * example, loading (sleep and !gie) into the CC register could halt the CPU.
4095
+ * Hence, we only allow loads into the GENERAL_REG class.
4096
+ */
4097
+#define        PREFERRED_RELOAD_CLASS(X, CLASS)        GENERAL_REGS
4098
+
4099
+/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS(RTX,RCLASS) ... Like TARGET_PREFERRED_..
4100
+ * RELOAD_CLASS, but for output instead of input reloads.
4101
+ *
4102
+ * ZipCPU --- there's gotta be a valid default behaviour for this.
4103
+ */
4104
+
4105
+/* LIMIT_RELOAD_CLASS(MODE, CL) ...
4106
+ *
4107
+ * Don't define this macro unless the target machine has limitations which
4108
+ * require the macro to do something nontrivial.  ZipCPU doesn't, so we won't.
4109
+ */
4110
+
4111
+/* TARGET_SECONDARY_RELOAD
4112
+ * SECONDARY_ ...
4113
+ * Don't think we need these ...
4114
+ */
4115
+
4116
+/* CLASS_MAX_NREGS(CLASS,MODE) ... A C expression for the maximum number of
4117
+ * consecutive registers of class CLASS needed to hold a value of mode MODE.
4118
+ *
4119
+ * This is closely related to the macro HARD_REGNO_NREGS.  In fact, the value
4120
+ * of the macro CLASS_MAX_REGS(CL,M) should be the maximum value of
4121
+ * HARD_REGNO_NREGS(REGNO,MODE) for all REGNO values in the class CLASS.
4122
+ *
4123
+ * This macro helps control the handling of multiple word values in the reload
4124
+ * pass.
4125
+ *
4126
+ * ZipCPU --- We'll just use HARDNO_REGNO_NREGS, since CLASS is independent for
4127
+ * us.  We'll also choose register R0, since ... well, since it simply doesn't
4128
+ * matter.  (HARD_REGNO_NREGS ignores this anyway)
4129
+ */
4130
+#define        CLASS_MAX_NREGS(CLASS, MODE)    HARD_REGNO_NREGS(0,MODE)
4131
+
4132
+/* CANNOT_CHANGE_MODE_CLASS
4133
+ * ???
4134
+ */
4135
+
4136
+/* TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
4137
+ */
4138
+
4139
+/* TARRGET_LRA_P
4140
+ * Default looks good.
4141
+ */
4142
+
4143
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
4144 111 dgisselq
+ * priority number to which the register HARD_REGNO belongs to.  The bigger the
4145 102 dgisselq
+ * number
4146
+ *
4147
+ * The default version of this target hook returns always zero---good enough for
4148
+ * the ZipCPU.
4149
+ */
4150
+
4151
+/* TARGET_REGISTER_USAGE_LEVELING_P(VOID) ... A target hook which returns true
4152
+ * if we need register usage leveling.  That means if a few hard registers are
4153
+ * equally good for the assignment, we choose the least used hard register.  The
4154
+ * register usage leveling may be profitable for some targets.  Don't use usage
4155
+ * leveling for targets with conditional execution or targets with big register
4156
+ * files as it hurts if-conversion and cross-jumping optimizations.  The default
4157
+ * version of this target hook returns always false.
4158
+ *
4159
+ * ZipCPU --- Default is the right answer.
4160
+ */
4161
+
4162
+/* TARGET_DIFFERENT_ADDR_DISPLACEMENT_P ...
4163
+ * Default looks good.
4164
+ */
4165
+
4166
+/* TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P ...
4167
+ * Default looks good.
4168
+ */
4169
+
4170
+/* TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT ....
4171
+ */
4172
+
4173
+/* TARGET_SPILL_CLASS
4174
+ *
4175
+ * ZipCPU --- If we were running in supervisor mode only, this might be the
4176
+ * user set of registers.  However, we're not building for that mode (now),
4177
+ * so we'll leave this at the default of NO_REGS.
4178
+ */
4179
+
4180
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
4181
+ * boolean result of conditional store patterns.  The OCIDE argument is the
4182
+ * instruction code for the cstore being performed.  Not defining this hook is
4183
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
4184
+ * patterns.
4185
+ *
4186
+ * ??? ZipCPU --- I don't follow this documentation.  We'll leave this at the
4187
+ * default therefore.
4188
+ */
4189
+
4190
+/* 17.09 Stack Layout and Calling Conventions */
4191
+
4192
+
4193
+/* STACK_GROWS_DOWNWARD ... Define this macro if pushing a word onto the stack
4194
+ * moves the stack pointer to a smaller address, and false otherwise.
4195
+ *
4196
+ * ZipCPU ... well, our stack does grow downward, but it doesn't do so auto-
4197
+ * magically.  We have to move the stack pointer ourselves.  However, since this
4198
+ * is our convention, we'll define it as such.
4199
+ */
4200
+#undef STACK_GROWS_DOWNWARD
4201
+#define        STACK_GROWS_DOWNWARD    1
4202
+
4203
+/* STACK_PUSH_CODE ... This macro defines the operation used when something is
4204
+ * pushed on the stack.  In RTL, a push operation will be
4205
+ * (set (mem( STACK_PUSH_CODE(reg sp))) ...) The choiecs are PRE_DEC, POST_DEC,
4206
+ * PRE_INC, and POST_INC.  Which of these is correct depends on the stack
4207
+ * direction and on whether the stack pointer points to the last item on the
4208
+ * stack or whether it points to the space for the next item on the stack.
4209
+ * The default is PRE_DECC when STACK_GROWS_DOWNWARD is true, which is almost
4210
+ * always right, and PRE_INC otherwise, which is often wrong.
4211
+ *
4212
+ * ZipCPU --- None of these is right, so let's leave this at the default and
4213
+ * see how badly we get mangled.  In particular, ZipCPU doesn't have any of the
4214
+ * PRE_DEC, POST_DEC, PRE_INC, or POST_INC addressing modes used here.
4215
+ */
4216
+
4217
+/* FRAME_GROWS_DOWNWARD ... Define this macro to nonzero if the addresses of
4218
+ * local variable slots are at negative offsets from the frame pointer.
4219
+ *
4220
+ * ZipCPU --- If the frame pointer is defined as the stack pointer upon the
4221 103 dgisselq
+ * start of function execution, and that stack pointer grows downward, then
4222 102 dgisselq
+ * this should be the case as well.
4223
+ */
4224
+#undef FRAME_GROWS_DOWNWARD
4225
+#define        FRAME_GROWS_DOWNWARD    1
4226
+// #define     FRAME_GROWS_DOWNWARD    0        // This was ECO32's value
4227
+
4228
+
4229
+/* ARGS_GROW_DOWNWARD ... Define this macro if successive arguments to a
4230
+ * function occupy decreasing addresses on the stack.
4231
+ *
4232
+ * ZipCPU -- we can leave this up to the compiler's preferred implementation,
4233
+ * it is of no consequence to the hardware.
4234
+ */
4235
+
4236
+/* STARTING_FRAME_OFFSET ... Offset from the frame pointer to the first local
4237
+ * variable slot to be allocated.  If FRAME_GROWS_DOWNWARD, find the next slot's
4238
+ * offset by subtracting the firstt slot's length from STARTING_FRAME_OFFSET.
4239
+ * Otherwise it is found by adding the length of the first slot to the value
4240
+ * START_FRAME_OFFSET.
4241
+ *
4242
+ * ZipCPU --- I'm not certain on this, let's come back after we look at how
4243
+ * the code is getting generated.  However, the ECO32 code I am copying from
4244
+ * suggests that 0 is the right value, so we'll use that here.
4245
+ */
4246
+// #warning "Re-evaluate me"
4247
+#define        STARTING_FRAME_OFFSET   0
4248
+
4249
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
4250
+ * stack during reload.  The nonzero default for this macro is suitable for most
4251
+ * ports.
4252
+ *
4253
+ * ZipCPU --- we'll leave this at the default, although if any alignment code
4254
+ * shows up on the stack we may need to adjust it.
4255
+ */
4256
+
4257
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
4258
+ * which outgoing arguments are placed.  If not specified, the default value
4259
+ * of zero is used.  This is the proper value for most machines.
4260
+ */
4261
+#define        STACK_POINTER_OFFSET    0
4262
+
4263
+/* FIRST_PARM_OFFSET ... Offset from the argument pointer register to the first
4264
+ * argument's address.  On some machines it may depend on the data type of the
4265
+ * function.
4266
+ */
4267
+#define        FIRST_PARM_OFFSET(F)    0
4268
+
4269
+/* STACK_DYNAMIC_OFFSET(F) ... Offset from the stack pointer register to an item
4270
+ * dynamically allocated on the stack, e.g., by alloca.  The default value for
4271
+ * this macro is STACK_POINTER_OFFSET plus the length of the outgoing arguments.
4272
+ * The default is correct for most machines, ...
4273
+ *
4274
+ * ZipCPU --- so we'll use it for the ZipCPU.
4275
+ */
4276
+
4277
+/* INITIAL_FRAME_ADDRESS_RTX ... A C expression whose value is RTL representing
4278
+ * the address of the initial stack frame.  This address is passed to
4279
+ * RETURN_ADDR_RTX and DYNAMIC_CHAIN_ADDRESS.  If you don't define this macro,
4280
+ * a reasonable default value will be used.  Define this macro in order to make
4281
+ * frame pointer elimination work in the presence of __builtin_frame_address(C)
4282
+ * and __builtin_return_address(C) for (C) not equal to zero.
4283
+ *
4284
+ * ZipCPU --- Let's try the reasonable default and see what happens.
4285
+ */
4286
+
4287
+/* SETUP_FRAME_ADDRESSES ... A C expression that produces the machine-specific
4288
+ * code to setup the stack so that arbitrary frames can be accessed.  For
4289
+ * example, on the SPARC, we must flush all of the register windows to the stack
4290
+ * before we can access arbitrary stack frames.  You will seldom need to define
4291
+ * this macro.  The default is to do nothing.
4292
+ *
4293
+ * ZipCPU --- which is what we shall do here.
4294
+ */
4295
+
4296
+/* TARGET_BUILTIN_SETJMP_FRAME_VALUE(VOID) ... This target hook should return
4297
+ * an RTX that is used to store the address of the current frame into the
4298
+ * builtin setjmp buffer.  The default value, virtual_stack_vars_rtx, is correct
4299
+ * for most machines.  One reason you may need to define this target hook is if
4300
+ * hard_frame_pointer_rtx is the appropriate value on your machine.
4301
+ *
4302
+ * ZipCPU --- leave this undefined, since the default value should be correct
4303
+ * for "most" machines.
4304
+ */
4305
+
4306
+/* FRAME_ADDR_RTX ... most machines do not need to define it.
4307
+ */
4308
+
4309
+/* RETURN_ADDR_RTX(COUNT,FRAMEADDR) ... A C expression whose value is RTL
4310
+ * representing the value of the return address for the frame COUNT steps up
4311
+ * from the current frame, after the prologue.  FRAMEADDR is the frame pointer
4312
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
4313
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero.  The value of the expression must
4314
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
4315
+ * there is no way to determine the return address of other frames.
4316
+ *
4317
+ * ZipCPU --- I have no idea how we'd do this, so let's just return NULL_RTX.
4318
+ */
4319
+#undef RETURN_ADDR_RTX
4320
+#define        RETURN_ADDR_RTX(COUNT,FRAMEADDR)        NULL_RTX
4321
+
4322
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
4323
+ * return address of a particular stack frame is accessed from the frame pointer
4324
+ * of the previous stack frame.  The zero default for this macro is suitable
4325
+ * for most ports.
4326
+ *
4327
+ * ZipCPU---Default works here as well.
4328
+ */
4329
+
4330
+/* INCOMING_RETURN_ADDR_RTX ... A C expression whose value is RTL representing
4331
+ * the location of the incoming return address at the beginning of any function,
4332
+ * before the prologue.  This RTL is either a REG, indicating that the return
4333
+ * value is saved in 'REG', or a MEM representing the location in the stack.
4334
+ * If this RTL is a REG, you should define DWARF_RETURN_COLUMN to
4335
+ * DWARF_FRAME_REGNUM(REGNO).
4336
+ *
4337
+ * ZipCPU --- While our incoming return address could theoretically be in any
4338
+ * register, our machine description file is going to place it into register
4339
+ * R0, so that's what we return here.
4340
+ */
4341
+#undef INCOMING_RETURN_ADDR_RTX
4342
+#define        INCOMING_RETURN_ADDR_RTX        gen_rtx_REG(SImode, zip_R0)
4343
+
4344
+
4345
+/* DWARF_ALT_FRAME_RETURN_COLUMN
4346
+ */
4347
+
4348
+/* DWARF_ZERO_REG ... A C exrpession whose value is an integer giving a DWARF2
4349
+ * register number that is considered to always have the value zero.  This
4350
+ * should only be defined if the target has an architected zero register (ZipCPU
4351
+ * does not), and someone decided it was a good idea to use that register number
4352
+ * to terminate the stack backtrace.  New ports should avoid this (so the
4353
+ * ZipCPU port will avoid it as well).
4354
+ *
4355
+ */
4356
+
4357
+/* TARGET_DWARF_HANDLE_FRAME_UNSPEC
4358
+ */
4359
+
4360
+/* INCOMING_FRAME_SP_OFFSET
4361
+ */
4362
+#define        INCOMING_FRAME_SP_OFFSET        0
4363
+
4364
+/* ARG_POINTER_CFA_OFFSET
4365
+ */
4366
+
4367
+/* FRAME_POINTER_CFA_OFFSET
4368
+ */
4369
+
4370
+/* CFA_FRAME_BASE_OFFSET
4371
+ */
4372
+
4373
+/* 17.09.02 Exception handling support */
4374
+
4375
+/* EH_RETURN_DATA_REGNO(N) ... A C expression whose value is the Nth register
4376
+ * number used for data by exception handlers, or INVALID_REGNUM if fewer than
4377
+ * N registers are usable.  The exception handling library routines communicate
4378
+ * with the exception handlers via a set of agreed upon registers.  Ideally
4379
+ * these registers should be call clobbered; it is possible to use call-saved
4380
+ * registers, but may negatively impact code size.  The target must support at
4381
+ * least 2 data registers, but should define 4 if their are enough free
4382
+ * registers.
4383
+ *
4384
+ * You must define this macro if you want to support call frame exception
4385
+ * handling like that provided by DWARF 2.
4386
+ */
4387
+#define        EH_RETURN_DATA_REGNO(N) (((N<ZIP_FIRST_ARG_REGNO)||(N>ZIP_LAST_ARG_REGNO))?(N-1):INVALID_REGNUM)
4388
+
4389
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
4390
+ * a location in which to store a stack adjustment to be applied before function
4391
+ * return.  This is used to unwind the stack to an exception handler's call
4392
+ * frame.  It will be assigned zero on code paths that return normally.
4393
+ *
4394
+ * Do not define this macro if the stack pointer is saved and restored by the
4395
+ * regular prolog and epilog code in the call frame itself (which it is for the
4396
+ * ZipCPU); in this case, the exception handling library routines will update
4397
+ * the stack location to be restored in place.  Otherwise, you must define this
4398
+ * macro if you want to support call frame exception handling like that provided
4399
+ * by DWARF 2.
4400
+ *
4401
+ */
4402
+
4403
+/* EH_RETURN_HANDLER_RTX ... A C expression whose value is RTL representing a
4404
+ * location in which to store the address of an exception handler to which we
4405
+ * should return.  It will not be assigned on code paths that return normally.
4406
+ *
4407
+ * Typcally this is the location in the call frame at which the normal return
4408
+ * address is stored.  For targets that return by popping an address of the
4409
+ * stack, this might be a memory address just below the target callf rame
4410
+ * rather than inside the current call frame.  If defined,
4411
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
4412
+ * to calculate the location of the target call frame.
4413
+ *
4414
+ * If you want to support call frame exception handling, you must define either
4415
+ * this macro or the eh_return instruction pattern.
4416
+ */
4417
+// #warning "I don't know what to do here."
4418
+
4419
+/*
4420
+ *
4421
+ *
4422
+ *
4423
+ *   REST OF SECTION SKIPPED ...
4424
+ *
4425
+ *
4426
+ *
4427
+ */
4428
+
4429
+/* 17.09.03 Specifying how stack checking is done */
4430
+
4431
+/* STACK_CHECK_BUILTIN ... a non-zero value if stack checking is done by the
4432
+ * configuration files in a machine-dependent manner.  You should define this
4433
+ * macro if stack checking is required by the ABI of your machine or if you
4434
+ * would like to do stack checking in some more efficient way than the generic
4435
+ * appraoch.  The default value of this macro is zero.
4436
+ *
4437
+ * ZipCPU --- The default makes sense for us.
4438
+ */
4439
+// #define STACK_CHECK_BUILTIN 0
4440
+
4441
+/* STACK_CHECK_STATIC_BUILTIN ... A nonzero value if static stack checking is
4442
+ * done by the configuration files in a machine-dependent manner.  You should
4443
+ * define this macro if you would like to do static stack checking in some more
4444
+ * efficient way than the generic approach.  The default value of this macro
4445
+ * is zero.
4446
+ *
4447
+ * ZipCPU --- The default makes sense for us.
4448
+ */
4449
+
4450
+/* STACK_CHECK_PROBE_INTERVAL_EXP ...  An integer specifying the interval at
4451
+ * which GCC must generate stack probe instructions, defined as 2 raised to this
4452
+ * interval.  You will normally define this macro so that the interval is no
4453
+ * larger than the size of the "guard pages" at the end of a stack area.  The
4454
+ * default value of 12 (4096-byte interval) is suitable for most systems.
4455
+ *
4456
+ * ZipCPU --- Default.
4457
+ */
4458
+
4459
+/* STACK_CHECK_MOVING_SP ... An integer which is non-zero if GCC should move
4460
+ * the stack pointer page by page when doing probes.  This can be necessary
4461
+ * on systems where the stack pointer contains the bottom address of the memory
4462
+ * area accessible to the executing thread at any point in time.  In this
4463
+ * situation, an alternate signal stack is required in order to be able to
4464
+ * recover from a stack overflow.  The default value of this macro is zero.
4465
+ *
4466
+ * ZipCPU -- Default.
4467
+ */
4468
+
4469
+/* STACK_CHECK_PROTECT
4470
+ */
4471
+/* STACK_CHECK_MAX_FRAME_SIZE
4472
+ * ... you should normally not change the default value of this macro.
4473
+ */
4474
+/* STACK_CHECK_FIXED_FRAME_SIZE
4475
+ * ... you ... will normally use the default of four words.
4476
+ */
4477
+
4478
+/* STACK_CHECK_MAX_VAR_SIZE
4479
+ * ... you will normally not need to override that default.
4480
+ */
4481
+
4482
+/* 17.09.04 Registers that Address the Stack Frame*/
4483
+
4484
+/* STACK_POINTER_REGNUM ... The register number of the stack pointer register,
4485
+ * which must also be a fixed register according to FIXED_REGISTERS.  On most
4486
+ * machines, the hardware determines which register this is.
4487
+ */
4488
+#undef STACK_POINTER_REGNUM
4489
+#define        STACK_POINTER_REGNUM    zip_SP
4490
+
4491
+/* FRAME_POINTER_REGNUM ... The register number of the frame pointer register,
4492
+ * which is used to access certain automatic variables in the stack frame.  On
4493
+ * some machines, the hardware determines which register this is.  On other
4494
+ * machines you can choose any register you wish for this purpose.
4495
+ *
4496
+ * ZipCPU --- While I'd like to dump this pointer, since I don't really see
4497
+ * a need for it, alloca() requires it.  Therefore let's assine a register to
4498
+ * this purpose and watch what the compiler does with it.
4499
+ */
4500 103 dgisselq
+#ifdef zip_FP_PSEUDO
4501
+#define        FRAME_POINTER_REGNUM    zip_FP_PSEUDO
4502
+#else
4503 102 dgisselq
+#define        FRAME_POINTER_REGNUM    zip_FP
4504 103 dgisselq
+#endif
4505 102 dgisselq
+
4506
+/* HARD_FRAME_POINTER_REGNUM ... On some machines the offset between the frame
4507
+ * pointer and starting offset of the automatic variables is not known until
4508
+ * after register allocation has been done (for example, because the saved
4509
+ * registers are between these two locations).  On those machines, define
4510
+ * FRAME_POINTER_REGNUM the number of a special, fixed register to be used
4511
+ * internally until the offset is known, and define HARD_FRAME_POINTER_REGNUM
4512
+ * to be the actual hard register number used for the frame pointer.
4513
+ *
4514
+ * Do not define this macro if it would be the same as FRAME_POINTER_REGNUM
4515
+ *
4516
+ * ZipCPU --- we do not define this macro.
4517
+ */
4518 103 dgisselq
+#if (zip_FP == FRAME_POINTER_REGNUM)
4519
+#define HARD_FRAME_POINTER_REGNUM      zip_FP
4520
+#endif
4521 102 dgisselq
+
4522
+/* ARG_POINTER_REGNUM ... The register number of the arg pointer register, which
4523
+ * is used to access the function's argument list.  On some machines, this is
4524
+ * the same as the frame pointer register.  On some machines, the hardware
4525
+ * determines which register this is.  On other machines, you can choose any
4526
+ * register you wish for this purpose.  If this is not the same register as the
4527
+ * frame pointer register, then you must mark it as a fixed register according
4528
+ * to FIXED_REGISTERs, or arrange to be able to eliminate it.
4529
+ *
4530
+ * ZipCPU --- We really don't want to lose another register to something
4531
+ * pointless, so let's set this to be the frame pointer register.  Especially
4532
+ * given the ZipCPU's ease of accessing things via offsets of registers, this
4533
+ * should work for a rather large stack frame.
4534
+ */
4535 103 dgisselq
+#define ARG_POINTER_REGNUM     FRAME_POINTER_REGNUM
4536 102 dgisselq
+
4537
+/* HARD_FRAME_POINTER_IS_FRAME_POINTER ... define this to be a preprocessor
4538
+ * constant that is nonzero if hard_frame_pointer_rtx and frame_pointer_rtx
4539
+ * should be the same.  The default definition is sufficient for us.
4540
+ */
4541
+
4542
+/* HARD_FRAME_POINTER_IS_ARG_POINTER ...
4543
+ * ZipCPU doesn't need this macro
4544
+ */
4545
+
4546
+/* RETURN_ADDRESS_POINTER_REGNUM ... The register number of the return address
4547
+ * pointer register, which is used to access the current function's return
4548
+ * address from the stack.  On some machines, the return address is not at a
4549
+ * fixed offset from the frame pointer or stack pointer or argument pointer.
4550
+ * This register can be defined to point to the return address on the stack, and
4551
+ * then to be converted by ELIMINABLE_REGS into either the frame pointer or the
4552
+ * stack pointer.
4553
+ *
4554
+ * Do not define this macro unless there is no other way to get the return
4555
+ * address from the stack.
4556
+ *
4557
+ * ZipCPU---we need this.
4558
+ */
4559
+#define        RETURN_ADDRESS_REGNUM   zip_R0
4560
+
4561
+
4562
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
4563
+ * static chain pointer.  If register windows are used, the register number as
4564
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
4565
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM.  If
4566
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
4567
+ * defined.
4568
+ *
4569
+ * ZipCPU doesn't have register windows, so we don't need to define this.
4570
+ */
4571
+// #warning "I have no reason to believe this will even work"
4572
+#define        STATIC_CHAIN_REGNUM     zip_GOT
4573
+
4574
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
4575
+ * al for targets that may use different static chain locations for different
4576
+ * nested functions.  This may be required if the target has function attributes
4577
+ * that affect the calling conventions of the function and those calling
4578
+ * conventions use different static chain locations.
4579
+ *
4580
+ * ZipCPU --- don't need this.
4581
+ */
4582
+// #define     STATIC_CHAIN_REGNUM     zip_R11
4583
+
4584
+
4585
+/* DWARF_FRAME_REGISTERS ... This macro specifies  the maximum number of hard
4586
+ * registers that can be saved in a call frame.  This is used to size data
4587
+ * structures used in DWARF2 exception handling.
4588
+ *
4589
+ * Prior to GCC 3.0, this macro was needed in order to establish a stable
4590
+ * exception handling ABI in the face of adding new hard registers for ISA
4591
+ * extensions.  In GCC 3.0 and later, the EH ABI is insulated from changes in
4592
+ * the number of hard registers.  Nevertheless, this macro can still be used to
4593
+ * reduce the runtime memory requirements of the exception handling routines,
4594
+ * which can be substantial if the ISA contains a lot of registers that are not
4595
+ * call-saved.
4596
+ *
4597
+ * If this macro is not defined, it defaults to FIRST_PSEUDO_REGISTER.
4598
+ *
4599
+ * ZipCPU --- The default is not sufficient.  The CC and PC registers need to
4600
+ * be saved and examined as well in any debug/exception context.  Hence, we
4601
+ * define this to be all of our registers.
4602
+ */
4603
+#undef DWARF_FRAME_REGISTERS
4604
+#define        DWARF_FRAME_REGISTERS   16
4605
+
4606
+/* PRE_GCC3_DWARF_FRAME_REGISTERS ... This macro is similar to DWARF_FRAME_REG..
4607
+ * but is provided for backward compatibility in pre GCC 3.0 compiled code.
4608
+ *
4609
+ * If not defined, it defaults to DWARF_FRAME_REGISTERS---which is perfect for
4610
+ * the ZipCPU.
4611
+ */
4612
+
4613
+/* DWARF_REG_TO_UNWIND_COLUMN(REGNO) ... Define this macro if the target's
4614
+ * representation for dwarf registers is different than the internal
4615
+ * representation for unwind column.  Given a dwarf register, this macro should
4616
+ * return the unwind column number to use instead.
4617
+ *
4618
+ * ... ???
4619
+ */
4620
+
4621
+/* DWARF_FRAME_REGNUM(REGNO) ... Define this macro is the target's
4622
+ * representation for dwarf registers used in .eh_frame or .debug_frame is
4623
+ * different from that used in other debug info sections.  Given a GCC hard
4624
+ * register number, this macro should return the .eh_frame register number.
4625
+ * The default is DBX_REGISTER_NUMBER(REGNO).
4626
+ *
4627
+ * ZipCPU --- provided we define DBX_REGISTER_NUMBER(REGNO) well, this default
4628
+ * should still work for us.
4629
+ */
4630
+
4631
+/* DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) ... Define this macro to map register
4632
+ * numbers held in the call frame info that GCC has collected using
4633
+ * DWARF_FRAME_REGNO to those that should be output in .debug_frame (for_eh is
4634
+ * zero) and .eh_frame (for_eh is non-zero). The default is to return REGNO.
4635
+ *
4636
+ * ZipCPU --- Default is good enough.
4637
+ */
4638
+
4639
+/* REG_VALUE_IN_UNWIND_CONTEXT ... Define this macro if the target stores
4640
+ * register values as _Unwind_Word type in unwind context.  It should be defined
4641
+ * if target register size is larger than the size of void *.  The default
4642
+ * is to store register values as void *type.
4643
+ *
4644
+ * ZipCPU --- Default is what we need.
4645
+ */
4646
+
4647
+/* ASSUME_EXTENDED_UNWIND_CONTEXT ... Define this macro to be 1 if the target
4648
+ * always uses extended unwind context with version, args_size, and by_value
4649
+ * fields.  If it is undefined, it will always be defined to 1 when REG_VALUE_IN_UNWIND_CONTEXT is defined and 0 otherwise.
4650
+ *
4651
+ */
4652
+
4653
+
4654
+/* 17.09.05 Eliminating Frame Pointer and Arg Pointer */
4655
+
4656
+/* TARGET_FRAME_POINTER_REQUIRED(VOID) ... This target hook should return true
4657
+ * if a function must have and use a frame pointer.  This target hook is
4658
+ * called in the reload pass.  If its return value is true, the function will
4659
+ * have a frame pointer.
4660
+ *
4661
+ * This target hook can in principle examine the current function and decide
4662
+ * according to the facts, but on most machines the constant false or the
4663
+ * constant true suffices.  Use false when the machine allows code to be
4664
+ * generated with no frame pointer, and doing so saves some time or space.
4665
+ * Use true when there is no possible advantage to avoiding a frame pointer.
4666
+ *
4667
+ * ZipCPU---if we add in a frame pointer, we become register starved.  Hence,
4668
+ * we'll treat this as a constant false--which is also the default value.
4669
+ */
4670
+#define        target_frame_pointer_required   zip_frame_pointer_required
4671
+
4672
+/* INITIAL_FRAME_POINTER_OFFSET ... A C statement to store in the variable
4673
+ * depth-var the difference between the frame pointer and the stack pointer
4674
+ * values immediately after the function prologue.  The value would be computed
4675
+ * from information such as the result of get_frame_size() and the tables of
4676
+ * registers regs_ever_live and call_used_regs.
4677
+ *
4678
+ * If ELIMINABLE_REGS is defined, this macro will not be used and need not be
4679
+ * defined.  Otherwise, it must be defined even if TARGET_FRAME_POINTER_REQD
4680
+ * always returns true; in that case you may set depth-var to anything.
4681
+ *
4682
+ * ZipCPU --- we intend to set ELIMINABLE_REGS, so this is not necessary.
4683
+ */
4684
+// #define     INITIAL_FRAME_POINTER_OFFSET(DEPTH)     (DEPTH) = 0
4685
+
4686
+
4687
+/* ELIMINABLE_REGS ... If defined, this macro specifies a table of register
4688
+ * pairs used to eliminate unneeded registers that point into the stack frame.
4689
+ * If it is not defined, the only elimination attempted by the compiler is to
4690
+ * replace references to the frame pointer with references to the stack pointer.
4691
+ *
4692
+ * On some machines, the position of the argument pointer is not known until
4693
+ * the compilation is completed.  In such a case, a separate hard register
4694
+ * must be used for the argument pointer.  This register can be eliminated by
4695
+ * replacing it with either the frame pointer or the argument pointer,
4696
+ * depending on whether or not the frame pointer has been eliminated.
4697
+ *
4698
+ * ZipCPU we'll take their suggestion and define this as:
4699
+ */
4700
+#undef ELIMINABLE_REGS
4701 103 dgisselq
+#ifdef zip_FP_PSEUDO
4702 102 dgisselq
+#define        ELIMINABLE_REGS \
4703 103 dgisselq
+        {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},          \
4704
+         { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},     \
4705
+         { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},        \
4706
+         { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
4707
+#else
4708
+# if (ARG_POINTER_REGNUM == FRAME_POINTER_REGNUM)
4709
+#  define      ELIMINABLE_REGS \
4710
+        {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
4711
+# else
4712
+#  define      ELIMINABLE_REGS \
4713 102 dgisselq
+       {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },  \
4714
+        { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },  \
4715
+        { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
4716 103 dgisselq
+# endif
4717
+#endif
4718 102 dgisselq
+
4719
+/* bool TARGET_CAN_ELIMINATE(FROM,TO) ... This target function should return
4720
+ * true if the compiler is allowed to try to replace register number FROM with
4721
+ * register number TO.  This target hook need only be defined if ELIMINABLE_REGS
4722
+ * is defined, and will usually return true since most of the cases preventing
4723
+ * register elimination are things that the compiler  already knows about.
4724
+ *
4725
+ * ZipCPU ... does the compiler  know about my decision as to whether or not
4726 117 dgisselq
+ * the frame pointer was needed?  Yes it does, but it's kept separately.  We'll
4727
+ * just say everything can be eliminated.
4728 102 dgisselq
+ */
4729
+#define TARGET_CAN_ELIMINATE   zip_can_eliminate
4730
+
4731
+/* INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) ... This macro is similar to
4732
+ * INITIAL_FRAME_POINTER_OFFSET.  It specifies the initial difference between
4733
+ * the specified pair of registers.  This macro must be defined if
4734
+ * ELIMINABLE_REGS is defined.
4735
+ *
4736 117 dgisselq
+ * ZipCPU---We had at one time set this to a default offset of 0.  This didn't
4737
+ * work.  It turns out that this is not only the *initial* elimination offset,
4738
+ * but also the offset along the way.  Hence, when a variable needs to be
4739
+ * spilled to the stack, this offset must change.  Reload goes and checks for
4740
+ * this, and adjusts registers if the offset has changed.  Hence, without this,
4741
+ * we get negative (i.e. illegal) stack offsets.
4742 102 dgisselq
+ */
4743
+#define        INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)            \
4744
+       do { (OFFSET) = zip_initial_elimination_offset((FROM), (TO)); } \
4745
+       while(0)                                        \
4746
+
4747
+/* 17.09.06 Passing function arguments on the stack */
4748
+
4749
+/* TARGET_PROMOTE_PROTOTYPES ... Returns true if an argument declared in a
4750
+ * prototype as an integral type smaller than int should actually be
4751
+ * passed as an int.  In addition to avoiding errors in certain cases of
4752
+ * mismatch, it also makes for better code on certain machines.  The default is
4753
+ * to not promote prototypes.
4754
+ *
4755
+ * Since everything is an int on the ZipCPU, let's promote anything smaller
4756
+ * (which should still be an int) up to an int anyway.
4757
+ */
4758
+#undef TARGET_PROMOTE_PROTOTYPES
4759
+#define        TARGET_PROMOTE_PROTOTYPES       hook_bool_const_tree_true
4760
+
4761
+/* PUSH_ARGS ... A C expression.  If nonzero, push instructions will be used to
4762
+ * pass outgoing arguments.  If the target machine does not have a push
4763
+ * instruction, set it to zero.  That directs GCC to use an alternate strategy:
4764
+ * to allocate the entire argument block and then store the arguments into it.
4765
+ * When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too.
4766
+ *
4767
+ * ZipCPU does not have a push instruction, so we set this to zero.
4768
+ */
4769
+#undef PUSH_ARGS
4770
+#define        PUSH_ARGS       0
4771
+
4772
+/* PUSH_ARGS_REVERSED ... A C expression.  If nonzero, function arguments will
4773
+ * be evaluated last to first, rather than first to last.  If this macro is
4774
+ * not defined, it defaults to PUSH_ARGS on targets where the stack and args
4775
+ * grow in opposite directions, and zero otherwise.
4776
+ *
4777
+ * ZipCPU---Let's evaluate our arguments first to last.
4778
+ */
4779
+#define        PUSH_ARGS_REVERSED      1
4780
+
4781
+/* PUSH_ROUNDING(NPUSHED) ... A C expression that is the number of bytes
4782
+ * actually pushed onto the stack when an instruction attempts to push
4783
+ * (NPUSHED) bytes.
4784
+ *
4785
+ * ZipCPU---We cannot push bytes.  Let's leave this undefined and see what
4786
+ * happens.
4787
+ */
4788
+// #warning "No appropriate definition seemed right."
4789
+
4790
+/* ACCUMULATE_OUTGOING_ARGS ... A C expression.  If non-zero, the maximum amount
4791
+ * of space required for outgoing arguments will be computed and placed into
4792
+ * crtl->outgoing_args_size.  No space will be pushed onto the stack for each call; instead the function prologue should increase the stack frame size by this
4793
+ * amount.
4794
+ *
4795
+ * ZipCPU---This is *cool* and so necessary---it saves an extra two instructions
4796
+ * each time we try to call a function/routine.  Yes, we want and *need* this
4797
+ * for good performance.  I mean, think of it, free performance increase?  Who
4798
+ * could argue with that?
4799
+ */
4800
+#undef ACCUMULATE_OUTGOING_ARGS
4801
+#define        ACCUMULATE_OUTGOING_ARGS        1
4802
+
4803
+
4804
+/* REG_PARM_STACK_SPACCE(FN) ... Define this macro if functions should assume
4805
+ * that stack space has been allocated for arguments even when their values
4806
+ * are passed in registers.  The value of this macro is the size, in bytes, of
4807
+ * the area reserved for arguments passed in registers for the function
4808
+ * represented by FN, which can be zero if GCC is calling a library function.
4809
+ * The argument FN can be the FUNCTION_DECL, or the type itself of the function.
4810
+ *
4811
+ * This space can be allocated by the caller, or be part of the machine
4812
+ * dependent stack frame: OUTGOING_REG_PARM_STACK_SPACE says which.
4813
+ *
4814
+ * ZipCPU --- Why allocate space you won't use?  Let's leave this undefined
4815
+ * therefore.
4816
+ */
4817
+// #undef      REG_PARM_STACK_SPACE
4818
+
4819
+
4820
+
4821
+/* INCOMING_REG_PARM_STACK_SPACE(FN) ... Like REG_PARM_STACK_SPACE, but for
4822
+ * incoming register arguments.  Define this macro if space guaranteed when
4823
+ * compiling a function body is different to space required when making a call,
4824
+ * a situation that can arise with K&R style function definitions.
4825
+ *
4826
+ */
4827
+
4828
+/* OUTGOING_REG_PARM_STACK_SPACE(FN) ... Define this to a nonzero value if it
4829
+ * is the responsibility of the caller to allocate the area reserved for
4830
+ * arguments passed in registers when calling a function of FN.  FN may be NULL
4831
+ * if the function called is a library function.
4832
+ *
4833
+ * ZipCPU---Why allocate space you don't need?
4834
+ */
4835
+#define        OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)   0
4836
+
4837
+
4838
+/* STACK_PARMS_IN_REG_PARM_AREA ... Define this macro if REG_PARM_STACK_SPACE
4839
+ * is defined, buyt the stack parameters don't skip the area specified by it.
4840
+ *
4841
+ * ZipCPU---We didn't define REG_PARM_STACK_SPACE, so we won't define this.
4842
+ */
4843
+
4844
+/* TARGET_RETURN_POPS_ARGS(DECL,FNTYPE,SZ) ... This target hook returns the
4845
+ * number of bytes of its own arguments that a function pops on returning, or 0
4846
+ * if the function pops no arguments and the caller must therefore pop them all
4847
+ * after the function returns.
4848
+ *
4849
+ * ZipCPU --- If we define this, we'll lose our gain from
4850
+ * ACCUMULATE_OUTOING_ARGS.  Thus, we leave this undefined.
4851
+ */
4852
+
4853
+/* CALL_POPS_ARGS(CUM) ... A C expression that should indicate the number of
4854
+ * bytes a call sequence pops off of the stack.  It is added to the value of
4855
+ * RETURN_POPS_ARGS when compiling a function call.  CUM is the variable in
4856
+ * which all arguments to the function have been accumulated.
4857
+ *
4858
+ * ZipCPU---The call sequence, by itself, doesn't touch the stack.  Therefore
4859
+ * this is zero.
4860
+ */
4861
+#undef CALL_POPS_ARGS
4862
+#define        CALL_POPS_ARGS(CUM)     0
4863
+
4864
+
4865
+/* 17.09.07 Passing arguments in registers */
4866
+
4867
+/* TARGET_FUNCTION_ARG ... Return an RTX indicating whether a function argument
4868
+ * is passed in a register, and if so, which register.
4869
+ */
4870
+/*
4871
+ * This has been poisoned ... so let's not define it anymore and look for
4872
+ * a better way to do this ...
4873
+ *
4874
+ * #define     FUNCTION_ARG(CUM, MODE, TYPE, NAMED) (((NAMED) == 0) ? NULL_RTX
4875
+ *     : targetm.calls.must_pass_in_stack(MODE, TYPE)  ? NULL_RTX
4876
+ *     : (CUM) > ZIP_LAST_ARG_REGNO                    ? NULL_RTX
4877
+ *     : gen_rtx_REG(MODE, CUM))
4878
+ */
4879
+#define        TARGET_FUNCTION_ARG     zip_function_arg
4880
+
4881
+
4882
+/* TARGET_MUST_PASS_IN_STACK ...
4883
+ */
4884
+// #undef      TARGET_MUST_PASS_IN_STACK
4885
+// #define     TARGET_MUST_PASS_IN_STACK       zip_must_pass_in_stack
4886
+
4887
+/* TARGET_FUNCTION_INCOMING_ARG ... Define this hook if the target machine
4888
+ * has register windows, ... which ZipCPU does not have.
4889
+ */
4890
+
4891
+/* TARGET_USE_PSEUDO_PIC_REG(void) ... This hook should return 1 in case
4892
+ * pseudo register should be created for pic_offset_table_rtx during function
4893
+ * expand.
4894
+ *
4895
+ * This should be defined by global parameters, isn't it?
4896
+ */
4897
+
4898
+/* TARGET_INIT_PIC_REG(v) ... Perform a target dependent initialization of
4899
+ * pic_offset_table_rtx.  This hook is called at the start of register
4900
+ * allocation.
4901
+ *
4902
+ * ZipCPU---Let's revisit this.
4903
+ */
4904
+// #warning "Come back and relook at relocations"
4905
+
4906
+/* TARGET_ARG_PARTIAL_BYTES ... This target hook returns the number of bytes
4907
+ * at the beginning of an argument that must be put in registers.  The value
4908
+ * must be zero for arguments that are passed entirely in registers or that
4909
+ * are entirely pushed on the stack.
4910
+ */
4911
+// #undef      TARGET_ARG_PARTIAL_BYTES
4912
+// #define     TARGET_ARG_PARTIAL_BYTES        zip_arg_partial_bytes
4913
+
4914
+/* TARGET_PASS_BY_REFERENCE(CUM,MOD,TREE,NAMED) ... This target hook should
4915
+ * return true if an argument at the position indicated by CUM should be passed
4916
+ * by reference.  This predicate is queried after target independent reasons
4917
+ * for being pssed by reference, such as TREE_ADDRESSABLE(TREE).
4918
+ *
4919
+ */
4920
+// #undef      TARGET_PASS_BY_REFERENCE
4921
+// #define     TARGET_PASS_BY_REFERENCE        zip_pass_by_reference
4922
+
4923
+/* CUMULATIVE ARGS ...  A C type for declaring a variable that is used as the
4924
+ * first argument of 'FUNCTION_ARG' and other related values.
4925
+ *
4926
+ * ZipCPU---We're in trouble if an 'int' won't work, so let's just use that.
4927
+ */
4928
+#define        CUMULATIVE_ARGS int
4929
+
4930
+/*
4931
+ * OVERRIDE_ABI_FORMAT
4932
+ */
4933
+
4934
+/* INIT_CUMULATIVE_ARGS ... A C statement (sans semicolon) for initializing the
4935
+ * variable CUM for the state at the beginning of the argument list.
4936
+ *
4937
+ *
4938
+ * ZipCPU---The first argument is passed in register ZIP_FIRST_ARG_REGNO, or
4939
+ * R1 (unless it has been redefined above ...)
4940
+ */
4941
+#define        INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) (CUM = 0)
4942
+
4943
+/* INIT_CUMULATIVE_LIBCALL_ARGS
4944
+ * INIT_CUMULATIVE_INCOMING_ARGS
4945
+ *
4946
+ * These default to the last INIT_CUM_ARGS value above.
4947
+ */
4948
+
4949
+/* TARGET_FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) .. This hook updates
4950
+ * the summarizer variable pointed to by CUM to advance past an argument in
4951
+ * the argument list.  The values MODE, TYPE, and NAMED describe that
4952
+ * argument.  Once this is done, the variable CUM is suitable for analyzing the
4953
+ * following argument with TARGET_FUNCTION_ARG, etc.  This hook need not do
4954
+ * anything if the argument in question was passed on the stack.  The compiler
4955
+ * knows how to track the amount of stack space used for arguments without
4956
+ * any special help.
4957
+ *
4958
+ * ZipCPU---Here we simply copy from ECO32.
4959
+ */
4960
+#define        TARGET_FUNCTION_ARG_ADVANCE     zip_function_arg_advance
4961
+
4962
+/*
4963
+ * TARGET_ARG_OFFSET --- not necessary
4964
+ * FUNCTION_ARG_PADDING        --- not necessary, since we shouldn't be padding
4965
+ * PAD_VARARGS_DOWN    --- not necessary, since we shouldn't be padding
4966
+ * BLOCK_REG_PADDING
4967
+ * TARGET_FUNCTION_ARG_BOUNDARY
4968
+ * TARGET_FUNCTION_ARG_ROUND_BOUNDARY
4969
+ */
4970
+
4971
+/* FUNCTION_ARG_REGNO_P(REGNO) ... A C expression that is nonzero if REGNO is
4972
+ * the number of a hard register in which function arguments are sometimes
4973
+ * passed.  This does not include implicit arguments such as the static chain
4974
+ * and the structure-value address.  On many machines, no registers can be used
4975
+ * for this purpose since all function arguments are pushed on the stack.
4976
+ */
4977
+#define        FUNCTION_ARG_REGNO_P(r) ((r >= ZIP_FIRST_ARG_REGNO)&&(r<=ZIP_LAST_ARG_REGNO))
4978
+
4979
+/* TARGET_SPLIT_COMPLEX_ARG(TYPE) ... This hook should return true if parameter
4980
+ * of type TYPE are passed as two scalar parameters.  By default, GCC will
4981
+ * attempt to pack complex arguments into the target's word size.  Some ABI's
4982
+ * require complex arguments to be split and treated as their individual
4983
+ * components.
4984
+ *
4985
+ * The default value of this hook is NULL, which is treated as always false,
4986
+ * and which should be good enough for ZipCPU--which can go either way.
4987
+ */
4988
+
4989
+/* TARGET_BUILD_BUILTIN_VA_LIST ... This hook returns a type node for va_list
4990
+ * for the target.  The default version of the hook returns void*.
4991
+ *
4992
+ */
4993
+
4994
+/* TARGET_ENUM_VA_LIST_P
4995
+ */
4996
+
4997
+/* TARGET_FN_ABI_VA_LIST ... This hook returns the va_list type of the calling
4998
+ * convention specified by FN.  The default version of this returns va_list_type_node.
4999
+ */
5000
+
5001
+/* TARGET_FN_ABI_VA_LIST
5002
+ */
5003
+
5004
+/* TARGET_CANONICAL_VA_LIST_TYPE
5005
+ */
5006
+
5007
+/* TARGET_GIMPLIFY_VA_ARG_EXPR
5008
+ */
5009
+
5010
+/* TARGET_VALID_POINTER_MODE(MODE) ... Define this to return nonzero if the
5011
+ * port can handle pointers with machine mode MODE.  The default version of this
5012
+ * hook returns true for both ptr_mode and Pmode.
5013
+ *
5014
+ * ZipCPU---if Pmode is properly defined (above, and I think it is), then the
5015
+ * default behavior is quite appropriate.
5016
+ */
5017
+
5018
+/* TARGET_REF_MAY_ALIAS_ERRNO(REFP) ... Define this to return nonzero if the
5019
+ * memory reference REF may alias with the system C library errno location.
5020
+ * The default version of this hook assumes the system C library errno location
5021
+ * is either a declaration of type int or accessed by dereferencing a pointer
5022
+ * to int.
5023
+ *
5024
+ * ZipCPU --- Default sounds good to me.
5025
+ */
5026
+
5027
+
5028
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
5029
+ * the port is prepared to handl instructions involving scalar mode MODE.  For
5030
+ * a scalar mode to be considered supported, all the basic arithmetic and
5031
+ * comparisons must work.
5032
+ *
5033
+ * The default version of this hook returns true for any mode required to
5034
+ * handle the basic C types (as defined by the port).  Included here are the
5035
+ * double-word arithmetic supported by the code in optabs.c.
5036
+ */
5037
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
5038
+#define        TARGET_SCALAR_MODE_SUPPORTED_P  zip_scalar_mode_supported_p
5039
+
5040
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
5041
+ * port is prepared to handle instructions involving vector mode MODE.  At the
5042
+ * very least, it must have move patterns for this mode.
5043
+ *
5044
+ * ZipCPU---does not support any vector modes.
5045
+ */
5046
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
5047
+#define        TARGET_VECTOR_MODE_SUPPORTED_P  hook_bool_mode_false
5048
+
5049
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
5050
+ * try to use a scalar mode to store an array of NELEMS elements, given that
5051
+ * each element has mode MODE.  Returning true here overrides the usual MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
5052
+ *
5053
+ * ZipCPU---Sounds good.
5054
+ */
5055
+// #undef      TARGET_ARRAY_MODE_SUPPORTED_P
5056
+// #define     TARGET_ARRAY_MODE_SUPPORTED_P   zip_array_mode_supported_p
5057
+
5058
+/* TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P(MODE) ... Define this to return
5059
+ * nonzero if libgcc provides support for the floating-point mode MODE, which is
5060
+ * known to pass TARGET_SCALAR_MODE_SUPPORTED_P.  The default version of this
5061
+ * hook returns true for all of SFmode, DFmode, XFmode, and TFmode, if such
5062
+ * modes exist.
5063
+ *
5064
+ * ZipCPU---We only support SFmode and DFmode, but for now only in emulation
5065
+ * (if we can).  Let's allow both of those and see how far we get.
5066
+ */
5067
+#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
5068
+#define        TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P zip_libgcc_floating_mode_supported_p
5069
+
5070
+/* TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P(MODE) ... Define this to return
5071
+ * nonzero for machine modes for which the port has small register classes.  If
5072
+ * target hook returns nonzero for a given MODE, the compiler will try to
5073
+ * minimize the lifetime of registers in MODE.  The hook may be called with
5074
+ * VOIDmode as an argument.  In this case, the hook is expected to return
5075
+ * nonzero if it returns nonzero for any mode.
5076
+ *
5077
+ * The default version of this hook returns false for any mode.
5078
+ *
5079
+ * ZipCPU---Default sounds good.
5080
+ */
5081
+
5082
+/* 17.09.08 How scalar function values are returned */
5083
+
5084
+/* TARGET_FUNCTION_VALUE
5085
+ */
5086
+
5087
+/* LIBCALL_VALUE
5088
+ */
5089
+
5090
+
5091
+/* 17.09.09 How large values are returned */
5092
+
5093
+/* TARGET_RETURN_IN_MEMORY(TYP,FNTYP) ... This target hook should return a
5094
+ * nonzero value to say to return the function value in memory, just as large
5095
+ * structures are always returned.  Here type will be the data type of the value
5096
+ * and FNTYP will be the type of the function doing the returning, or NULL
5097
+ * for libcalls.
5098
+ *
5099
+ */
5100
+#undef TARGET_RETURN_IN_MEMORY
5101
+#define        TARGET_RETURN_IN_MEMORY zip_return_in_memory
5102
+
5103
+/* DEFAULT_PCC_STRUCT_RETURN
5104
+ * TARGET_STRUCT_VALUE_RTX
5105
+ * PCC_STATIC_STRUCT_RETURN
5106
+ * TARGET_GET_RAW_RESULT_MODE
5107
+ * TARGET_GET_RAW_ARG_MODE
5108
+ */
5109
+
5110
+
5111
+/* 17.09.10 Caller-Saves Register Allocation */
5112
+/* 17.09.11 Function Entry and Exit */
5113 111 dgisselq
+// TARGET_ASM_FUNCTION_PROLOGUE
5114
+// TARGET_ASM_FUNCTION_END_PROLOGUE
5115
+// TARGET_ASM_FUNCCTION_BEGIN_EPILOGUE
5116
+// TARGET_ASM_FUNCTION_EPILOGUE
5117
+/* EXIT_IGNORE_STACK ... Define this macro as a C expression that is nonzero
5118
+ * if the return instruction or the function epilogue ignores the value of the
5119
+ * stack pointer; in other words, if it is safe to delete an instruction to
5120
+ * adjust the stack pointer before a return from the function.
5121
+ *
5122
+ * The default is 0.
5123
+ *
5124
+ * Note that this macro's value is relevant only for functions for which frame
5125
+ * pointers are maintained.  It is never safe to delete a final stack adjustment
5126
+ * in a function that has no frame pointer, and the compiler knows this
5127
+ * regardless of EXIT_IGNORE_STACK.
5128
+ *
5129
+ * ZipCPU -- Thanks to the example of the m68k, and a careful selection of what
5130
+ * our options otherwise could have been, our epilogue code does not use the
5131
+ * stack register at all, but rather starts by moving the frame register into
5132
+ * the stack register.
5133
+ */
5134
+#define EXIT_IGNORE_STACK      1
5135
+// EPILOGUE_USES(regno)
5136
+// EH_USES(regno)
5137
+// TARGET_ASM_OUTPUT_MI_THUNK
5138
+// TARGET_ASM_CAN_OUTPUT_MI_THUNK
5139
+
5140 102 dgisselq
+/* 17.09.12 Generating code for profiling */
5141 111 dgisselq
+// FUNCTION_PROFILER
5142
+// PROFILE_HOOK
5143
+// NO_PROFILE_COUNTERS
5144
+// PROFILE_BEFORE_PROLOGUE
5145
+// TARGET_KEEP_LEAF_WHEN_PROFILED
5146
+
5147 102 dgisselq
+/* 17.09.13 Permitting tail calls*/
5148 111 dgisselq
+
5149
+/* TARGET_FUNCTION_OK_FOR_SIBCALL(DECL,EXP) ... True if it is OK to do sibling
5150
+ * call optimizations for the specified call expression EXP.  DECL will be the
5151
+ * called function, or NULL if this is an indirect call.
5152
+ *
5153
+ * It is not uncommon for limitations of calling conventions to prevent tail
5154
+ * calls to functions outside the current unit of translation, or during PIC
5155
+ * compilation.  The hook is used to enforce these restrictions, as the sibcall
5156
+ * md pattern can not fail, or fall over to a 'normal' call.  The criteria for
5157
+ * successful sibling call optimization may vary greatly between different
5158
+ * architectures.
5159
+ *
5160
+ * ?? What's a sibling call?
5161
+ */
5162
+
5163
+// TARGET_EXTRA_LIVE_ON_ENTRY
5164
+// TARGET_SET_UP_BY_PROLOGUE
5165
+// TARGET_WARN_FUNC_RETURN
5166
+
5167 102 dgisselq
+/* 17.09.14 Stack smashing protection */
5168 111 dgisselq
+// TARGET_STACK_PROTECT_GUARD
5169
+// TARGET_STACK_PROTECT_FAIL
5170
+// TARGET_SUPPORTS_SPLIT_STACK
5171
+
5172 102 dgisselq
+/* 17.09.15 Miscellaneous register hooks */
5173
+
5174 111 dgisselq
+// TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
5175
+
5176 102 dgisselq
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
5177
+ * ZipCPU --- default is good enough for us.
5178
+ */
5179
+
5180
+/* 17.10 Implementing VARARGS MACROS */
5181
+
5182
+/* ...
5183
+ */
5184
+
5185
+/* void TARGET_SETUP_INCOMING_VARARGS(A,M,T,I,S) ... This target hook offers an
5186
+ * alternative to using __builtin_saveregs and defining the hook TARGET_EXPAND..
5187
+ * _BUILTIN_SAVEREGS.  Use it to store the anonymous register arguments into the
5188
+ * stack so that all the arguments appear to have been passed consecutively
5189
+ * on the stack.  Once this is done, you can use the standard implementation
5190
+ * of varargs that works for machines that pass all their arguments on the
5191
+ * stack.
5192
+ */
5193
+// #undef      TARGET_SETUP_INCOMING_VARARGS
5194
+// #define     TARGET_SETUP_INCOMING_VARARGS   zip_setup_incoming_varargs
5195
+
5196
+/* ...
5197
+ */
5198
+
5199
+/* 17.11 Trampolines for Nested Functions */
5200
+
5201
+/* TARGET_ASM_TRAMPOLINE_TEMPLATE ... This hook is called by
5202
+ * assemble_trampoline_template to output, on the stream f, assembler code for
5203
+ * a block of data that contains the constant parts of a trampoline.  This code
5204
+ * should not include a label--the label is taken care of automatically.
5205
+ *
5206
+ * ZipCPU -- looks like we need to do this.
5207
+ */
5208
+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
5209
+#define        TARGET_ASM_TRAMPOLINE_TEMPLATE  zip_asm_trampoline_template
5210
+
5211
+/* TRAMPOLINE_SECTION ... Return the section into which the trampoline template
5212
+ * is to be placed.  The default value is readonly_data_section.
5213
+ *
5214
+ * ZipCPU--default should be good enough.
5215
+ */
5216
+
5217
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
5218
+ * as an integer.
5219
+ *
5220
+ * ZipCPU--it's three instructions, or 96 bits.  However, 32-bits is our minimal
5221
+ * addressible unit, so what size do we offer here?  We'll stick with the number
5222
+ * of bytes, but we may need to change this later.
5223
+ *
5224
+ */
5225
+// #warning "May need to redefine trampoline_size in words, not bytes"
5226
+#undef TRAMPOLINE_SIZE
5227
+#define        TRAMPOLINE_SIZE 3
5228
+
5229
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
5230
+ *
5231
+ * Well that's well known in ZipCPU --- 32-bits.
5232
+ */
5233
+#undef TRAMPOLINE_ALIGNMENT
5234
+#define        TRAMPOLINE_ALIGNMENT    32
5235
+
5236
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
5237
+ * initialize a trampoline.  m_tramp is an RTX for the memory block for the
5238
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion;  CH is an
5239
+ * rtx for the static chain value that should be passed to the function when
5240
+ * it is called.
5241
+ *
5242
+ * ZipCPU ... Can we get by without this?
5243
+ */
5244
+#undef TARGET_TRAMPOLINE_INIT
5245
+#define        TARGET_TRAMPOLINE_INIT  zip_trampoline_init
5246
+
5247
+/* TARGET_TRAMPOLINE_ADJUST_ADDRESS(RTX) ... This hook should perform any
5248
+ * machine-specific adjustment in the address of the trampoline.  Its argument
5249
+ * contains the address of the memory block that was passed to
5250
+ * TARGET_TRAMPOLINE_INIT.  In case the address to be used for a function call
5251
+ * should be different from the address at which the template was stored, the
5252
+ * different address should be returned; otherwise addr should be returned
5253
+ * unchanged.  If the hook is not defined, RTX (addr) will be used for function
5254
+ * calls.
5255
+ *
5256
+ * ZipCPU--works for us!
5257
+ */
5258
+
5259
+/* CLEAR_INSN_CACHE(BEG,END) ... If defined, expands to a C expression clearing
5260
+ * the instruction cache in the specified interval.  The definition of this
5261
+ * macro would typically be a series of asm statements.   Both BEG and END are
5262
+ * pointer expressions.
5263
+ *
5264
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
5265
+ */
5266
+
5267
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
5268 111 dgisselq
+ * subroutine to do their work.  The macro should expand to a series of asm
5269 102 dgisselq
+ * statements which will be compiled with GCC.  They go in a library function
5270
+ * named __transfer_from_trampoline.
5271
+ *
5272
+ * We may need to rethink trampolines on ZipCPU.
5273
+ */
5274
+
5275
+
5276
+/* 17.12 Implicit Calls to Library Routines */
5277
+
5278
+/* DECLARE_LIBRARY_RENAMES
5279
+ *
5280
+ * ZipCPU: Don't need it.
5281
+ */
5282
+
5283
+/* TARGET_INIT_LIBFUNCS(VOID) ... This hook should declare additional library
5284
+ * routines or rename existing ones, using the functions set_optab_libfunc and
5285
+ * init_one_libfunc defined in optabs.c.  init_optabs calls this macro after
5286
+ * initializing all the normal library routines.
5287
+ *
5288
+ * Most ports don't need to define this hook, so we won't either.
5289
+ */
5290
+
5291
+/* TARGET_LIBFUNC_GNU_PREFIX ... If false (the default), internal library
5292
+ * routines start with two underscores.  If set to true, these routines start
5293
+ * with __gnu_ instead.
5294
+ *
5295
+ * ZipCPU: No change necessary.
5296
+ */
5297
+
5298
+/* FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE,COMPARISON) ... This macro should return
5299
+ * true if the library routine that implements the floating point comparison
5300
+ * operator comparison in mode mode will return a boolean and false if it will
5301
+ * return a tristate.
5302
+ *
5303
+ * Most ports don't need to define this macro, so Zip CPU won't either.
5304
+ */
5305
+
5306
+/* TARGET_HAS_NO_HW_DIVIDE ... This macro should be defined if the target has no
5307
+ * hardware divide instructions.  If this macro is defined, GCC will use an
5308
+ * algorithm which makes use of simple logical and arithmetic operations for
5309
+ * 64-bit division.  If the macro is not defined, GCC will use an algorithm
5310
+ * which makes use of a 64-bit by 32-bit divide primitive.
5311
+ *
5312
+ * Zip CPU, though, doesn't have the 64-bit by 32-bit divide primitive, thus
5313
+ * we have no HW DIVIDE (for now).
5314
+ */
5315
+#define        TARGET_HAS_NO_HW_DIVIDE
5316
+
5317
+/* TARGET_EDOM ... The value of EDOM on the target machine, as a C integer
5318
+ * expression.  If you don't define this macro, GCC does not attempt to deposit
5319
+ * the value of EDOM into errno directly.  Look in /usr/include/errno.h to find
5320
+ * the value of EDOM on your system.
5321
+ *
5322
+ * EDOM is the error created when a math argument is out of the domain of the
5323
+ * function.
5324
+ *
5325
+ * ZipCPU: Don't need it---I don't think.
5326
+ */
5327
+
5328
+/* GEN_ERRNO_RTX ... Define this macro as a C exrpession to create an rtl
5329
+ * expression that refers to the global "variable" errno.  (On certain
5330
+ * systems, errno may not actually be a variable.)  If you don't define this
5331
+ * macro, a reasonable default is used.
5332
+ *
5333
+ * ZipCPU --- if a reasonable default is used, we'll use that--especially since
5334
+ * I doubt we'll be using errno for a while.
5335
+ */
5336
+
5337
+/* NEXT_OBJC_RUNTIME ... Set this macro to 1 to use the "NeXT" Objective-C
5338
+ * message sending conventions by default.  This calling convention involves
5339
+ * passing the object, the selector and the method arguments all at once to the
5340
+ * method-lookup library function.  This is the usual setting when targetting
5341
+ * Darwin/Mac OS X systems, which have the NeXT runtime installed.
5342
+ *
5343
+ * If the macro is set to 0, ...
5344
+ *
5345
+ * Doesn't look relevant (yet) for the Zip CPU--especially since we don't have
5346
+ * an O/S yet.
5347
+ */
5348
+
5349
+
5350
+
5351
+/* 17.13 Addressing Modes */
5352
+
5353
+/* C expressions that are nonzero if the machine supports pre-increment,
5354
+ * pre-decrement, post-increment, or post-decrement addressing respectively.
5355
+ */
5356
+#define        HAVE_PRE_INCREMENT      (0)
5357
+#define        HAVE_PRE_DECREMENT      (0)
5358
+#define        HAVE_POST_INCREMENT     (0)
5359
+#define        HAVE_POST_DECREMENT     (0)
5360
+
5361
+/* C expression that is nonzero if the machine supports pre- or post- address
5362
+ * side-effect generation involving constants other than the size of the memory
5363
+ * operand.
5364
+ */
5365
+#define        HAVE_PRE_MODIFY_DISP    (0)
5366
+#define        HAVE_POST_MODIFY_DISP   (0)
5367
+
5368
+/* C expression that is non-zero if the machine supports pre- or post-address
5369
+ * side-effect generation involving a register displacement.
5370
+ */
5371
+#define        HAVE_PRE_MODIFY_REG     (0)
5372
+#define        HAVE_POST_MODIFY_REG    (0)
5373
+
5374
+/* CONSTANT_ADDRESS_P(X) ... A C expression that is 1 if the RTX X is a constant
5375
+ * which is a valid address.  On most machines the default definition ... is
5376
+ * acceptable, but a few machines are more restrictive as to which constant
5377
+ * addresses are supported.
5378
+ *
5379
+ * Zip CPU is designed for offset addresses, not constant addresses.  Although
5380
+ * the CPU will support 18-bit signed constant addresses, the assembler and
5381
+ * general programming model do not.  Further, without knowing where the final
5382
+ * address will be located, this is an unusable model.  Therefore we will
5383
+ * define this as not supported.
5384
+ *
5385
+ * In hindsight, this isn't true--labels and symbols are valid addresses, and
5386
+ * they are also constant addresses.  Hence, we leave this at its default.
5387
+ */
5388
+// #undef      CONSTANT_ADDRESS_P
5389
+// #define     CONSTANT_ADDRESS_P(X)   (0)
5390
+
5391 111 dgisselq
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code,
5392
+ * accepts integer values expressions whose values are not explicitly known,
5393
+ * such as symbol_ref, label_ref, and high expressions and const arithmetic
5394
+ * expressions, in addition to const_int and const_double expressions.
5395 102 dgisselq
+ *
5396
+ * Huh???
5397
+ */
5398
+// #define CONSTANT_P(X) ???
5399
+
5400 111 dgisselq
+/* MAX_REGS_PER_ADDRESS ... A number, the maximum number of registers that can
5401
+ * appear in a valid memory address.  Note that it is up to you to specify a
5402
+ * value equal to the maximum number that TARGET_LEGITIMATE_ADDRESS_P would
5403
+ * ever accept.
5404 102 dgisselq
+ */
5405
+#define        MAX_REGS_PER_ADDRESS    1
5406
+
5407
+/* TARGET_LEGITIMATE_ADDRESS_P(MODE,RTX,STRICT) ... A function that returns
5408
+ * whether RTX is a legitimate memory address on the target machine for a
5409
+ * memory operation of mode MODE.
5410
+ */
5411
+#undef TARGET_LEGITIMATE_ADDRESS_P
5412
+#define TARGET_LEGITIMATE_ADDRESS_P    zip_legitimate_address_p
5413
+
5414
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
5415
+ * default 'm' character for general memory addresses.  This defines the
5416
+ * constraint letter which matches the memory addresses accepted by
5417
+ * TARGET_LEGITIMATE_ADDRESS_P.  Define this macro if you want to support new
5418
+ * address format in your back end without changing the semantics of the 'm'
5419
+ * constraint.  This is necessary in order to preserve functionality of inline
5420
+ * assembly constructs using the 'm' constraint.
5421
+ *
5422
+ * ZipCPU--doesn't look like we need to define this at all.
5423
+ */
5424
+
5425
+/* FIND_BASE_TERM(X) ... A C expression to determine the base term of address
5426
+ * X or to provide a simplified version of X from which alias.c can easily find
5427
+ * the base term.  This macro is used in only two places: find_base_value and
5428
+ * find_base_term in alias.c.
5429
+ *
5430
+ * It is always safe for this macro  to not be defined.  It exists so that
5431
+ * alias analysis can understand machine-dependent addresses.
5432
+ *
5433
+ * ZipCPU: We'll skip this then.
5434
+ */
5435
+
5436
+/* TARGET_LEGITIMIZE_ADDRESS(RTX,OLD,MODE) ... This hook is given an invalid
5437
+ * memory address RTX for an operand of mode MODE and should try to return a
5438
+ * valid memory address.  RTX will always be the result of a call to
5439
+ * break_out_memory_refs, and OLD will be the operand that was given to that
5440
+ * function to produce RTX.
5441
+ *
5442 111 dgisselq
+ * ZipCPU --
5443 102 dgisselq
+ */
5444 111 dgisselq
+#undef TARGET_LEGITIMIZE_ADDRESS
5445
+#define        TARGET_LEGITIMIZE_ADDRESS       zip_legitimize_address
5446 102 dgisselq
+
5447
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
5448
+ * that attempts to replace X, which is an address that needs reloading, with
5449
+ * a valid memory address for an operand of mode MODE.  WIN will be a C
5450
+ * statement label elsewhere in the code.  It is not necessary to define this
5451
+ * macro, but it might be useful for performance reasons.
5452
+ *
5453
+ * ZipCPU: This is worth coming back to, according to the notes page, but it
5454
+ * may also be a difficult macro to use.  Look at other implementations before
5455
+ * we dive into this.
5456
+ */
5457
+// #undef LEGITIMIZE_RELOAD_ADDRESS
5458
+// #define LEGITIMIZE_RELOAD_ADDRESS
5459
+
5460
+/* TARGET_MODE_DEPENDENT_ADDRESS_P(ADDR,SPACE) ... This hook returns true
5461
+ * if memory address addr in address space addrspace can have different meanings
5462
+ * depending on the machine mode of the memory reference it is used for or if
5463
+ * the address is valid for some modes but not others.
5464
+ */
5465
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
5466
+#define        TARGET_MODE_DEPENDENT_ADDRESS_P         zip_mode_dependent_address_p
5467
+
5468 111 dgisselq
+/* TARGET_LEGITIMATE_CONSTANT_P(MODE,RTX) ... This hook returns true if x is a
5469
+ * legitimate constant for a MODE-mode immediate operand on the target machine.
5470
+ * You can assume the RTX satisfies CONSTANT_P, so you need not check this.
5471
+ *
5472
+ * The default definition returns true.
5473 102 dgisselq
+ */
5474
+
5475
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
5476
+ */
5477
+
5478
+/* TARGET_CONST_NOT_OK_FOR_DEBUG_P(RTX) ... This hook should return true if RTX
5479
+ * should not be emitted into debug sections.
5480
+ */
5481
+
5482
+/* TARGET_CANNOT_FORCE_CONST_MEM(MODE,RTX) ... This hook should return true if
5483
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
5484
+ * MODE is the mode of X.  The default version returns false.
5485
+ */
5486 111 dgisselq
+// #define     TARGET_CANNOT_FORCE_CONST_MEM   hook_bool_mode_rtx_false
5487 102 dgisselq
+
5488
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
5489
+ * if pool entries for constant RTX can be placed in an object_block structure.
5490
+ * MODE is the mode of X.  The default version returns false for all constants.
5491
+ *
5492
+ *????
5493
+ */
5494
+// #warning "Huh?"
5495
+
5496
+/* TARGET_USE_BLOCKS_FOR_DECL_P(DECL) ... This hook should return true if pool
5497
+ * entries for DECL should be placed in an object_block structure.  The default
5498
+ * version returns true for all DECL's.
5499
+ *
5500
+ * Sounds good.
5501
+ */
5502
+
5503
+/* TARGET_BUILTIN_RECIPROCAL(TREE) ... This hook should return the DECL of a
5504
+ * function that implements the reciprocal of the machine specific builtin
5505
+ * function fndecl, or NULL_TREE if such a function is not available.
5506
+ */
5507
+
5508
+/* TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD(VOID) ... This hook should return the
5509
+ * DECL of a function f that given an address addr as an argument returns a mask
5510
+ * m that can be used to extrract from two vectors the relevant data that
5511
+ * resides in addr in case addr is not properly aligned.
5512
+ *
5513
+ * Zip CPU does not support vectorization.
5514
+ */
5515
+
5516
+/* Other vector, SIMD, and GOACC macros skipped as Zip CPU doesn't support
5517
+ * such data accesses and manipulation.
5518
+ */
5519
+
5520
+/* 17.14 Anchored Addresses */
5521
+
5522
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
5523
+ * a section anchor.  On most targets, it should be the smallest offset that
5524
+ * can be applied to a base register while still giving a legitimate address for
5525
+ * every mode.  The default value is 0.
5526
+ *
5527
+ * On the Zip CPU, this is the minimum operand B offset to a LOD or STO
5528
+ * operation, which would be a signed 14 bit number.
5529
+ */
5530
+#undef TARGET_MIN_ANCHOR_OFFSET
5531
+#define TARGET_MIN_ANCHOR_OFFSET       zip_min_anchor_offset
5532
+
5533
+/* TARGET_MAX_ANCHOR_OFFSET ... Like TARGET_MIN_ANCHOR_OFFSET, but the maximum
5534
+ * (inclusive) offset that should be applied to section anchors.  The default
5535
+ * value is 0.
5536
+ */
5537
+#undef TARGET_MAX_ANCHOR_OFFSET
5538
+#define TARGET_MAX_ANCHOR_OFFSET       zip_max_anchor_offset
5539
+
5540
+/* TARGET_ASM_OUTPUT_ANCHOR(RTX) ... Write the assembly code to define section
5541
+ * anchor RTX, which is a SYMBOL_REF for which 'SYMBOL_REF_ANCHOR_P(RTL) is
5542
+ * true.  The hook is called with the assembly output position set to the
5543
+ * beginning of SYMBOL_REF_BLOCK(X).
5544
+ *
5545
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
5546
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'.  If ASM_OUTPUT_DEF
5547
+ * is not available, the hook's default definition is NULL, which disables the
5548
+ * use of section anchors altogether.
5549
+ *
5550
+ * Section anchors will be very valuable in Zip CPU assembly, therefore we
5551
+ * must define this hook.
5552
+ */
5553
+// #undef      TARGET_ASM_OUTPUT_ANCHOR
5554
+// #define     TARGET_ASM_OUTPUT_ANCHOR        zip_asm_output_anchor
5555
+
5556
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
5557
+ * to use anchors to access SYMBOL_REF X.  You can assume SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
5558
+ *
5559
+ * The default version is correct for most targets, but you might need to intercept this hook to handle things like target specific attributes or target-specific sections.
5560
+ *
5561
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
5562
+ */
5563
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
5564
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P     zip_use_anchors_for_symbol_p
5565
+
5566
+/* 17.15 Condition Code Status */
5567
+
5568
+/* 17.15.1 Representation of condition codes using (cc0) --- that's us */
5569
+
5570
+/* CC_STATUS_MDEP ... C code for a data type which is used for declaring
5571
+ * the mdep component of cc_status.  It defaults to int.
5572
+ *
5573
+ * ZipCPU---Int is good for us.
5574
+ */
5575
+
5576
+/* CC_STATUS_MDEP_INIT ... A C expression to initialize the mdep field to
5577
+ * "empty".  The default definition does nothing, since most machines don't
5578
+ * use the field anyway.  If you want to use the field, you should probably
5579
+ * define  this macro to initialize it.
5580
+ */
5581
+
5582
+/* NOTICE_UPDATE_CC(EXP, INSN) ... A C compound statement to set the components
5583
+ * of cc_status appropriately for an insn insn whose body is exp.  It is this
5584
+ * macro's responsibility to recognize insns that set the condition code as
5585
+ * a byproduct of other activity as well as those that explicitly set (cc0).
5586
+ *
5587
+ * ZipCPU --- We need this, as not all expressions set (cc0).
5588
+ *
5589
+ */
5590 122 dgisselq
+#ifdef HAVE_cc0
5591 102 dgisselq
+#define        NOTICE_UPDATE_CC(EXP, INSN)     zip_update_cc_notice(EXP, INSN)
5592 122 dgisselq
+#endif
5593 102 dgisselq
+
5594
+
5595
+/* 17.15.2 Representation of condition codes using registers */
5596
+/* ... which the ZipCPU doesn't have.  The ZipCPU has a CC0 register, and hence
5597
+ * this section isn't supposed to apply.
5598
+ */
5599
+
5600 122 dgisselq
+/* SELECT_CC_MODE(op, x, y) ... On many machines, the condition code may be
5601
+ * produced by other instructions than compares, for example the branch can use
5602
+ * directyl the condition code set by a subtract instruction.  However, on some
5603
+ * machines when the condition code is set this way some bits (such as the
5604
+ * overflow bit) are not set in the same way as a test instruction, so that a
5605
+ * different branch instruction must be used for some conditional branches.
5606
+ * When this happens, use the machinemode of the condition code register to
5607
+ * record different formats of the condition code register.  Modes can also be
5608
+ * used to reccord which compare instruction (e.g. a signed or an unsigned
5609
+ * comparison) produced the condition codes.
5610
+ *
5611
+ * If other modes than CCmode are required, add them to 'machine-modes.def' and
5612
+ * define SELECT_CC_MODE to choose a mode given an operand of a compare.  This
5613
+ * is needed because the modes have to be chosen not only during RTL generation
5614
+ * but also, for example, by instruction combination.  The result of
5615
+ * SELECT_CC_MODE should be consistent with the mode used in the patterns; ...
5616
+ *
5617
+ * ZipCPU ... We have only one CC Mode, so we'll use the CCmode defined in
5618
+ * machine-modes.def and should be fine with it.  Hence, this doesn't need
5619
+ * to be defined.
5620 102 dgisselq
+ */
5621
+
5622
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines
5623
+ * (such as the ZipCPU) not all possible comparisons are defined, but you can
5624
+ * convert an invalid comparison into a valid one.  For example, the Alpha
5625
+ * does not have a GT comparison, but you can use an LT comparison instead and
5626
+ * swap the order of the operands.
5627
+ *
5628
+ * On such machines, implement this hook to do any required conversions:  code
5629
+ * is the initial comparison code and op0 and op1 are the left and right
5630
+ * operands of the comparison, respectively.  If op0_preserve_value is true the
5631
+ * implementation is not allowed to change the value of op0 since the value
5632
+ * might be used in RTXs which aren't comparisons.  E.g. the implementation is
5633
+ * not allowed to swap operands in that case.
5634
+ *
5635
+ * GCC will not assume that the comparison resulting from this macro is valid
5636
+ * but will see if the resulting insn matches a pattern in the 'md' file.
5637
+ *
5638
+ * You need not implement this hook if it would never change the comparison
5639
+ * code or operands.
5640
+ *
5641
+ * In the case of the ZipCPU, the ZipCPU only keeps track of 8 possible
5642
+ * comparisons, and bastardizing other comparisons into those 8 is extremely
5643
+ * painful.  Therefore, we *need* this capability to make certain we can use
5644
+ * our comparisons successfully.
5645
+ *
5646
+ * The only problem is ... this hook appears to only be called on non-CC0
5647
+ * machines.  Hence, defining it hasn't done anything for us.
5648
+ */
5649 122 dgisselq
+#define        TARGET_CANONICALIZE_COMPARISON  zip_canonicalize_comparison
5650 102 dgisselq
+
5651 122 dgisselq
+/* REVERSIBLE_CC_MODE(MODE) ... A C expression whose value is one if it is
5652
+ * always safe to reverse a comparison whose mode is MODE.  If SELECT_CC_MODE
5653
+ * can ever return MODE for a floating-point inequality comparison, than
5654
+ * REVERSIBLE_CC_MODE(MODE) must be zero.
5655
+ *
5656
+ * You need not define this macro if it would always return zero or if the
5657
+ * floating-point format is anything other than IEEE_FLOAT_FORMAT.  For example,
5658
+ * here ...
5659
+ *
5660
+ * ZipCPU -- We'll always return zero, so this need not be defined.
5661
+ */
5662
+
5663
+/* REVERSE_CONDITION(CODE,MODE) ... A C expression whose value is reversed
5664
+ * condition code of thecode for comparison done in CC_MODE MODE.  This macro
5665
+ * is used only in case REVERSIBLE_CC_MODE(MODE) is nonzero. ...
5666
+ *
5667
+ * ZipCPU ... Since REVERSIBLE_CC_MODE(MODE) will always be zero, we'll leave
5668
+ * this undefined.
5669
+ */
5670
+
5671
+/* bool TARGET_FIXED_CONDITION_CODE_REGS(int *, int *) ... On targets which do
5672
+ * not use (cc0), and which use a hard register rather than a pseudo-register
5673
+ * to hold condition codes, the regular CSE passes are often not able to
5674
+ * identify cases in which the hard register is set to a common value.  Use this
5675
+ * hook to enable a small pass which optimizes such cases.  This hook should
5676
+ * return true to enable this pass, and it should set the integers to which its
5677
+ * arguments point to the hard register numbers used for condition codes.  When
5678
+ * there is only one such register, as is true on most systems, the integer
5679
+ * pointed to by p2 should  be set to INVALID_REGNUM.
5680
+ *
5681
+ * The default version of this hook returns false.
5682
+ *
5683
+ * ZipCPU --- I like the idea of enabling optimizations.  Let's return
5684
+ * something other than false.
5685
+ */
5686
+#define        TARGET_FIXED_CONDITION_CODE_REGS        zip_fixed_condition_code_regs
5687
+
5688
+/* machine_mode TARGET_CC_MODES_COMPATIBLE(M1,M2) .. On targets which use
5689
+ * multiple condition code modes in class MODE_CC, it is sometimes the case
5690
+ * that a comparison can be validly done in more than one mode.  On such a
5691
+ * system, define this target hook to take two mode arguments and to return a
5692
+ * mode in which both comparisons may be validly done.  If there is no such
5693
+ * mode, return VOIDmode.
5694
+ *
5695
+ * The default version of this hook checks whether the modes are the same.  If
5696
+ * they are, it returns that mode.  If they are different, it returns VOIDmode.
5697
+ *
5698
+ * ZipCPU--Given that we only have the one CCmode, the default definition works
5699
+ * well enough for us.
5700
+ */
5701
+
5702
+/* unsigned int TARGET_FLAGS_REGNUM ... If the target has a dedicated flags
5703
+ * register, and it needs to use the post-reload comparison elimination pass,
5704
+ * then this value should be set appropriately.
5705
+ *
5706
+ * ZipCPU---Looks like we can set this easily enough without any problems.
5707
+ */
5708
+#undef TARGET_FLAGS_REGNUM
5709
+#define        TARGET_FLAGS_REGNUM     zip_CC
5710
+
5711 102 dgisselq
+/* 17.16 Relative costs of operations */
5712
+
5713
+
5714
+// #define     REGISTER_MOVE_COST(MODE,FROM,TO)        ((MODE==DImode)||(MODE==DFmode))?4:2
5715
+// #define     TARGET_REGISTER_MOVE_COST
5716
+// #define     MEMORY_MOVE_COST(MODE, CLASS, IN)       ((MODE==DImode)||(MODE==DFmode))?8:7
5717
+/* TARGET_REGISTER_MOVE_COST(M,FRM,TO) ... This target hook should return the
5718
+ * cost of moving data of mode M from a register in class FRM to one in class
5719
+ * TO.  The classes are expressed using the enumeration values such as
5720
+ * GENERAL_REGS.  A value of 2 is the default; other values are interpreted
5721
+ * relative to that.
5722
+ *
5723
+ * It is not required that the cost always equal 2 when FROM is the same as TO;
5724
+ * on some machines it is expensive to move between registers if they are not
5725
+ * general registers.
5726
+ *
5727
+ * If reload sees ...
5728
+ *
5729
+ * ZipCPU ... We can leave this at its default value of 2.
5730
+ */
5731
+
5732
+/* TARGET_MEMORY_MOVE_COST(MOD,CL,IN) ... This target hook should return the
5733
+ * cost of moving data of mode MOD between a register of class CL and memory.
5734
+ * IN is false if the value is to be written to memory, true if it is to be
5735
+ * read in.  This cost is relative to those in TARGET_REGISTER_MOVE_COST.
5736
+ * If moving between registers and memory is more expensive that between two
5737
+ * registers, you should add this target hook to express the relative cost.
5738
+ *
5739
+ * If you do not add this target hook, GCC uses a default cost of 4 plus the
5740
+ * cost of copying via a secondary reload register, if one is needed.  If your
5741
+ * machine requires a secondary reload register to copy between memory and a
5742
+ * register of CL but the reload mechanism is more complex than copying via
5743
+ * an intermediate, use this target hook to reflect the actual cost of the
5744
+ * move.
5745
+ *
5746
+ * ZipCPU --- Memory moves are more expensive than twice the cost of register
5747
+ * moves, so let's make certain this is defined.
5748
+ */
5749
+#define        TARGET_MEMORY_MOVE_COST zip_memory_move_cost
5750
+
5751
+// #warning "This needs to be double checked, and annotated"
5752 111 dgisselq
+#define        BRANCH_COST(SPEED,PREDICTABLE)          ((PREDICTABLE)?2:5)
5753 102 dgisselq
+
5754
+/* Define this macro as a C expression which is nonzero if accessing less than
5755
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
5756
+ * a word of memory.
5757
+ */
5758
+#define        SLOW_BYTE_ACCESS        1
5759
+
5760
+/* MOVE_RATIO(SPD) ... The threshold of number of scalar memory-to-memory move
5761
+ * instructions, below which a sequence of instructions should be generated
5762
+ * instead of a string move instruction or a library call.  Increasing the
5763
+ * value will always make code faster, but eventually incurs high cost in
5764
+ * increased code size.
5765
+ */
5766
+#define        MOVE_RATIO(SPD) 5
5767
+
5768
+/* TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(SZ,ALGN,OP,SPD) ...
5769
+ */
5770
+// #undef      TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)
5771
+// #define     TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)// needs hook
5772
+
5773
+/* CLEAR_RATIO(SPD) ... The threshold number of scalar move instructions, below
5774
+ * which a sequence of instructions should be generated to clear memory instead
5775
+ * of a string clear instruction or a library call.  Increasing the value will
5776
+ * always make the code faster, but eventually incurs high cost in increased
5777
+ * code size.
5778
+ */
5779
+#define        CLEAR_RATIO(SPD)        MOVE_RATIO(SPD)
5780
+
5781
+/* NO_FUNCTION_CSE ... Define this macro to be true if it is as good or better
5782
+ * to call a constant function address than to call an address kept in a
5783
+ * register.
5784
+ *
5785
+ * On the Zip CPU, constant function addresses--especially relative ones,
5786
+ * can be optimized into a single cycle delay.  Register jumps will always
5787
+ * stall the whole (5-stage) pipeline.
5788
+ */
5789
+#define        NO_FUNCTION_CSE
5790
+
5791 111 dgisselq
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
5792
+ * the relative costs of RTL expressions.
5793
+ *
5794
+ * The cost may depend on the precise form of the expression, which is avaialble
5795
+ * for examination in X, and the fact that X appears as operand OPNO of an
5796
+ * expression with rtx code OUTER.  That is, the hook can assume that there is
5797
+ * some RTX Y such that GET_CODE(Y)==OUTER and such that either (a) XEXP(Y,OPNO)
5798
+ * == X or (b) XVEC(Y,OPNO) contains X.
5799
+ *
5800
+ * ...
5801
+ * The hook returns true when all subexpressions of x have been processed and
5802
+ * false when rtx_cost should recurse.
5803 102 dgisselq
+ */
5804 111 dgisselq
+
5805 102 dgisselq
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
5806
+ * addressing mode that contains ADDR.  If not defined, the cost is computed
5807
+ * from the ADDR expression and the TARGET_RTX_COST hook.  In cases where more
5808
+ * than one form of an address is known, the form with the lowest cost will be
5809
+ * used.  If multiple forms have the same, lowest, cost, the one that is the
5810
+ * most complex will be used.
5811
+ *
5812
+ * ZipCPU really has only one address cost, the only type of address it
5813
+ * supports.  Sure, index addressing would cost us more, but we don't support
5814
+ * that so ... I think we're okay defining this as a constant.  Indeed, the
5815
+ * docs state that, "On RISC amchines, all instructions normally have the same
5816
+ * length and execution time.  Hence all addresses will have equal costs."
5817
+ */
5818
+#undef TARGET_ADDRESS_COST
5819
+#define        TARGET_ADDRESS_COST     zip_address_cost
5820
+
5821
+
5822
+/* TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P ... This predicate controls the use
5823
+ * of the eager delay slot filler to disallow speculatively executed
5824
+ * instructions being placed in delay slots.  Targets such as certain MIPS
5825
+ * architectures posess both branches with and without delay slots.  As the
5826
+ * eager delay slot filler can decrease performance, disabling it is beneficial
5827
+ * when ordinary branches are available.  Use of delay slot branches filled
5828
+ * using basic filler is often still desirable as the delay slot can hide a
5829
+ * pipeline bubble.
5830
+ */
5831
+// How should Zip CPU define this--we have no delay slots.
5832
+
5833
+
5834
+/* 17.17 Instruction Scheduler */
5835
+
5836
+#define        TARGET_SCHED_ISSUE_RATE zip_sched_issue_rate
5837
+
5838
+/* 17.18 Dividing the Output into Sections */
5839
+
5840
+/* Switch to the text or data segment. */
5841
+#define        TEXT_SECTION_ASM_OP     "\t.text"
5842
+#define        DATA_SECTION_ASM_OP     "\t.data"
5843
+
5844
+// #undef      TARGET_LIBGCC_SDATA_SECTION
5845
+// #define     TARGET_LIBGCC_SDATA_SECTION     ".sdata"
5846
+
5847
+
5848
+/* 17.19 Position Independent Code */
5849
+
5850
+#define        PIC_OFFSET_TABLE_REGNUM                 zip_GOT
5851
+#define        PIC_OFFSET_TABLE_REG_CALL_CLOBBERED     0
5852
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
5853
+
5854
+/* 17.20 Defining the Output Assembler Language */
5855
+
5856
+/* 17.20.4 Output and Generation of Labels */
5857
+
5858
+/* ASM_OUTPUT_LABEL
5859
+ * ... A default definition of this macro is provided which is correct for
5860
+ * most systems.
5861
+ */
5862
+
5863
+/* ASM_OUTPUT_FUNCTION_LABEL
5864
+ * ... if not defined, then the function name is defined in the usual manner
5865
+ * as a label.
5866
+ */
5867
+
5868
+/* ASM_OUTPUT_INTERNAL_LABEL ... Identical to ASM_OUTPUT_LABEL, except that name
5869
+ * is known to refer to a compiler-generated label.  The default definition
5870
+ * uses assemble_name_raw, which is like assemble_name except that it is more
5871
+ * efficient.
5872
+ */
5873
+
5874
+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive
5875
+ * to specify the size of a symbol, without any arguments.  ON systems that
5876
+ * use ELF, the dfault is "\t.size\t"; on other systems, the default is not to
5877
+ * define this macro.
5878
+ *
5879
+ * Define this amcro only if it is correct to use the default definitions of
5880
+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.
5881
+ * If you need your own custom definitions of those macros, or if you do not
5882
+ * need explicit symbol sizes at all, do not define this macro.
5883
+ */
5884
+
5885
+/* ASM_OUTPUT_SIZE_DIRECTIVE
5886
+ * ASM_OUTPUT_MEASURED_SIZE
5887
+ */
5888
+
5889
+/* NO_DOLLAR_IN_LABEL ... Define this macro if the assembler does not accept
5890
+ * the character '$' in label names.  By default constructors and destructors
5891
+ * in G++ have "$" in the identifiers.  If this label is defined, '.' is
5892
+ * used instead.
5893
+ */
5894
+
5895
+/* NO_DOT_IN_LABEL ... Define this macro if the assembler does not accept the
5896
+ * character '.' in label names.  By default constructors and destructors in
5897
+ * G++ have names that use '.'.  If this macro is defined, these names are
5898
+ * rewritten to avoid '.'.
5899
+ */
5900
+
5901
+/* TYPE_ASM_OP ... A C string containing the appropriate assembler directive to
5902
+ * specify the type of a symbol, without any arguments.  On systems that use
5903
+ * ELF the default in config/elfos.h is "\t.type\t"; on other systems, the default is not to define this macro.
5904
+ *
5905
+ * Define this macro only if it is correct to use the default definition of
5906
+ * ASM_OUTPUT_TYPE_DIRECTIVE forr your system.  If you need your own custom
5907
+ * definition of this macr, or if you do not need explicit symbol types at all,
5908
+ * do not define this macro.
5909
+ */
5910
+
5911
+/* TYPE OPERAND_FMD ... A
5912
+ */
5913
+
5914
+/* ASM_OUTPUT_TYPE_DIRECTIVE
5915
+ */
5916
+
5917
+/* ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) ...
5918
+ * if this macro is not defined, then the function name is defined in the usual
5919
+ * manner as a label (by means of ASM_OUTPUT_FUNCTION_LABEL).
5920
+ */
5921
+
5922
+/* ASM_DECLARE_FUNCTION_SIZE
5923
+ * ASM_DECLARE_COLD_FUNCTION_NAME
5924
+ * ASM_DECLARE_COLD_FUNCTION_SIZE
5925
+ * ASM_DECLARE_OBJECT_NAME
5926
+ * TARGET_ASM_DECLARE_CONSTANT_NAME
5927
+ */
5928
+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement
5929
+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for
5930
+ * claiming a register REGNO for a global variable DECL with name NAME.
5931
+ *
5932
+ * If you don't defin this macro, that is equivalent to dfining it to do
5933
+ * nothing.
5934
+ */
5935
+
5936
+/* ASM_FINISH_DECLARE_OBJECT
5937
+ * TARGET_ASM_GLOBALIZE_LABEL
5938
+ * TARGET_ASM_GLOBALIZE_DECL_NAME
5939
+ * TARGET_ASM_ASSEMBLE_UNDEFINED_DECL
5940
+ * ASM_WEAKEN_LABEL
5941
+ * ASM_WEAKEN_DECL
5942
+ * ASM_OUTPUT_WEAKREF
5943
+ * SUPPORTS_WEAK
5944
+ * TARGET_SUPPORTS_WEAK
5945
+ * MAKE_DECL_ONE_ONLY
5946
+ * SUPPORTS_ONE_ONLY
5947
+ * TARGTE_ASM_ASSEMBLE_VISIBILITY
5948
+ * TARGET_WEAK_NOT_IN_ARCHIVE_TOC
5949
+ * ASM_OUTPUT_EXTERNAL
5950
+ * TARGET_ASM_EXTERNAL_LIBCALL
5951
+ * TARGET_ASM_MARK_DECLPRESERVED
5952
+ * ASM_OUTPUT_LABELREF
5953
+ * TARGET_MANGLE_ASSEMBLER_NAME
5954
+ * ASM_OUTPUT_SYMBOL_REF
5955
+ * ASM_OUTPUT_LABEL_REF
5956
+ * TARGET_ASM_INTERNAL_LABEL
5957
+ * ASM_OUTPUT_DEBUG_LABEL
5958
+ * ASM_GENERATE_INTERNAL_LABEL
5959
+ * ASM_FORMAT_PRIVATE_NAME
5960
+ */
5961
+
5962
+/* ASM_OUTPUT_DEF ... A C statement to output to the stdio stream STREAM
5963
+ * assembler code which defines (equates) the symbol NAME to have the value
5964
+ * VALUE.
5965
+ *
5966
+ * ZipCPU---So many other things that we need depend upon this, that we need
5967
+ * to implement a non-default version.
5968
+ */
5969
+#define        ASM_OUTPUT_DEF  zip_asm_output_def
5970
+
5971
+/* ASM_OUTPUT_DEF_FROM_DECLS
5972
+ * TARGET_DEFERRED_OUTPUT_DEFS
5973
+ * ASM_OUTPUT_WEAK_ALIAS
5974
+ * OBJ_GEN_METHOD_LABEL
5975
+ */
5976
+
5977
+
5978
+/* 17.20.7 Output of Assembler Instructions */
5979
+
5980
+#define        REGISTER_NAMES { "R0","R1","R2","R3","R4","R5","R6","R7","R8","R9", \
5981
+       "R10","R11","R12","SP","CC","PC" }
5982
+
5983
+/* REGISTER_PREFIX     (Undefined by default)
5984
+ * LOCAL_LABEL_PREFIX  (Undefined by default)
5985
+ * USER_LABEL_PREFIX   defaults to "*"
5986
+ * IMMEDIATE_PREFIX    (Undefined by default)
5987
+ *
5988
+ * If defined, C string expressions to be used for the '%R', '%L', '%U', and
5989
+ * '%I' options of asm_fprintf (see 'final.c').  These are useful when a single
5990
+ * 'md' file must support multiple assembler formats.  In that case, the various
5991
+ * 'tm.h' files can define these macros differently.
5992
+ */
5993
+// #define     USER_LABEL_PREFIX       "*"
5994
+
5995
+/* Defining memory operand address formats is in this section. */
5996
+
5997
+/* 17.20.10 Assembler Commands for Alignment */
5998
+
5999
+/* JUMP_ALIGN(label) ... The alignment (log base 2) to put in front of label,
6000
+ * which is a common destination of jumps and has no fallthru incoming
6001
+ * edge.  This macro need not be defined if you don't want any special alignment
6002
+ * to be done at such a time.  Most machine descriptions do not currently define
6003
+ * this macro.
6004
+ *
6005
+ * ZipCPU---The assembler should automatically deal with label alignment, so
6006
+ * let's not do anything about it here.
6007
+ */
6008
+
6009
+/* TARGET_ASM_JUMP_ALIGN_MAX_SKIP
6010
+ */
6011
+
6012
+/* LABEL_ALIGN_AFTER_BARRIER
6013
+ * TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
6014
+ */
6015
+
6016
+/* LOOP_ALIGN(label)
6017
+ * TARGET_ASM_LOOP_ALIGN_MAX_SKIP
6018
+ * LABEL_ALIGN
6019
+ * TARGET_ASM_LABEL_ALIGN_MAX_SKIP
6020
+ */
6021
+
6022
+/* ASM_OUTPUT_SKIP(STREAM, NBYTES) A C statement to output to the stdio
6023
+ * stream an assembler instruction to advance the location counter by nbytes
6024
+ * bytes.
6025
+ */
6026
+
6027
+/* TARGET_ASM_LABEL_ALIGN */
6028
+/* Assembler Commands for Alignment */
6029
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
6030 127 dgisselq
+       { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
6031 102 dgisselq
+
6032
+
6033
+
6034
+/* 17.21 Controlling Debugging Information Format */
6035
+/* 17.22 Cross Compilation and Floating Point */
6036 111 dgisselq
+
6037
+// REAL_VALUE_TYPE
6038
+// REAL_VALUES_EQUAL
6039
+// REAL_VALUES_LESS ... Tess whether x is less than y
6040
+/* REAL_VALUE_FIX ... Truncates x to an unsigned integer, rouding toward zero.
6041
+ * If x is negative, returns zero.
6042
+ */
6043
+// REAL_VALUE_ATOF
6044
+// REAL_VALUE_NEGATIVE
6045
+// REAL_VALUE_ISINF
6046
+// REAL_VALUE_ISNAN
6047
+/* REAL_ARITHMETIC(OUT,CODE,X,Y) ... (Macro) Calculates an arithmetic operation
6048
+ * on two floating point values X and Y, storing the result in OUT (which must
6049
+ * be a variable).
6050
+ *
6051
+ * The operation to be performed is specified by CODE.  Only the following
6052
+ * codes are supported: PLUS_EXPR, MINUS_EXPR, MULT_EXPR, RDIV_EXPR, MAX_EXPR,
6053
+ * MIN_EXPR.
6054
+ *
6055
+ * If REAL_ARITHMETIC is asked to evaluate division by zero and the target's
6056
+ * floating point format cannot represent infinity, it will call abort().
6057
+ * Callers shoudl check for this situation first, using MODE_HAS_INFINITIES.
6058
+ */
6059
+/* REAL_VALUE_NEGATE(X) ... [Macro] Returns the negative of the floating point
6060
+ * value X.
6061
+ */
6062
+/* REAL_VALUE_ABS(X) ... [Macro] Returns the absolute value of X.
6063
+ */
6064 102 dgisselq
+/* 17.23 Mode switching instructions */
6065
+/* 17.24 Defining target-specific uses of __attribute__ */
6066
+#undef TARGET_OPTION_OVERRIDE
6067
+#define        TARGET_OPTION_OVERRIDE  zip_override_options
6068
+
6069
+/* 17.25 Emulating TLS */
6070
+/* 17.26 Defining coprocessor specifics for MIPS targets*/
6071
+
6072
+ // ZipCPU isn't MIPS.
6073
+
6074
+/* 17.27 Parameters for Precompiled Header Validity Checking */
6075
+/* 17.28 C++ ABI parameters */
6076
+/* 17.29 Adding support for named address spaces */
6077
+/* 17.30 Miscellaneous Parameters */
6078
+
6079
+/* HAS_LONG_COND_BRANCH ... Define this boolean macro to indicate whether or
6080
+ * not your architecture has conditional branches that can span all of memory.
6081
+ * It is used in conjunction with an optimization that partitions hot and
6082
+ * cold basic blocks into separate sections of the executable.  If this macro
6083
+ * is set to false, gcc will convert any conditional branches that attempt to
6084
+ * cross between sections into unconditional branches or indirect jumps.
6085
+ *
6086
+ * ZipCPU --- The assembler renders long unconditional branch code without
6087
+ * problems, so we can pretend that such long branches exist.
6088
+ */
6089
+#define        HAS_LONG_COND_BRANCH true
6090
+
6091
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
6092
+ * or not your architecture has unconditional branches that can span all of
6093
+ * memory.  (ZipCPU does ... via the LOD (PC),PC instruction.)  It is used in
6094
+ * conjunction with an optimization that partitions hot and cold basic blocks
6095
+ * into separate sections of the executable.  If this macro is set to false,
6096
+ * gcc will convert any unconditional branches that attempt to cross between
6097
+ * sections into indirect jumps.
6098
+ *
6099
+ * ZipCPU has the LOD (PC),PC instruction which can be used to implement a long
6100
+ * jump.
6101
+ */
6102
+#define        HAS_LONG_UNCOND_BRANCH  true
6103
+
6104
+/* CASE_VECTOR_MODE ... An alias for a machine mode name.  This is the machine
6105
+ * mode that eleemnts of a jump-table should have.
6106
+ *
6107
+ */
6108
+#define        CASE_VECTOR_MODE        SImode
6109
+
6110
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
6111
+ * mode for an addr_diff_vec when the minimum and maximum offset are known.
6112
+ * If you define this, it enables extra code in branch shortening to deal with
6113
+ * addr_diff_vec.  To make this work, you also have to define INSN_ALIGN and
6114
+ * make the alignment for addr_diff_vec explicit.  The body argument is provided so that the offset_unsigned and scale flags can be updated.
6115
+ *
6116
+ * ZipCPU---No advantage here.
6117
+ */
6118
+
6119
+/* CASE_VECTOR_PC_RELATIVE ... Define this exrpession to indicate when
6120
+ * jump-tables should contain relative addresses.  You need not define this
6121
+ * macro if jump-tables never contain relative addresses, or jump-tables
6122
+ * should contain relative addresses only when -fPIC or -FPIC is in effect.
6123
+ *
6124
+ * ZipCPU---No advantage in PC-Relative jump tables--except in PIC relative
6125
+ * code.
6126
+ */
6127
+
6128
+/* TARGET_CASE_VALUES_THRESHOLD(VOID) ... This function returns the smallest
6129
+ * number of different values for which it is best to use a jump-table instead
6130
+ * of a tree of conditional branches.  The default is four for machines with a
6131
+ * casesi instruction and five otherwise.  This is best for most machines.
6132
+ *
6133
+ * ZipCPU---Leave at the default.
6134
+ */
6135
+
6136
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between
6137
+ * registers with integral mode smaller than a word are always performed on the
6138
+ * entire register.  Most RISC machines have this property and most CISC
6139
+ * machines do not.
6140
+ *
6141
+ * ZipCPU---We have the property, 'cause we're fairly risk.
6142
+ */
6143
+#undef WORD_REGISTER_OPERATIONS
6144
+#define        WORD_REGISTER_OPERATIONS        1
6145
+
6146
+/* LOAD_EXTEND_OP(MEMODE) ... Define this macro to be a C expression indicating
6147
+ * when insns that read memory in MEMMODE, an integral mode narrower than a
6148
+ * word, set the bits outside of MEMMODE to be either the sign extension or
6149
+ * zero-extension of the data read.  Return SIGN_EXTEND for values of MEMMODE
6150
+ * for which the insn sign-extends, ZERO_EXTEND for which it zero-extends, and
6151
+ * UNKNOWN for other modes.
6152
+ *
6153
+ * Do not define this macro if it would always return UNKNOWN.
6154
+ *
6155
+ * ZipCPU---This should be irrelevant, so we leave it undefined.
6156
+ */
6157
+#undef LOAD_EXTEND_OP
6158
+#define        LOAD_EXTEND_OP(MEM)     SIGN_EXTEND
6159
+
6160
+/* SHORT_IMMEDIATES_SIGN_EXTEND ... Define this macro to 1 if loading short immediate values into registers sign extends.
6161
+ *
6162
+ * ZipCPU---All immediates are sign extended, so yes.
6163
+ */
6164
+#undef SHORT_IMMEDIATES_SIGN_EXTEND
6165
+#define        SHORT_IMMEDIATES_SIGN_EXTEND    1
6166
+
6167
+/* TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
6168
+ */
6169
+
6170
+/* MOVE_MAX ... The maximum number of bytes that a single instruction can move
6171
+ * quickly between memory and registers or between two memory locations.
6172
+ *
6173
+ * ZipCPU --- Although we can move 32-bits at a time, and most people would call
6174
+ * this 4-bytes, the compiler defines a byte as the minimum addressable unit.
6175
+ * Therefore, this is defined to be one.
6176
+ */
6177
+#define        MOVE_MAX        1
6178
+
6179
+/* MAX_MOVE_MAX ... The maximum number of bytes that a single instruction can
6180
+ * move quickly between memory and registers or between two memory ...
6181
+ *
6182
+ * ZipCPU --- this sounds just the same as MOVE_MAX, which is the default
6183
+ * definition of this.
6184
+ */
6185
+
6186
+/* SHIFT_COUNT_TRUNCATED ... A C expression that is nonzero if on this machine
6187
+ * the number of bits actually used for the count of a shift operation is equal
6188
+ * to the number of bits needed to represent the size of the object being
6189
+ * shifted.
6190
+ *
6191
+ * You need not define this macro if it would have the value of zero.
6192
+ *
6193
+ * ZipCPU---A shift of 33 (or more) in either direction will wipe out the
6194
+ * value in the register, therefore this value should be zero, the default.
6195
+ */
6196
+
6197
+/* TARGET_SHIFT_TRUNCATION_MASK(MODE) ... This function describes how the
6198
+ * standard shift patterns for MODE deal with shifts by negative amounts or by
6199
+ * more than the width of the mode.
6200
+ *
6201
+ * ZipCPU---The default is zero, since we didn't define SHIFT_COUNT_TRUNCATED.
6202
+ * This is the case for the ZipCPU as well.
6203
+ */
6204
+
6205
+/* TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) ... A C expression which is nonzero
6206
+ * if on this machine it is safe to "convert" an integer of INPREC bits to one
6207
+ * of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on
6208
+ * it as if it had OUTPREC bist.  On many machines, this expression can be 1.
6209
+ *
6210
+ * ZiPCPU ... If both values are 32-bit, what conversion takes place?  If one is
6211
+ * 64-bit and the other 32-bit ... I suppose it would then be safe.
6212
+ */
6213
+#undef TRULY_NOOP_TRUNCATION
6214
+#define TRULY_NOOP_TRUNCATION(O,I)     1
6215
+
6216
+/* TARGET_MODE_REP_EXTENDED(MODE,REPMODE) ... The representation of an integral
6217
+ * mode can be such that the values are always extended to a wider integral
6218
+ * mode.  Return SIGN_EXTEND if values of MODE are represented in sign-extended
6219
+ * form to REPMODE.  Return UNKNOWN otherwise.  (Currently none of the targets
6220
+ * use zero-extended.
6221
+ *
6222
+ */
6223
+// #undef      TARGET_MODE_REP_EXTENDED
6224
+// #define     TARGET_MODE_REP_EXTENDED(R,M)   SIGN_EXTEND
6225
+
6226
+/* STORE_FLAG_VALUE ... A C expression describing the value returned by a
6227
+ * comparison operator with an integral mode and stored by a store-flag
6228
+ * instruction (cstoremode4) when the condition is true.  This description
6229
+ * must apply to all the cstoremode4 patterns and all the comparison operators
6230
+ * whose results have MODE_INT mode.
6231
+ *
6232
+ * ZipCPU---Doesn't really have a STORE_FLAG_VALUE instruction ...
6233
+ */
6234
+
6235
+/* FLOAT_STORE_FLAG_VALUE
6236
+ *
6237
+ * ZipCPU
6238
+ */
6239
+
6240
+/* VECTOR_STORE_FLAG_VALUE ... define this macro on machines that have vector
6241
+ * comparison operations that return a vector result ...
6242
+ *
6243
+ * ZipCPU---Doesn't support vector operations.
6244
+ */
6245
+
6246
+/* CLZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
6247
+ * CTZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
6248
+ *
6249
+ * A C expression that indicates whetther the architecture defines a value for
6250
+ * clz or ctz with a zero operand.  A result of 0 indicates the value is
6251
+ * undefined.  If the value is defined for only the RTL expression, the macro should evaluate to 1.  If the value also applies to the corresponding optab
6252
+ * entry, then the macro should evaluate to 2.  In cases where the value is
6253
+ * defined, value should be set to this value.
6254
+ * If this macro is not defined, the value of clz or ctz at zero is assumed to
6255
+ * be undefined.
6256
+ *
6257
+ * ZipCPU---Has neither clz nor ctz instructions, so we don't need this.
6258
+ */
6259
+
6260
+/* Pmode ... An alias for the machine mode for pointers.  On most machines,
6261
+ * define this to be the integer mode corresponding to the width of a
6262
+ * hardware pointer.  SImode on 32-bits machines, or DImode on 64-bit machines.
6263
+ * On some machines you must define this to be one of the partial
6264
+ * integer modes, such as PSImode.
6265
+ */
6266
+#undef Pmode
6267
+#define        Pmode   SImode
6268
+
6269
+/* FUNCTION_MODE ... An alais for the machine mode used for memory references to
6270
+ * function being called, in call RTL expressions.  On most CISC machines, where
6271
+ * an instruction can begin at any byte address, this should be QImode.  On most
6272
+ * RISC machines, where all instructions have fixed size and alignment, this
6273
+ * should be a mode with the same size and alignment as the machine instruction
6274
+ * words--typically SImode or HImode.
6275
+ *
6276
+ * ZipCPU---Definitely SImode, as with Pmode.  (All words are 32-bits, including
6277
+ * addresses on the ZipCPU.
6278
+ */
6279
+#undef FUNCTION_MODE
6280
+#define        FUNCTION_MODE   SImode
6281
+
6282
+/* STDC_0_IN_SYSTEM_HEADERS
6283
+ */
6284
+
6285
+/* TARGET_C_PREINCLUDE(V) ... Define this hook to return the name of  a header
6286
+ * file to be included at the start of all compilations, as if it had been
6287
+ * included with #include <file>.  If this hook returns NULL, or is not defined,
6288
+ * or if the header is not found, or if the user specifies -ffreestanding or
6289
+ * -nostdinc, no header is included.
6290
+ *
6291
+ * ZipCPU --- We don't have a standard library defined yet, so we'll leave this
6292
+ * as NULL.
6293
+ */
6294
+#undef TARGET_C_PREINCLUDE
6295
+#define        TARGET_C_PREINCLUDE     NULL
6296
+
6297
+/* TARGET_CXX_IMPLICIT_EXTERN_C(CONST CHAR *) ... Define this hook to add target
6298
+ * specific C++ implicit extern C functions.  If this function returns true
6299
+ * for the name of a file-scope function, that function implicitly gets extern
6300
+ * "C" linkage rather than whatever linkage the declaration would normally have.
6301
+ * An example of such function is WinMain on Win32 targets.
6302
+ *
6303
+ * ZipCPU---Not ready to deal with this yet.
6304
+ */
6305
+
6306
+/* NO_IMPLICIT_EXTERN_C ... Define this macro if the system header files
6307
+ * support C++ as well as C.  This macro inhibits the usual method of using
6308
+ * system header files in C++, which is to pretend that the file's contents
6309
+ * are enclosed in 'extern "C" {...}'.
6310
+ *
6311
+ *
6312
+ * ZipCPU --- Don't have either C or C++ headers, so let's skip this for now.
6313
+ * Eventually, though, I think ZipCPU and C++ would go very well together.
6314
+ */
6315
+
6316
+/* REGISTER_TARGET_PRAGMAS ... Define this macro if you want to implement any
6317
+ * target specific pragmas.
6318
+ *
6319
+ * ZipCPU --- let's not.
6320
+ */
6321
+
6322
+/* HANDLE_PRAGMA_PACK_WITH_EXPANSION ... Define this macro if macros should be
6323
+ * expanded in the arguments of #pragma pack().
6324
+ *
6325
+ * ZipCPU ... why?
6326
+ */
6327
+
6328
+/* TARGET_DEFAULT_PACK_STRUCT ... If your target requires a struct packing
6329
+ * default other than 0 (meaning the machine default), define this macro to
6330
+ * the necessary value (in bytes).  This must be a value that would also be
6331
+ * valid to use with #pragma pack() (that is a small power of two.
6332
+ */
6333
+
6334
+/* DOLLARS_IN_IDENTIFIERS
6335
+ * ZipCPU --- Default (not changing C)
6336
+ */
6337
+
6338
+/* INSN_SETS_ARE_DELAYED(INSN) ... Define this macro as a C expression that
6339
+ * is nonzero if it is safe for the delay slot schedule to place instructions
6340
+ * in the delay slot of INSN, even if they appear to use a resource set or
6341
+ * clobbered in INSN.  INSN is always a ...
6342
+ *
6343
+ * ZipCPU --- You need not define this macro if it would always return zero.
6344
+ */
6345
+
6346
+/* INSN_REFERENCES_ARE_DELAYED(INSN) ... Define this macro as a C expression
6347
+ * that is nonzero if it is safe for the delay slot schedule to place
6348
+ * instructions in the delay slot of INSN, even if they appear to set or clobber
6349
+ * a resource referenced in INSN.  INSN is always a jump_insn or an insn.  On
6350
+ * machines where some insn or jump_insn is really a function call and ...
6351
+ *
6352
+ * ZipCPU --- You need not define this macro if it would always return zero.
6353
+ */
6354
+
6355
+/* MULTIPLE_SYMBOL_SPACES ... Define this macro as a C expression that is
6356
+ * nonzero if, in some cases, global symbols from one translation unit may not
6357
+ * be bound to undefined symbols in another translation unit without user
6358
+ * intervention.  For instance, under Microsoft Windows symbols must be
6359
+ * explicitly imported from shared libraries (DLLs).
6360
+ *
6361
+ * ZipCPU---You need not define this macro if it would always evaluate to zero,
6362
+ * so we won't.
6363
+ */
6364
+
6365
+/* TARGET_MD_ASM_ADJUST
6366
+ */
6367
+/* MATH_LIBRARY ... Define this macro as a C constant ... you only need to
6368
+ * define this macro if the default of "m" is wrong.
6369
+ *
6370
+ * ZipCPU --- as we don't have a math library yet, building one such that "m"
6371
+ * works doesn't sound like a problem.  Let's not define this.
6372
+ */
6373
+
6374
+/* LIBRARY_PATH_ENV ... Define this as a C string constant for the environment
6375
+ * variable that specifies where the linker should look for libraries.
6376
+ *
6377
+ * Just in case we want to add libraries for ZipCPU, let's place them in
6378
+ * /usr/local/zip/lib, so as not to confuse them with our local systems
6379
+ * libraries.
6380
+ */
6381
+#define        LIBRARY_PATH_ENV        "/usr/local/zip/lib"
6382
+
6383
+/* TARGET_POSIX_IO ... Define this macro if the target supports the following
6384
+ * POSIX file fucntions: access, mkdir, and file locking with fcntl/F_SETLKW.
6385
+ *
6386
+ * ZipCPU does not.
6387
+ */
6388
+
6389
+/* MAX_CONDITIONAL_EXECUTE ... A C expression for the maximum number of
6390
+ * instructions to execute via conditional execution instructions instead of a
6391
+ * branch.  A value of BRANCH_COST+1 is the default if the machine does not use
6392
+ * cc0 and 1 if it does use cc0.
6393
+ *
6394
+ * ZipCPU---This sounds good enough for the ZipCPU as well--as long as we have
6395
+ * BRANCH_COST defined.  However, BRANCH_COST is defined as conditionally to
6396
+ * something else, so let's keep looking into this.
6397
+ */
6398
+
6399
+/* IFCVT_MODIFY_TESTS(CEINFO,TRUE,FALSE) ... Used if the target needs to
6400 103 dgisselq
+ * perform machine-dependent modifications on the conditionals used for turning
6401 102 dgisselq
+ * basic blocks into conditionally executed code.  CEINFO points to a data
6402
+ * structure, struct ce_if_block, which contains information about the currently
6403
+ * processed blocks.  TRUE and FALSE are the tests that are used for
6404
+ * converting the then-block and the else-block, respectively.  Set either TRUE
6405
+ * or FALSE to a null pointer if the tests cannot be converted.
6406
+ *
6407
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6408
+ * execution and conditional testing capabilities.
6409
+ */
6410 122 dgisselq
+#define        IFCVT_MODIFY_TESTS(CI,TR,FL)    zip_ifcvt_modify_tests(CI,&TR,&FL)
6411 102 dgisselq
+
6412
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like
6413
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements
6414
+ * into conditions combined by and and or operations.  BB contains the basic
6415
+ * block that contains the test that is currently being processed and about to
6416
+ * be turned into a condition.
6417
+ *
6418
+ *
6419
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6420
+ * execution and conditional testing capabilities.
6421
+ */
6422
+// #warning "Need to come back to this."
6423 122 dgisselq
+#define        IFCVT_MODIFY_MULTIPLE_TESTS(CI,BB,TR,FL) TR=NULL_RTX
6424 102 dgisselq
+
6425
+
6426
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the
6427
+ * PATTERN of an INSN that is to be converted to conditional execution format.
6428
+ * CEINFO points to a data structure, struct ce_if_block, which contains
6429
+ * information about the currently processed blocks.
6430
+ *
6431
+ *
6432
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6433
+ * execution and conditional testing capabilities.
6434
+ */
6435
+// #warning "Need to come back to this."
6436
+
6437
+
6438
+/* IFCVT_MODIFY_FINAL(CEINFO) ... A C expression to perform any final
6439
+ * machine dependent modifications in converting code to conditional
6440
+ * execution.  The involved basic blocks can be found in struct ce_if_block
6441
+ * structure pointed to be CEINFO.
6442
+ *
6443
+ *
6444
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6445
+ * execution and conditional testing capabilities.
6446
+ */
6447
+// #warning "Need to come back to this."
6448 122 dgisselq
+#define        IFCVT_MODIFY_FINAL(CEINFO)      zip_ifcvt_modify_final(CEINFO)
6449 102 dgisselq
+
6450
+
6451
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine
6452
+ * dependent modifications in converting code to conditional execution.  The
6453
+ * involved basic blocks can be found in the struct ce_if_block structure that
6454
+ * is pointed to by CEINFO.
6455
+ *
6456
+ *
6457
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6458
+ * execution and conditional testing capabilities.
6459
+ */
6460
+// #warning "Need to come back to this."
6461 122 dgisselq
+#define        IFCVT_MODIFY_CANCEL(CEINFO)     zip_ifcvt_modify_cancel(CEINFO)
6462 102 dgisselq
+
6463
+
6464
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine
6465
+ * specific data for if-conversion of the if-block in the CEINFO block structure
6466
+ * that is pointed by CEINFO.
6467
+ *
6468
+ *
6469
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6470
+ * execution and conditional testing capabilities.
6471
+ */
6472
+// #warning "Need to come back to this."
6473 122 dgisselq
+#define        IFCVT_MACHDEP_INIT(CEINFO)      zip_ifcvt_machdep_init(CEINFO)
6474 102 dgisselq
+
6475
+
6476
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a
6477
+ * target specific pass over the instruction stream.  The compiler will run it
6478
+ * at all optimization levels, just before the point at which it normally does
6479
+ * delayed branch scheduling.
6480
+ *
6481
+ * You need not implement the hook if it has nothing to do.
6482
+ *
6483
+ * ZipCPU---This may be part of a later upgrade, but shouldn't be needed to
6484
+ * just get us started.
6485
+ */
6486
+
6487
+
6488
+/* TARGET_INIT_BUILTINS(VOID) ... Define this hook if you ahve any machine
6489
+ * specific builtin functions that need to be defined.  It should be a function
6490
+ * that performs the necessary setup.  Machine specific builtin functions can be
6491
+ * useful to expand special machine instructions that would otherwise not
6492
+ * normally be generated because they have no equivalent in the source language.
6493
+ *
6494
+ * To create a built in function, call the function lang_hooks.builtin_function
6495
+ * which is defined by the language front end.  You can use any type nodes
6496
+ * set up by build_common_tree_nodes; only language front ends that use those
6497
+ * two functions will call "TARGET_INIT_BUILTINS".
6498
+ *
6499
+ * ZipCPU---We need to come back to this.  We should have several built-ins
6500
+ * defined: rtu(), wait(), halt(), save_context(cstackregno), and
6501
+ * restore_context(cstackregno).
6502
+ *
6503
+ */
6504
+#undef TARGET_INIT_BUILTINS
6505
+#define        TARGET_INIT_BUILTINS    zip_init_builtins
6506
+
6507
+/* TARGET_BUILTIN_DECL(CODE,INITP) ... Define this hook if you have any
6508
+ * machine specific builtin functions that need to be defined.  It should be a
6509
+ * function that returns the builtin function declaration for the builtin
6510
+ * function code code.  If there is no such builtin and it cannot be initialized
6511
+ * at this time if INITP is true the function should return NULL_TREE.  If
6512
+ * CODE is out of range the fucntion should return error-mark_node.
6513
+ *
6514
+ * ZipCPU ... needs to be done, don't know how to do it yet.
6515
+ */
6516
+#undef TARGET_BUILTIN_DECL
6517
+#define        TARGET_BUILTIN_DECL     zip_builtin_decl
6518
+
6519
+
6520
+/* TARGET_EXPAND_BUILTIN(TREE,TGT,SUB,MODE,IGNORE) ... Expand a call to a
6521
+ * machine specific built-in function that was set up by TARGET_INIT_BUILTINS.
6522
+ * TREE is the expression for the function call; the result should go to
6523
+ * TGT if that is convenient, and have mode MODE if that is convenient.  SUB
6524
+ * may be used as the target for computing one of EXP's operands.  IGNORE is
6525
+ * non-zero if the value is to be ignored.  This function should return the
6526
+ * result of the call to the built-in function.
6527
+ *
6528
+ * ZipCPU ... needs to do it, just to get our special intrinsic functions
6529
+ */
6530
+#define        TARGET_EXPAND_BUILTIN   zip_expand_builtin
6531
+
6532
+
6533
+/* TARGET_BUILTIN_CHKP_FUNCTION(FCODE) ... Allows the target to redefine
6534
+ * builtin functions used by Pointer Bounds Checker for code instrumentation.
6535
+ *
6536
+ * ZipCPU --- not interested.
6537
+ */
6538
+/* TARGET_CHKP_BOUND_TYPE
6539
+ * TARGET_CHKP_MAKE_BOUNDS_CONSTANT
6540
+ * TARGET_CHKP_INITIALIZE_BOUNDS
6541
+ *
6542
+ * ZipCPU --- Same as last one.
6543
+ */
6544
+
6545
+
6546
+/* TARGET_RESOLVE_OVERLOADED_BUILTIN(LOC, FN, ARGS) ... Select a replacement
6547
+ * for a machine specific built-in function that was set up by
6548
+ * TARGET_INIT_BUILTINS.
6549
+ *
6550
+ * ZipCPU --- If I go to the trouble to create a builtin, why would I want
6551
+ * to then overload it?
6552
+ */
6553
+
6554
+/* TARGET_FOLD_BUILTIN(FN,NARGS,ARGP,IGNORE) ... Fold a call to a machine
6555
+ * specific built-in function that was set up by 'TARGET_INIT_BUILTINS'  FN
6556
+ * is the declaration of the built-in function.  NARGS is the number of
6557
+ * arguments passed to the function; the arguments themselves are pointed to by
6558
+ * ARGP.  The result is another tree, valid for both GIMPLE and GENERIC,
6559
+ * containing as simplified expression for the call's result.  If IGNORE is
6560
+ * true the value will be ignored.
6561
+ *
6562
+ * ZipCPU --- You know, this and the previous couple sound like something
6563
+ * whereby I might be able replace bit-reversal code with my bit reverse
6564
+ * instruction.  That would be very useful, but not necessary to get me
6565
+ * started.
6566
+ */
6567
+
6568
+/* TARGET_GIMPLE_FOLD_BUILTIN
6569
+ * TARGET_COMPARE_VERSION_PRIORITY
6570
+ * TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
6571
+ * TARGET_GENERATE_VERSION_DISPATCHER_BODY
6572
+ * TARGET_CAN_USE_DOLOOP_P
6573
+ * TARGET_INVALID_WITHIN_DOOLOOP
6574
+ * TARGET_LEGITIMATE_COMBINED_INSN
6575
+ * TARGET_CAN_FOLLOW_JUMP
6576
+ * TARGET_COMMUTATIVE_P
6577
+ */
6578
+
6579
+/* TARGET_ALLOCATE_INITIAL_VALUE(REGNO)  ... When the initial value of a hard
6580
+ * register has been copied in a pseudo register, it is often not necessary
6581
+ * ...
6582
+ */
6583
+/* TARGET_UNSPEC_MAY_TRAP_P(RTX,FLAGS)  ... This target hook returns nonzero in
6584
+ * RTX, un unspec or unspec_volatile operation, might cause a trap.  Targets
6585
+ * can use this hook to enhance precision of analysis for unspec and
6586
+ * unspec_volatile operations.  You may call may_trap_p_1 to analyze inner
6587
+ * elements of RTX in which case flags should be passed along.
6588
+ */
6589
+
6590
+/* TARGET_SET_CURRENT_FUNCTION(TREE)  The compiler invokes this hook whenever
6591
+ * it changes its current function context (CFUN).  You can define this
6592
+ * function if the back end needs to perform any initialization or reset
6593
+ * actions on a per-function basis.  For example, it may be used to implement
6594
+ * function attributes that affect register usage or code generation patterns.
6595
+ */
6596
+
6597
+/* TARGET_OBJECT_SUFFIX ... Define this macro to be a C string representing the
6598
+ * suffix for object files on your target machine.  If you do not define this
6599
+ * macro, GCC will use ".o" as the suffix for object files.
6600
+ */
6601
+#define        TARGET_OBJECT_SUFFIX    ".o"
6602
+
6603
+/* TARGET_EXECUTABLE_SUFFIX
6604
+ */
6605
+#define        TARGET_EXECUTABLE_SUFFIX        ""
6606
+
6607
+/* COLLECT_EXPORT_LIST ... If defined, collect2 will scan the individual object
6608
+ * files specified on its command line and create an export list for the linker.
6609
+ * Define this macro for systems like AIX, where the linker discards object
6610
+ * files that are not referenced from main and uses export lists.
6611
+ *
6612
+ * ZipCPU --- shoudln't need this.
6613
+ */
6614
+
6615
+/* MODIFY_JNI_METHOD_CALL(MDECL)  ... Define this macro to a C expression
6616
+ * representing a variant of the method call mdecl, if Java Native Interface
6617
+ * (JNI) methods must be invoked differently from other methods on your
6618
+ * target.  For example, on 32-bit MSWindows, JNI methods must be invoked
6619
+ * using the stdcall calling convention and this macro is then ...
6620
+ *
6621
+ * ZipCPU----Don't need this.  (yet)
6622
+ */
6623
+
6624
+
6625
+/* TARGET_CANNOT_MODIFY_JUMPS_P ... This target hook returns true past the
6626
+ * point in which a new jump instructions could be created.  On machines that
6627
+ * require a register for every jump such as the SHmedia ISA of SH5, this point
6628
+ * would typically be reload, so thiss target hook should be defined to a
6629
+ * function such as:
6630
+ *
6631 117 dgisselq
+ * ZipCPU --- I don't get what this is for.
6632
+ *     Actually, in hind sight, ZipCPU needs this.  Without this, the
6633
+ * compiler will try to reorder basic blocks, shuffling logic around and so
6634
+ * fortch, preventing our comparison optimizations from being used.  By setting
6635
+ * this function appropriately, we can prevent it from reversing conditions into
6636
+ * conditions we don't support.
6637 102 dgisselq
+ */
6638 117 dgisselq
+#define        TARGET_CANNOT_MODIFY_JUMPS_P    zip_cannot_modify_jumps_p
6639 102 dgisselq
+
6640
+/* TARGET_BRANCH_TARGET_REGISTER_CLASS ... This target hook returns a register
6641
+ * class for which branch target register optimizations should be applied.  All
6642
+ * registers in this class should be usable interchangably.  After reload,
6643
+ * registers in this class will be re-allocated and loads will be hoisted out of
6644
+ * loops and be subjected to inter-block scheduling.
6645
+ *
6646
+ * ZipCPU---GENERAL_REGS, but this should be a default already ...
6647
+ */
6648
+
6649
+
6650
+/* TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED ...  Branch target register
6651
+ * optimization will by default exclude callee-saved registers that are not
6652
+ * already live during the current function.  If this target hook returns true,
6653
+ * they will be included.  The target code must then make sure that all target
6654
+ * registers in the class returned by TARGET_BRANCH_REGISTER_CLASS that might
6655
+ * be saved are saaved.
6656
+ *
6657
+ * ZipCPU---
6658
+ */
6659
+
6660
+
6661
+/* TARGET_HAVE_CONDITIONAL_EXECUTION(VOID) ... This target hook returns true
6662
+ * if the target supports conditional execution.  This target hook is required
6663
+ * only when the target has several different modes and they have different
6664
+ * conditional execution capability, such as ARM.
6665
+ *
6666
+ * ZipCPU---Yes!  All instructions may be conditionally executed (except the
6667
+ * long version load immediate ...)
6668
+ */
6669
+#define        TARGET_HAVE_CONDITIONAL_EXECUTION       hook_bool_void_true
6670
+
6671
+/* TARGET_GEN_CCMP_FIRST(PREP,GEN,CODE,OP0,OP1) .. This function prepares to
6672
+ * emit a comparison instruction for the first compare in a sequence of
6673
+ * conditional comparisons.  It returns an appropriate comparison with CC for
6674
+ * passing to gen_ccmp_next or cbranch_optab.  The instructions to prepare the
6675
+ * compare are saved in prep_seq and the compare instructions are saved in
6676
+ * gen_seq.  They will be emitted when all the compares in the conditional
6677
+ * comparison are generated without error.  CODE is the rtx_code of the compare
6678
+ * for op0 and op1.
6679
+ *
6680
+ *
6681
+ * ZipCPU---???
6682
+ */
6683
+
6684
+/* TARGET_GEN_CCMP_NEXT(PREP,GEN,PREV,CMP,OP0,OP1,BITCODE) ... This function
6685
+ * prepares to emit a conditional comparison within a sequence of conditional
6686
+ * comparisons.  It returns an appropriate comparison with CC for passing to
6687
+ * gen_ccmp_next or cbranch_optab.  The insn to prepare the compare are saved
6688
+ * in prep_seq and the compare instructions are saved in gen_seq.  They will be
6689
+ * emitted when all the compares in the conditional comparison are generated
6690
+ * without error.  The pPREV expression is the result of a prior call to either
6691
+ * gen_ccmp_first or gen_ccmp_next.  It may return NULL if the combination of
6692
+ * PREV and this comparison is not supported, otherwise the result must be the
6693
+ * appropriate for passing to gen_ccmp_next or cbranch_optab.  CODE is the RTX
6694
+ * code of the compare for op0 and op1.  BITCODE is AND or IOR, which is the op
6695
+ * on the compares.
6696
+ *
6697
+ *
6698
+ * ZipCPU --- ???
6699
+ */
6700
+
6701
+/* TARGET_LOOP_UNROLL_ADJUST(NUNROLL, LOOP) ... This target hook returns a new
6702
+ * value for the number of times loop should be unrolled.  The parameter NUNROLL
6703
+ * is the number of times the loop is to be unrolled.  The parameter loop is a
6704
+ * pointer to the loop, which is going to be checked for unrolling.  The target
6705
+ * hook is required only when the target has special constraints like maximum number of memory accesses.
6706
+ *
6707
+ *
6708
+ * ZipCPU -- ???
6709
+ */
6710
+
6711
+
6712
+/* POWI_MAX_MULTS ... If defined, this macro is interpreted as a signed integer
6713
+ * C expression that specifies the maximum number of floating point
6714
+ * multiplications that should be emitted when expanding exponentiation by an
6715
+ * integer constant inline.  When this value is defined, exponentiation
6716
+ * requiring more than this number of multiplications is implemented by calling
6717
+ * the system library's pow, powf, or powl routines.  The default value
6718
+ places no upper bound on the multiplication count.
6719
+ *
6720
+ * ZipCPU---As we have no system library pow() routine (yet) ... we're not
6721
+ * ready for this macro.
6722
+ */
6723
+
6724
+
6725
+/* TARGET_EXTRA_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
6726
+ * register any extra include files for the target.  The parameter stdinc
6727
+ * indicates if normal include files are present.  The parameter SYSROOT is the
6728
+ * system root directory.  The parameter PFX is the prefix for the GCC
6729
+ * directoiry.
6730
+ *
6731
+ *
6732
+ * ZipCPU---None yet.
6733
+ */
6734
+
6735
+/* TARGET_EXTRA_PRE_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
6736
+ * register any extrra include files for the target before any standard headers.
6737
+ * The parameter stdinc indicates if normal include files are present.
6738
+ *
6739
+ * ZipCPU --- None.
6740
+ */
6741
+
6742
+/* TARGET_OPTF(PATH) ... This target hook should register special include paths
6743
+ * for the target.  The parameter path is the integer to register.  On Darwin
6744
+ * systems, this is used for Framework includes, which have semantics that are
6745
+ * different from -I.
6746
+ *
6747
+ *
6748
+ * ZipCPU --- None.
6749
+ */
6750
+
6751
+/* TARGET_USE_LOCAL_THUNK_ALIAS_P(FN) ... This target macro returns if it is
6752
+ * safe to use a local alias for a virtual function FN when constructing
6753
+ * thunks, false otherwise.  By default, the macro returns true for all
6754
+ * functions, if a target supports aliases (i.e. defines ASM_OUTPUT_DEF),
6755
+ * false otherwise.
6756
+ *
6757
+ *
6758
+ * ZipCPU --- ???
6759
+ */
6760
+// #warning "ASM_OUTPUT_DEF's definition has not been considered"
6761
+
6762
+
6763
+/* TARGET_FORMAT_TYPES ... If defined, this macro is the name of a global
6764
+ * variable containing target-specific format checking information for the
6765
+ * -Wformat option.  The default is to have no target-specific format checks.
6766
+ *
6767
+ * ZipCPU --- Default
6768
+ */
6769
+
6770
+/* TARGET_N_FORMAT_TYPES
6771
+ *
6772
+ * ZipCPU --- Default
6773
+ */
6774
+
6775
+/* TARGET_OVERRIDES_FORMAT_ATTRIBUTES ... If defined, this macro is the name of
6776
+ * a global variable containing target-specific format overrides for the
6777
+ * -Wformat option.  The default is to have no target specific format overrides.
6778
+ *
6779
+ * ZipCPU --- Default
6780
+ */
6781
+
6782
+/* TARGET_OVERRIDEES_FORMAT_ATTRIBUTES
6783
+ * TARGET_OVERRIDEES_FORMAT_ATTRIBUTES_COUNT
6784
+ *
6785
+ * If defined, the (first) macro is the name of a global variable containing
6786
+ * target-specific format overrides for the -Wformat option.
6787
+ */
6788
+/* TARGET_OVERRIDES_FORMAT_INIT ... If defined, this macro specifies the
6789
+ * optional initialization routine for target specific customizations of the
6790
+* system printf and scanf formatter settings.
6791
+ */
6792
+
6793
+/* TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN(TLIST,FN,VAL) ... If defined, this
6794
+ * macro returns the diagnostic message when it is illegal to pass an argument
6795
+ * VAL to function FN with prototype TLIST.
6796
+ *
6797
+ * ZipCPU---Default.
6798
+ */
6799
+
6800
+/* TARGET_INVALID_CONVERSION
6801
+ * TARGET_INVALID_UNARY_OP
6802
+ * TARGET_INVALID_BINARY_OP
6803
+ * TARGET_INVALID_PARAMETER_TYPE
6804
+ * TARGET_INVALID_RETURN_TYPE
6805
+ * TARGET_PROMOTED_TYPE
6806
+ * TARGET_CONVERT_TO_TYPE
6807
+ * TARGET_USE_JCR_SECTION_TYPE
6808
+ * OBJC_JBLEN
6809
+ * LIBGCC2_UNWIND_ATTRIBUTE
6810
+ * TARGET_UPDATE_STACK_BOUNDARY
6811
+ * TARGET_GET_DRAP_RTX
6812
+ * TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
6813
+ */
6814
+/* TARGET_CONST_ANCHOR ... On some architectures it can take multiple
6815
+ * instructions to synthesize a constant. If there is another constant already
6816
+ * in a register that is close enough in value then it is preferable that the
6817
+ * new constant is computed from the register using immediate addition or
6818
+ * subtraction.  We accomplish this through CSE.  Besides the value of the
6819
+ * constant we also add a lower and an upper constant anchor to the available
6820
+ * expressions.  These are then queried when encountering new constants.  The
6821
+ * anchors are computed by rounding the constant up and down to a multiple of
6822
+ * the value of TARGET_CONST_ANCHOR.  TARGET_CONST_ANCHOR should be the maximum
6823
+ * positive value accepted by immediate-add plus one.  We currently assume that
6824
+ * the value of TARGET_CONST_ANCHOR is a poewr of 2.  For example, on MIPS,
6825
+ * where add-immediate takes a 16-bit signed value, TARGET_CONST_ANCHOR is set
6826
+ * to 0x8000.  The default value is zero, which disables this optimization.
6827
+ *
6828
+ * ZipCPU---One of the great strengths of the ZipCPU ISA is its ability to
6829
+ * access registers plus immediates.  To use this, we *need* this capability.
6830
+ * So, we define it here. (to 0x20000, or 2^17 because we can handle 18-bits of
6831
+ * signed immediate offsets)
6832
+ *
6833
+ * On ZipCPU---2^17
6834
+ */
6835
+#define        TARGET_CONST_ANCHOR     zip_const_anchor
6836
+
6837
+/* TARGET_ASAN_SHADOW_OFFSET ... Return the offset bitwise ored into shifted
6838
+ * address to get corresponding Address Sanitizer shadow memory address.  NULL
6839
+ * if address Sanitizer is not supported by the target.
6840
+ */
6841
+#define        TARGET_ASAN_SHADOW_OFFSET       NULL
6842
+
6843
+/* TARGET_MEMMODEL_CHECK
6844
+ */
6845
+/* TARGET_ATOMIC_TEST_AND_SET_TRUEVAL ... This value should be set if the result
6846
+ * written by atomic test and set is not exactly 1, i.e. the bool true.
6847
+ */
6848
+/* TARGET_HAS_IFUNC_P ... It returns true if the target supports GNU indirect
6849
+ * functions.  The support includes the assembler, linker, and dynamic linker.
6850
+ * The default value of this hook is based on target's libc.
6851
+ */
6852
+#define        TARGET_HAS_IFUNC_P      hook_bool_void_true
6853
+
6854
+/* TARGET_ATOMIC_ALIGN_FOR_MODE(MODE) ... If defined, this function returns
6855
+ * an appropriate alignment in bits for an atomic object of machine mode
6856
+ * MODE.  If 0 is returned then the default alignment for the specified mode
6857
+ * is used.
6858
+ *
6859
+ * ZipCPU---Both default and 2 would be valid.  We'll stick to the default.
6860
+ */
6861
+
6862
+/* TARGET_ATOMIC_ASSIGN_EXPAND_FENV --- ISO C11 requires atomic compound
6863
+ * assignments that may raise floating-point exceptions to raise exceptions
6864
+ * corresponding to the arithmetic operation whose result was successfully
6865
+ * stored in a compare-and-exchange sequence.  This requires code equivalent to
6866
+ * calls to feholdexcept, feclearexcept and feupdateenv to be generated at
6867
+ * appropriate points in the compare-and-exchange sequence.  This hook should
6868
+ * set *hold to an expression equivalent
6869
+ *
6870
+ * ZipCPU --- ???
6871
+ */
6872
+
6873
+/* TARGET_RECORD_OFFLOAD_SYMBOL ... Used when offloaded functions are seen in
6874
+ * the compilation unit and no named sections are available.  It is called once
6875
+ * for each symbol that must be recorded in the offload function and variable
6876
+ * table.
6877
+ *
6878
+ * ZipCPU --- Offloaded functions?
6879
+ */
6880
+
6881
+/* TARGET_OFFLOAD_OPTIONS
6882
+ *
6883
+ * ZipCPU---none defined
6884
+ */
6885
+
6886
+/* TARGET_SUPPORTS_WIDE_INT ... On older ports, large integers are stored
6887
+ * in CONST_DOUBLE rtl objects.  Newer ports define TARGET_SUPPORTS_WIDE_INT
6888
+ * to be nonzero to indicate that large integers are stored in CONST_WIDE_INT
6889
+ * rtl objects.  The CONST_WIDE_INT allows very large integer constants to be
6890
+ * represented.  CONST_DOUBLE is limited to twice the size of the hosts
6891
+ * HOST_WIDE_INT representation.
6892
+ *
6893
+ * ZipCPU---We don't need these yet, so this isn't yet relevant.  (These ints
6894
+ * are wider than DImode ...)
6895
+ */
6896
+#define        TARGET_SUPPORTS_WIDE_INT        0
6897
+
6898
+
6899
+/* Now, for the prototype functions ...*/
6900
+// These have been moved to zip-protos.h
6901
+
6902
+// extern void zip_init_builtins(void);
6903
+// extern void zip_asm_output_anchor(rtx x);
6904
+// extern bool zip_legitimate_address_p(enum machine_mode mode, rtx x, bool string);
6905
+// extern void zip_asm_trampoline_template(FILE *);
6906
+// extern void zip_initial_elimination_offset(int from, int to);
6907
+// extern void zip_print_operand(FILE *stream, rtx *x, int code);
6908
+// extern void zip_print_operand_address(FILE *stream, rtx *x);
6909
+// extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
6910
+// extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
6911
+// extern      int zip_address_operand(rtx op);
6912
+// extern      int zip_const_address_operand(rtx op);
6913
+// extern void zip_expand_prologue(void);
6914
+// extern void zip_expand_epilogue(void);
6915
+// extern bool zip_gen_move_rtl(rtx, rtx);
6916
+// extern bool zip_load_address_lod(rtx, rtx);
6917
+// extern bool zip_load_address_sto(rtx, rtx);
6918
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
6919
+// extern void zip_print_operand_address(FILE *fp, rtx x);
6920
+// extern bool zip_use_return_insn(void);
6921
+
6922 111 dgisselq
+#define        UQQmode USQmode
6923
+#define        UHQmode USQmode
6924
+#define        UHAmode USAmode
6925
+#define        QQmode  SQmode
6926
+#define        HQmode  SQmode
6927 102 dgisselq
+#define        QImode  SImode
6928
+#define        HImode  SImode
6929 111 dgisselq
+#define        QAmode  SAmode
6930
+#define        HAmode  SAmode
6931 102 dgisselq
+
6932
+#include "insn-modes.h"
6933
+#include "zip-protos.h"
6934
+
6935
+#endif /* GCC_ZIP_H */
6936
+
6937
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
6938
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
6939 127 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-04-21 20:01:08.790659796 -0400
6940
@@ -0,0 +1,2961 @@
6941 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6942
+;;
6943
+;; Filename:   zip.md
6944
+;;
6945
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
6946
+;;
6947
+;; Purpose:    This is the machine description of the Zip CPU as needed by the
6948
+;;             GNU compiler collection (GCC).
6949
+;;
6950
+;;
6951
+;; Creator:    Dan Gisselquist, Ph.D.
6952
+;;             Gisselquist Technology, LLC
6953
+;;
6954
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6955
+;;
6956
+;; Copyright (C) 2015, Gisselquist Technology, LLC
6957
+;;
6958
+;; This program is free software (firmware): you can redistribute it and/or
6959
+;; modify it under the terms of  the GNU General Public License as published
6960
+;; by the Free Software Foundation, either version 3 of the License, or (at
6961
+;; your option) any later version.
6962
+;;
6963
+;; This program is distributed in the hope that it will be useful, but WITHOUT
6964
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
6965
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
6966
+;; for more details.
6967
+;;
6968
+;; License:    GPL, v3, as defined and found on www.gnu.org,
6969
+;;             http://www.gnu.org/licenses/gpl.html
6970
+;;
6971
+;;
6972
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6973
+;;
6974
+;;
6975
+;; - Immediate integer operand constraints
6976
+;;     'I'     -2^22 ... 2^22-1, or -4194304 .. 4194303        (LDI insn)
6977
+;;     'M'     -2^12 ... 2^12-1, or -4096 ... 4095             (MOV offset)
6978
+;;     'N'     -2^14 ... 2^14-1, or -16384 ... 16383           (OpB offset)
6979
+;;     'O'     -2^17 ... 2^17-1, or -131072 ... 131071         (OpB Immediate)
6980
+;;     'R'     0...31                                          (Shift value)
6981
+;; - Memory constraints
6982 111 dgisselq
+;;     "Q"     Op-B capable references to memory
6983
+;;     "S"     References to constant memory
6984 102 dgisselq
+;; - Address constraints
6985 111 dgisselq
+;;     "U"     Op-B capable address that references to memory
6986
+;;     "T"     Constant memory addresses
6987 102 dgisselq
+(define_constraint "M"
6988
+  "An 13-bit signed immediate such as a MOV instruction can handle"
6989
+  (and (match_code "const_int")
6990
+       (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
6991
+(define_constraint "N"
6992
+  "An 14-bit signed immediate offset such as an Op-B register offset"
6993
+  (and (match_code "const_int")
6994
+       (match_test "(ival < 0x2000) && (ival >= -0x2000)")))
6995
+(define_constraint "O"
6996
+  "An 18-bit signed immediate such as an Op-B Immediate can handle"
6997
+  (and (match_code "const_int")
6998
+       (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
6999
+(define_constraint "R"
7000
+  "Bits that a value may be shifted"
7001
+  (and (match_code "const_int")
7002
+       (match_test "(ival < 32) && (ival >= 0)")))
7003
+;;
7004
+;
7005
+;
7006
+; Our builtin functions, by identifier
7007
+;
7008
+(define_constants
7009 117 dgisselq
+       [(UNSPEC_RTU             1)
7010
+       (UNSPEC_HALT             2)
7011
+       (UNSPEC_IDLE             3)
7012
+       (UNSPEC_SYSCALL          4)
7013
+       (UNSPEC_SAVE_CONTEXT     5)
7014
+       (UNSPEC_RESTORE_CONTEXT  6)
7015
+       (UNSPEC_BITREV           7)
7016
+       (UNSPEC_GETUCC           8)
7017
+       (UNSPEC_GETCC            9)
7018
+       (UNSPEC_LDILO           10)
7019 127 dgisselq
+       ; (UNSPEC_RAW_CALL      11)
7020 102 dgisselq
+       ])
7021
+;
7022
+;
7023
+; Registers by name
7024
+(define_constants
7025
+  [(RTN_REG            0)      ; Return address register
7026
+   (RTNV_REG           1)      ; Subroutine return value register
7027
+   (AP_REG             10)     ; Hopefully never used
7028
+   (GBL_REG            11)     ; Hopefully never used, but just in case ...
7029
+   (FP_REG             12)
7030
+   (SP_REG             13)
7031
+   (CC_REG             14)
7032
+   (PC_REG             15)
7033
+  ])
7034
+;
7035
+;
7036
+;
7037
+
7038
+;; Predicates
7039
+(define_predicate "zip_const_address_operand_p"
7040
+       (match_code "symbol_ref,const,label_ref,code_label")
7041
+{
7042
+       return zip_const_address_operand(op);
7043
+})
7044
+
7045
+(define_predicate "zip_address_operand_p"
7046
+       (match_code "reg,plus")
7047
+{
7048 111 dgisselq
+       return zip_pd_opb_operand(op);
7049 102 dgisselq
+})
7050
+
7051 111 dgisselq
+(define_predicate "zip_opb_operand_p"
7052 122 dgisselq
+       (match_code "reg,plus,const_int,subreg")
7053 111 dgisselq
+{
7054
+       return zip_pd_opb_operand(op);
7055
+})
7056
+
7057 122 dgisselq
+(define_predicate "zip_opb_immv_p"
7058
+       (match_code "const_int")
7059
+{
7060
+       return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
7061
+})
7062
+
7063 111 dgisselq
+(define_predicate "zip_opb_single_operand_p"
7064 122 dgisselq
+       (match_code "reg,subreg,const_int")
7065 111 dgisselq
+{
7066
+       return zip_pd_opb_operand(op);
7067
+})
7068
+
7069 102 dgisselq
+(define_predicate "zip_mov_operand_p"
7070
+       (match_code "reg,plus")
7071
+{
7072
+       return zip_pd_mov_operand(op);
7073
+})
7074
+
7075
+(define_predicate "zip_memory_operand_p"
7076
+       (match_code "mem")
7077
+{
7078 111 dgisselq
+       return zip_pd_opb_operand(XEXP(op,0));
7079 102 dgisselq
+})
7080
+
7081 111 dgisselq
+(define_predicate "zip_imm_operand_p"
7082
+       (match_code "const_int")
7083
+{
7084
+       return zip_pd_imm_operand(op);
7085
+})
7086
+
7087
+(define_predicate "zip_mvimm_operand_p"
7088
+       (match_code "const_int")
7089
+{
7090
+       return zip_pd_mvimm_operand(op);
7091
+})
7092
+
7093
+(define_predicate "zip_movdst_operand_p"
7094
+       (match_code "mem,reg,subreg")
7095
+{
7096
+       if (MEM_P(op)) // Check for valid store address
7097
+               return zip_pd_opb_operand(XEXP(op,0));
7098 122 dgisselq
+       else if (SUBREG_P(op))
7099
+               return 1;
7100
+       else if ((REG_P(op))||(SUBREG_P(op)))
7101
+               return register_operand(op, GET_MODE(op));
7102 111 dgisselq
+       return 1;
7103
+})
7104
+
7105
+(define_predicate "zip_movsrc_operand_p"
7106
+       (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
7107
+{
7108
+       if (MEM_P(op))
7109
+               return zip_pd_opb_operand(XEXP(op,0));
7110
+       else if (GET_CODE(op)==PLUS)
7111
+               return zip_pd_opb_operand(op);
7112 122 dgisselq
+       else if (SUBREG_P(op)) {
7113
+               //; As far as predicates are concerned, subregs must be valid.
7114
+               //; The details of them are settled within the constraints.
7115
+               return 1;
7116
+       } else if ((REG_P(op))||(SUBREG_P(op)))
7117
+               return register_operand(op,SImode);
7118
+       else if (CONST_INT_P(op))
7119
+               return 1;
7120 111 dgisselq
+       return 1;
7121
+})
7122
+
7123 102 dgisselq
+;; Constraints
7124
+;
7125
+(define_memory_constraint "S"
7126
+       "Any memory referenced by a constant address, possibly unknown at compile time"
7127
+       (and (match_code "mem")
7128
+               (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
7129
+(define_memory_constraint "Q"
7130
+       "Any memory addressed suitably for a load or store instruction"
7131
+       (and (match_code "mem")
7132
+               (match_test "zip_ct_address_operand(XEXP(op,0))")))
7133
+(define_address_constraint "U"
7134
+       "An address suitable for a load or store instruction"
7135
+       (and (match_code "reg,plus")
7136
+               (match_test "zip_ct_address_operand(op)")))
7137
+(define_address_constraint "T"
7138
+       "Any constant address, to include those made by symbols unknown at compile time"
7139
+       (and (match_code "label_ref,code_label,symbol_ref,const")
7140
+               (match_test "zip_ct_const_address_operand(op)")))
7141
+;
7142
+;
7143
+;; Attributes
7144
+;
7145
+(define_attr "predicable"  "no,yes" (const_string "yes"))
7146
+(define_attr "conditional" "no,yes" (const_string "no"))
7147
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
7148
+;
7149
+; Mode attributes
7150
+; (define_mode_iterator ZI [QI HI SI])
7151
+; (define_mode_attr zipa [(QI "") (HI "") (SI "")])
7152
+(define_mode_iterator ZI [SI])
7153
+(define_mode_attr zipa [(SI "")])
7154
+;
7155
+;
7156
+;
7157
+;; Instructions
7158
+;
7159
+; (define_insn
7160
+;      optional name
7161
+;      RTL template -- a vector of incomplete RTL expressions describing the
7162
+;              semantics of the instruction.  It is incomplete because it may
7163
+;              contain match_operand, match_operator, and match_dup expressions
7164
+;      The condition --- contains a C expression, may be an empty string
7165
+;      output template or output statement--fragment of C code returning a str
7166
+;      Attributes --
7167
+;      )
7168
+;
7169
+; (match_operand:m n predicate constraint)
7170
+;      Placeholder for operand #n of the instruction
7171
+;      Predicate       string that is the name of a fucntion w/ 2 arguments:
7172
+;                              (expression, machine mode)
7173
+;              we can build functions:
7174
+;                      "isregister"    to describe a register
7175
+;                      "isimmediate"   to describe an immediate
7176
+;                      "offsetreg"     to describe a register plus offset
7177
+;                      "anyregister"   to describe *ANY* register (uRx or Rx)
7178
+;              But ... functions "address_operand", "immediate_operand",
7179
+;                      "register_operand", "indirect_operand"
7180
+;              "comparison_operatot" and "ordered_comparison_operator"
7181
+;              are also available--be aware, they include more comparisons
7182
+;              than Zip CPU can do.
7183
+;
7184
+;
7185
+;
7186
+;
7187
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7188
+;;
7189
+;; Move instructions: both
7190
+;      (arbitrary) from variables to variables, but this gets
7191
+;              expanded into:
7192
+;      from registers to registers
7193
+;      from immediates to registers
7194
+;;
7195
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7196
+;
7197
+;
7198
+;
7199
+(define_expand "mov<mode>"
7200 111 dgisselq
+       [(set (match_operand:ZI 0 "nonimmediate_operand" "")
7201
+               (match_operand:ZI 1 "general_operand" ""))]
7202 102 dgisselq
+       ""
7203 111 dgisselq
+       {//; Everything except mem=const or mem=mem can be done easily
7204
+       //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
7205
+       //; fprintf(stderr, "ZIP-GEN-MOVE\n");
7206
+       //; zip_debug_rtx_pfx("FROM: ", operands[1]);
7207
+       //; zip_debug_rtx_pfx("TO  : ", operands[0]);
7208
+
7209
+       //; Need to load into a register between memory slots
7210
+       if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
7211
+               //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
7212
+               if (can_create_pseudo_p()) {
7213
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
7214
+                       emit_insn(gen_movsi(tmp,operands[1]));
7215
+                       operands[1] = tmp;
7216
+               }
7217 102 dgisselq
+       }
7218 111 dgisselq
+
7219
+       //; Op[0] has a bad address, need to legitimize it
7220
+       if ((MEM_P(operands[0]))&&
7221
+               ((zip_const_address_operand(XEXP(operands[0],0)))
7222
+               ||(!zip_pd_opb_operand(XEXP(operands[0],0))))
7223
+               )
7224
+               {
7225
+               //; fprintf(stderr, "GEN-MOVSI: Not to a MEM(REG)\n");
7226
+               if (can_create_pseudo_p()) {
7227
+                       rtx tmp = gen_reg_rtx(Pmode);
7228
+                       //; Load the address into a register
7229
+                       emit_insn(gen_movsi(tmp,XEXP(operands[0],0)));
7230
+                       XEXP(operands[0],0) = tmp;
7231
+                       mark_reg_pointer(tmp,1);
7232
+               }
7233
+       }
7234
+       //; Op[1] is a constant.  Need to load into a register before we can
7235
+       //; place it into memory.
7236
+       if ((MEM_P(operands[0]))&&
7237
+               ((CONSTANT_P(operands[1]))
7238
+               ||(CONST_INT_P(operands[1])))) {
7239
+               //; fprintf(stderr, "GEN-MOVSI: CONST -> MEM\n");
7240
+               //; zip_debug_rtx_pfx("MEM  : ", operands[0]);
7241
+               //; zip_debug_rtx_pfx("CONST: ", operands[1]);
7242
+               if (can_create_pseudo_p()) {
7243
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[0]));
7244
+                       emit_insn(gen_movsi(tmp,operands[1]));
7245
+                       operands[1] = tmp;
7246
+               }
7247
+       }
7248
+       //; Op[1] has a bad address, need to legitimize it
7249
+       if ((MEM_P(operands[1]))&&
7250
+               //; (!REG_P(XEXP(operands[1],0)))
7251
+               ((zip_const_address_operand(XEXP(operands[1],0)))
7252 122 dgisselq
+               ||(!zip_pd_opb_operand(XEXP(operands[1],0))))) {
7253 111 dgisselq
+               //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
7254
+               if (can_create_pseudo_p()) {
7255
+                       rtx tmp = gen_reg_rtx(Pmode);
7256
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
7257
+                       XEXP(operands[1],0) = tmp;
7258
+               } else if (REG_P(operands[0])) { //; Can we steal Op[0]'s reg?
7259
+                       rtx tmp = operands[0];
7260
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
7261
+                       XEXP(operands[1],0) = tmp;
7262
+               }
7263
+       }
7264
+       }
7265 102 dgisselq
+       [(set_attr "ccresult" "unchanged")])
7266 111 dgisselq
+(define_insn "movsi_raw"
7267
+       [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
7268
+               (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
7269 122 dgisselq
+       "(register_operand(operands[0],SImode))||(register_operand(operands[1],SImode))"
7270 111 dgisselq
+       "@
7271
+       MOV\t%1,%0
7272
+       STO\t%1,%0
7273
+       LOD\t%1,%0
7274
+       LDI\t%1,%0"
7275
+       [(set_attr "ccresult" "unchanged")])
7276 102 dgisselq
+(define_insn "mov<mode>_reg"   ; Register to register move
7277
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7278
+               (match_operand:ZI 1 "register_operand" "r"))]
7279
+       ""
7280
+       "MOV    %1,%0"
7281
+       [(set_attr "ccresult" "unchanged")])
7282 124 dgisselq
+(define_insn "mov<mode>_reg_off" ; Register to register move, used by prologue
7283 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7284
+               (plus:ZI (match_operand:ZI 1 "register_operand" "r")
7285 111 dgisselq
+                       (match_operand:ZI 2 "zip_mvimm_operand_p" "M")))
7286
+               ]
7287 102 dgisselq
+       ""
7288
+       "MOV    %2(%1),%0"
7289
+       [(set_attr "ccresult" "unchanged")])
7290 103 dgisselq
+;(define_insn "mov<mode>_lod"  ; Load from memory
7291
+;      [(set (match_operand:ZI 0 "register_operand" "=r")
7292
+;              (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
7293
+;      ""
7294
+;      "LOD    %1,%0"
7295
+;      [(set_attr "ccresult" "unchanged")])
7296
+;(define_insn "mov<mode>_sto"  ; Store into memory
7297
+;      [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
7298
+;              (match_operand:ZI 1 "register_operand" "r"))]
7299
+;      ""
7300
+;      "STO    %1,%0"
7301
+;      [(set_attr "ccresult" "unchanged")])
7302
+(define_expand "mov<mode>_lod" ; Load from memory
7303 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7304
+               (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
7305 103 dgisselq
+       "")
7306
+(define_insn "*movsi_lod"
7307
+       [(set (match_operand:SI 0 "register_operand" "=r")
7308 111 dgisselq
+               (match_operand:SI 1 "zip_memory_operand_p" ""))]
7309 102 dgisselq
+       ""
7310 103 dgisselq
+       "LOD\t%1,%0"
7311
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7312 124 dgisselq
+(define_insn "movsi_lod_off" ; used by epilogue code
7313
+       [(set (match_operand:SI 0 "register_operand" "=r")
7314
+               (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
7315
+                       (match_operand:SI 2 "const_int_operand" "N"))))]
7316
+       ""
7317
+       "LOD\t%2(%1),%0"
7318
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7319 103 dgisselq
+(define_expand "mov<mode>_sto" ; Store into memory
7320 102 dgisselq
+       [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
7321
+               (match_operand:ZI 1 "register_operand" "r"))]
7322 103 dgisselq
+       "")
7323
+(define_insn "*movsi_sto"
7324 111 dgisselq
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
7325 103 dgisselq
+               (match_operand:SI 1 "register_operand" "r"))]
7326 102 dgisselq
+       ""
7327 111 dgisselq
+       "STO\t%1,%0"
7328 103 dgisselq
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7329 124 dgisselq
+(define_insn "movsi_sto_off" ; used by prologue code
7330
+       [(set (mem:SI (plus:SI
7331
+                       (match_operand:SI 0 "register_operand" "r")
7332
+                       (match_operand:SI 1 "const_int_operand" "N")))
7333
+               (match_operand:SI 2 "register_operand" "r"))]
7334
+       ""
7335
+       "STO\t%2,%1(%0)"
7336
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7337 102 dgisselq
+(define_insn "mov<mode>_ldi"   ; Load immediate
7338
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7339
+               (match_operand:ZI 1 "immediate_operand" "ipU"))]
7340
+       ""
7341
+       "LDI    %1,%0"
7342
+       [(set_attr "ccresult" "unchanged")])
7343
+;
7344
+;
7345
+;
7346
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7347
+;;
7348
+;; Load and store multiple values
7349
+;;
7350
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7351
+;
7352
+; So far, from the code I've seen from GCC's output,
7353
+; these instructions do not appear to be necessary.
7354
+;
7355
+;(define_insn "load_multiple"
7356
+;      for(a=0; a<%2; a++)
7357
+;              LOD a(%1),%0+a
7358
+;(define_insn "store_multiple"
7359
+;      for(a=0; a<%2; a++)
7360
+;              STO %0+a,a(%1)
7361
+; pushsi -- Do not define, compiler will work around it nicely w/o our help
7362
+;
7363
+;
7364
+;
7365
+;
7366
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7367
+;;
7368 127 dgisselq
+;; Substitution Pattern
7369
+;;
7370
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7371
+;
7372
+;
7373
+(define_subst "cc_substitution"
7374
+       ; The pattern may not have any match_dup expressions.
7375
+       [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7376
+               (clobber (reg:CC CC_REG))]
7377
+       ""
7378
+       [(set (match_dup 0) (match_dup 1))
7379
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
7380
+       ])
7381
+;
7382
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
7383
+;
7384
+;
7385
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7386
+;;
7387 102 dgisselq
+;; General arithmetic instructions
7388
+;;
7389
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7390
+;
7391
+;
7392
+;
7393
+;
7394 111 dgisselq
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
7395 127 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7396 103 dgisselq
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7397 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
7398 127 dgisselq
+       ])
7399
+(define_insn_and_split "add<mode>3_split_reg"
7400
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7401
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7402
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7403
+       ""
7404
+       "#"     ; This code means the instruction *must* be split
7405
+       "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
7406
+       [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) (match_dup 2)))
7407
+               (clobber (reg:CC CC_REG))])]
7408
+       ""
7409
+       [(set_attr "predicable" "yes")])
7410
+(define_insn_and_split "add<mode>3_split_off"
7411
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7412
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7413
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7414
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7415
+       ""
7416
+       "#"     ; This code means the instruction *must* be split
7417
+       "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
7418
+       [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1)
7419
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7420
+               (clobber (reg:CC CC_REG))])]
7421
+       ""
7422
+       [(set_attr "predicable" "yes")])
7423
+(define_insn "addsi3_reg_clobber"
7424 122 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
7425
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
7426
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7427 127 dgisselq
+       (clobber (reg:CC CC_REG))]
7428
+       ""
7429
+       "ADD    %2,%0"
7430
+       [(set_attr "ccresult" "set")])
7431
+(define_insn "addsi3_reg_raw"
7432
+       [(set (match_operand:SI 0 "register_operand" "=r")
7433
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
7434
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7435 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7436 102 dgisselq
+       ""
7437
+       "ADD    %2,%0"
7438
+       [(set_attr "ccresult" "set")])
7439 127 dgisselq
+(define_insn "add<mode>3_off_raw"
7440 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7441 103 dgisselq
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7442
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7443 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7444
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7445 102 dgisselq
+       ""
7446
+       "ADD    %3+%2,%0"
7447
+       [(set_attr "ccresult" "set")])
7448 127 dgisselq
+(define_insn "add<mode>3_off_clobber"
7449
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7450
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7451
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7452
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7453
+       (clobber (reg:CC CC_REG))]
7454
+       ""
7455
+       "ADD    %3+%2,%0"
7456
+       [(set_attr "ccresult" "set")])
7457 102 dgisselq
+;
7458
+;
7459
+;
7460 103 dgisselq
+(define_expand "sub<mode>3"
7461 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
7462 103 dgisselq
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7463 111 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
7464 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])])
7465 127 dgisselq
+(define_insn_and_split "sub<mode>3_split_reg"
7466 103 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7467
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7468 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7469
+       ""
7470
+       "#"
7471
+       "(reload_completed)"
7472
+       [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) (match_dup 2)))
7473
+       (clobber (reg:CC CC_REG))])]
7474
+       ""
7475
+       [(set_attr "ccresult" "set")])
7476
+(define_insn "sub<mode>3_reg_raw"
7477
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7478
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7479 111 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7480 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7481 102 dgisselq
+       ""
7482
+       "SUB    %2,%0"
7483
+       [(set_attr "ccresult" "set")])
7484 127 dgisselq
+(define_insn "sub<mode>3_reg_clobber"
7485 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7486 103 dgisselq
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7487 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7488
+       (clobber (reg:CC CC_REG))]
7489
+       ""
7490
+       "SUB    %2,%0"
7491
+       [(set_attr "ccresult" "set")])
7492
+(define_insn_and_split "sub<mode>3_off_split"
7493
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7494
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7495 103 dgisselq
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
7496 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7497
+       ""
7498
+       "#"
7499
+       "(reload_completed)"
7500
+       [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1)
7501
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7502
+       (clobber (reg:CC CC_REG))])]
7503
+       ""
7504
+       [(set_attr "ccresult" "set")])
7505
+(define_insn "sub<mode>3_off_raw"
7506
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7507
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7508
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
7509 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7510
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7511 102 dgisselq
+       ""
7512
+       "SUB    %3+%2,%0"
7513
+       [(set_attr "ccresult" "set")])
7514 127 dgisselq
+(define_insn "sub<mode>3_off_clobber"
7515
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7516
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7517
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
7518
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7519
+       (clobber (reg:CC CC_REG))]
7520
+       ""
7521
+       "SUB    %3+%2,%0"
7522
+       [(set_attr "ccresult" "set")])
7523 102 dgisselq
+(define_insn "mul<mode>3"
7524
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7525
+               (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
7526
+                       (match_operand:ZI 2 "register_operand" "r")))
7527 122 dgisselq
+       (clobber (match_scratch:ZI 3 "=r"))
7528
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7529 102 dgisselq
+       ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
7530
+       ""
7531
+       "MOV    %1,%0
7532
+       MPYS    %2,%0
7533
+       MOV     %1,%3
7534
+       ROL     16,%3
7535
+       MPYS    %2,%3
7536
+       ROL     16,%3
7537
+       AND     0x0ffff,%3
7538
+       ADD     %3,%0
7539
+       MOV     %2,%3
7540
+       ROL     16,%3
7541
+       MPYS    %1,%3
7542
+       ROL     16,%3
7543
+       AND     0x0ffff,%3
7544
+       ADD     %3,%0"
7545
+       [(set_attr "ccresult" "unknown")])
7546
+
7547 111 dgisselq
+(define_expand "div<mode>3"
7548 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
7549 103 dgisselq
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
7550 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
7551
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
7552 111 dgisselq
+       "(ZIP_DIVIDE)")
7553
+(define_insn "div<mode>3_reg"
7554
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7555
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
7556 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7557
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7558 111 dgisselq
+       "(ZIP_DIVIDE)"
7559 102 dgisselq
+       "DIVS   %2,%0"
7560
+       [(set_attr "ccresult" "set")])
7561
+(define_insn "div<mode>3_off"
7562
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7563 103 dgisselq
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
7564
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7565 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7566
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7567 111 dgisselq
+       "(ZIP_DIVIDE)"
7568 102 dgisselq
+       "DIVS   %3+%2,%0"
7569
+       [(set_attr "ccresult" "set")])
7570 111 dgisselq
+(define_expand "udiv<mode>3"
7571 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
7572 103 dgisselq
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
7573 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
7574
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
7575 111 dgisselq
+       "(ZIP_DIVIDE)")
7576
+(define_insn "udiv<mode>3_reg"
7577
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7578
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
7579 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7580
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7581 111 dgisselq
+       "(ZIP_DIVIDE)"
7582 102 dgisselq
+       "DIVU   %2,%0"
7583
+       [(set_attr "ccresult" "set")])
7584
+(define_insn "udiv<mode>3_off"
7585
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7586 103 dgisselq
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
7587
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7588 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7589
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7590 111 dgisselq
+       "(ZIP_DIVIDE)"
7591 102 dgisselq
+       "DIVU   %3+%2,%0"
7592
+       [(set_attr "ccresult" "set")])
7593
+;;
7594
+;; modsi3
7595
+;; umodsi3
7596
+;;
7597
+(define_insn "umin<mode>3"
7598
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7599
+               (umin:ZI (match_operand:ZI 1 "register_operand" "%0")
7600
+                       (match_operand:ZI 2 "register_operand" "r")))
7601 122 dgisselq
+       (clobber (reg:CC CC_REG))
7602 102 dgisselq
+       ]
7603
+       ""
7604
+       "CMP    %0,%2
7605
+       MOV.C   %2,%0"
7606
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
7607
+(define_insn "umax<mode>3"
7608
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7609
+               (umax:ZI (match_operand:ZI 1 "register_operand" "%0")
7610
+                       (match_operand:ZI 2 "register_operand" "r")))
7611 122 dgisselq
+       (clobber (reg:CC CC_REG))
7612 102 dgisselq
+       ]
7613
+       ""
7614
+       "CMP    %2,%0
7615
+       MOV.C   %2,%0"
7616
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
7617
+(define_insn "smin<mode>3"
7618
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7619
+               (smin:ZI (match_operand:ZI 1 "register_operand" "%0")
7620
+                       (match_operand:ZI 2 "register_operand" "r")))
7621 122 dgisselq
+       (clobber (reg:CC CC_REG))
7622 102 dgisselq
+       ]
7623
+       ""
7624
+       "CMP    %2,%0
7625
+       MOV.GT  %2,%0"
7626
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
7627
+(define_insn "smax<mode>3"
7628
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7629
+               (smax:ZI (match_operand:ZI 1 "register_operand" "%0")
7630
+                       (match_operand:ZI 2 "register_operand" "r")))
7631 122 dgisselq
+       (clobber (reg:CC CC_REG))
7632 102 dgisselq
+       ]
7633
+       ""
7634
+       "CMP    %0,%2
7635
+       MOV.LT  %2,%0"
7636
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
7637 127 dgisselq
+;
7638
+;
7639 111 dgisselq
+(define_expand "and<mode>3"
7640 127 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7641 102 dgisselq
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
7642 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
7643
+(define_insn_and_split "and<mode>3_reg_split"
7644 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7645
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
7646 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7647
+       ""
7648
+       "#"
7649
+       "(reload_completed)"
7650
+       [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) (match_dup 2)))
7651
+       (clobber (reg:CC CC_REG))])]
7652
+       ""
7653
+       [(set_attr "ccresult" "set")])
7654
+(define_insn "and<mode>3_reg_raw"
7655
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7656
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
7657 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7658
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7659 102 dgisselq
+       ""
7660
+       "AND    %2,%0"
7661
+       [(set_attr "ccresult" "set")])
7662 127 dgisselq
+(define_insn "and<mode>3_reg_clobber"
7663 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7664 127 dgisselq
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
7665
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7666
+       (clobber (reg:CC CC_REG))]
7667
+       ""
7668
+       "AND    %2,%0"
7669
+       [(set_attr "ccresult" "set")])
7670
+(define_insn_and_split "and<mode>3_off_split"
7671
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7672 102 dgisselq
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
7673
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7674 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7675
+       ""
7676
+       "#"
7677
+       "(reload_completed)"
7678
+       [(parallel [(set (match_dup 0) (and:ZI (match_dup 1)
7679
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7680
+       (clobber (reg:CC CC_REG))])]
7681
+       ""
7682
+       [(set_attr "ccresult" "set")])
7683
+(define_insn "and<mode>3_off_raw"
7684
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7685
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
7686
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7687 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7688
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7689 102 dgisselq
+       ""
7690
+       "AND    %3+%2,%0"
7691
+       [(set_attr "ccresult" "set")])
7692 127 dgisselq
+(define_insn "and<mode>3_off_clobber"
7693
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7694
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
7695
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7696
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7697
+       (clobber (reg:CC CC_REG))]
7698
+       ""
7699
+       "AND    %3+%2,%0"
7700
+       [(set_attr "ccresult" "set")])
7701
+;
7702
+;
7703 111 dgisselq
+(define_expand "ior<mode>3"
7704 127 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7705 102 dgisselq
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
7706 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
7707
+(define_insn_and_split "ior<mode>3_reg_split"
7708 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7709
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
7710 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7711
+       ""
7712
+       "#"
7713
+       "(reload_completed)"
7714
+       [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) (match_dup 2)))
7715
+       (clobber (reg:CC CC_REG))])]
7716
+       ""
7717
+       [(set_attr "ccresult" "set")])
7718
+(define_insn "ior<mode>3_reg_raw"
7719
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7720
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
7721 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7722
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7723 102 dgisselq
+       ""
7724
+       "OR     %2,%0"
7725
+       [(set_attr "ccresult" "set")])
7726 127 dgisselq
+(define_insn "ior<mode>3_reg_clobber"
7727 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7728 127 dgisselq
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
7729
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7730
+       (clobber (reg:CC CC_REG))]
7731
+       ""
7732
+       "OR     %2,%0"
7733
+       [(set_attr "ccresult" "set")])
7734
+(define_insn_and_split "ior<mode>3_off_split"
7735
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7736 102 dgisselq
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
7737
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7738 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7739
+       ""
7740
+       "#"
7741
+       "(reload_completed)"
7742
+       [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1)
7743
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7744
+       (clobber (reg:CC CC_REG))])]
7745
+       ""
7746
+       [(set_attr "ccresult" "set")])
7747
+(define_insn "ior<mode>3_off_raw"
7748
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7749
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
7750
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7751 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7752
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7753 102 dgisselq
+       ""
7754
+       "OR     %3+%2,%0"
7755
+       [(set_attr "ccresult" "set")])
7756 127 dgisselq
+(define_insn "ior<mode>3_off_clobber"
7757
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7758
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
7759
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7760
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7761
+       (clobber (reg:CC CC_REG))]
7762
+       ""
7763
+       "OR     %3+%2,%0"
7764
+       [(set_attr "ccresult" "set")])
7765
+;
7766
+;
7767
+;
7768 111 dgisselq
+(define_expand "xor<mode>3"
7769 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
7770 102 dgisselq
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
7771 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
7772
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
7773
+       "")
7774 127 dgisselq
+(define_insn_and_split "xor<mode>3_reg_split"
7775 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7776
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
7777 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7778
+       ""
7779
+       "#"
7780
+       "(reload_completed)"
7781
+       [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) (match_dup 2)))
7782
+       (clobber (reg:CC CC_REG))])]
7783
+       ""
7784
+       [(set_attr "ccresult" "set")])
7785
+(define_insn "xor<mode>3_reg_raw"
7786
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7787
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
7788 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7789
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7790 102 dgisselq
+       ""
7791
+       "XOR    %2,%0"
7792
+       [(set_attr "ccresult" "set")])
7793 127 dgisselq
+(define_insn "xor<mode>3_reg_clobber"
7794 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7795 127 dgisselq
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
7796
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7797
+       (clobber (reg:CC CC_REG))]
7798
+       ""
7799
+       "XOR    %2,%0"
7800
+       [(set_attr "ccresult" "set")])
7801
+(define_insn_and_split "xor<mode>3_off_split"
7802
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7803 102 dgisselq
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
7804
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7805 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7806
+       ""
7807
+       "#"
7808
+       "(reload_completed)"
7809
+       [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1)
7810
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7811
+       (clobber (reg:CC CC_REG))])]
7812
+       ""
7813
+       [(set_attr "ccresult" "set")])
7814
+(define_insn "xor<mode>3_off_raw"
7815
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7816
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
7817
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7818 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7819
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7820 102 dgisselq
+       ""
7821
+       "XOR    %3+%2,%0"
7822
+       [(set_attr "ccresult" "set")])
7823 127 dgisselq
+(define_insn "xor<mode>3_off_clobber"
7824
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7825
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
7826
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7827
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7828
+       (clobber (reg:CC CC_REG))]
7829
+       ""
7830
+       "XOR    %3+%2,%0"
7831
+       [(set_attr "ccresult" "set")])
7832 102 dgisselq
+;(define_insn "addv<mode>4"
7833
+       ;[(set (match_operand:ZI 0 "register_operand" "=r")
7834
+               ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
7835
+                       ;(match_operand:ZI 2 "general_operand" "rO")))
7836 122 dgisselq
+       ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
7837 102 dgisselq
+                       ;(label_ref (match_operand 3))
7838
+                       ;(pc)))]
7839
+       ;""
7840
+       ;"MOV   %1,%0
7841
+       ;ADD    %2,%0
7842
+       ;BV     %3"
7843
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "set")])
7844
+;;(define_insn "subvsi4"
7845
+;;     MOV     %1,%0
7846
+;;     SUB     %2,%0
7847
+;;     BV      %3
7848
+;;(mulvsi4)
7849
+;;(define_insn "uaddvsi4"
7850
+;;     ADD     %2,%0
7851
+;;     BC      %3
7852
+;;(define_insn "usubvsi4"
7853
+;;     MOV     %1,%0
7854
+;;     SUB     %2,%0
7855
+;;     BC      %3
7856
+;;
7857
+;; (define_insn "umulvsi4"
7858
+;;     ... ???)
7859
+;;
7860 127 dgisselq
+(define_expand "ashr<mode>3"
7861 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7862
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7863 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
7864
+(define_insn_and_split "ashr<mode>3_split"
7865
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7866
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7867
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
7868
+       ""
7869
+       "#"
7870
+       "(reload_completed)"
7871
+       [(parallel [(set (match_dup 0) (ashiftrt:ZI (match_dup 1) (match_dup 2)))
7872
+       (clobber (reg:CC CC_REG))])]
7873
+       ""
7874
+       [(set_attr "ccresult" "set")])
7875
+(define_insn "ashr<mode>3_raw"
7876
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7877
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7878 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7879
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7880 102 dgisselq
+       ""
7881
+       "ASR    %2,%0"
7882
+       [(set_attr "ccresult" "set")])
7883 127 dgisselq
+(define_insn "ashr<mode>3_clobber"
7884 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7885 127 dgisselq
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7886
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7887
+       (clobber (reg:CC CC_REG))]
7888
+       ""
7889
+       "ASR    %2,%0"
7890
+       [(set_attr "ccresult" "set")])
7891
+;
7892
+;
7893
+(define_expand "ashl<mode>3"
7894
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7895 111 dgisselq
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
7896 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
7897
+(define_insn_and_split "ashl<mode>3_split"
7898
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7899
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
7900
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
7901
+       ""
7902
+       "#"
7903
+       "(reload_completed)"
7904
+       [(parallel [(set (match_dup 0) (ashift:ZI (match_dup 1) (match_dup 2)))
7905
+       (clobber (reg:CC CC_REG))])]
7906
+       ""
7907
+       [(set_attr "ccresult" "set")])
7908
+(define_insn "ashl<mode>3_raw"
7909
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7910
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
7911 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7912
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7913 111 dgisselq
+       ""
7914 122 dgisselq
+       "LSL    %2,%0"
7915 111 dgisselq
+       [(set_attr "ccresult" "set")])
7916 127 dgisselq
+(define_insn "ashl<mode>3_clobber"
7917 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7918 127 dgisselq
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
7919
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7920
+       (clobber (reg:CC CC_REG))]
7921
+       ""
7922
+       "LSL    %2,%0"
7923
+       [(set_attr "ccresult" "set")])
7924
+;
7925
+;
7926
+(define_expand "lshr<mode>3"
7927
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7928 102 dgisselq
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7929 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
7930
+(define_insn_and_split "lshr<mode>3_split"
7931
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7932
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7933
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
7934
+       ""
7935
+       "#"
7936
+       "(reload_completed)"
7937
+       [(parallel [(set (match_dup 0) (lshiftrt:ZI (match_dup 1) (match_dup 2)))
7938
+       (clobber (reg:CC CC_REG))])]
7939
+       ""
7940
+       [(set_attr "ccresult" "set")])
7941
+(define_insn "lshr<mode>3_raw"
7942
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7943
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7944
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7945 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7946 102 dgisselq
+       ""
7947
+       "LSR    %2,%0"
7948
+       [(set_attr "ccresult" "set")])
7949 127 dgisselq
+(define_insn "lshr<mode>3_clobber"
7950 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7951 127 dgisselq
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7952
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7953
+       (clobber (reg:CC CC_REG))]
7954
+       ""
7955
+       "LSR    %2,%0"
7956
+       [(set_attr "ccresult" "set")])
7957
+;
7958
+;
7959
+(define_expand "rotl<mode>3"
7960
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7961 102 dgisselq
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
7962 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
7963
+(define_insn_and_split "rotl<mode>3_split"
7964
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7965
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
7966
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
7967
+       ""
7968
+       "#"
7969
+       "(reload_completed)"
7970
+       [(parallel [(set (match_dup 0) (rotate:ZI (match_dup 1) (match_dup 2)))
7971
+       (clobber (reg:CC CC_REG))])]
7972
+       ""
7973
+       [(set_attr "ccresult" "set")])
7974
+(define_insn "rotl<mode>3_raw"
7975
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7976
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
7977 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7978
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7979 102 dgisselq
+       ""
7980
+       "ROL    %2,%0"
7981
+       [(set_attr "ccresult" "set")])
7982 127 dgisselq
+(define_insn "rotl<mode>3_clobber"
7983
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7984
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
7985
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
7986
+       (clobber (reg:CC CC_REG))]
7987
+       ""
7988
+       "ROL    %2,%0"
7989
+       [(set_attr "ccresult" "set")])
7990 102 dgisselq
+;
7991 127 dgisselq
+;
7992
+;
7993 102 dgisselq
+(define_insn "neg<mode>2"
7994
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7995
+               (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
7996 122 dgisselq
+       (clobber (reg:CC CC_REG))]
7997 102 dgisselq
+       ""
7998
+       "NEG    %1,%0"
7999
+       [(set_attr "ccresult" "validzn")])
8000
+(define_insn "abs<mode>2"
8001
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8002
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
8003 122 dgisselq
+       (clobber (reg:CC CC_REG))]
8004 102 dgisselq
+       ""
8005
+       "TEST   %0
8006
+       NEG.LT  %0"
8007
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8008
+(define_insn "popcount<mode>2"
8009
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8010
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
8011 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8012 102 dgisselq
+       ""
8013
+       "POPC   %1,%0"
8014
+       [(set_attr "ccresult" "set")])
8015
+(define_expand "parity<mode>2"
8016 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
8017 102 dgisselq
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
8018 127 dgisselq
+               (clobber (reg:CC CC_REG))])
8019 122 dgisselq
+       (parallel [
8020
+               (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
8021
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
8022 102 dgisselq
+       ])
8023
+(define_insn "one_cmpl<mode>2"
8024
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8025
+               (not:ZI (match_operand:ZI 1 "register_operand" "0")))
8026 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8027 102 dgisselq
+       ""
8028
+       "XOR    -1,%0"
8029
+       [(set_attr "ccresult" "set")])
8030
+;
8031
+;
8032
+;
8033
+;
8034 117 dgisselq
+;
8035 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8036
+;;
8037
+;; General arithmetic instructions -- double words
8038
+;;
8039
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8040
+;
8041
+;
8042
+;
8043 111 dgisselq
+(define_expand "movdi3"
8044
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
8045
+               (match_operand:DI 1 "general_operand" ""))])
8046
+(define_insn "movdi_lod"
8047
+       [(set (match_operand:DI 0 "register_operand" "=r")
8048 122 dgisselq
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
8049 111 dgisselq
+       ""
8050
+       {
8051 122 dgisselq
+               if (REG_P(operands[1]))
8052 111 dgisselq
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
8053 122 dgisselq
+               else if (GET_CODE(operands[1])==PLUS) {
8054
+                       if ((REG_P(XEXP(operands[1],0)))
8055
+                               &&(CONST_INT_P(XEXP(operands[1],1)))) {
8056 111 dgisselq
+                               static  char    buf[64];
8057
+                               sprintf(buf,
8058
+                                       "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
8059 122 dgisselq
+                                       INTVAL(XEXP(operands[1],1)),
8060
+                                       INTVAL(XEXP(operands[1],1)+1));
8061 111 dgisselq
+                               return buf;
8062
+                       }
8063 122 dgisselq
+               } return "BREAK";
8064 111 dgisselq
+       }
8065
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8066
+(define_insn "movdi_sto"
8067
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
8068
+               (match_operand:DI 1 "register_operand" "r"))]
8069
+       ""
8070
+       {
8071
+               if (REG_P(operands[0]))
8072
+                       return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
8073
+               else if (GET_CODE(operands[0])==PLUS) {
8074
+                       if ((REG_P(XEXP(operands[0],0)))
8075
+                               &&(CONST_INT_P(XEXP(operands[0],1)))) {
8076
+                               static  char    buf[64];
8077
+                               sprintf(buf,
8078
+                                       "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
8079
+                                       INTVAL(XEXP(operands[0],1)),
8080
+                                       INTVAL(XEXP(operands[0],1)+1));
8081
+                               return buf;
8082
+                       }
8083 127 dgisselq
+               } return "BREAK";
8084 111 dgisselq
+       }
8085
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8086
+(define_insn "movdi_ldi"
8087
+       [(set (match_operand:DI 0 "register_operand" "=r")
8088
+               (match_operand:DI 1 "immediate_operand" "i"))]
8089
+       ""
8090
+       "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
8091
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8092 102 dgisselq
+(define_insn "adddi3" ; Fastest/best instruction always goes first
8093
+       [(set (match_operand:DI 0 "register_operand" "=r")
8094 103 dgisselq
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
8095 102 dgisselq
+                       (match_operand:DI 2 "register_operand" "r")))
8096 122 dgisselq
+       (clobber (reg:CC CC_REG))
8097 102 dgisselq
+       ]
8098
+       ""
8099
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
8100
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8101
+;
8102
+(define_insn "subdi3"
8103
+       [(set (match_operand:DI 0 "register_operand" "=r")
8104 103 dgisselq
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
8105 102 dgisselq
+                       (match_operand:DI 2 "register_operand" "r")))
8106 122 dgisselq
+       (clobber (reg:CC CC_REG))
8107 102 dgisselq
+       ]
8108
+       ""
8109
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
8110
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8111
+;
8112
+(define_insn "anddi3"
8113
+       [(set (match_operand:DI 0 "register_operand" "=r")
8114
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
8115
+                       (match_operand:DI 2 "register_operand" "r")))
8116 122 dgisselq
+       (clobber (reg:CC CC_REG))
8117 102 dgisselq
+       ]
8118
+       ""
8119
+       "AND    %L2,%L0\n\tAND\t%H2,%H0"
8120
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8121
+;
8122
+(define_insn "iordi3"
8123
+       [(set (match_operand:DI 0 "register_operand" "=r")
8124
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
8125
+                       (match_operand:DI 2 "register_operand" "r")))
8126 122 dgisselq
+       (clobber (reg:CC CC_REG))
8127 102 dgisselq
+       ]
8128
+       ""
8129
+       "OR     %2,%0\n\tOR\t%H2,%H0"
8130
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8131
+;
8132
+(define_insn "xordi3"
8133
+       [(set (match_operand:DI 0 "register_operand" "=r")
8134
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
8135
+                       (match_operand:DI 2 "register_operand" "r")))
8136 122 dgisselq
+       (clobber (reg:CC CC_REG))
8137 102 dgisselq
+       ]
8138
+       ""
8139
+       "XOR    %2,%0\n\tXOR\t%H2,%H0"
8140
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8141
+;
8142
+(define_insn "negdi2"
8143
+       [(set (match_operand:DI 0 "register_operand" "=r")
8144 122 dgisselq
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
8145
+       (clobber (reg:CC CC_REG))
8146
+       ]
8147 102 dgisselq
+       ""
8148
+       "XOR    -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
8149
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8150
+;
8151
+(define_insn "absdi2"
8152 122 dgisselq
+       [(set (match_operand:DI 0 "register_operand" "=r")
8153
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
8154
+       (clobber (match_scratch:SI 2 "=r"))
8155
+       (clobber (reg:CC CC_REG))
8156
+       ]
8157 102 dgisselq
+       ""
8158
+       "CLR    %2
8159
+       TEST    %H0             ; Problem, we can't tell conditions
8160
+       LDILO.LT        1,%2
8161
+       XOR.LT  -1,%L0
8162
+       XOR.LT  -1,%H0
8163
+       ADD     %2,%L0
8164 122 dgisselq
+       ADD.C   1,%H0"
8165 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8166
+(define_insn "one_cmpldi2"
8167
+       [(set (match_operand:DI 0 "register_operand" "=r")
8168
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
8169 122 dgisselq
+       (clobber (reg:CC CC_REG))
8170 102 dgisselq
+       ]
8171
+       ""
8172
+       "XOR    -1,%L0\n\tXOR\t-1,%H0"
8173
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8174
+(define_insn "umindi3"
8175
+       [(set (match_operand:DI 0 "register_operand" "=r")
8176
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
8177
+                       (match_operand:DI 2 "register_operand" "r")))
8178 122 dgisselq
+       (clobber (reg:CC CC_REG))
8179 102 dgisselq
+       ]
8180
+       ""
8181
+       "CMP    %H0,%H2
8182
+       CMP.Z   %L0,%L2
8183
+       MOV.C   %H2,%H0
8184
+       MOV.C   %L2,%L0"
8185
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8186
+(define_insn "umaxdi3"
8187
+       [(set (match_operand:DI 0 "register_operand" "=r")
8188
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
8189
+                       (match_operand:DI 2 "register_operand" "r")))
8190 122 dgisselq
+       (clobber (reg:CC CC_REG))
8191 102 dgisselq
+       ]
8192
+       ""
8193
+       "CMP    %H2,%H0
8194
+       CMP.Z   %L2,%L0
8195
+       MOV.C   %H2,%H0
8196
+       MOV.C   %L2,%L0"
8197
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8198
+(define_insn "popcountdi2"
8199
+       [(set (match_operand:SI 0 "register_operand" "=r")
8200 122 dgisselq
+               (popcount:SI (match_operand:DI 1 "register_operand" "r")))
8201 102 dgisselq
+       (clobber (match_scratch:SI 2 "=r"))
8202 122 dgisselq
+       (clobber (reg:CC CC_REG))
8203 102 dgisselq
+       ]
8204
+       ""
8205
+       "POPC   %L1,%0
8206
+       POPC    %H1,%2
8207
+       ADD     %2,%0"
8208
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8209
+(define_expand "paritydi2"
8210
+       [(set (match_operand:SI 0 "register_operand" "=r")
8211
+               (popcount (match_operand:DI 1 "register_operand" "r")))
8212
+       (set (match_dup 0) (and:SI (match_dup 0) (const_int -2)))
8213
+       ])
8214 117 dgisselq
+;(define_insn "extendsidi2"
8215
+;      [(set (match_operand:DI 0 "register_operand" "=r")
8216
+;              (sign_extend:DI (match_operand:SI 0 "register_operand" "r")))]
8217
+;      ""
8218
+;      "TEST\t%1\nMOV\t%1,%L0\nCLR\t%L1\nLDI.LT\t-1,%L1"
8219
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8220
+;(define_insn "mulsidi3"
8221
+;      [(set (match_operand:DI 0 "register_operand" "=r")
8222
+;              (mult:SI (match_operand:SI 1 "register_operand" "%r")
8223
+;                      (match_operand:SI 2 "register_operand" "r")))
8224
+;      (clobber (match_scratch:SI 3 "=r"))]
8225
+;      ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
8226
+;      ""
8227
+;      "MOV    %1,%L0
8228
+;      MPYS    %2,%L0                  ; L0 = R2 * R1
8229
+;      MOV     %1,%3                   ; R3 = R1
8230
+;      ROL     16,%3                   ; R3 = (R1 <<< 16)
8231
+;      MPYS    %2,%3                   ; R3 = (R1 <<< 16) * R2
8232
+;      ROL     16,%3                   ; R3 = upper bits of (R1<<<16)*R2
8233
+;      AND     0x0ffff,%3
8234
+;      ADD     %3,%L0                  ; L0 = L0 + R3 = L0  + (R1>>16)*R2
8235
+;      MOV     %2,%3
8236
+;      ROL     16,%3
8237
+;      MPYS    %1,%3
8238
+;      ROL     16,%3
8239
+;      AND     0x0ffff,%3
8240
+;      ADD     %3,%0"
8241
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8242
+
8243 102 dgisselq
+;
8244
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
8245
+;      mult:di, div:di, divu:di
8246
+;
8247
+;
8248
+;
8249
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8250
+;;
8251
+;; Conditional arithmetic instructions
8252
+;;
8253
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8254
+;
8255
+;
8256
+;
8257
+;
8258
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3
8259 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 2 "register_operand" "r")
8260
+               (match_operand:ZI 3 "zip_opb_operand_p" "rO")))
8261 102 dgisselq
+       (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
8262
+                       (match_operator 1 "ordered_comparison_operator"
8263 122 dgisselq
+                                       [(reg:CC CC_REG) (const_int 0)])
8264 102 dgisselq
+                       (const_int 1) (const_int 0)))]
8265
+       ""
8266
+       )
8267
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
8268
+       [(set (match_operand:SI 0 "register_operand" "=r")
8269
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
8270 122 dgisselq
+                       [(match_operand:DI 2 "register_operand" "r")
8271
+                               (match_operand:DI 3 "register_operand" "r")])
8272
+                       (const_int 1) (const_int 0)))
8273
+       (clobber (reg:CC CC_REG))]
8274 102 dgisselq
+       ""
8275
+       {
8276
+               switch(GET_CODE(operands[1])) {
8277
+               case EQ:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
8278
+               case NE:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
8279
+               case LTU:       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
8280
+               case LEU:       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
8281
+               case GTU:       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
8282
+               case GEU:       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
8283
+               default:
8284
+                       gcc_unreachable();
8285
+               }
8286
+       }
8287
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8288
+;
8289
+;
8290
+;
8291
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8292
+;;
8293
+;; Comparison instructions, both compare and test
8294
+;;
8295
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8296
+;
8297
+;
8298
+;
8299
+;; This will only work so well, since the direction of the compare is
8300
+;; important in unsigned compares.
8301
+;;
8302 122 dgisselq
+(define_expand "cmp<mode>"
8303
+       [(set (reg:CC CC_REG) (compare:CC
8304
+               (match_operand:ZI 0 "register_operand" "r")
8305
+               (match_operand:ZI 1 "nonmemory_operand" "")))]
8306 102 dgisselq
+       ""
8307 122 dgisselq
+       {
8308
+               if (!zip_opb_operand_p(operands[1],SImode)) {
8309
+                       if (can_create_pseudo_p()) {
8310
+                               //; fprintf(stderr, "Generating pseudo register for compare\n");
8311
+                               rtx tmp = gen_reg_rtx(SImode);
8312
+                               emit_insn(gen_movsi(tmp,operands[1]));
8313
+                               operands[1] = tmp;
8314
+                       } else FAIL;
8315
+               }
8316
+       })
8317
+(define_insn "cmp<mode>_reg"
8318
+       [(set (reg:CC CC_REG) (compare:CC
8319
+               (match_operand:ZI 0 "register_operand" "r")
8320
+               (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")))]
8321
+       ""
8322 102 dgisselq
+       "CMP\t%1,%0"
8323
+       [(set_attr "ccresult" "set")])
8324
+(define_insn "cmp<mode>_off"
8325 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
8326
+               (match_operand:ZI 0 "register_operand" "r")
8327 117 dgisselq
+               (plus (match_operand:ZI 1 "register_operand" "r")
8328 122 dgisselq
+                       (match_operand 2 "zip_opb_immv_p" "N"))))]
8329 102 dgisselq
+       ""
8330
+       "CMP\t%2+%1,%0"
8331
+       [(set_attr "ccresult" "set")])
8332
+(define_insn "test<mode>"
8333 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_operand:ZI 0 "register_operand" "r")
8334
+                               (match_operand:ZI 1 "zip_opb_single_operand_p" "rO"))
8335 102 dgisselq
+                       (const_int 0)))]
8336
+       ""
8337
+       "TEST   %1,%0"
8338
+       [(set_attr "ccresult" "set")])
8339
+(define_insn "test<mode>_off"
8340 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
8341
+               (and:ZI (match_operand:ZI 0 "register_operand" "r")
8342
+                       (plus:ZI
8343
+                               (match_operand:ZI 1 "register_operand" "r")
8344
+                               (match_operand:ZI 2 "zip_opb_immv_p" "N")))
8345
+               (const_int 0)))]
8346 102 dgisselq
+       ""
8347
+       "TEST   %2+%1,%0"
8348
+       [(set_attr "ccresult" "set")])
8349
+(define_insn "nop"
8350
+       [(const_int 0)]
8351
+       ""
8352
+       "NOOP"
8353
+       [(set_attr "ccresult" "unchanged")])
8354
+;
8355
+;
8356
+;
8357
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8358
+;;
8359
+;; Conditional execution predicates
8360
+;;
8361
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8362
+;
8363
+; Sadly, these aren't complete like they should be.  Although these are all of
8364
+; the conditional execution prefixes that the Zip CPU supports, GCC looks for
8365
+; other conditions then these.  That is, (cond_exec ...) is not as well
8366
+; recognized as (if_then_else ...).  So we have to duplicate things to support
8367
+; both methods.
8368
+;
8369
+(define_cond_exec
8370 122 dgisselq
+       [(ne (reg:CC CC_REG) (const_int 0))]
8371 102 dgisselq
+       ""
8372
+       "(NZ)"
8373
+       [(set_attr "conditional" "yes")])
8374
+(define_cond_exec
8375 122 dgisselq
+       [(lt (reg:CC CC_REG) (const_int 0))]
8376 102 dgisselq
+       ""
8377
+       "(LT)"
8378
+       [(set_attr "conditional" "yes")])
8379
+(define_cond_exec
8380 122 dgisselq
+       [(eq (reg:CC CC_REG) (const_int 0))]
8381 102 dgisselq
+       ""
8382
+       "(Z)"
8383
+       [(set_attr "conditional" "yes")])
8384
+(define_cond_exec
8385 122 dgisselq
+       [(gt (reg:CC CC_REG) (const_int 0))]
8386 102 dgisselq
+       ""
8387
+       "(GT)"
8388
+       [(set_attr "conditional" "yes")])
8389
+(define_cond_exec
8390 122 dgisselq
+       [(ge (reg:CC CC_REG) (const_int 0))]
8391 102 dgisselq
+       ""
8392
+       "(GE)"
8393
+       [(set_attr "conditional" "yes")])
8394
+(define_cond_exec
8395 122 dgisselq
+       [(ltu (reg:CC CC_REG) (const_int 0))]
8396 102 dgisselq
+       ""
8397
+       "(C)"
8398
+       [(set_attr "conditional" "yes")])
8399
+;
8400
+;
8401
+;
8402
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8403
+;;
8404
+;; Conditional move instructions, since these won't accept conditional
8405
+;;     execution RTL
8406
+;;
8407
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8408
+;
8409
+; // Look for #define HAVE_conditional_move to understand how these might be
8410
+; // used.
8411
+;
8412
+(define_insn "set_zero_or_one<mode>"
8413
+       [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
8414
+                       (match_operator 1 "ordered_comparison_operator"
8415 122 dgisselq
+                                       [(reg:CC CC_REG) (const_int 0)])
8416 102 dgisselq
+                       (const_int 1) (const_int 0)))]
8417
+       ""
8418
+       { return (zip_set_zero_or_one(operands[1], operands[0]));
8419
+       }
8420
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8421 127 dgisselq
+(define_expand "mov<mode>cc"
8422 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8423 127 dgisselq
+               (if_then_else:ZI (match_operand 1 "comparison_operator")
8424 102 dgisselq
+                       (match_operand:ZI 2 "general_operand" "rio")
8425
+                       (match_operand:ZI 3 "nonmemory_operand" "rio")))]
8426
+       ""
8427
+       {
8428 127 dgisselq
+       zip_expand_movsicc(operands[0], operands[1], operands[2], operands[3]);
8429
+       DONE;
8430
+       })
8431
+(define_insn_and_split "movsicc_bare"
8432
+       [(set (match_operand:SI 0 "register_operand" "=r")
8433
+               (if_then_else (match_operator 1 "ordered_comparison_operator"
8434
+                               [(reg:CC CC_REG) (const_int 0)])
8435
+                       (match_operand:SI 2 "general_operand" "rio")
8436
+                       (match_operand:SI 3 "register_operand" "0")))]
8437
+       "(zip_supported_condition(GET_CODE(operands[1])))"
8438
+       "#"
8439
+       "(reload_completed)"
8440
+       [(cond_exec (match_operator 1 "ordered_comparison_operator"
8441
+                               [(reg:CC CC_REG) (const_int 0)])
8442
+                       (set (match_dup 0) (match_dup 2)))]
8443
+       "" [(set_attr "predicable" "no")])
8444 102 dgisselq
+(define_insn "add<mode>cc"
8445
+       [(set (match_operand:ZI 0 "register_operand" "=r,r")
8446
+               (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
8447 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
8448 102 dgisselq
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
8449
+                               (match_operand:ZI 3 "nonmemory_operand" "rO,M"))
8450
+                       (match_dup 0)))]
8451
+       ""
8452
+       {
8453
+       return zip_addsicc(operands[0], operands[1], operands[2], operands[3]);
8454
+       }
8455
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8456
+;
8457
+;
8458
+;
8459
+; While an interesting approach, the following suffers from problems when the
8460
+; move amount is constant.  At anything less than four, moves should not require
8461
+; the movmemSI instruction.  At anything greater, if constant, the initial tests
8462
+; are not required and should result in a hardcoded result.  Practically,
8463
+; though, this should really be a define_expand instruction, calling on the
8464 127 dgisselq
+; RTX's of all the respective subinstructions found below.  Or, perhaps, it is
8465
+; better as a subroutine?
8466 102 dgisselq
+;
8467
+;(define_insn "movmemSI"
8468
+;      [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst
8469
+;                      (mem:BLK (match_operand 1 "register_operand" "+r")));Src
8470
+;              (use (match_operand:SI 2 "register_operand" "+r"))]); Length
8471
+;              (match_operand 3 "" "")                 ;Alignment
8472
+;              (clobber (match_scratch:SI 4 "=r"))
8473
+;              (clobber (match_scratch:SI 5 "=r"))
8474
+;              (clobber (match_scratch:SI 6 "=r"))
8475
+;              (clobber (match_scratch:SI 7 "=r"))]
8476
+;      ""
8477
+;      "TEST\t1,%2
8478
+;      LOD.NZ\t%1,%4
8479
+;      STO.NZ\t%4,%0
8480
+;      ADD.NZ\t1,%0
8481
+;      ADD.NZ\t1,%1
8482
+;      TEST\t2,%2
8483
+;      LOD.NZ\t%1,%4
8484
+;      LOD.NZ\t1(%1),%5
8485
+;      STO.NZ\t%4,(%0)
8486
+;      STO.NZ\t%4,1(%0)
8487
+;      ADD.NZ\t2,%0
8488
+;      ADD.NZ\t2,%1
8489
+;      AND\t-4,%2
8490
+;      BZ\t.Lskp%=\n.Ltop%=:
8491
+;      LOD\t(%1),%4
8492
+;      LOD\t1(%1),%5
8493
+;      LOD\t2(%1,%6
8494
+;      LOD\t3(%1),%7
8495
+;      STO\t%4,(%1)
8496
+;      STO\t%5,1(%1)
8497
+;      STO\t%6,2(%1)
8498
+;      STO\t%7,3(%1)
8499
+;      SUB\t4,%2
8500
+;      BZ\t%.Lskp%=
8501
+;      BRA\t.Ltop%=\n.Lskp%=:"
8502
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8503
+;(define_insn "setmemsi"
8504
+;      [(parallel
8505
+;              [(set (mem:BLK
8506
+;                      (match_operand 0 "register_operand" "+r")); Destination
8507
+;                      (match_operand:SI 2 "register_operand" "r")) ; Source
8508
+;              (use (match_operand:SI 1 "register_operand" "+r"))])  ; Length
8509
+;              (match_operand 3 "" "")]
8510
+;      ""
8511
+;      "TEST\t1,%1
8512
+;      STO.NZ\t%2,(%0)
8513
+;      ADD.NZ\t1,%0
8514
+;      TEST\t2,%1
8515
+;      STO.NZ\t%2,(%0)
8516
+;      STO.NZ\t%2,1(%0)
8517
+;      ADD.NZ\t2,%0
8518
+;      AND\t-4,%1
8519
+;      BZ\t.Lskp%=\n.Ltop%=:\n
8520
+;      STO\t%2,(%0)
8521
+;      STO\t%2,1(%0)
8522
+;      STO\t%2,2(%0)
8523
+;      STO\t%2,3(%0)
8524
+;      SUB\t%4,%0
8525
+;      BZ\t.Lskp%=
8526
+;      BRA\t.Ltop%=\n.Lskp%=:"
8527
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8528
+;;
8529
+;
8530
+;
8531
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8532
+;;
8533
+;; Control flow instructions
8534
+;;
8535
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8536
+;
8537
+;
8538
+;
8539
+(define_expand "jump"
8540
+       [(set (pc)
8541
+               (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro"
8542 127 dgisselq
+(define_insn "jump_const"
8543
+       [(set (pc)
8544 102 dgisselq
+               (match_operand:SI 0 "zip_const_address_operand_p" ""))]
8545
+       ""
8546
+       "BRA    %0"
8547
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8548
+(define_insn "jump_label"      ; Must be modeless, VOIDmode, not SI or any othr
8549
+       [(set (pc)      ; Otherwise it won't accept jumps to labels
8550
+               (label_ref (match_operand 0 "" "")))]
8551
+       ""
8552
+       "BRA    %0"
8553
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8554
+;
8555
+; This is really the same thing as an indirect jump ... the big difference
8556
+; is that the zip_address_operand_p checks for an "N" type condition, not an
8557
+; "M" type condition ... a bug, but one that works for now.  (The assembler
8558
+; should be able to catch and except on it ...)
8559
+;
8560
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
8561
+(define_insn "jump_variable"
8562
+       [(set (pc)
8563
+               (match_operand:SI 0 "zip_address_operand_p" ""))]
8564
+       ""
8565
+       "JMP    %0"
8566
+       [(set_attr "ccresult" "unchanged")])
8567
+;
8568
+; Indirect jumps ... both to registers, and registers plus offsets
8569
+;
8570
+(define_insn "indirect_jump"
8571
+       [(set (pc)
8572
+               (match_operand:SI 0 "register_operand" "r"))]
8573
+       ""
8574
+       "JMP    %0"
8575
+       [(set_attr "ccresult" "unchanged")])
8576
+(define_insn "indirect_jump_mem"
8577
+       [(set (pc) (match_operand:SI 0 "zip_memory_operand_p" "o"))]
8578
+       ""
8579
+       "LOD    %0,PC"
8580
+       [(set_attr "ccresult" "unchanged")])
8581
+(define_insn "indirect_jump_off"
8582
+       [(set (pc)
8583
+               (plus:SI (match_operand:SI 0 "register_operand" "r")
8584
+                       (match_operand:SI 1 "const_int_operand" "M")))]
8585
+       ""
8586
+       "JMP    %1(%0)"
8587
+       [(set_attr "ccresult" "unchanged")])
8588
+;;
8589
+; cbranchsi4
8590
+;;     Op 0 = the comparison operator (le,lt,eq,ne,gt,ge,and usgn ltu,geu,etc.)
8591
+;;     Op 1&2 the operands of the compare instruction
8592
+;;     Op 3 is the jump label
8593
+;;
8594
+;;
8595
+;; #warning Need to adjust this so that the "LT" code doesnt get generated ...
8596
+;;
8597
+(define_expand "cbranch<mode>4"
8598 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
8599
+               (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
8600 102 dgisselq
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
8601 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
8602 102 dgisselq
+                       (label_ref (match_operand 3 "" ""))
8603
+                       (pc)))]
8604
+       ""
8605
+       {
8606 125 dgisselq
+               if (true) {
8607 117 dgisselq
+               extern void zip_debug_rtx_pfx(const char *, const_rtx);
8608 102 dgisselq
+               //; Two branches give us no end of difficulty when implementing.
8609
+               //; Let's check for these two branch codes, and swap the
8610
+               //; comparison to simplify them.
8611 122 dgisselq
+               //; fprintf(stderr, "CBRANCH\n");
8612
+               //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
8613
+               //; zip_debug_rtx_pfx("- A  : ", operands[1]);
8614
+               //; zip_debug_rtx_pfx("- B  : ", operands[2]);
8615
+               //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
8616 117 dgisselq
+               //; Can we do better if we reverse some compares?
8617 102 dgisselq
+               if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) {
8618 122 dgisselq
+                       //; fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n");
8619
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
8620 102 dgisselq
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
8621
+                       DONE;
8622
+               } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
8623 122 dgisselq
+                       //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
8624
+                       emit_insn(gen_cmpsi_off(operands[2], operands[1],
8625
+                                       GEN_INT(1)));
8626
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
8627 102 dgisselq
+                       DONE;
8628 117 dgisselq
+               } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
8629 122 dgisselq
+                       //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
8630 117 dgisselq
+                       //; Swap operands, turn into a GTE compare
8631 122 dgisselq
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
8632 117 dgisselq
+                       emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
8633
+                       DONE;
8634 102 dgisselq
+               } // ; Otherwise ... just handle the branch normally
8635
+
8636
+               //; Except ... we can do better for some instructions, such as
8637
+               //; LE.  While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
8638
+               //; would be difficult to explain to users why MIN_INT didn't
8639
+               //; compare properly.  Hence we only adjust constant integers.
8640
+               //;
8641 122 dgisselq
+               if (GET_CODE(operands[0])==LE) {
8642
+                       if ((CONST_INT_P(operands[2]))
8643 117 dgisselq
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
8644 122 dgisselq
+                               //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
8645
+                               emit_insn(gen_cmpsi(operands[1],
8646
+                                               GEN_INT(INTVAL(operands[2])+1)));
8647
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
8648
+                               DONE;
8649
+                       //; Now for the controversial ones--where we add one
8650
+                       //; when it may or may not be permissable.  For now, we
8651
+                       //; just do it anyway and postpone the philosophical
8652
+                       //; discussion for later.
8653
+                       } else if (REG_P(operands[2])) {
8654
+                               emit_insn(gen_cmpsi_off(operands[1],
8655
+                                               operands[2],GEN_INT(1)));
8656
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
8657
+                               DONE;
8658
+                       } else if ((GET_CODE(operands[2])==PLUS)
8659
+                               &&(REG_P(XEXP(operands[2],0)))
8660
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
8661
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
8662
+                               emit_insn(gen_cmpsi_off(operands[1],
8663
+                                               XEXP(operands[2],0),
8664
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
8665
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
8666
+                               DONE;
8667
+                       }
8668
+               } else if (GET_CODE(operands[0])==LEU) {
8669
+                       if ((CONST_INT_P(operands[2]))
8670 102 dgisselq
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
8671 122 dgisselq
+                               //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
8672
+                               emit_insn(gen_cmpsi(operands[1],
8673
+                                               GEN_INT(INTVAL(operands[2])+1)));
8674
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
8675
+                               DONE;
8676
+                       //; Now for the controversial ones--this time having
8677
+                       //; to do with unsigned compares.
8678
+                       } else if (REG_P(operands[2])) {
8679
+                               emit_insn(gen_cmpsi_off(operands[1],
8680
+                                                       operands[2],GEN_INT(1)));
8681
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
8682
+                               DONE;
8683
+                       } else if ((GET_CODE(operands[2])==PLUS)
8684
+                               &&(REG_P(XEXP(operands[2],0)))
8685
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
8686
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
8687
+                               emit_insn(gen_cmpsi_off(operands[1],
8688
+                                       XEXP(operands[2],0),
8689
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
8690
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
8691
+                               DONE;
8692
+                       }
8693 124 dgisselq
+               }}
8694 102 dgisselq
+       })
8695
+(define_insn "cbranch_jmp_eq"
8696 122 dgisselq
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
8697 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8698
+                (pc)))]
8699
+       ""
8700
+       "BZ\t%0"
8701
+       [(set_attr "predicable" "no")
8702
+               (set_attr "conditional" "yes")
8703
+               (set_attr "ccresult" "unchanged")])
8704
+(define_insn "cbranch_jmp_neq"
8705 122 dgisselq
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
8706 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8707
+                (pc)))]
8708
+       ""
8709
+       "BNZ\t%0"
8710
+       [(set_attr "predicable" "no")
8711
+               (set_attr "conditional" "yes")
8712
+               (set_attr "ccresult" "unchanged")])
8713
+(define_insn "cbranch_jmp_lt"
8714 122 dgisselq
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
8715 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8716
+                (pc)))]
8717
+       ""
8718
+       "BLT\t%0"
8719
+       [(set_attr "predicable" "no")
8720
+               (set_attr "conditional" "yes")
8721
+               (set_attr "ccresult" "unchanged")])
8722
+(define_insn "cbranch_jmp_le"
8723 122 dgisselq
+       [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
8724 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8725
+                (pc)))]
8726
+       ""
8727
+       "BLT\t%0
8728
+       BZ\t%0"
8729
+       [(set_attr "predicable" "no")
8730
+               (set_attr "conditional" "yes")
8731
+               (set_attr "ccresult" "unchanged")])
8732
+(define_insn "cbranch_jmp_gt"
8733 122 dgisselq
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
8734 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8735
+                (pc)))]
8736
+       ""
8737
+       "BGT\t%0"
8738
+       [(set_attr "predicable" "no")
8739
+               (set_attr "conditional" "yes")
8740
+               (set_attr "ccresult" "unchanged")])
8741
+(define_insn "cbranch_jmp_ge"
8742 122 dgisselq
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
8743 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8744
+                (pc)))]
8745
+       ""
8746
+       "BGE\t%0"
8747
+       [(set_attr "predicable" "no")
8748
+               (set_attr "conditional" "yes")
8749
+               (set_attr "ccresult" "unchanged")])
8750
+(define_insn "cbranch_jmp_ltu"
8751 122 dgisselq
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
8752 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8753
+                (pc)))]
8754
+       ""
8755
+       "BC\t%0"
8756
+       [(set_attr "predicable" "no")
8757
+               (set_attr "conditional" "yes")
8758
+               (set_attr "ccresult" "unchanged")])
8759
+(define_insn "cbranch_jmp_gtu"
8760 122 dgisselq
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
8761 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8762 122 dgisselq
+                (pc)))
8763
+       ;(clobber (reg:CC CC_REG))
8764
+       ]
8765 102 dgisselq
+       ""      ; Flip the condition, and then we can jump
8766 127 dgisselq
+       "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
8767 102 dgisselq
+       [(set_attr "predicable" "no")
8768
+               (set_attr "conditional" "yes")
8769
+               (set_attr "ccresult" "unknown")])
8770
+(define_insn "cbranch_jmp_leu"
8771 122 dgisselq
+       [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
8772 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8773
+                (pc)))]
8774
+       ""      ; Need to check for both LTU (i.e. C) and Z
8775
+       "BC\t%0
8776
+       BZ\t%0"
8777
+       [(set_attr "predicable" "no")
8778
+               (set_attr "conditional" "yes")
8779
+               (set_attr "ccresult" "unchanged")])
8780
+(define_insn "cbranch_jmp_geu"
8781 122 dgisselq
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
8782 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
8783 122 dgisselq
+                (pc)))
8784
+       ;(clobber (reg:CC CC_REG))
8785
+       ]
8786 127 dgisselq
+       ""
8787
+       "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
8788 102 dgisselq
+       [(set_attr "predicable" "no")
8789
+               (set_attr "conditional" "yes")
8790
+               (set_attr "ccresult" "unknown")])
8791
+(define_insn "cbranchdi4"
8792
+       [(set (pc) (if_then_else
8793
+               (match_operator 0 "ordered_comparison_operator"
8794
+                       [(match_operand:DI 1 "register_operand" "r")
8795 122 dgisselq
+                               (match_operand:DI 2 "register_operand" "r")])
8796 102 dgisselq
+                       (label_ref (match_operand 3 "" ""))
8797
+                       (pc)))
8798 122 dgisselq
+       (clobber (reg:CC CC_REG))]
8799 102 dgisselq
+       ""
8800
+       {
8801
+               switch(GET_CODE(operands[0])) {
8802
+               case EQ:
8803
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
8804
+               case NE:
8805
+                       return "CMP\t%H2,%H1\n\tCMP.NZ\t%L2,%L1\n\tBNZ\t%3";
8806
+               case LE:
8807
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
8808
+               case GT:
8809
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
8810
+               case LT:
8811
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n.Ldi%=:";
8812
+               case GE:
8813
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\nBZ\t%3\n.Ldi%=:";
8814
+               case LTU:
8815
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n";
8816
+               case LEU:
8817
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
8818
+               case GTU:
8819
+                       return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\n";
8820
+               case GEU:
8821
+                       return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\nBZ\t%3";
8822
+               default:
8823
+                       gcc_unreachable();
8824
+               }
8825
+       }
8826
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8827
+;
8828
+;
8829
+;
8830
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8831
+;;
8832
+;; Subroutine call
8833
+;;
8834
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8835
+;
8836
+;
8837
+; There are two types of calls: "call" and "call_value".
8838
+;
8839
+; Each of these types of calls are then expanded into one of:
8840
+;
8841
+;      _const          - A call to a constant address, such as a symbol
8842
+;                      reference or a fixed location
8843
+;
8844
+;      _label          - This should be the same as _const, except that for
8845
+;                      some reason the RTL and matching rules are separate.
8846
+;                      Hence we have a separate rule for this.
8847
+;
8848
+;      _mem            - The memory address we wish to jump to is stored in
8849
+;                      memory somewhere, and we have only a pointer.  In this
8850
+;                      case, we load that pointer straight to the PC and go.
8851
+;
8852
+;      _var            - The address to jump to is given as an offset to a
8853
+;                      register, such as X+R3.  This is an indirect jump.
8854
+;                      Although we support it, it does require different RTL
8855
+;                      code.
8856
+;
8857
+(define_expand "call"
8858
+       [(call (match_operand 0 "" "")
8859
+               (match_operand 1 "" ""))]
8860
+       ""
8861
+       {
8862
+               if (MEM_P(operands[0])) {
8863
+                       // This should always be the case
8864
+                       rtx addr = XEXP(operands[0],0);
8865
+                       if (zip_const_address_operand_p(addr, SImode)) {
8866 122 dgisselq
+                               //; fprintf(stderr, "Generating gen_void_call_const()\n");
8867 102 dgisselq
+                               emit_call_insn(gen_void_call_const(addr,
8868
+                                               operands[1]));
8869
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
8870
+                                                       XEXP(addr,0)))) {
8871
+                               emit_call_insn(gen_void_call_mem(XEXP(addr,0),
8872
+                                                                operands[1]));
8873
+                       } else {
8874
+                               emit_call_insn(gen_void_call_var(addr,
8875
+                                                                operands[1]));
8876
+                       }
8877
+                       DONE;
8878
+               }
8879
+       })
8880
+;
8881
+;
8882
+;
8883
+; How do we want to do this better?
8884
+;      Replace the RTL w/
8885
+;              return_label= gen_label_rtx();
8886
+;              emit_movsi(gen_rtx_REG(zip_R0),plus_constant(
8887
+;                      gen_rtx_REG(zip_PC),return_label));
8888
+;              emit_jump(label_rtx(
8889
+;
8890
+;              emit_label(return_label);
8891
+;
8892
+; The problem is: we can't!  GCC distinguishes between jumps and calls when
8893
+; optimizing, and it doesn't see the need to keep the label around.  Thus, the
8894
+; label gets removed and the call gets lost.  Hence we do it this way (below).
8895
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
8896
+; recognize as such, but for now we'll use .Lcall# as our label.
8897
+;
8898
+(define_insn "void_call_const"
8899 122 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
8900 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
8901 122 dgisselq
+               (clobber (reg:SI RTN_REG))
8902
+               (clobber (reg:CC CC_REG))]
8903 102 dgisselq
+       ""
8904
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
8905
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8906
+(define_insn "void_call_mem"
8907 122 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
8908 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
8909 122 dgisselq
+               (clobber (reg:SI RTN_REG))
8910
+               (clobber (reg:CC CC_REG))]
8911 102 dgisselq
+       ""
8912
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
8913
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8914
+;
8915
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
8916
+(define_insn "void_call_var"
8917 122 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
8918 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
8919 122 dgisselq
+               (clobber (reg:SI RTN_REG))
8920
+               (clobber (reg:CC CC_REG))]
8921 102 dgisselq
+       ""
8922
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
8923
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8924
+(define_expand "call_value"
8925 122 dgisselq
+       [(parallel [(set (reg:SI RTNV_REG)
8926 102 dgisselq
+               (call (match_operand:SI 1 "" "")
8927 111 dgisselq
+                       (match_operand 2 "const_int_operand" "n")))
8928 122 dgisselq
+       (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))
8929
+       (clobber (reg:CC CC_REG))])]
8930 102 dgisselq
+       ""
8931
+       {
8932 122 dgisselq
+               //; extern void zip_debug_rtx(const_rtx);
8933
+               //; fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
8934
+               //; zip_debug_rtx(operands[1]);
8935 102 dgisselq
+               if (MEM_P(operands[1])) {
8936 122 dgisselq
+                       //; fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n");
8937
+                       //; zip_debug_rtx(operands[1]);
8938
+                       //; This should always be the case
8939 102 dgisselq
+                       rtx addr = XEXP(operands[1],0);
8940
+                       if (zip_const_address_operand_p(addr, SImode)) {
8941 122 dgisselq
+                               //; fprintf(stderr, "Generating gen_reg_call_const()\n");
8942 102 dgisselq
+                               emit_call_insn(gen_reg_call_const(addr, operands[2]));
8943
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
8944 122 dgisselq
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
8945 102 dgisselq
+                               emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2]));
8946
+                       } else {
8947 122 dgisselq
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
8948 102 dgisselq
+                               emit_call_insn(gen_reg_call_var(addr, operands[2]));
8949
+                       }
8950
+                       DONE;
8951
+               }
8952
+       })
8953
+(define_insn "reg_call_const"
8954 122 dgisselq
+       [(set (reg:SI RTNV_REG)
8955 102 dgisselq
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
8956 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n")))
8957 122 dgisselq
+               (clobber (reg:SI RTN_REG))
8958
+               (clobber (reg:CC CC_REG))]
8959 102 dgisselq
+       ""
8960
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
8961
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8962
+(define_insn "reg_call_mem"
8963
+       [(set (reg:SI RTNV_REG)
8964 111 dgisselq
+               (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
8965
+                       (match_operand 1 "const_int_operand" "n")))
8966 122 dgisselq
+               (clobber (reg:SI RTN_REG))
8967
+               (clobber (reg:CC CC_REG))]
8968 102 dgisselq
+       ""
8969 111 dgisselq
+       "MOV    .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
8970 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8971 111 dgisselq
+;
8972 102 dgisselq
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
8973
+(define_insn "reg_call_var"
8974 122 dgisselq
+       [(set (reg:SI RTNV_REG)
8975 102 dgisselq
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
8976 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n")))
8977 122 dgisselq
+               (clobber (reg:SI RTN_REG))
8978
+               (clobber (reg:CC CC_REG))]
8979 102 dgisselq
+       ""
8980 111 dgisselq
+       "MOV    .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
8981 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8982
+;
8983
+;
8984
+;
8985
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8986
+;;
8987
+;; Frame manipulation RTX
8988
+;;
8989
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8990
+;
8991
+;
8992
+;
8993
+(define_expand "prologue"
8994
+       [(const_int 0)]
8995
+       ""
8996
+       "{ zip_expand_prologue(); DONE; }")
8997
+(define_expand "epilogue"
8998
+       [(return)]
8999
+       ""
9000
+       "{ zip_expand_epilogue(); DONE; }")
9001
+(define_expand "return" ; In order to use the function predicate, this *must*
9002
+       [(return)]      ; be a define_expand
9003
+       "zip_use_return_insn()")
9004
+       ; "JMP  R0"
9005
+       ; [(set_attr "ccresult" "unchanged")])
9006
+(define_insn "*return" ; A "*" -- means it cannot be called from C
9007
+       [(return)]
9008
+       ""
9009
+       "JMP    R0"
9010
+       [(set_attr "ccresult" "unchanged")])
9011
+(define_insn "simple_return"   ; A "*" -- means it cannot be called from C
9012
+       [(simple_return)]
9013
+       ""
9014
+       "JMP    R0"
9015
+       [(set_attr "ccresult" "unchanged")])
9016
+;
9017
+;
9018
+;
9019
+;;;;;;;;;;;;;;;;;;;;;;;;;;
9020
+;;
9021
+;; Zip Builtin Functions
9022
+;;
9023
+;;;;;;;;;;;;;;;;;;;;;;;;;;
9024
+;
9025
+;
9026
+;
9027
+(define_insn "zip_rtu"
9028
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU)
9029 122 dgisselq
+       (clobber (reg:CC CC_REG))]
9030 102 dgisselq
+       "(!ZIP_USER)"
9031
+       "RTU"
9032
+       [(set_attr "ccresult" "unknown")])
9033
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out
9034
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT)
9035 122 dgisselq
+       (clobber (reg:CC CC_REG))]
9036 102 dgisselq
+       "(!ZIP_USER)"
9037
+       "HALT"
9038
+       [(set_attr "ccresult" "unknown")])
9039
+(define_insn "zip_idle"
9040
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE)
9041 122 dgisselq
+       (clobber (reg:CC CC_REG))]
9042 102 dgisselq
+       ""
9043
+       "WAIT"
9044
+       [(set_attr "ccresult" "unknown")])
9045
+(define_insn "zip_syscall"
9046
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_SYSCALL)]
9047
+       ""
9048
+       "CLR\tCC"
9049
+       [(set_attr "ccresult" "unknown")])
9050
+;
9051
+;
9052
+; Operator "save_context"
9053
+;
9054 117 dgisselq
+;      Okay, so we're not really reading and writing operand 0, %0, however
9055
+;      if we don't list it as a "+r" register, the compiler may allocate it
9056
+;      among the other registers, thus we clobber it in the middle of the
9057
+;      operation before the task is complete.
9058 102 dgisselq
+;
9059
+(define_insn "zip_save_context"
9060 117 dgisselq
+       [(unspec_volatile
9061
+                       [ (match_operand:SI 0 "register_operand" "+r") ]
9062 102 dgisselq
+                       UNSPEC_SAVE_CONTEXT)
9063
+               (clobber (match_scratch:SI 1 "=r"))
9064
+               (clobber (match_scratch:SI 2 "=r"))
9065
+               (clobber (match_scratch:SI 3 "=r"))
9066 117 dgisselq
+               (clobber (match_scratch:SI 4 "=r"))]
9067 102 dgisselq
+       "(!ZIP_USER)"
9068
+       "MOV\tuR0,%1
9069
+       MOV\tuR1,%2
9070
+       MOV\tuR2,%3
9071
+       MOV\tuR3,%4
9072
+       STO\t%1,%0
9073
+       STO\t%2,1(%0)
9074
+       STO\t%3,2(%0)
9075
+       STO\t%4,3(%0)
9076
+       MOV\tuR4,%1
9077
+       MOV\tuR5,%2
9078
+       MOV\tuR6,%3
9079
+       MOV\tuR7,%4
9080
+       STO\t%1,4(%0)
9081
+       STO\t%2,5(%0)
9082
+       STO\t%3,6(%0)
9083
+       STO\t%4,7(%0)
9084
+       MOV\tuR8,%1
9085
+       MOV\tuR9,%2
9086
+       MOV\tuR10,%3
9087
+       MOV\tuR11,%4
9088
+       STO\t%1,8(%0)
9089
+       STO\t%2,9(%0)
9090
+       STO\t%3,10(%0)
9091
+       STO\t%4,11(%0)
9092
+       MOV\tuR12,%1
9093
+       MOV\tuSP,%2
9094
+       MOV\tuCC,%3
9095
+       MOV\tuPC,%4
9096
+       STO\t%1,12(%0)
9097
+       STO\t%2,13(%0)
9098
+       STO\t%3,14(%0)
9099
+       STO\t%4,15(%0)"
9100 122 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9101 117 dgisselq
+;
9102
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
9103
+; even though we don't really read (or change) its value throughout this
9104
+; operation.
9105
+;
9106 102 dgisselq
+(define_insn "zip_restore_context"
9107
+       [(unspec_volatile [
9108 117 dgisselq
+               (match_operand:SI 0 "register_operand" "+r")] UNSPEC_RESTORE_CONTEXT)
9109 102 dgisselq
+       (clobber (match_scratch:SI 1 "=r"))
9110
+       (clobber (match_scratch:SI 2 "=r"))
9111
+       (clobber (match_scratch:SI 3 "=r"))
9112 117 dgisselq
+       (clobber (match_scratch:SI 4 "=r"))]
9113 102 dgisselq
+       "(!ZIP_USER)"
9114
+       "LOD\t0(%0),%1
9115
+       LOD\t1(%0),%2
9116
+       LOD\t2(%0),%3
9117
+       LOD\t3(%0),%4
9118
+       MOV\t%1,uR0
9119
+       MOV\t%2,uR1
9120
+       MOV\t%3,uR2
9121
+       MOV\t%4,uR3
9122
+       LOD\t4(%0),%1
9123
+       LOD\t5(%0),%2
9124
+       LOD\t6(%0),%3
9125
+       LOD\t7(%0),%4
9126
+       MOV\t%1,uR4
9127
+       MOV\t%2,uR5
9128
+       MOV\t%3,uR6
9129
+       MOV\t%4,uR7
9130
+       LOD\t8(%0),%1
9131
+       LOD\t9(%0),%2
9132
+       LOD\t10(%0),%3
9133
+       LOD\t11(%0),%4
9134
+       MOV\t%1,uR8
9135
+       MOV\t%2,uR9
9136
+       MOV\t%3,uR10
9137
+       MOV\t%4,uR11
9138
+       LOD\t12(%0),%1
9139
+       LOD\t13(%0),%2
9140
+       LOD\t14(%0),%3
9141
+       LOD\t15(%0),%4
9142
+       MOV\t%1,uR12
9143
+       MOV\t%2,uSP
9144
+       MOV\t%3,uCC
9145
+       MOV\t%4,uPC"
9146 122 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9147 102 dgisselq
+(define_insn "zip_bitrev"
9148
+       [(set (match_operand:SI 0 "register_operand" "=r")
9149
+               (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV))
9150
+       ]
9151
+       ""
9152
+       "BREV\t%1,%0"
9153 122 dgisselq
+       [(set_attr "ccresult" "unchanged")])
9154 102 dgisselq
+(define_insn "zip_cc"
9155
+       [(set (match_operand:SI 0 "register_operand" "=r")
9156
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
9157
+       ""
9158
+       "MOV\tCC,%0"
9159
+       [(set_attr "ccresult" "unchanged")])
9160 117 dgisselq
+(define_insn "zip_ucc"
9161
+       [(set (match_operand:SI 0 "register_operand" "=r")
9162
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETUCC))]
9163
+       ""
9164
+       "MOV\tuCC,%0"
9165
+       [(set_attr "ccresult" "unchanged")])
9166 111 dgisselq
+(define_insn "zip_cc_sto"
9167
+       [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
9168 117 dgisselq
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
9169 111 dgisselq
+       ""
9170
+       "STO\tCC,(%0)"
9171
+       [(set_attr "ccresult" "unchanged")])
9172
+(define_insn "zip_cc_sto_off"
9173
+       [(set (mem:SI (plus:SI
9174
+                       (match_operand:SI 0 "register_operand" "r")
9175
+                       (match_operand:SI 1 "const_int_operand" "N")))
9176 117 dgisselq
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
9177 111 dgisselq
+       ""
9178
+       "STO\tCC,%1(%0)"
9179
+       [(set_attr "ccresult" "unchanged")])
9180 102 dgisselq
+(define_insn "ldilo"
9181
+       [(set (match_operand:SI 0 "register_operand" "=r")
9182
+               (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
9183
+       ""
9184
+       "LDILO  %1,%0"
9185
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
9186
+
9187
+;
9188
+;
9189
+;
9190
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9191
+;;
9192
+;; Floating point Op-codes
9193
+;;
9194
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9195
+;
9196
+;
9197
+;
9198
+(define_insn "addsf3"
9199
+       [(set (match_operand:SF 0 "register_operand" "=r")
9200
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
9201 122 dgisselq
+                       (match_operand:SF 2 "register_operand" "r")))
9202
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
9203 102 dgisselq
+       "(ZIP_FPU)"
9204
+       "FPADD  %2,%0"
9205
+       [(set_attr "ccresult" "unknown")])
9206
+(define_insn "subsf3"
9207
+       [(set (match_operand:SF 0 "register_operand" "=r")
9208
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
9209 122 dgisselq
+                       (match_operand:SF 2 "register_operand" "r")))
9210
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
9211 102 dgisselq
+       "(ZIP_FPU)"
9212
+       "FPSUB  %2,%0"
9213
+       [(set_attr "ccresult" "unknown")])
9214
+(define_insn "mulsf3"
9215
+       [(set (match_operand:SF 0 "register_operand" "=r")
9216
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
9217 122 dgisselq
+                       (match_operand:SF 2 "register_operand" "r")))
9218
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
9219 102 dgisselq
+       "(ZIP_FPU)"
9220
+       "FPMUL  %2,%0"
9221
+       [(set_attr "ccresult" "unknown")])
9222
+(define_insn "divsf3"
9223
+       [(set (match_operand:SF 0 "register_operand" "=r")
9224
+               (div:SF (match_operand:SF 1 "register_operand" "0")
9225 122 dgisselq
+                       (match_operand:SF 2 "register_operand" "r")))
9226
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
9227 102 dgisselq
+       "(ZIP_FPU)"
9228
+       "FPDIV  %2,%0"
9229
+       [(set_attr "ccresult" "unknown")])
9230 111 dgisselq
+(define_expand "negsf2"
9231
+       [(set (match_operand:SF 0 "register_operand" "=r")
9232
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
9233
+       ]
9234
+       ""
9235
+       {
9236
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
9237
+               if (can_create_pseudo_p()) {
9238
+                       rtx tmp = gen_reg_rtx(SImode);
9239
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
9240 122 dgisselq
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
9241 111 dgisselq
+                       DONE;
9242
+               } else {
9243
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
9244 122 dgisselq
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
9245
+                               gen_int_mode(1,SImode)));
9246 111 dgisselq
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
9247
+                       DONE;
9248
+               }
9249
+       })
9250
+(define_expand "abssf2"
9251 122 dgisselq
+       [(set (match_operand:SF 0 "register_operand" "=r")
9252
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
9253 111 dgisselq
+       ]
9254
+       ""
9255
+       {
9256
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
9257
+               if (can_create_pseudo_p()) {
9258
+                       rtx tmp = gen_reg_rtx(SImode);
9259
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
9260 122 dgisselq
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
9261 111 dgisselq
+                       DONE;
9262
+               } else {
9263
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
9264 122 dgisselq
+                       emit_insn(gen_andsi3(operands[0], operands[0],
9265
+                               gen_int_mode(-2,SImode)));
9266 111 dgisselq
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
9267
+                       DONE;
9268
+               }
9269
+       })
9270 102 dgisselq
+;
9271
+;
9272
+;
9273
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9274
+;;
9275
+;; Trap Instruction
9276
+;;
9277
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9278
+;
9279
+;
9280
+; The ZipCPU doesn't really have a "trap" instruction per se.  The goal is that
9281
+; *nothing* should ever trap, and so we should never get here.  However, the
9282
+; compiler seems to want a trap instruction for some reason.  (It keeps us
9283
+; from calling the abort() function, if we don't define these ...)  So let's
9284
+; just grab onto the break instruction and declare it to be a trap instruction
9285
+; for our purposes.  Alternatively, we might've used a syscall, but ... this
9286
+; will work for both user and system instructions.
9287
+;
9288
+(define_insn "trap"
9289
+       [(trap_if (const_int 1) (const_int 0))]
9290
+       ""
9291
+       "BREAK"
9292
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
9293
+;
9294
+(define_expand "ctrap<mode>4"
9295 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9296
+               (match_operand:ZI 1 "register_operand" "r")
9297
+               (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
9298 102 dgisselq
+       (trap_if (match_operator 0 "ordered_comparison_operator"
9299 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
9300 102 dgisselq
+                       (match_operand 3 "const_int_operand" "O"))]
9301
+       ""
9302
+       )
9303
+(define_insn "trapif"
9304
+       [(trap_if (match_operator 0 "ordered_comparison_operator"
9305 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
9306 102 dgisselq
+                       (match_operand 1 "const_int_operand" "O"))]
9307
+       ""
9308
+       "BREAK\t%1"
9309
+       [(set_attr "predicable" "no")])
9310
+;
9311
+;
9312
+;
9313
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9314
+;;
9315
+;; Unimplemented (or not yet implemented) RTL Codes
9316
+;;
9317
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9318
+;
9319
+;
9320
+;
9321
+;(define_insn "sync_compare_and_swapsi"
9322
+;      [(set ...
9323
+;              )]
9324
+;      "(ZIP_ATMOC)"
9325
+;      LOCK            (alu)           // Hmmm ... need to modify if I will
9326
+;      LOD     %1,%0   OP-VALID        // operate on the value before the store
9327
+;      CMP     %0,%2   DCD-valid
9328
+;      STO.Z   %2,%1   PF-valid
9329
+;
9330
+;(define_insn "sync_lock_test_and_setsi"
9331
+;      LOCK
9332
+;      LOD     %1,%0
9333
+;      STO     %0,%1
9334
+;
9335
+;(define_insn "sync_lock_releasesi"
9336
+;      STO     %1,%0
9337
+;
9338
+;
9339
+;(define_insn "negvsi3"
9340
+;      "MOV    %1,%0
9341
+;      XOR     -1,%0
9342
+;      ADD     1,%0
9343
+;      BV      %2"
9344
+;      "")
9345 124 dgisselq
+;
9346
+; Match:
9347
+;      CMP     R1,R0
9348
+;      BGTU    lbl
9349
+; Transform to:
9350
+;      CMP     R0,R1
9351
+;      BC      lbl
9352
+;
9353 117 dgisselq
+(define_peephole2
9354 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9355
+               (match_operand:SI 0 "register_operand")
9356
+               (match_operand:SI 1 "register_operand")))
9357
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9358
+                       (label_ref (match_operand 2 ""))
9359 117 dgisselq
+                       (pc)))]
9360 127 dgisselq
+       "(ZIP_PEEPHOLE)"
9361 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
9362
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
9363 117 dgisselq
+                       (label_ref (match_dup 2))
9364
+                       (pc)))]
9365
+       "")
9366 127 dgisselq
+(define_peephole2
9367
+       [(match_scratch:SI 3 "=r")
9368
+       (set (reg:CC CC_REG) (compare:CC
9369
+               (match_operand:SI 0 "register_operand")
9370
+               (match_operand 1 "const_int_operand")))
9371
+       (match_dup 3)
9372
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9373
+                       (label_ref (match_operand 2 ""))
9374
+                       (pc)))]
9375
+       "(ZIP_PEEPHOLE)"
9376
+       [(set (match_dup 3) (match_dup 1))
9377
+       (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))
9378
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
9379
+                       (label_ref (match_dup 2))
9380
+                       (pc)))]
9381
+       "")
9382
+;(define_peephole2
9383
+;      [(set (reg:CC CC_REG) (compare:CC
9384
+;              (match_operand:SI 0 "register_operand")
9385
+;              (match_operand 1 "const_int_operand")))
9386
+;      (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9387
+;                      (label_ref (match_operand 2 ""))
9388
+;                      (pc)))]
9389
+;      ""
9390
+;      [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
9391
+;      (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
9392
+;                      (label_ref (match_dup 2))
9393
+;                      (pc)))]
9394
+;      "operands[1] = GEN_INT(INTVAL(operands[1])-1);")
9395 124 dgisselq
+;
9396
+;
9397
+; Match:
9398
+;      CMP     R1,R0
9399
+;      BGEU    lbl
9400
+; Transform to:
9401
+;      CMP     1(R0),R1
9402
+;      BC      lbl
9403
+;
9404 117 dgisselq
+(define_peephole2
9405 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9406
+               (match_operand:SI 0 "register_operand")
9407
+               (match_operand:SI 1 "register_operand")))
9408
+       (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
9409
+                       (label_ref (match_operand 2 ""))
9410 117 dgisselq
+                       (pc)))]
9411 127 dgisselq
+       "(ZIP_PEEPHOLE)"
9412 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9413
+               (match_dup 1) (plus (match_dup 0) (const_int 1))))
9414
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
9415 117 dgisselq
+                       (label_ref (match_dup 2))
9416
+                       (pc)))]
9417
+       "")
9418 124 dgisselq
+;
9419
+;
9420
+; Match:
9421
+;      CMP     R1,R0
9422
+;      BGE     lbl
9423
+; Transform to:
9424
+;      CMP     1(R0),R1
9425
+;      BLT     lbl
9426
+;
9427 117 dgisselq
+(define_peephole2
9428 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9429
+               (match_operand:SI 0 "register_operand")
9430
+               (match_operand:SI 1 "register_operand")))
9431
+       (set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
9432
+                       (label_ref (match_operand 2 ""))
9433 117 dgisselq
+                       (pc)))]
9434 127 dgisselq
+       "(ZIP_PEEPHOLE)"
9435 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1)
9436
+                       (plus:SI (match_dup 0) (const_int 1))))
9437
+       (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
9438 117 dgisselq
+                       (label_ref (match_dup 2))
9439
+                       (pc)))]
9440
+       "")
9441 124 dgisselq
+;
9442
+;
9443
+; Match:
9444
+;      CMP     R1,R0
9445
+;      BLEU    lbl
9446
+; Transform to:
9447
+;      CMP     1(R1),R0
9448
+;      BLT     lbl
9449
+;
9450 117 dgisselq
+(define_peephole2
9451 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9452
+               (match_operand:SI 0 "register_operand" "")
9453 117 dgisselq
+               (match_operand:SI 1 "register_operand" "")))
9454 122 dgisselq
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
9455 117 dgisselq
+                       (label_ref (match_operand 2 "" ""))
9456
+                       (pc)))]
9457 127 dgisselq
+       "(ZIP_PEEPHOLE)"
9458 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
9459
+                       (plus (match_dup 1) (const_int 1))))
9460
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
9461 117 dgisselq
+                       (label_ref (match_dup 2))
9462
+                       (pc)))]
9463
+       "")
9464
+;
9465 127 dgisselq
+(define_peephole2
9466
+       [(set (reg:CC CC_REG)
9467
+               (compare:CC (match_operand:SI 0 "register_operand" "")
9468
+                       (match_operand:SI 1 "const_int_operand" "")))
9469
+       (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
9470
+                       (label_ref (match_operand 2 "" ""))
9471
+                       (pc)))]
9472
+       "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
9473
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
9474
+       (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
9475
+                       (label_ref (match_dup 2))
9476
+                       (pc)))]
9477
+       "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
9478
+(define_peephole2
9479
+       [(set (reg:CC CC_REG)
9480
+               (compare:CC (match_operand:SI 0 "register_operand" "")
9481
+                       (match_operand:SI 1 "const_int_operand" "")))
9482
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
9483
+                       (label_ref (match_operand 2 "" ""))
9484
+                       (pc)))]
9485
+       "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
9486
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
9487
+       (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
9488
+                       (label_ref (match_dup 2))
9489
+                       (pc)))]
9490
+       "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
9491 102 dgisselq
+;
9492 117 dgisselq
+;
9493
+;
9494
+;
9495 127 dgisselq
+; Match:
9496
+;      (parallel [(set () ()) (clobber (CC))])
9497
+;      (compare () ())
9498
+; Transform to:
9499
+;      (parallel [(set () ()) (set (CC) (0))]
9500
+;      (compare () ())
9501 117 dgisselq
+;
9502 127 dgisselq
+(define_peephole2
9503
+       [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
9504
+               (clobber (reg:CC CC_REG))])
9505
+       (set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "")
9506
+                       (match_operand:SI 3 "")))]
9507
+       "(ZIP_PEEPHOLE)&&zip_insn_sets_cc(insn)"
9508
+       [(parallel [(set (match_dup 0) (match_dup 1))
9509
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9510
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (match_dup 3)))]
9511
+       "")
9512
+;
9513
+;
9514
+;
9515 122 dgisselq
+; Match:
9516 127 dgisselq
+;      (parallel [(set () ()) (clobber (CC))])
9517
+;      (set () ())
9518
+;      (compare () ())
9519
+; Transform to:
9520
+;      (parallel [(set () ()) (set (CC) (0))]
9521
+;      (set () ())
9522
+;      (compare () ())
9523
+;
9524
+(define_peephole2
9525
+       [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
9526
+               (clobber (reg:CC CC_REG))])
9527
+       (set (match_operand 2 "") (match_operand 3 ""))
9528
+       (set (reg:CC CC_REG) (compare:CC (match_operand:SI 4 "")
9529
+                       (match_operand:SI 5 "")))]
9530
+       "(ZIP_PEEPHOLE)&&(zip_insn_sets_cc(insn))&&((!REG_P(operands[2]))||(REGNO(operands[2])!=CC_REG))"
9531
+       [(parallel [(set (match_dup 0) (match_dup 1))
9532
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9533
+       (set (match_dup 2) (match_dup 3))
9534
+       (set (reg:CC CC_REG) (compare:CC (match_dup 4) (match_dup 5)))]
9535
+       "")
9536
+;
9537
+;
9538
+;
9539
+; Match:
9540 122 dgisselq
+;      MOV A(R1),R3
9541
+;      CMP R3,R0
9542
+;      (R3 is dead)
9543
+; Transform to:
9544
+;      CMP A(R1),R0
9545
+;
9546
+(define_peephole2
9547
+       [(set (match_operand:SI 3 "register_operand")
9548
+               (plus:SI (match_operand:SI 1 "register_operand")
9549
+                       (match_operand:SI 2 "zip_mvimm_operand_p")))
9550
+       (set (reg:CC CC_REG)
9551
+               (compare:CC (match_operand:SI 0 "register_operand")
9552
+                       (match_dup 3)))]
9553 127 dgisselq
+       "(ZIP_PEEPHOLE)&&peep2_regno_dead_p(2, REGNO(operands[3]))"
9554 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
9555
+               (plus:SI (match_dup 1) (match_dup 2))))]
9556
+       "")
9557
+;
9558
+;
9559
+; Match:
9560
+;      ALU OpB,R0
9561
+;      CMP 0,R0
9562
+; Transform to:
9563
+;      ALU OpB,R0
9564
+;
9565
+(define_peephole2
9566 124 dgisselq
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9567
+                       (match_operand:SI 1 ""))
9568 122 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9569
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
9570 127 dgisselq
+       "(ZIP_PEEPHOLE)"
9571 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
9572
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9573
+       ])
9574
+;
9575
+;
9576
+; Match:
9577
+;      ALU OpB,R0
9578
+;      MOV R1,R2       // Can be LDI, LOD, STO, etc.
9579 127 dgisselq
+;      CMP 0,R0
9580 122 dgisselq
+; Transform to:
9581
+;      ALU OpB,R0
9582
+;      MOV R0,R1
9583
+;
9584
+(define_peephole2
9585 124 dgisselq
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9586
+                       (match_operand:SI 1 ""))
9587 122 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9588 124 dgisselq
+       (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 ""))
9589 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
9590 127 dgisselq
+       "(ZIP_PEEPHOLE)&&((!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>=FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG))))"
9591 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
9592
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9593
+       (set (match_dup 2) (match_dup 3))
9594
+       ])
9595
+;
9596
+;
9597
+; Match:
9598
+;      ALU OpB,R0
9599
+;      MOV R0,R1
9600
+;      CMP 0,R1
9601
+; Transform to:
9602
+;      ALU OpB,R0
9603
+;      MOV R0,R1
9604
+;
9605
+(define_peephole2
9606 124 dgisselq
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9607
+                       (match_operand:SI 1 ""))
9608 122 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9609 124 dgisselq
+       (set (match_operand:SI 2 "register_operand") (match_dup 0))
9610 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
9611 127 dgisselq
+       "(ZIP_PEEPHOLE)"
9612 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
9613
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9614
+       (set (match_dup 2) (match_dup 3))
9615
+       ])
9616
+;
9617 124 dgisselq
+;
9618
+; Match:
9619
+;      MOV R1,R0
9620
+;      ADD $x,R0
9621
+;      (CCREG is dead, and x is within range ...)
9622
+; Transform to:
9623 127 dgisselq
+;      MOV $x(R1),R0
9624 124 dgisselq
+(define_peephole2
9625
+       [(set (match_operand:SI 0 "register_operand")
9626
+               (match_operand:SI 1 "register_operand"))
9627
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
9628
+                               (match_operand 2 "zip_mvimm_operand_p")))
9629
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9630
+       ]
9631 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))"
9632 124 dgisselq
+       [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
9633
+;
9634 127 dgisselq
+; Match:
9635
+;      MOV A(R0),R0
9636
+;      ADD $x,R1
9637
+;      (CCREG is dead, and (A+x) is within range ...)
9638
+; Transform to:
9639
+;      MOV $x(R1),R0
9640 124 dgisselq
+;
9641 127 dgisselq
+(define_peephole2
9642
+       [(set (match_operand:SI 0 "register_operand")
9643
+               (plus:SI (match_operand:SI 1 "register_operand")
9644
+                       (match_operand 2 "zip_mvimm_operand_p")))
9645
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
9646
+                               (match_operand 3 "zip_mvimm_operand_p")))
9647
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9648
+       ]
9649
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
9650
+               &&(INTVAL(operands[2])+INTVAL(operands[3])<((1<<17)))
9651
+               &&(INTVAL(operands[2])+INTVAL(operands[3])>=-(1<<17))"
9652
+       [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
9653
+       "operands[2]=GEN_INT(INTVAL(operands[2])+INTVAL(operands[3]));")
9654 124 dgisselq
+;
9655 127 dgisselq
+;
9656
+;
9657 124 dgisselq
+; Match:
9658
+;      ADD $x,R0
9659
+;      MOV R0,R1
9660
+;      (CCREG is dead, and R0 is dead)
9661
+; Transform to:
9662
+;      MOV (A+$x)(R0),R1
9663
+; ... again, how do I build this plus?
9664
+;
9665
+(define_peephole2
9666
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9667
+                       (plus:SI (match_dup 0)
9668
+                               (match_operand 1 "zip_mvimm_operand_p")))
9669
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9670
+       (set (match_operand:SI 2 "register_operand") (match_dup 0))]
9671 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))"
9672 124 dgisselq
+       [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])
9673
+;
9674
+;
9675 127 dgisselq
+;
9676 124 dgisselq
+; Match:
9677 127 dgisselq
+;      ADD $x,R0
9678
+;      MOV A(R0),R1
9679
+;      (CCREG is dead, and R0 is dead)
9680
+; Transform to:
9681
+;      MOV (A+$x)(R0),R1
9682
+;
9683
+(define_peephole2
9684
+       [(parallel [
9685
+               (set (match_operand:SI 0 "register_operand")
9686
+                       (plus:SI (match_dup 0)
9687
+                               (match_operand 1 "zip_mvimm_operand_p")))
9688
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9689
+       (set (match_operand:SI 2 "register_operand")
9690
+               (plus:SI (match_dup 0)
9691
+                       (match_operand 3 "zip_mvimm_operand_p")))
9692
+       ]
9693
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
9694
+               &&(peep2_regno_dead_p(1,REGNO(operands[0])))
9695
+               &&(INTVAL(operands[1])+INTVAL(operands[3])<((1<<17)))
9696
+               &&(INTVAL(operands[1])+INTVAL(operands[3])>=-(1<<17))"
9697
+       [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
9698
+       "operands[3]=GEN_INT(INTVAL(operands[1])+INTVAL(operands[3]));")
9699
+;
9700
+;
9701
+;
9702
+; Match:
9703 124 dgisselq
+;      ADD     $x,R0
9704
+;      ADD     R0,Rn
9705
+;      (R0 is dead, if R0 is not Rn)
9706
+; Transform to:
9707
+;      ADD     $x(R0),Rn
9708
+;
9709
+(define_peephole2
9710
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9711
+                       (plus:SI (match_dup 0)
9712
+                               (match_operand 1 "zip_opb_immv_p")))
9713
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9714
+       (parallel [(set (match_operand:SI 2 "register_operand")
9715
+                       (plus:SI (match_dup 2) (match_dup 0)))
9716
+               (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
9717
+       ]
9718 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
9719 124 dgisselq
+       [(parallel [(set (match_dup 2)
9720
+                       (plus:SI (match_dup 2)
9721
+                               (plus:SI (match_dup 0)
9722
+                                       (match_dup 1))))
9723
+               (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
9724
+       ])
9725
+;
9726
+; Match:
9727
+;      ADD     $x,R0
9728
+;      LOD     -x(R0),R1
9729
+; Transform to:
9730
+;      LOD     (R0),R1
9731
+;      ADD     $x,R0
9732
+;
9733
+(define_peephole2
9734
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9735
+                       (plus:SI (match_dup 0)
9736
+                               (match_operand 1 "zip_opb_immv_p")))
9737
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9738
+       (set (match_operand:SI 3 "register_operand")
9739
+               (mem:SI (plus:SI (match_dup 0)
9740
+                       (match_operand 2 "zip_opb_immv_p"))))
9741
+       ]
9742 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
9743 124 dgisselq
+       [(set (match_dup 3) (mem:SI (match_dup 0)))
9744
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
9745
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9746
+       ])
9747 127 dgisselq
+(define_peephole2
9748
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9749
+                       (plus:SI (match_dup 0)
9750
+                               (match_operand 1 "zip_opb_immv_p")))
9751
+               (clobber (reg:CC CC_REG))])
9752
+       (set (match_operand:SI 3 "register_operand")
9753
+               (mem:SI (plus:SI (match_dup 0)
9754
+                       (match_operand 2 "zip_opb_immv_p"))))
9755
+       ]
9756
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
9757
+       [(set (match_dup 3) (mem:SI (match_dup 0)))
9758
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
9759
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9760
+       ])
9761 124 dgisselq
+;
9762
+;
9763
+;
9764
+; Match:
9765
+;      ADD     $x,R0
9766
+;      STO     R1,-x(R0)
9767
+; Transform to:
9768
+;      STO     R1,(R0)
9769
+;      ADD     $x,R0
9770
+;
9771
+(define_peephole2
9772
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9773
+                       (plus:SI (match_dup 0)
9774
+                               (match_operand 1 "zip_opb_immv_p")))
9775
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9776
+       (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
9777
+               (match_operand:SI 3 "register_operand"))
9778
+       ]
9779 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
9780 124 dgisselq
+       [(set (mem:SI (match_dup 0)) (match_dup 3))
9781
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
9782
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9783
+       ])
9784 127 dgisselq
+(define_peephole2
9785
+       [(parallel [(set (match_operand:SI 0 "register_operand")
9786
+                       (plus:SI (match_dup 0)
9787
+                               (match_operand 1 "zip_opb_immv_p")))
9788
+               (clobber (reg:CC CC_REG))])
9789
+       (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
9790
+               (match_operand:SI 3 "register_operand"))
9791
+       ]
9792
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
9793
+       [(set (mem:SI (match_dup 0)) (match_dup 3))
9794
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
9795
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9796
+       ])
9797 124 dgisselq
+;
9798
+;
9799
+; Match:
9800
+;      ADD     $x,R0
9801
+;      ANY     R1,R2 (destination is not R0, source does not reference R0)
9802
+;      ADD     R0,Rn (could be 1 or 2, not 0)
9803
+;      (R0 is dead)
9804
+; Transform to:
9805
+;      ANY     R1,R2
9806
+;      ADD     $x(R0),Rn
9807
+;
9808
+;
9809
+;
9810 127 dgisselq
+; Match:
9811
+;      MOV     R1,R0
9812
+;      AND     #/R2,R0
9813
+;      (Ry dead ...)
9814
+; Transform to:
9815
+;      TEST    #/Rz,Rx
9816 124 dgisselq
+;
9817 127 dgisselq
+(define_peephole2
9818
+       [(set (match_operand:SI 0 "register_operand")
9819
+               (match_operand:SI 1 "register_operand"))
9820
+       (parallel [(set (match_dup 0)
9821
+                       (and:SI (match_dup 0)
9822
+                               (match_operand:SI 2 "zip_opb_single_operand_p")))
9823
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
9824
+       ]
9825
+       "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
9826
+       [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_dup 1) (match_dup 2))
9827
+                       (const_int 0)))])
9828
+;
9829
+; Match:
9830
+;      (call ...
9831
+;      (set (pc) (label))
9832
+;  or (in asm)
9833
+;      MOV     .Lcallx(PC),R0
9834
+;      BRA     (somewhere)
9835
+; .Lcallx
9836
+;      BRA     (somewhere-else)
9837
+; Transform to:
9838
+;
9839
+;      (sequence [(call ...
9840
+;              (set (pc) (label))])
9841
+;   or (in asm)
9842
+;      "LDI    (somewhere-else),R0
9843
+;      BRA     subroutine"
9844
+;
9845
+; While the following looks good, it doesnt work.  My guess is that the reason
9846
+; why it doesnt work is that the jump at the end crosses basic block boundaries.
9847
+;
9848
+;(define_insn "void_call_mem_unspec"
9849
+;      [(call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p" ""))] UNSPEC_RAW_CALL)
9850
+;                      (match_operand 1 "const_int_operand" "n"))
9851
+;              (clobber (reg:SI RTN_REG))
9852
+;              (clobber (reg:CC CC_REG))]
9853
+;      ""
9854
+;      "BRA\t%0,PC"
9855
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9856
+;(define_peephole2
9857
+;      [(parallel [(call (mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))
9858
+;                      (match_operand 1 "const_int_operand"))
9859
+;              (clobber (reg:SI RTN_REG))
9860
+;              (clobber (reg:CC CC_REG))])
9861
+;      ; The match operand for the (set (pc) ...) cannot have anything but
9862
+;      ; VOIDmode, or it wont match.
9863
+;      (set (pc) (match_operand:VOID 2 "zip_const_address_operand_p"))]
9864
+;      ""
9865
+;      [(set (reg:SI RTN_REG) (match_dup 2))
9866
+;      (call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))] UNSPEC_RAW_CALL)
9867
+;                      (match_operand 1 "const_int_operand"))
9868
+;              (use (reg:SI RTN_REG))
9869
+;              (clobber (reg:SI RTN_REG))
9870
+;              (clobber (reg:CC CC_REG))]
9871
+;      "fprintf(stderr, \"CALL-JUMP Matched\");")
9872
+;
9873
+;
9874
+;
9875
+; So, the following *should* have worked as well.  However, this falls apart
9876
+; because the 'final' routine can't tell if we are calling a subroutine in this
9877
+; function or not.
9878
+;
9879
+;(define_peephole
9880
+       ;[(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p"))
9881
+                       ;(match_operand 1 "const_int_operand"))
9882
+               ;(clobber (reg:SI RTN_REG))
9883
+               ;(clobber (reg:CC CC_REG))])
9884
+       ;(set (pc) (label_ref (match_operand 2 "")))]
9885
+       ;""
9886
+       ;"LDI\t%2,R0\;BRA\t%0"
9887
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9888
+;
9889 124 dgisselq
+; and for
9890
+;      BRA target
9891
+;      BRA target ; two branches to the same identical target in a row ...
9892
+;
9893
+;
9894
+;
9895 102 dgisselq
+; STILL MISSING:
9896
+;      SYSCALL(ID)
9897
+;              MOV %ID,R0
9898
+;              CLR     CC
9899
+;      cmove   ... the conditional move, created from a
9900
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
9901
+;      pattern
9902
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
9903
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def     1969-12-31 19:00:00.000000000 -0500
9904 111 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def  2016-03-08 12:10:21.982586940 -0500
9905
@@ -0,0 +1,23 @@
9906 102 dgisselq
+/*
9907
+ * Commends in C-long comment form
9908
+ * class
9909
+ *     Mode = "SI"
9910
+ *     PRECISION, BYTESIZE, COUNT ??
9911
+ *     FORMAT
9912
+ *     EXPR
9913 111 dgisselq
+ *
9914
+ * The manual says I need to define BITS_PER_UNIT here.
9915 102 dgisselq
+ */
9916
+// INT_MODE(QI, 1);
9917
+// INT_MODE(HI, 1);
9918
+// INT_MODE(SI, 1);
9919
+// INT_MODE(DI, 2);
9920
+
9921
+// FLOAT_MODE(SF, 1, ieee_single_format);
9922
+// FLOAT_MODE(DF, 2, ieee_single_format);
9923
+
9924
+// We cannot override machmodes.def from here.  Thus, even though our QI,
9925
+// HI, and SI modes are all 1-byte, we cant set them that way here.  The
9926
+// change needed to be made in machmodes.def.  Hence, here is a target
9927
+// configuration change--in machmodes.def--that properly belonged in the
9928
+// config directory.
9929
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
9930
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
9931 127 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-04-21 16:19:02.122215475 -0400
9932
@@ -0,0 +1,82 @@
9933 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
9934
+//
9935
+// Filename:   zip-protos.h
9936
+//
9937
+// Project:    Zip CPU backend for the GNU Compiler Collection
9938
+//
9939
+// Purpose:
9940
+//
9941
+// Creator:    Dan Gisselquist, Ph.D.
9942
+//             Gisselquist Technology, LLC
9943
+//
9944
+////////////////////////////////////////////////////////////////////////////////
9945
+//
9946
+// Copyright (C) 2016, Gisselquist Technology, LLC
9947
+//
9948
+// This program is free software (firmware): you can redistribute it and/or
9949
+// modify it under the terms of  the GNU General Public License as published
9950
+// by the Free Software Foundation, either version 3 of the License, or (at
9951
+// your option) any later version.
9952
+//
9953
+// This program is distributed in the hope that it will be useful, but WITHOUT
9954
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
9955
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
9956
+// for more details.
9957
+//
9958
+// You should have received a copy of the GNU General Public License along
9959
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
9960
+// target there if the PDF file isn't present.)  If not, see
9961
+// <http://www.gnu.org/licenses/> for a copy.
9962
+//
9963
+// License:    GPL, v3, as defined and found on www.gnu.org,
9964
+//             http://www.gnu.org/licenses/gpl.html
9965
+//
9966
+//
9967
+////////////////////////////////////////////////////////////////////////////////
9968
+#ifndef        ZIP_PROTOS_H
9969
+#define        ZIP_PROTOS_H
9970
+
9971 127 dgisselq
+extern bool    zip_supported_condition(int c);
9972 102 dgisselq
+extern void    zip_expand_prologue(void);
9973
+extern void    zip_expand_epilogue(void);
9974 127 dgisselq
+extern void    zip_expand_movsicc(rtx,rtx,rtx,rtx);
9975 102 dgisselq
+extern int     zip_initial_elimination_offset(int, int);
9976
+extern void    zip_print_operand(FILE *, rtx, int);
9977
+extern void    zip_print_operand_address(FILE *, rtx);
9978
+extern enum    reg_class       zip_reg_class(int);
9979
+extern rtx     zip_return_addr_rtx(int, rtx);
9980
+extern int     zip_num_arg_regs(enum machine_mode, tree);
9981
+
9982
+extern void    zip_asm_output_def(FILE *s, const char *n, const char *v);
9983 122 dgisselq
+
9984
+#ifdef HAVE_cc0
9985 102 dgisselq
+extern void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
9986 122 dgisselq
+#else
9987
+extern void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
9988
+#endif
9989 102 dgisselq
+extern int     zip_address_operand(rtx op);
9990
+extern int     zip_const_address_operand(rtx op);
9991
+extern bool    zip_gen_move_rtl(rtx, rtx);
9992
+extern bool    zip_use_return_insn(void);
9993
+extern const char *zip_set_zero_or_one(rtx, rtx);
9994
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
9995
+
9996 127 dgisselq
+extern int     zip_insn_sets_cc(rtx_insn *insn);
9997
+extern int     zip_is_conditional(rtx_insn *insn);
9998 102 dgisselq
+extern int     zip_ct_address_operand(rtx op);
9999 111 dgisselq
+extern int     zip_pd_opb_operand(rtx op);
10000 102 dgisselq
+extern int     zip_pd_mov_operand(rtx op);
10001 111 dgisselq
+extern int     zip_pd_imm_operand(rtx op);
10002
+extern int     zip_pd_mvimm_operand(rtx op);
10003 102 dgisselq
+extern int     zip_ct_const_address_operand(rtx op);
10004
+extern int     zip_pd_const_address_operand(rtx op);
10005
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
10006
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
10007
+
10008 122 dgisselq
+extern void    zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
10009
+extern void    zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
10010
+extern void    zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
10011
+extern void    zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
10012
+
10013 102 dgisselq
+#endif
10014
+
10015
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
10016
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
10017
+++ gcc-5.3.0-zip/gcc/config.gcc        2016-02-14 00:53:37.389411987 -0500
10018
@@ -479,6 +479,10 @@
10019
 tilepro*-*-*)
10020
        cpu_type=tilepro
10021
        ;;
10022
+zip*)
10023
+       cpu_type=zip
10024
+       tmake_file=zip/t-zip
10025
+       ;;
10026
 esac
10027
 
10028
 tm_file=${cpu_type}/${cpu_type}.h
10029
@@ -2972,6 +2976,15 @@
10030
        c_target_objs="m32c-pragma.o"
10031
        cxx_target_objs="m32c-pragma.o"
10032
        ;;
10033
+zip-*-netbsd*)
10034
+       tm_file="${tm_file} elfos.h netbsd.h netbsd-elf.h zip/netbsd.h"
10035
+       tmake_file="${tmake_file} zip/t-zip"
10036
+       ;;
10037
+zip*)
10038
+       target_has_targetm_common=yes
10039
+       tm_file="elfos.h newlib-stdint.h ${tm_file}"
10040
+       tmake_file="${tmake_file} zip/t-zip"
10041
+       ;;
10042
 *)
10043
        echo "*** Configuration ${target} not supported" 1>&2
10044
        exit 1
10045
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
10046
--- gcc-5.3.0-original/gcc/cse.c        2015-02-03 15:41:38.000000000 -0500
10047 122 dgisselq
+++ gcc-5.3.0-zip/gcc/cse.c     2016-04-05 22:26:30.816200542 -0400
10048 111 dgisselq
@@ -634,6 +634,15 @@
10049 102 dgisselq
 
10050
 /* Nonzero if X has the form (PLUS frame-pointer integer).  */
10051
 
10052 111 dgisselq
+// #define     DO_ZIP_DEBUGS
10053 102 dgisselq
+#ifdef DO_ZIP_DEBUGS
10054
+#include <stdio.h>
10055
+extern void zip_debug_rtx(const_rtx);
10056
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s\n", STR); zip_debug_rtx(RTX); } while(0)
10057
+#else
10058
+#define        ZIP_DEBUG_LINE(STR,RTX)
10059
+#endif
10060
+
10061
 static bool
10062
 fixed_base_plus_p (rtx x)
10063
 {
10064
@@ -2898,6 +2907,7 @@
10065
          validate_canon_reg (&XVECEXP (x, i, j), insn);
10066
     }
10067
 
10068
+       ZIP_DEBUG_LINE("CANON-REG-RTN", x);
10069
   return x;
10070
 }
10071
 
10072
@@ -3144,14 +3154,16 @@
10073
   if (x == 0)
10074
     return x;
10075
 
10076
+       ZIP_DEBUG_LINE("FOLD-RTX", x);
10077
   /* Try to perform some initial simplifications on X.  */
10078
   code = GET_CODE (x);
10079
   switch (code)
10080
     {
10081
     case MEM:
10082
     case SUBREG:
10083
-      if ((new_rtx = equiv_constant (x)) != NULL_RTX)
10084
-        return new_rtx;
10085
+      if ((new_rtx = equiv_constant (x)) != NULL_RTX) {
10086
+       ZIP_DEBUG_LINE("FOLD-RTX-NEW", new_rtx);
10087
+        return new_rtx; }
10088
       return x;
10089
 
10090
     case CONST:
10091
@@ -3208,6 +3220,8 @@
10092
        rtx folded_arg = XEXP (x, i), const_arg;
10093
        machine_mode mode_arg = GET_MODE (folded_arg);
10094
 
10095
+       ZIP_DEBUG_LINE("FOLD-RTX-ARG = ", folded_arg);
10096
+
10097
        switch (GET_CODE (folded_arg))
10098
          {
10099
          case MEM:
10100
@@ -3317,6 +3331,7 @@
10101
        }
10102
 
10103
       apply_change_group ();
10104
+       ZIP_DEBUG_LINE("FOLD-RTX-CANONICALIZED = ", insn);
10105
     }
10106
 
10107
   /* If X is an arithmetic operation, see if we can simplify it.  */
10108
@@ -4203,6 +4218,7 @@
10109
 {
10110
   rtx dest = SET_DEST (set);
10111
   rtx src = SET_SRC (set);
10112
+       ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG", insn);
10113
 
10114
   if (REG_P (dest)
10115
       && REG_P (src) && ! HARD_REGISTER_P (src)
10116
@@ -4258,6 +4274,7 @@
10117
            }
10118
        }
10119
     }
10120
+       ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG, done", insn);
10121
 }
10122
 
10123
 /* Record all the SETs in this instruction into SETS_PTR,
10124
@@ -4351,6 +4368,7 @@
10125
   rtx tem;
10126
   rtx x = PATTERN (insn);
10127
   int i;
10128
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN", insn);
10129
 
10130
   if (CALL_P (insn))
10131
     {
10132
@@ -4364,6 +4382,7 @@
10133
       canon_reg (SET_SRC (x), insn);
10134
       apply_change_group ();
10135
       fold_rtx (SET_SRC (x), insn);
10136
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN, was set:", insn);
10137
     }
10138
   else if (GET_CODE (x) == CLOBBER)
10139
     {
10140
@@ -4400,6 +4419,7 @@
10141
     canon_reg (PATTERN (insn), insn);
10142
   else if (GET_CODE (x) == PARALLEL)
10143
     {
10144
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN/parallel", insn);
10145
       for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
10146
        {
10147
          rtx y = XVECEXP (x, 0, i);
10148
@@ -4491,6 +4511,7 @@
10149
 
10150
      The result of apply_change_group can be ignored; see canon_reg.  */
10151
 
10152
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN/done", insn);
10153
   apply_change_group ();
10154
 }
10155
 
10156
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/defaults.h gcc-5.3.0-zip/gcc/defaults.h
10157
--- gcc-5.3.0-original/gcc/defaults.h   2015-03-03 10:04:02.000000000 -0500
10158
+++ gcc-5.3.0-zip/gcc/defaults.h        2016-02-06 16:57:53.939410173 -0500
10159
@@ -480,6 +480,8 @@
10160
 #define LOG2_BITS_PER_UNIT 3
10161
 #elif BITS_PER_UNIT == 16
10162
 #define LOG2_BITS_PER_UNIT 4
10163
+#elif BITS_PER_UNIT == 32
10164
+#define LOG2_BITS_PER_UNIT 5
10165
 #else
10166
 #error Unknown BITS_PER_UNIT
10167
 #endif
10168 127 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/df-scan.c gcc-5.3.0-zip/gcc/df-scan.c
10169
--- gcc-5.3.0-original/gcc/df-scan.c    2015-01-09 15:18:42.000000000 -0500
10170
+++ gcc-5.3.0-zip/gcc/df-scan.c 2016-04-14 16:12:03.614777002 -0400
10171
@@ -61,6 +61,14 @@
10172
 
10173
 typedef struct df_mw_hardreg *df_mw_hardreg_ptr;
10174
 
10175
+// #define     DO_ZIP_DEBUGS
10176
+#ifdef DO_ZIP_DEBUGS
10177
+extern void    zip_debug_rtx(const_rtx);
10178
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
10179
+#else
10180
+#define        ZIP_DEBUG_LINE(STR,RTX)
10181
+#endif
10182
+
10183
 
10184
 #ifndef HAVE_epilogue
10185
 #define HAVE_epilogue 0
10186 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log
10187
--- gcc-5.3.0-original/gcc/doc/gcc.log  1969-12-31 19:00:00.000000000 -0500
10188
+++ gcc-5.3.0-zip/gcc/doc/gcc.log       2016-01-30 15:18:43.262724969 -0500
10189
@@ -0,0 +1,214 @@
10190
+This is pdfTeX, Version 3.1415926-2.5-1.40.14 (TeX Live 2013/Debian) (format=pdfetex 2014.5.7)  30 JAN 2016 15:17
10191
+entering extended mode
10192
+ restricted \write18 enabled.
10193
+ file:line:error style messages enabled.
10194
+ %&-line parsing enabled.
10195
+**\catcode126=12 \def\normaltilde{~}\catcode126=13 \let~\normaltilde  \input ./
10196
+gcc.texi
10197
+(./gcc.texi (/usr/share/texmf/tex/texinfo/texinfo.tex
10198
+Loading texinfo [version 2013-09-11.11]:
10199
+\bindingoffset=\dimen16
10200
+\normaloffset=\dimen17
10201
+\pagewidth=\dimen18
10202
+\pageheight=\dimen19
10203
+\outerhsize=\dimen20
10204
+\outervsize=\dimen21
10205
+\cornerlong=\dimen22
10206
+\cornerthick=\dimen23
10207
+\topandbottommargin=\dimen24
10208
+\headlinebox=\box16
10209
+\footlinebox=\box17
10210
+\margin=\insert252
10211
+\EMsimple=\toks13
10212
+\groupbox=\box18
10213
+\groupinvalidhelp=\toks14
10214
+\mil=\dimen25
10215
+\exdentamount=\skip18
10216
+\inmarginspacing=\skip19
10217
+\centerpenalty=\count27
10218
+ pdf,
10219
+\tempnum=\count28
10220
+\lnkcount=\count29
10221
+\filename=\toks15
10222
+\filenamelength=\count30
10223
+\pgn=\count31
10224
+\toksA=\toks16
10225
+\toksB=\toks17
10226
+\toksC=\toks18
10227
+\toksD=\toks19
10228
+\boxA=\box19
10229
+\countA=\count32
10230
+\nopdfimagehelp=\toks20
10231
+ fonts,
10232
+\sffam=\fam8
10233
+\textleading=\dimen26
10234
+ markup,
10235
+\fontdepth=\count33
10236
+ glyphs,
10237
+\errorbox=\box20
10238
+
10239
+page headings,
10240
+\titlepagetopglue=\skip20
10241
+\titlepagebottomglue=\skip21
10242
+\evenheadline=\toks21
10243
+\oddheadline=\toks22
10244
+\evenfootline=\toks23
10245
+\oddfootline=\toks24
10246
+ tables,
10247
+\tableindent=\dimen27
10248
+\itemindent=\dimen28
10249
+\itemmargin=\dimen29
10250
+\itemmax=\dimen30
10251
+\itemno=\count34
10252
+\multitableparskip=\skip22
10253
+\multitableparindent=\skip23
10254
+\multitablecolspace=\dimen31
10255
+\multitablelinespace=\skip24
10256
+\colcount=\count35
10257
+\everytab=\toks25
10258
+ conditionals,
10259
+\doignorecount=\count36
10260
+ indexing,
10261
+\whatsitskip=\skip25
10262
+\whatsitpenalty=\count37
10263
+\secondaryindent=\skip26
10264
+\partialpage=\box21
10265
+\doublecolumnhsize=\dimen32
10266
+ sectioning,
10267
+\unnumberedno=\count38
10268
+\chapno=\count39
10269
+\secno=\count40
10270
+\subsecno=\count41
10271
+\subsubsecno=\count42
10272
+\appendixno=\count43
10273
+\absseclevel=\count44
10274
+\secbase=\count45
10275
+\chapheadingskip=\skip27
10276
+\secheadingskip=\skip28
10277
+\subsecheadingskip=\skip29
10278
+ toc,
10279
+\tocfile=\write0
10280
+\contentsrightmargin=\skip30
10281
+\savepageno=\count46
10282
+\lastnegativepageno=\count47
10283
+\tocindent=\dimen33
10284
+ environments,
10285
+\lispnarrowing=\skip31
10286
+\envskipamount=\skip32
10287
+\circthick=\dimen34
10288
+\cartouter=\dimen35
10289
+\cartinner=\dimen36
10290
+\normbskip=\skip33
10291
+\normpskip=\skip34
10292
+\normlskip=\skip35
10293
+\lskip=\skip36
10294
+\rskip=\skip37
10295
+\nonfillparindent=\dimen37
10296
+\tabw=\dimen38
10297
+\verbbox=\box22
10298
+
10299
+defuns,
10300
+\defbodyindent=\skip38
10301
+\defargsindent=\skip39
10302
+\deflastargmargin=\skip40
10303
+\defunpenalty=\count48
10304
+\parencount=\count49
10305
+\brackcount=\count50
10306
+ macros,
10307
+\paramno=\count51
10308
+\macname=\toks26
10309
+ cross references,
10310
+\auxfile=\write1
10311
+\savesfregister=\count52
10312
+\toprefbox=\box23
10313
+\printedrefnamebox=\box24
10314
+\infofilenamebox=\box25
10315
+\printedmanualbox=\box26
10316
+ insertions,
10317
+\footnoteno=\count53
10318
+\SAVEfootins=\box27
10319
+\SAVEmargin=\box28
10320
+
10321
+(/usr/share/texlive/texmf-dist/tex/generic/epsf/epsf.tex
10322
+This is `epsf.tex' v2.7.4 <14 February 2011>
10323
+\epsffilein=\read1
10324
+\epsfframemargin=\dimen39
10325
+\epsfframethickness=\dimen40
10326
+\epsfrsize=\dimen41
10327
+\epsftmp=\dimen42
10328
+\epsftsize=\dimen43
10329
+\epsfxsize=\dimen44
10330
+\epsfysize=\dimen45
10331
+\pspoints=\dimen46
10332
+)
10333
+\noepsfhelp=\toks27
10334
+ localization,
10335
+\nolanghelp=\toks28
10336
+\countUTFx=\count54
10337
+\countUTFy=\count55
10338
+\countUTFz=\count56
10339
+ formatting,
10340
+\defaultparindent=\dimen47
10341
+ and turning on texinfo input format.)
10342
+\openout1 = `gcc.aux'.
10343
+
10344
+@cpindfile=@write2
10345
+@fnindfile=@write3
10346
+@vrindfile=@write4
10347
+@tpindfile=@write5
10348
+@kyindfile=@write6
10349
+@pgindfile=@write7
10350
+texinfo.tex: doing @include of gcc-common.texi
10351
+
10352
+
10353
+./gcc.texi:25: I can't find file `gcc-common.texi'.
10354
+@temp ->@input gcc-common.texi
10355
+
10356
+@includezzz ...and @input #1 }@expandafter }@temp
10357
+                                                  @popthisfilestack
10358
+l.25 @include gcc-common.texi
10359
+
10360
+(Press Enter to retry, or Control-D to exit)
10361
+Please type another input file name: include/gcc-common.texi
10362
+(./include/gcc-common.texi
10363
+texinfo.tex: doing @include of gcc-vers.texi
10364
+
10365
+
10366
+./include/gcc-common.texi:11: I can't find file `gcc-vers.texi'.
10367
+@temp ->@input gcc-vers.texi
10368
+
10369
+@includezzz ...and @input #1 }@expandafter }@temp
10370
+                                                  @popthisfilestack
10371
+l.11 @include gcc-vers.texi
10372
+
10373
+(Press Enter to retry, or Control-D to exit)
10374
+Please type another input file name: include/gcc-vers.texi
10375
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
10376
+@temp ->@input gcc-vers.texi
10377
+
10378
+@includezzz ...and @input #1 }@expandafter }@temp
10379
+                                                  @popthisfilestack
10380
+l.11 @include gcc-vers.texi
10381
+
10382
+(Press Enter to retry, or Control-D to exit)
10383
+Please type another input file name:
10384
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
10385
+@temp ->@input gcc-vers.texi
10386
+
10387
+@includezzz ...and @input #1 }@expandafter }@temp
10388
+                                                  @popthisfilestack
10389
+l.11 @include gcc-vers.texi
10390
+
10391
+(Press Enter to retry, or Control-D to exit)
10392
+Please type another input file name:
10393
+./include/gcc-common.texi:11: Emergency stop.
10394
+@temp ->@input gcc-vers.texi
10395
+
10396
+@includezzz ...and @input #1 }@expandafter }@temp
10397
+                                                  @popthisfilestack
10398
+l.11 @include gcc-vers.texi
10399
+
10400
+End of file on the terminal!
10401
+
10402
+./include/gcc-common.texi:11:  ==> Fatal error occurred, no output PDF file pro
10403
+duced!
10404 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c
10405
--- gcc-5.3.0-original/gcc/emit-rtl.c   2015-08-05 07:20:59.000000000 -0400
10406 127 dgisselq
+++ gcc-5.3.0-zip/gcc/emit-rtl.c        2016-04-20 20:54:45.148982373 -0400
10407 117 dgisselq
@@ -81,6 +81,15 @@
10408
 #include "builtins.h"
10409
 #include "rtl-iter.h"
10410
 
10411
+// #define     DO_ZIP_DEBUGS
10412
+#include <stdio.h>
10413
+#ifdef DO_ZIP_DEBUGS
10414
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
10415
+extern void    zip_debug_rtx(const_rtx);
10416
+#else
10417
+#define        ZIP_DEBUG_LINE(STR,RTX)
10418
+#endif
10419
+
10420
 struct target_rtl default_target_rtl;
10421
 #if SWITCHABLE_TARGET
10422
 struct target_rtl *this_target_rtl = &default_target_rtl;
10423 127 dgisselq
@@ -2979,6 +2988,8 @@
10424 117 dgisselq
       break;
10425
     }
10426
 
10427
+ZIP_DEBUG_LINE("Before RTX_FLAG",x);
10428
+
10429
   /* This rtx may not be shared.  If it has already been seen,
10430
      replace it with a copy of itself.  */
10431
 
10432 127 dgisselq
@@ -2989,6 +3000,8 @@
10433 117 dgisselq
     }
10434
   RTX_FLAG (x, used) = 1;
10435
 
10436
+ZIP_DEBUG_LINE("Post RTX_FLAG",x);
10437
+
10438
   /* Now scan the subexpressions recursively.
10439
      We can store any replaced subexpressions directly into X
10440
      since we know X is not shared!  Any vectors in X
10441 127 dgisselq
@@ -3665,7 +3678,9 @@
10442
     split_branch_probability = XINT (note, 0);
10443
   probability = split_branch_probability;
10444
 
10445
+ZIP_DEBUG_LINE("Before split", trial);
10446
   seq = safe_as_a <rtx_insn *> (split_insns (pat, trial));
10447
+ZIP_DEBUG_LINE("After split", seq);
10448
 
10449
   split_branch_probability = -1;
10450
 
10451
@@ -3834,6 +3849,7 @@
10452
     if (! tem->deleted () && INSN_P (tem))
10453
       tem = try_split (PATTERN (tem), tem, 1);
10454
 
10455
+
10456
   /* Return either the first or the last insn, depending on which was
10457
      requested.  */
10458
   return last
10459 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c
10460
--- gcc-5.3.0-original/gcc/expr.c       2015-04-07 10:34:06.000000000 -0400
10461 103 dgisselq
+++ gcc-5.3.0-zip/gcc/expr.c    2016-03-08 04:07:01.426335724 -0500
10462 102 dgisselq
@@ -7999,6 +7999,8 @@
10463
    the back of the caller.
10464
    The normal operating mode is to pass FALSE for this parameter.  */
10465
 
10466
+#include "print-tree.h"
10467
+
10468
 rtx
10469
 expand_expr_real (tree exp, rtx target, machine_mode tmode,
10470
                  enum expand_modifier modifier, rtx *alt_rtl,
10471 111 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
10472
--- gcc-5.3.0-original/gcc/final.c      2015-01-15 08:28:42.000000000 -0500
10473 127 dgisselq
+++ gcc-5.3.0-zip/gcc/final.c   2016-04-20 20:52:07.186056061 -0400
10474 111 dgisselq
@@ -109,6 +109,14 @@
10475
 #include "wide-int-print.h"
10476
 #include "rtl-iter.h"
10477
 
10478 122 dgisselq
+// #define     DO_ZIP_DEBUGS
10479 111 dgisselq
+#ifdef DO_ZIP_DEBUGS
10480
+extern void zip_debug_rtx(const_rtx);
10481
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
10482
+#else
10483
+#define        ZIP_DEBUG_LINE(STR,RTX)
10484
+#endif
10485
+
10486
 #ifdef XCOFF_DEBUGGING_INFO
10487
 #include "xcoffout.h"          /* Needed for external data
10488
                                   declarations for e.g. AIX 4.x.  */
10489
@@ -2071,6 +2079,8 @@
10490
   /* Output the insns.  */
10491
   for (insn = first; insn;)
10492
     {
10493
+       ZIP_DEBUG_LINE("final()\n", insn);
10494
+
10495
       if (HAVE_ATTR_length)
10496
        {
10497
          if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
10498 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
10499
--- gcc-5.3.0-original/gcc/genmodes.c   2015-01-05 07:33:28.000000000 -0500
10500
+++ gcc-5.3.0-zip/gcc/genmodes.c        2016-03-04 21:27:49.669147699 -0500
10501
@@ -330,7 +330,8 @@
10502
         the size of a CC mode is four units.  */
10503
       validate_mode (m, UNSET, UNSET, UNSET, UNSET, UNSET);
10504
 
10505
-      m->bytesize = 4;
10506
+       /* For the ZipCPU, however, it is only one unit */
10507
+      m->bytesize = 1;
10508
       m->ncomponents = 1;
10509
       m->component = 0;
10510
       break;
10511
@@ -766,11 +767,12 @@
10512
 
10513
   /* So put the default value unless the target needs a non standard
10514
      value. */
10515
-#ifdef BITS_PER_UNIT
10516
-  bits_per_unit = BITS_PER_UNIT;
10517
-#else
10518
-  bits_per_unit = 8;
10519
-#endif
10520
+// #ifdef BITS_PER_UNIT
10521
+  // bits_per_unit = BITS_PER_UNIT;
10522
+// #else
10523
+  bits_per_unit = 32;
10524
+#warning "Is there a more automated way to set bits per unit?"
10525
+// #endif
10526
 
10527
 #ifdef MAX_BITSIZE_MODE_ANY_INT
10528
   max_bitsize_mode_any_int = MAX_BITSIZE_MODE_ANY_INT;
10529
@@ -1083,7 +1085,7 @@
10530
       first = modes[c];
10531
       last = 0;
10532
       for (m = first; m; last = m, m = m->next)
10533
-       ;
10534
+       if ((m->next)&&(m->next->bytesize == m->bytesize)) first = m;
10535
 
10536
       /* Don't use BImode for MIN_MODE_INT, since otherwise the middle
10537
         end will try to use it for bitfields in structures and the
10538
@@ -1268,7 +1270,7 @@
10539
            continue;
10540
          if (m->precision != (unsigned int) -1)
10541
            {
10542
-             if (m2->precision != 2 * m->precision)
10543
+             if (m2->precision < 2 * m->precision)
10544
                continue;
10545
            }
10546
          else
10547
@@ -1323,7 +1325,6 @@
10548
       tagged_printf ("MODE_MASK (%u)", m->precision, m->name);
10549
     else
10550
       tagged_printf ("MODE_MASK (%u*BITS_PER_UNIT)", m->bytesize, m->name);
10551
-
10552
   puts ("#undef MODE_MASK");
10553
   print_closer ();
10554
 }
10555
@@ -1351,12 +1352,23 @@
10556
   int c;
10557
   struct mode_data *m;
10558
 
10559
+  puts(
10560
+"\n\n/* This is a rather strange conundrum.  Alignment is used by the host in\n"
10561
+" * the assembly file, whereas the size is used by the target.  Thus, for\n"
10562
+" * now, to align to a single target word means to align to 4 8-bit bytes in\n"
10563
+" * assembly.  If you get it wrong, the assembler will try to help.  Thus,\n"
10564
+" * aligning to anything less than 4 (1 target word) will cause an alignment\n"
10565
+" * of the target word in size.  However, this tries to do a little something\n"
10566
+" * teach our compiler what we are doing.\n"
10567
+" */\n");
10568
   print_maybe_const_decl ("%sunsigned char",
10569
                          "mode_base_align", "NUM_MACHINE_MODES",
10570
                          alignment);
10571
 
10572
   for_all_modes (c, m)
10573
-    tagged_printf ("%u", m->alignment, m->name);
10574
+    tagged_printf ("%u", 4*m->bytesize,
10575
+               // m->alignment,
10576
+               m->name);
10577
 
10578
   print_closer ();
10579
 }
10580 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c
10581
--- gcc-5.3.0-original/gcc/jump.c       2015-01-27 04:19:30.000000000 -0500
10582 122 dgisselq
+++ gcc-5.3.0-zip/gcc/jump.c    2016-04-06 14:06:50.207563805 -0400
10583 117 dgisselq
@@ -80,6 +80,14 @@
10584
 #include "target.h"
10585
 #include "rtl-iter.h"
10586
 
10587
+// #define     DO_ZIP_DEBUGS
10588
+#ifdef DO_ZIP_DEBUGS
10589
+#include <stdio.h>
10590
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
10591
+extern void zip_debug_rtx(const_rtx);
10592
+#else
10593
+#define        ZIP_DEBUG_LINE(STR,RTX)
10594
+#endif
10595
 /* Optimize jump y; x: ... y: jumpif... x?
10596
    Don't know if it is worth bothering with.  */
10597
 /* Optimize two cases of conditional jump to conditional jump?
10598
@@ -1136,6 +1144,7 @@
10599
   int i;
10600
   const char *fmt;
10601
 
10602
+ZIP_DEBUG_LINE("Mark jump label",insn);
10603
   switch (code)
10604
     {
10605
     case PC:
10606
@@ -1248,6 +1257,8 @@
10607
       break;
10608
     }
10609
 
10610
+ZIP_DEBUG_LINE("Post case",insn);
10611
+
10612
   fmt = GET_RTX_FORMAT (code);
10613
 
10614
   /* The primary target of a tablejump is the label of the ADDR_VEC,
10615 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
10616
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
10617 111 dgisselq
+++ gcc-5.3.0-zip/gcc/machmode.def      2016-03-08 11:56:45.375491523 -0500
10618 102 dgisselq
@@ -184,11 +184,11 @@
10619
    larger types, then corresponding modes must be added here.  The
10620
    name OI is reserved for a 256-bit type (needed by some back ends).
10621
     */
10622
-INT_MODE (QI, 1);
10623
-INT_MODE (HI, 2);
10624
-INT_MODE (SI, 4);
10625
-INT_MODE (DI, 8);
10626
-INT_MODE (TI, 16);
10627
+// INT_MODE (QI, 1);
10628
+// INT_MODE (HI, 1);
10629
+INT_MODE (SI, 1);
10630
+INT_MODE (DI, 2);
10631
+INT_MODE (TI, 4);
10632
 
10633
 /* No partial integer modes are defined by default.  */
10634
 
10635 111 dgisselq
@@ -206,35 +206,35 @@
10636 102 dgisselq
    These are the IEEE mappings.  They can be overridden with
10637
    RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE).  */
10638
 
10639
-FLOAT_MODE (SF, 4, ieee_single_format);
10640
-FLOAT_MODE (DF, 8, ieee_double_format);
10641
+FLOAT_MODE (SF, 1, ieee_single_format);
10642
+FLOAT_MODE (DF, 2, ieee_double_format);
10643
 
10644
 /* Basic CC modes.
10645
    FIXME define this only for targets that need it.  */
10646 111 dgisselq
 CC_MODE (CC);
10647 102 dgisselq
 
10648
 /* Fixed-point modes.  */
10649 111 dgisselq
-FRACT_MODE (QQ, 1, 7); /* s.7 */
10650 102 dgisselq
-FRACT_MODE (HQ, 2, 15); /* s.15 */
10651
-FRACT_MODE (SQ, 4, 31); /* s.31 */
10652
-FRACT_MODE (DQ, 8, 63); /* s.63 */
10653
-FRACT_MODE (TQ, 16, 127); /* s.127 */
10654 111 dgisselq
-
10655
-UFRACT_MODE (UQQ, 1, 8); /* .8 */
10656 102 dgisselq
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
10657
-UFRACT_MODE (USQ, 4, 32); /* .32 */
10658
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
10659
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
10660 111 dgisselq
-
10661
-ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
10662
-ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
10663
-ACCUM_MODE (DA, 8, 32, 31); /* s32.31 */
10664
-ACCUM_MODE (TA, 16, 64, 63); /* s64.63 */
10665
-
10666
-UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
10667
-UACCUM_MODE (USA, 4, 16, 16); /* 16.16 */
10668
-UACCUM_MODE (UDA, 8, 32, 32); /* 32.32 */
10669
-UACCUM_MODE (UTA, 16, 64, 64); /* 64.64 */
10670
+/* FRACT_MODE (QQ, 1, 7); /* s.7 */
10671
+/* FRACT_MODE (HQ, 1, 15); /* s.15 */
10672
+FRACT_MODE (SQ, 1, 31); /* s.31 */
10673
+FRACT_MODE (DQ, 2, 63); /* s.63 */
10674
+FRACT_MODE (TQ, 4, 127); /* s.127 */
10675
+
10676
+/* UFRACT_MODE (UQQ, 1, 8); /* .8 */
10677
+/* UFRACT_MODE (UHQ, 1, 16); /* .16 */
10678 102 dgisselq
+UFRACT_MODE (USQ, 1, 32); /* .32 */
10679
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
10680
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
10681 111 dgisselq
+
10682
+/* ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
10683
+ACCUM_MODE (SA, 1, 16, 15); /* s16.15 */
10684
+ACCUM_MODE (DA, 2, 32, 31); /* s32.31 */
10685
+ACCUM_MODE (TA, 4, 64, 63); /* s64.63 */
10686
+
10687
+/* UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
10688
+UACCUM_MODE (USA, 1, 16, 16); /* 16.16 */
10689
+UACCUM_MODE (UDA, 2, 32, 32); /* 32.32 */
10690
+UACCUM_MODE (UTA, 4, 64, 64); /* 64.64 */
10691 102 dgisselq
 
10692 111 dgisselq
 /* Allow the target to specify additional modes of various kinds.  */
10693
 #if HAVE_EXTRA_MODES
10694 102 dgisselq
@@ -246,9 +246,9 @@
10695
 COMPLEX_MODES (FLOAT);
10696
 
10697
 /* Decimal floating point modes.  */
10698
-DECIMAL_FLOAT_MODE (SD, 4, decimal_single_format);
10699
-DECIMAL_FLOAT_MODE (DD, 8, decimal_double_format);
10700
-DECIMAL_FLOAT_MODE (TD, 16, decimal_quad_format);
10701
+DECIMAL_FLOAT_MODE (SD, 1, decimal_single_format);
10702
+DECIMAL_FLOAT_MODE (DD, 2, decimal_double_format);
10703
+DECIMAL_FLOAT_MODE (TD, 4, decimal_quad_format);
10704
 
10705
 /* The symbol Pmode stands for one of the above machine modes (usually SImode).
10706
    The tm.h file specifies which one.  It is not a distinct mode.  */
10707
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.h gcc-5.3.0-zip/gcc/machmode.h
10708
--- gcc-5.3.0-original/gcc/machmode.h   2015-01-05 07:33:28.000000000 -0500
10709
+++ gcc-5.3.0-zip/gcc/machmode.h        2016-02-06 17:21:49.592924065 -0500
10710
@@ -180,13 +180,7 @@
10711
 /* Get the size in bytes and bits of an object of mode MODE.  */
10712
 
10713
 extern CONST_MODE_SIZE unsigned char mode_size[NUM_MACHINE_MODES];
10714
-#if GCC_VERSION >= 4001
10715
-#define GET_MODE_SIZE(MODE) \
10716
-  ((unsigned short) (__builtin_constant_p (MODE) \
10717
-                    ? mode_size_inline (MODE) : mode_size[MODE]))
10718
-#else
10719
 #define GET_MODE_SIZE(MODE)    ((unsigned short) mode_size[MODE])
10720
-#endif
10721
 #define GET_MODE_BITSIZE(MODE) \
10722
   ((unsigned short) (GET_MODE_SIZE (MODE) * BITS_PER_UNIT))
10723
 
10724
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/objc/objc-encoding.c gcc-5.3.0-zip/gcc/objc/objc-encoding.c
10725
--- gcc-5.3.0-original/gcc/objc/objc-encoding.c 2015-01-09 15:18:42.000000000 -0500
10726
+++ gcc-5.3.0-zip/gcc/objc/objc-encoding.c      2016-03-04 22:53:40.431902505 -0500
10727
@@ -765,10 +765,14 @@
10728
        {
10729
          switch (TYPE_MODE (type))
10730
            {
10731
+#ifdef HAVE_QImode
10732
            case QImode:
10733
              charType = 'C'; break;
10734
+#endif
10735
+#ifdef HAVE_HImode
10736
            case HImode:
10737
              charType = 'S'; break;
10738
+#endif
10739
            case SImode:
10740
              {
10741
                if (type == long_unsigned_type_node)
10742
@@ -788,10 +792,14 @@
10743
        {
10744
          switch (TYPE_MODE (type))
10745
            {
10746
+#ifdef HAVE_QImode
10747
            case QImode:
10748
              charType = 'c'; break;
10749
+#endif
10750
+#ifdef HAVE_HImode
10751
            case HImode:
10752
              charType = 's'; break;
10753
+#endif
10754
            case SImode:
10755
              {
10756
                if (type == long_integer_type_node)
10757
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
10758
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
10759 111 dgisselq
+++ gcc-5.3.0-zip/gcc/postreload.c      2016-03-24 21:30:23.402590035 -0400
10760
@@ -71,6 +71,14 @@
10761 102 dgisselq
 #include "df.h"
10762
 #include "dbgcnt.h"
10763
 
10764 111 dgisselq
+// #define     DO_ZIP_DEBUGS
10765 102 dgisselq
+#ifdef DO_ZIP_DEBUGS
10766
+extern void zip_debug_rtx(const_rtx);
10767
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
10768
+#else
10769
+#define        ZIP_DEBUG_LINE(STR,RTX)
10770
+#endif
10771
+
10772
 static int reload_cse_noop_set_p (rtx);
10773
 static bool reload_cse_simplify (rtx_insn *, rtx);
10774
 static void reload_cse_regs_1 (void);
10775 111 dgisselq
@@ -120,6 +128,8 @@
10776 102 dgisselq
   basic_block insn_bb = BLOCK_FOR_INSN (insn);
10777
   unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
10778
 
10779
+       ZIP_DEBUG_LINE("RELOAD-CSE-SIMPLIFY:",insn);
10780
+
10781
   if (GET_CODE (body) == SET)
10782
     {
10783
       int count = 0;
10784 111 dgisselq
@@ -147,6 +157,7 @@
10785 102 dgisselq
        apply_change_group ();
10786
       else
10787
        reload_cse_simplify_operands (insn, testreg);
10788
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
10789
     }
10790
   else if (GET_CODE (body) == PARALLEL)
10791
     {
10792 111 dgisselq
@@ -205,6 +216,7 @@
10793 102 dgisselq
        apply_change_group ();
10794
       else
10795
        reload_cse_simplify_operands (insn, testreg);
10796
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
10797
     }
10798
 
10799
 done:
10800 111 dgisselq
@@ -246,6 +258,7 @@
10801 102 dgisselq
          cfg_changed |= reload_cse_simplify (insn, testreg);
10802
 
10803
        cselib_process_insn (insn);
10804
+       ZIP_DEBUG_LINE("End-CSE-REGS-1:",insn);
10805
       }
10806
 
10807
   /* Clean up.  */
10808 111 dgisselq
@@ -276,6 +289,8 @@
10809 102 dgisselq
 #endif
10810
   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
10811
 
10812
+
10813
+       ZIP_DEBUG_LINE("RELOAD:Attempting to simplify set",set);
10814
   dreg = true_regnum (SET_DEST (set));
10815
   if (dreg < 0)
10816
     return 0;
10817 111 dgisselq
@@ -427,6 +442,7 @@
10818 102 dgisselq
   /* Array of alternatives, sorted in order of decreasing desirability.  */
10819
   int *alternative_order;
10820
 
10821
+       ZIP_DEBUG_LINE("Simplify-Operands", insn);
10822
   extract_constrain_insn (insn);
10823
 
10824
   if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
10825 111 dgisselq
@@ -519,6 +535,7 @@
10826 102 dgisselq
          SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
10827
     }
10828
 
10829
+       ZIP_DEBUG_LINE("Simplify-Operands - A", insn);
10830
   alternative_mask preferred = get_preferred_alternatives (insn);
10831
   for (i = 0; i < recog_data.n_operands; i++)
10832
     {
10833 111 dgisselq
@@ -617,6 +634,7 @@
10834 102 dgisselq
            }
10835
        }
10836
     }
10837
+       ZIP_DEBUG_LINE("Simplify-Operands - B", insn);
10838
 
10839
   /* Record all alternatives which are better or equal to the currently
10840
      matching one in the alternative_order array.  */
10841 111 dgisselq
@@ -666,6 +684,7 @@
10842 102 dgisselq
       validate_change (insn, recog_data.operand_loc[i],
10843
                       gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
10844
     }
10845
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
10846
 
10847
   for (i = recog_data.n_dups - 1; i >= 0; i--)
10848
     {
10849 111 dgisselq
@@ -679,6 +698,7 @@
10850 102 dgisselq
                       gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
10851
     }
10852
 
10853
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
10854
   return apply_change_group ();
10855
 }
10856
 
10857 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
10858
--- gcc-5.3.0-original/gcc/recog.c      2015-03-20 02:07:30.000000000 -0400
10859 127 dgisselq
+++ gcc-5.3.0-zip/gcc/recog.c   2016-04-14 23:19:07.630839483 -0400
10860 117 dgisselq
@@ -68,6 +68,15 @@
10861
 #include "df.h"
10862
 #include "insn-codes.h"
10863
 
10864
+// #define     DO_ZIP_DEBUGS
10865
+#ifdef DO_ZIP_DEBUGS
10866
+extern void    zip_debug_rtx(const_rtx);
10867
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
10868
+#else
10869
+#define        ZIP_DEBUG_LINE(STR,RTX)
10870
+#endif
10871
+
10872
+
10873
 #ifndef STACK_PUSH_CODE
10874
 #ifdef STACK_GROWS_DOWNWARD
10875
 #define STACK_PUSH_CODE PRE_DEC
10876 122 dgisselq
@@ -2283,6 +2292,7 @@
10877
   recog_data.n_dups = 0;
10878
   recog_data.is_asm = false;
10879
 
10880
+ZIP_DEBUG_LINE("Extract-insn", insn);
10881
   switch (GET_CODE (body))
10882
     {
10883
     case USE:
10884
@@ -3671,7 +3681,6 @@
10885 117 dgisselq
            break;
10886
 
10887
          /* The buffer filled to the current maximum, so try to match.  */
10888
-
10889
          pos = peep2_buf_position (peep2_current + peep2_current_count);
10890
          peep2_insn_data[pos].insn = PEEP2_EOB;
10891
          COPY_REG_SET (peep2_insn_data[pos].live_before, live);
10892 122 dgisselq
@@ -3704,6 +3713,7 @@
10893 117 dgisselq
     rebuild_jump_labels (get_insns ());
10894
   if (peep2_do_cleanup_cfg)
10895
     cleanup_cfg (CLEANUP_CFG_CHANGED);
10896
+
10897
 }
10898
 #endif /* HAVE_peephole2 */
10899
 
10900
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
10901
--- gcc-5.3.0-original/gcc/reload1.c    2015-01-15 08:28:42.000000000 -0500
10902 127 dgisselq
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-20 20:51:38.590252867 -0400
10903 117 dgisselq
@@ -72,6 +72,14 @@
10904
 #include "dumpfile.h"
10905
 #include "rtl-iter.h"
10906
 
10907
+// #define     DO_ZIP_DEBUGS
10908
+#ifdef DO_ZIP_DEBUGS
10909
+extern void    zip_debug_rtx(const_rtx);
10910
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
10911
+#else
10912
+#define        ZIP_DEBUG_LINE(STR,RTX)
10913
+#endif
10914
+
10915
 /* This file contains the reload pass of the compiler, which is
10916
    run after register allocation has been done.  It checks that
10917
    each insn is valid (operands required to be in registers really
10918 127 dgisselq
@@ -794,6 +802,20 @@
10919 117 dgisselq
   basic_block bb;
10920
   bool inserted;
10921
 
10922
+#ifdef DO_ZIP_DEBUGS
10923
+  {
10924 127 dgisselq
+       fprintf(stderr, "BEFORE-RELOAD\n");
10925 117 dgisselq
+       int     total_count = 0, current_count = 0;
10926
+       for (insn = first; insn; insn = NEXT_INSN (insn))
10927
+               total_count++;
10928
+       for (insn = first; insn; insn = NEXT_INSN (insn)) {
10929
+               fprintf(stderr, "B %3d/%3d", current_count++, total_count);
10930
+               zip_debug_rtx(insn);
10931
+       }
10932 127 dgisselq
+       fprintf(stderr, "BEFORE-RELOAD -- END OF INSTRUCTION LIST\n");
10933 117 dgisselq
+  }
10934
+#endif
10935
+
10936
   /* Make sure even insns with volatile mem refs are recognizable.  */
10937
   init_recog ();
10938
 
10939 127 dgisselq
@@ -1366,6 +1388,20 @@
10940 117 dgisselq
 
10941
   reload_completed = !failure;
10942
 
10943
+#ifdef DO_ZIP_DEBUGS
10944
+  {
10945 127 dgisselq
+       fprintf(stderr, "AFTER-RELOAD\n");
10946 117 dgisselq
+       int     total_count = 0, current_count = 0;
10947
+       for (insn = first; insn; insn = NEXT_INSN (insn))
10948
+               total_count++;
10949
+       for (insn = first; insn; insn = NEXT_INSN (insn)) {
10950
+               fprintf(stderr, "A %3d/%3d", current_count++, total_count);
10951
+               zip_debug_rtx(insn);
10952
+       }
10953 127 dgisselq
+       fprintf(stderr, "AFTER-RELOAD -- END OF INSTRUCTION LIST\n");
10954 117 dgisselq
+  }
10955
+#endif
10956
+
10957
   return need_dce;
10958
 }
10959
 
10960 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
10961
--- gcc-5.3.0-original/gcc/reload.c     2015-01-15 08:28:42.000000000 -0500
10962 122 dgisselq
+++ gcc-5.3.0-zip/gcc/reload.c  2016-04-06 17:49:33.418613170 -0400
10963
@@ -136,6 +136,15 @@
10964
 #include "target.h"
10965
 #include "ira.h"
10966
 
10967
+// #define     DO_ZIP_DEBUGS
10968
+#ifdef DO_ZIP_DEBUGS
10969
+extern void zip_debug_rtx(const_rtx);
10970
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
10971
+#else
10972
+#define        ZIP_DEBUG_LINE(STR,RTX)
10973
+#endif
10974
+
10975
+
10976
 /* True if X is a constant that can be forced into the constant pool.
10977
    MODE is the mode of the operand, or VOIDmode if not known.  */
10978
 #define CONST_POOL_OK_P(MODE, X)               \
10979
@@ -2700,6 +2709,8 @@
10980
   hard_regs_live_known = live_known;
10981
   static_reload_reg_p = reload_reg_p;
10982
 
10983
+ZIP_DEBUG_LINE("Find reloads\n", insn);
10984
+
10985
   /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
10986
      neither are insns that SET cc0.  Insns that use CC0 are not allowed
10987
      to have any input reloads.  */
10988
@@ -2707,8 +2718,17 @@
10989 102 dgisselq
     no_output_reloads = 1;
10990
 
10991
 #ifdef HAVE_cc0
10992
+  // If the instruction depends upon cc0, such as a branch, if_then_else, or
10993
+  // cond_exec instruction, we cannot change the input so that the instruction
10994
+  // relies on another register--cc0 is specific.  This requries that the
10995
+  // references be only cc0 and (const_int 0), rather than allowing other
10996
+  // registers here as well.
10997
   if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
10998
     no_input_reloads = 1;
10999
+  // If the result of an instruction is the cc0 register, that cannot
11000
+  // be changed, therefore no output reloading is allowed.  This only
11001
+  // works if instructions *only* set the cc0 register, and not multiple
11002
+  // registers.
11003
   if (reg_set_p (cc0_rtx, PATTERN (insn)))
11004
     no_output_reloads = 1;
11005
 #endif
11006
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp
11007
--- gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp    2015-11-26 05:10:58.000000000 -0500
11008
+++ gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp 2016-01-30 15:14:21.620586694 -0500
11009
@@ -503,6 +503,11 @@
11010
        return 0
11011
     }
11012
 
11013
+    # Zip CPU doesn't support profiling (yet)
11014
+    if { [istarget zip*] }
11015
+        return 0
11016
+    }
11017
+
11018
     # MinGW does not support -p.
11019
     if { [istarget *-*-mingw*] && $test_what == "-p" } {
11020
        return 0
11021
@@ -986,6 +991,12 @@
11022
        }]
11023
     }
11024
 
11025
+    # No real hardware FPU support for ZipCPU yet--even though the instruction
11026
+    # set supports it, the CPU just isn't ready yet.
11027
+    if { [istarget zip*-*-*] } {
11028
+        return 0
11029
+    }
11030
+
11031
     # This proc is actually checking the availabilty of FPU
11032
     # support for doubles, so on the RX we must fail if the
11033
     # 64-bit double multilib has been selected.
11034
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/tree-ssa-math-opts.c gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c
11035
--- gcc-5.3.0-original/gcc/tree-ssa-math-opts.c 2015-08-11 03:58:07.000000000 -0400
11036
+++ gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c      2016-02-12 11:21:11.309149239 -0500
11037
@@ -972,7 +972,7 @@
11038
     {
11039
       if (val & 1)
11040
        {
11041
-         digit = val & ((1 << POWI_WINDOW_SIZE) - 1);
11042
+         digit = val & ((1l << POWI_WINDOW_SIZE) - 1);
11043
          result += powi_lookup_cost (digit, cache)
11044
                    + POWI_WINDOW_SIZE + 1;
11045
          val >>= POWI_WINDOW_SIZE;
11046
@@ -1012,7 +1012,7 @@
11047
     }
11048
   else if (n & 1)
11049
     {
11050
-      digit = n & ((1 << POWI_WINDOW_SIZE) - 1);
11051
+      digit = n & ((1l << POWI_WINDOW_SIZE) - 1);
11052
       op0 = powi_as_mults_1 (gsi, loc, type, n - digit, cache);
11053
       op1 = powi_as_mults_1 (gsi, loc, type, digit, cache);
11054
     }
11055
@@ -1651,7 +1651,7 @@
11056
 };
11057
 
11058
 #define BITS_PER_MARKER 8
11059
-#define MARKER_MASK ((1 << BITS_PER_MARKER) - 1)
11060
+#define MARKER_MASK ((1l << BITS_PER_MARKER) - 1)
11061
 #define MARKER_BYTE_UNKNOWN MARKER_MASK
11062
 #define HEAD_MARKER(n, size) \
11063
   ((n) & ((uint64_t) MARKER_MASK << (((size) - 1) * BITS_PER_MARKER)))
11064
@@ -1687,7 +1687,7 @@
11065
   /* Zero out the extra bits of N in order to avoid them being shifted
11066
      into the significant bits.  */
11067
   if (size < 64 / BITS_PER_MARKER)
11068
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
11069
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
11070
 
11071
   switch (code)
11072
     {
11073
@@ -1714,7 +1714,7 @@
11074
     }
11075
   /* Zero unused bits for size.  */
11076
   if (size < 64 / BITS_PER_MARKER)
11077
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
11078
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
11079
   return true;
11080
 }
11081
 
11082
@@ -1761,7 +1761,7 @@
11083
   n->n = CMPNOP;
11084
 
11085
   if (size < 64 / BITS_PER_MARKER)
11086
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
11087
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
11088
 
11089
   return true;
11090
 }
11091
@@ -2020,7 +2020,7 @@
11092
          {
11093
            int i, size = TYPE_PRECISION (n->type) / BITS_PER_UNIT;
11094
            uint64_t val = int_cst_value (rhs2), mask = 0;
11095
-           uint64_t tmp = (1 << BITS_PER_UNIT) - 1;
11096
+           uint64_t tmp = (1l << BITS_PER_UNIT) - 1;
11097
 
11098
            /* Only constants masking full bytes are allowed.  */
11099
            for (i = 0; i < size; i++, tmp <<= BITS_PER_UNIT)
11100
@@ -2064,7 +2064,7 @@
11101
              {
11102
                /* If STMT casts to a smaller type mask out the bits not
11103
                   belonging to the target type.  */
11104
-               n->n &= ((uint64_t) 1 << (type_size * BITS_PER_MARKER)) - 1;
11105
+               n->n &= ((uint64_t) 1l << (type_size * BITS_PER_MARKER)) - 1;
11106
              }
11107
            n->type = type;
11108
            if (!n->base_addr)
11109
@@ -2177,7 +2177,7 @@
11110
     {
11111
       uint64_t mask;
11112
 
11113
-      mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;
11114
+      mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;
11115
       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
11116
       cmpnop &= mask;
11117
     }
11118
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
11119
--- gcc-5.3.0-original/gcc/var-tracking.c       2015-03-26 09:19:00.000000000 -0400
11120 117 dgisselq
+++ gcc-5.3.0-zip/gcc/var-tracking.c    2016-03-31 18:55:03.584197958 -0400
11121 102 dgisselq
@@ -143,6 +143,13 @@
11122
 #include "rtl-iter.h"
11123
 #include "fibonacci_heap.h"
11124
 
11125 117 dgisselq
+#ifdef DO_ZIP_DEBUGS
11126 102 dgisselq
+#include <stdio.h>
11127
+extern void zip_debug_rtx(const_rtx);
11128
+#define ZIP_DEBUG_LINE(STR,RTX) do {fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
11129
+#else
11130
+#define ZIP_DEBUG_LINE(STR,RTX)
11131
+#endif
11132
 typedef fibonacci_heap <long, basic_block_def> bb_heap_t;
11133
 typedef fibonacci_node <long, basic_block_def> bb_heap_node_t;
11134
 
11135
@@ -6356,6 +6363,7 @@
11136
                machine_mode indmode
11137
                  = TYPE_MODE (TREE_TYPE (argtype));
11138
                rtx mem = gen_rtx_MEM (indmode, x);
11139
+                       ZIP_DEBUG_LINE("Var-tracking mem-ref", mem);
11140
                cselib_val *val = cselib_lookup (mem, indmode, 0, VOIDmode);
11141
                if (val && cselib_preserved_value_p (val))
11142
                  {
11143
@@ -6462,12 +6470,14 @@
11144
       machine_mode mode
11145
        = TYPE_MODE (TREE_TYPE (OBJ_TYPE_REF_EXPR (obj_type_ref)));
11146
       rtx clobbered = gen_rtx_MEM (mode, this_arg);
11147
+                       ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered", clobbered);
11148
       HOST_WIDE_INT token
11149
        = tree_to_shwi (OBJ_TYPE_REF_TOKEN (obj_type_ref));
11150
       if (token)
11151
        clobbered = plus_constant (mode, clobbered,
11152
                                   token * GET_MODE_SIZE (mode));
11153
       clobbered = gen_rtx_MEM (mode, clobbered);
11154
+       ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered-2", clobbered);
11155
       x = gen_rtx_CONCAT (mode, gen_rtx_CLOBBER (VOIDmode, pc_rtx), clobbered);
11156
       call_arguments
11157
        = gen_rtx_EXPR_LIST (VOIDmode, x, call_arguments);
11158
@@ -9790,6 +9800,7 @@
11159
              machine_mode indmode
11160
                = TYPE_MODE (TREE_TYPE (TREE_TYPE (parm)));
11161
              rtx mem = gen_rtx_MEM (indmode, incoming);
11162
+       ZIP_DEBUG_LINE("Var-tracking mem-ref/incoming", incoming);
11163
              cselib_val *val = cselib_lookup_from_insn (mem, indmode, true,
11164
                                                         VOIDmode,
11165
                                                         get_insns ());
11166
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/config.host gcc-5.3.0-zip/libgcc/config.host
11167
--- gcc-5.3.0-original/libgcc/config.host       2015-10-01 08:01:18.000000000 -0400
11168
+++ gcc-5.3.0-zip/libgcc/config.host    2016-01-30 15:16:00.459883558 -0500
11169
@@ -195,6 +195,9 @@
11170
 tic6x-*-*)
11171
        cpu_type=c6x
11172
        ;;
11173
+zip*)
11174
+       cpu_type=zip
11175
+       ;;
11176
 esac
11177
 
11178
 # Common parts for widely ported systems.
11179
@@ -1300,6 +1303,9 @@
11180
        echo "*** Configuration ${host} not supported" 1>&2
11181
        exit 1
11182
        ;;
11183
+zip*)
11184
+       tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
11185
+       ;;
11186
 esac
11187
 
11188
 case ${host} in
11189
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgomp/configure.tgt gcc-5.3.0-zip/libgomp/configure.tgt
11190
--- gcc-5.3.0-original/libgomp/configure.tgt    2015-03-13 06:57:07.000000000 -0400
11191
+++ gcc-5.3.0-zip/libgomp/configure.tgt 2016-01-30 15:16:51.323521641 -0500
11192
@@ -150,6 +150,9 @@
11193
        # Need to link with -lpthread so libgomp.so is self-contained.
11194
        XLDFLAGS="${XLDFLAGS} -lpthread"
11195
        ;;
11196
+  zip*)
11197
+        config_path="bsd posix"
11198
+        ;;
11199
 
11200
   *)
11201
        ;;

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