1 |
202 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-6.2.0/config.sub gcc-6.2.0-zip/config.sub
|
2 |
|
|
--- gcc-6.2.0/config.sub 2015-12-31 16:13:28.000000000 -0500
|
3 |
|
|
+++ gcc-6.2.0-zip/config.sub 2017-01-11 11:07:21.116065311 -0500
|
4 |
|
|
@@ -355,6 +355,14 @@
|
5 |
|
|
xscaleel)
|
6 |
|
|
basic_machine=armel-unknown
|
7 |
102 |
dgisselq |
;;
|
8 |
202 |
dgisselq |
+ zip-*-linux*)
|
9 |
|
|
+ basic_machine=zip
|
10 |
|
|
+ os=-linux
|
11 |
|
|
+ ;;
|
12 |
|
|
+ zip*)
|
13 |
|
|
+ basic_machine=zip-unknown
|
14 |
|
|
+ os=-none
|
15 |
|
|
+ ;;
|
16 |
102 |
dgisselq |
|
17 |
202 |
dgisselq |
# We use `pc' rather than `unknown'
|
18 |
|
|
# because (1) that's what they normally are, and
|
19 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure gcc-6.2.0-zip/configure
|
20 |
|
|
--- gcc-6.2.0/configure 2016-03-17 18:54:19.000000000 -0400
|
21 |
|
|
+++ gcc-6.2.0-zip/configure 2017-02-06 21:54:22.244807700 -0500
|
22 |
|
|
@@ -3548,6 +3548,44 @@
|
23 |
|
|
ft32-*-*)
|
24 |
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
25 |
|
|
;;
|
26 |
|
|
+ zip*)
|
27 |
|
|
+ noconfigdirs="$noconfigdirs ${libgcj}"
|
28 |
|
|
+ noconfigdirs="$noconfigdirs target-boehm-gc"
|
29 |
|
|
+ noconfigdirs="$noconfigdirs target-libgfortran"
|
30 |
|
|
+ # noconfigdirs="$noconfigdirs target-libsanitizer"
|
31 |
|
|
+ # noconfigdirs="$noconfigdirs target-libada"
|
32 |
|
|
+ # noconfigdirs="$noconfigdirs target-libatomic"
|
33 |
|
|
+ # noconfigdirs="$noconfigdirs target-libcilkrts"
|
34 |
|
|
+ # noconfigdirs="$noconfigdirs target-libitm"
|
35 |
|
|
+ # noconfigdirs="$noconfigdirs target-libquadmath"
|
36 |
|
|
+ # noconfigdirs="$noconfigdirs target-libstdc++-v3"
|
37 |
|
|
+ # noconfigdirs="$noconfigdirs target-libssp"
|
38 |
|
|
+ # noconfigdirs="$noconfigdirs target-libgo"
|
39 |
|
|
+ # noconfigdirs="$noconfigdirs target-libgomp"
|
40 |
|
|
+ # noconfigdirs="$noconfigdirs target-libvtv"
|
41 |
|
|
+ # noconfigdirs="$noconfigdirs target-libobjc"
|
42 |
|
|
+ # target-libgcc
|
43 |
|
|
+ # target-liboffloadmic
|
44 |
|
|
+ # target-libmpx # Only gets enabled by request
|
45 |
|
|
+ # target-libbacktrace
|
46 |
|
|
+ # ${libgcj}
|
47 |
|
|
+ # target-boehm-gc
|
48 |
|
|
+ # target-libada
|
49 |
|
|
+ # target-libatomic
|
50 |
|
|
+ # target-libcilkrts
|
51 |
|
|
+ # target-libgfortran
|
52 |
|
|
+ # target-libgo
|
53 |
|
|
+ # target-libgomp
|
54 |
|
|
+ # target-libitm
|
55 |
|
|
+ # target-libobjc
|
56 |
|
|
+ # target-libquadmath
|
57 |
|
|
+ # target-libsanitizer
|
58 |
|
|
+ # target-libstdc++-v3
|
59 |
|
|
+ # target-libssp
|
60 |
|
|
+ # target-libvtv
|
61 |
|
|
+ # target-libgloss
|
62 |
|
|
+ # target-newlib
|
63 |
|
|
+ ;;
|
64 |
|
|
*-*-lynxos*)
|
65 |
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
66 |
|
|
;;
|
67 |
|
|
@@ -3575,6 +3613,9 @@
|
68 |
|
|
*-*-aix*)
|
69 |
|
|
noconfigdirs="$noconfigdirs target-libgo"
|
70 |
|
|
;;
|
71 |
|
|
+ zip*)
|
72 |
|
|
+ noconfigdirs="$noconfigdirs target-libgo"
|
73 |
|
|
+ ;;
|
74 |
|
|
esac
|
75 |
|
|
fi
|
76 |
|
|
|
77 |
|
|
@@ -3971,6 +4012,9 @@
|
78 |
102 |
dgisselq |
vax-*-*)
|
79 |
|
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
80 |
|
|
;;
|
81 |
|
|
+ zip*)
|
82 |
|
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
|
83 |
202 |
dgisselq |
+ ;;
|
84 |
102 |
dgisselq |
esac
|
85 |
|
|
|
86 |
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
87 |
202 |
dgisselq |
@@ -6785,16 +6829,16 @@
|
88 |
|
|
# CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
|
89 |
|
|
if test "x$CFLAGS_FOR_TARGET" = x; then
|
90 |
|
|
if test "x${is_cross_compiler}" = xyes; then
|
91 |
|
|
- CFLAGS_FOR_TARGET="-g -O2"
|
92 |
|
|
+ CFLAGS_FOR_TARGET="-O3"
|
93 |
|
|
else
|
94 |
|
|
CFLAGS_FOR_TARGET=$CFLAGS
|
95 |
|
|
case " $CFLAGS " in
|
96 |
|
|
- *" -O2 "*) ;;
|
97 |
|
|
- *) CFLAGS_FOR_TARGET="-O2 $CFLAGS_FOR_TARGET" ;;
|
98 |
|
|
+ *" -O3 "*) ;;
|
99 |
|
|
+ *) CFLAGS_FOR_TARGET="-O3 $CFLAGS_FOR_TARGET" ;;
|
100 |
|
|
esac
|
101 |
|
|
case " $CFLAGS " in
|
102 |
|
|
*" -g "* | *" -g3 "*) ;;
|
103 |
|
|
- *) CFLAGS_FOR_TARGET="-g $CFLAGS_FOR_TARGET" ;;
|
104 |
|
|
+ *) CFLAGS_FOR_TARGET="$CFLAGS_FOR_TARGET" ;;
|
105 |
|
|
esac
|
106 |
|
|
fi
|
107 |
|
|
fi
|
108 |
|
|
@@ -6802,16 +6846,16 @@
|
109 |
|
|
|
110 |
|
|
if test "x$CXXFLAGS_FOR_TARGET" = x; then
|
111 |
|
|
if test "x${is_cross_compiler}" = xyes; then
|
112 |
|
|
- CXXFLAGS_FOR_TARGET="-g -O2"
|
113 |
|
|
+ CXXFLAGS_FOR_TARGET="-O3"
|
114 |
|
|
else
|
115 |
|
|
CXXFLAGS_FOR_TARGET=$CXXFLAGS
|
116 |
|
|
case " $CXXFLAGS " in
|
117 |
|
|
- *" -O2 "*) ;;
|
118 |
|
|
- *) CXXFLAGS_FOR_TARGET="-O2 $CXXFLAGS_FOR_TARGET" ;;
|
119 |
|
|
+ *" -O3 "*) ;;
|
120 |
|
|
+ *) CXXFLAGS_FOR_TARGET="-O3 $CXXFLAGS_FOR_TARGET" ;;
|
121 |
|
|
esac
|
122 |
|
|
case " $CXXFLAGS " in
|
123 |
|
|
*" -g "* | *" -g3 "*) ;;
|
124 |
|
|
- *) CXXFLAGS_FOR_TARGET="-g $CXXFLAGS_FOR_TARGET" ;;
|
125 |
|
|
+ *) CXXFLAGS_FOR_TARGET="$CXXFLAGS_FOR_TARGET" ;;
|
126 |
|
|
esac
|
127 |
|
|
fi
|
128 |
|
|
fi
|
129 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure.ac gcc-6.2.0-zip/configure.ac
|
130 |
|
|
--- gcc-6.2.0/configure.ac 2016-03-17 18:54:19.000000000 -0400
|
131 |
|
|
+++ gcc-6.2.0-zip/configure.ac 2017-01-10 12:43:23.819301273 -0500
|
132 |
|
|
@@ -884,6 +884,9 @@
|
133 |
|
|
ft32-*-*)
|
134 |
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
135 |
|
|
;;
|
136 |
|
|
+ zip*)
|
137 |
|
|
+ noconfigdirs="$noconfigdirs ${libgcj}"
|
138 |
|
|
+ ;;
|
139 |
|
|
*-*-lynxos*)
|
140 |
|
|
noconfigdirs="$noconfigdirs ${libgcj}"
|
141 |
|
|
;;
|
142 |
|
|
@@ -911,6 +914,9 @@
|
143 |
|
|
*-*-aix*)
|
144 |
|
|
noconfigdirs="$noconfigdirs target-libgo"
|
145 |
|
|
;;
|
146 |
|
|
+ zip*)
|
147 |
|
|
+ noconfigdirs="$noconfigdirs target-libgo"
|
148 |
|
|
+ ;;
|
149 |
|
|
esac
|
150 |
|
|
fi
|
151 |
|
|
|
152 |
|
|
@@ -1307,6 +1313,10 @@
|
153 |
102 |
dgisselq |
vax-*-*)
|
154 |
|
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
155 |
|
|
;;
|
156 |
|
|
+ zip*)
|
157 |
202 |
dgisselq |
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof ${libgcj}"
|
158 |
|
|
+ unsupported_languages="$unsupported_languages fortran"
|
159 |
102 |
dgisselq |
+ ;;
|
160 |
|
|
esac
|
161 |
|
|
|
162 |
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
163 |
202 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c
|
164 |
|
|
--- gcc-6.2.0/gcc/cfgexpand.c 2016-04-27 08:23:50.000000000 -0400
|
165 |
|
|
+++ gcc-6.2.0-zip/gcc/cfgexpand.c 2016-12-31 16:38:36.195534819 -0500
|
166 |
|
|
@@ -74,6 +74,15 @@
|
167 |
117 |
dgisselq |
#include "tree-chkp.h"
|
168 |
|
|
#include "rtl-chkp.h"
|
169 |
|
|
|
170 |
202 |
dgisselq |
+
|
171 |
117 |
dgisselq |
+#ifdef DO_ZIP_DEBUGS
|
172 |
|
|
+#include <stdio.h>
|
173 |
202 |
dgisselq |
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
174 |
117 |
dgisselq |
+extern void zip_debug_rtx(const_rtx);
|
175 |
|
|
+#else
|
176 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
177 |
|
|
+#endif
|
178 |
|
|
+
|
179 |
|
|
/* Some systems use __main in a way incompatible with its use in gcc, in these
|
180 |
|
|
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
|
181 |
|
|
give the same symbol without quotes for an alternative entry point. You
|
182 |
202 |
dgisselq |
@@ -1172,7 +1181,7 @@
|
183 |
|
|
base_align = crtl->max_used_stack_slot_alignment;
|
184 |
|
|
else
|
185 |
|
|
base_align = MAX (crtl->max_used_stack_slot_alignment,
|
186 |
|
|
- GET_MODE_ALIGNMENT (SImode)
|
187 |
|
|
+ GET_MODE_ALIGNMENT (word_mode)
|
188 |
|
|
<< ASAN_SHADOW_SHIFT);
|
189 |
|
|
}
|
190 |
|
|
else
|
191 |
|
|
@@ -2225,7 +2234,7 @@
|
192 |
|
|
data.asan_vec.safe_push (offset);
|
193 |
|
|
/* Leave space for alignment if STRICT_ALIGNMENT. */
|
194 |
|
|
if (STRICT_ALIGNMENT)
|
195 |
|
|
- alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)
|
196 |
|
|
+ alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)
|
197 |
|
|
<< ASAN_SHADOW_SHIFT)
|
198 |
|
|
/ BITS_PER_UNIT, 1);
|
199 |
111 |
dgisselq |
|
200 |
202 |
dgisselq |
@@ -5745,7 +5754,7 @@
|
201 |
|
|
&& (last = get_last_insn ())
|
202 |
|
|
&& JUMP_P (last))
|
203 |
|
|
{
|
204 |
|
|
- rtx dummy = gen_reg_rtx (SImode);
|
205 |
|
|
+ rtx dummy = gen_reg_rtx (word_mode);
|
206 |
|
|
emit_insn_after_noloc (gen_move_insn (dummy, dummy), last, NULL);
|
207 |
|
|
}
|
208 |
|
|
|
209 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cgraphbuild.c gcc-6.2.0-zip/gcc/cgraphbuild.c
|
210 |
|
|
--- gcc-6.2.0/gcc/cgraphbuild.c 2016-01-04 09:30:50.000000000 -0500
|
211 |
|
|
+++ gcc-6.2.0-zip/gcc/cgraphbuild.c 2016-12-31 16:39:44.963107994 -0500
|
212 |
|
|
@@ -32,6 +32,15 @@
|
213 |
|
|
#include "ipa-utils.h"
|
214 |
|
|
#include "except.h"
|
215 |
|
|
|
216 |
|
|
+
|
217 |
111 |
dgisselq |
+#ifdef DO_ZIP_DEBUGS
|
218 |
202 |
dgisselq |
+#include <stdio.h>
|
219 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
220 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
221 |
111 |
dgisselq |
+#else
|
222 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
223 |
|
|
+#endif
|
224 |
|
|
+
|
225 |
|
|
/* Context of record_reference. */
|
226 |
|
|
struct record_reference_ctx
|
227 |
|
|
{
|
228 |
202 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/combine.c gcc-6.2.0-zip/gcc/combine.c
|
229 |
|
|
--- gcc-6.2.0/gcc/combine.c 2016-08-08 06:06:15.000000000 -0400
|
230 |
|
|
+++ gcc-6.2.0-zip/gcc/combine.c 2017-02-03 09:25:19.676720321 -0500
|
231 |
|
|
@@ -103,6 +103,15 @@
|
232 |
|
|
#include "rtl-iter.h"
|
233 |
|
|
#include "print-rtl.h"
|
234 |
|
|
|
235 |
|
|
+#define DO_ZIP_DEBUGS
|
236 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
237 |
|
|
+#include <stdio.h>
|
238 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
239 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
240 |
|
|
+#else
|
241 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
242 |
|
|
+#endif
|
243 |
|
|
+
|
244 |
|
|
#ifndef LOAD_EXTEND_OP
|
245 |
|
|
#define LOAD_EXTEND_OP(M) UNKNOWN
|
246 |
|
|
#endif
|
247 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/common/config/zip/zip-common.c gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c
|
248 |
|
|
--- gcc-6.2.0/gcc/common/config/zip/zip-common.c 1969-12-31 19:00:00.000000000 -0500
|
249 |
|
|
+++ gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c 2017-01-11 09:41:34.483106099 -0500
|
250 |
102 |
dgisselq |
@@ -0,0 +1,52 @@
|
251 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
252 |
|
|
+//
|
253 |
|
|
+// Filename: common/config/zip/zip-common.c
|
254 |
|
|
+//
|
255 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
256 |
|
|
+//
|
257 |
|
|
+// Purpose: To eliminate the frame register automatically.
|
258 |
|
|
+//
|
259 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
260 |
|
|
+// Gisselquist Technology, LLC
|
261 |
|
|
+//
|
262 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
263 |
|
|
+//
|
264 |
202 |
dgisselq |
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
265 |
102 |
dgisselq |
+//
|
266 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
267 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
268 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
269 |
|
|
+// your option) any later version.
|
270 |
|
|
+//
|
271 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
272 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
273 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
274 |
|
|
+// for more details.
|
275 |
|
|
+//
|
276 |
|
|
+// You should have received a copy of the GNU General Public License along
|
277 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
278 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
279 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
280 |
|
|
+//
|
281 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
282 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
283 |
|
|
+//
|
284 |
|
|
+//
|
285 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
286 |
|
|
+#include "config.h"
|
287 |
|
|
+#include "system.h"
|
288 |
|
|
+#include "coretypes.h"
|
289 |
|
|
+#include "tm.h"
|
290 |
|
|
+#include "common/common-target.h"
|
291 |
|
|
+#include "common/common-target-def.h"
|
292 |
|
|
+
|
293 |
|
|
+static const struct default_options zip_option_optimization_table[] =
|
294 |
|
|
+ {
|
295 |
|
|
+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
|
296 |
|
|
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
|
297 |
|
|
+ };
|
298 |
|
|
+
|
299 |
|
|
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
300 |
|
|
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
|
301 |
|
|
+
|
302 |
|
|
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
303 |
202 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c
|
304 |
|
|
--- gcc-6.2.0/gcc/config/zip/genzipops.c 1969-12-31 19:00:00.000000000 -0500
|
305 |
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c 2017-03-07 12:03:59.062584503 -0500
|
306 |
|
|
@@ -0,0 +1,444 @@
|
307 |
102 |
dgisselq |
+////////////////////////////////////////////////////////////////////////////////
|
308 |
|
|
+//
|
309 |
202 |
dgisselq |
+// Filename: genzipops.c
|
310 |
102 |
dgisselq |
+//
|
311 |
202 |
dgisselq |
+// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
312 |
102 |
dgisselq |
+//
|
313 |
202 |
dgisselq |
+// Purpose: This program generates the zip-ops.md machine description file.
|
314 |
102 |
dgisselq |
+//
|
315 |
202 |
dgisselq |
+// While I understand that this is not GCC's preferred method of generating
|
316 |
|
|
+// machine description files, there were just so many instructions to
|
317 |
|
|
+// generate, and so many forms of them, and the GCC infrastructure didn't
|
318 |
|
|
+// support the conditional execution model of the ZipCPU that ... I built
|
319 |
|
|
+// it this way.
|
320 |
|
|
+//
|
321 |
|
|
+// As of this writing, building zip-ops.md is not an automatic part of
|
322 |
|
|
+// making GCC. To build genzipops, just type:
|
323 |
|
|
+//
|
324 |
|
|
+// g++ genzipops.c -o genzipops
|
325 |
|
|
+//
|
326 |
|
|
+// And to run it, type:
|
327 |
|
|
+//
|
328 |
|
|
+// genzipops > zip-ops.md
|
329 |
|
|
+//
|
330 |
|
|
+// genzipops takes no arguments, and does nothing but write the machine
|
331 |
|
|
+// descriptions to the standard output.
|
332 |
|
|
+//
|
333 |
|
|
+//
|
334 |
102 |
dgisselq |
+// Creator: Dan Gisselquist, Ph.D.
|
335 |
|
|
+// Gisselquist Technology, LLC
|
336 |
|
|
+//
|
337 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
338 |
|
|
+//
|
339 |
202 |
dgisselq |
+// Copyright (C) 2017, Gisselquist Technology, LLC
|
340 |
102 |
dgisselq |
+//
|
341 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
342 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
343 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
344 |
|
|
+// your option) any later version.
|
345 |
|
|
+//
|
346 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
347 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
348 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
349 |
|
|
+// for more details.
|
350 |
|
|
+//
|
351 |
|
|
+// You should have received a copy of the GNU General Public License along
|
352 |
202 |
dgisselq |
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
353 |
102 |
dgisselq |
+// target there if the PDF file isn't present.) If not, see
|
354 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
355 |
|
|
+//
|
356 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
357 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
358 |
|
|
+//
|
359 |
|
|
+//
|
360 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
361 |
202 |
dgisselq |
+//
|
362 |
|
|
+//
|
363 |
|
|
+#include <unistd.h>
|
364 |
|
|
+#include <stdlib.h>
|
365 |
|
|
+#include <stdio.h>
|
366 |
|
|
+#include <string.h>
|
367 |
102 |
dgisselq |
+
|
368 |
202 |
dgisselq |
+void legal(FILE *fp) {
|
369 |
|
|
+ fprintf(fp, ""
|
370 |
|
|
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
371 |
|
|
+";;\n"
|
372 |
|
|
+";; Filename: zip-ops.md\n"
|
373 |
|
|
+";;\n"
|
374 |
|
|
+";; Project: Zip CPU -- a small, lightweight, RISC CPU soft core\n"
|
375 |
|
|
+";;\n"
|
376 |
|
|
+";; Purpose: This is a computer generated machine description of the\n"
|
377 |
|
|
+";; ZipCPU\'s operations. It is computer generated simply for\n"
|
378 |
|
|
+";; two reasons. First, I can\'t seem to find a way to generate this\n"
|
379 |
|
|
+";; information within GCC\'s current constructs. Specifically, the\n"
|
380 |
|
|
+";; CPU\'s instructions normally set the condition codes, unless they\n"
|
381 |
|
|
+";; are conditional instructions when they don\'t. Second, the ZipCPU is\n"
|
382 |
|
|
+";; actually quite regular. Almost all of the instructions have the same\n"
|
383 |
|
|
+";; form. This form turns into many, many RTL instructions. Because the\n"
|
384 |
|
|
+";; CPU doesn\'t match any of the others within GCC, that means either\n"
|
385 |
|
|
+";; I have a *lot* of cut, copy, paste, and edit to do to create the file\n"
|
386 |
|
|
+";; and upon any and every edit, or I need to build a program to generate\n"
|
387 |
|
|
+";; the remaining .md constructs. Hence, I chose the latter to minimize\n"
|
388 |
|
|
+";; the amount of work I needed to do.\n"
|
389 |
|
|
+";;\n"
|
390 |
|
|
+";;\n"
|
391 |
|
|
+";; Creator: Dan Gisselquist, Ph.D.\n"
|
392 |
|
|
+";; Gisselquist Technology, LLC\n"
|
393 |
|
|
+";;\n"
|
394 |
|
|
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
395 |
|
|
+";;\n"
|
396 |
|
|
+";; Copyright (C) 2017, Gisselquist Technology, LLC\n"
|
397 |
|
|
+";;\n"
|
398 |
|
|
+";; This program is free software (firmware): you can redistribute it and/or\n"
|
399 |
|
|
+";; modify it under the terms of the GNU General Public License as published\n"
|
400 |
|
|
+";; by the Free Software Foundation, either version 3 of the License, or (at\n"
|
401 |
|
|
+";; your option) any later version.\n"
|
402 |
|
|
+";;\n"
|
403 |
|
|
+";; This program is distributed in the hope that it will be useful, but WITHOUT\n"
|
404 |
|
|
+";; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
|
405 |
|
|
+";; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\n"
|
406 |
|
|
+";; for more details.\n"
|
407 |
|
|
+";;\n"
|
408 |
|
|
+";; License: GPL, v3, as defined and found on www.gnu.org,\n"
|
409 |
|
|
+";; http://www.gnu.org/licenses/gpl.html\n"
|
410 |
|
|
+";;\n"
|
411 |
|
|
+";;\n"
|
412 |
|
|
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
|
413 |
|
|
+";;\n"
|
414 |
|
|
+";;\n");
|
415 |
|
|
+}
|
416 |
102 |
dgisselq |
+
|
417 |
202 |
dgisselq |
+void gen_heading(FILE *fp, const char *heading) {
|
418 |
|
|
+ fprintf(fp, ";\n;\n; %s\n;\n;\n", heading);
|
419 |
|
|
+}
|
420 |
102 |
dgisselq |
+
|
421 |
202 |
dgisselq |
+void genzip_condop(FILE *fp, const char *md_opname,
|
422 |
|
|
+ const char *rtxstr, const char *insn_cond,
|
423 |
|
|
+ const char *zip_op,
|
424 |
|
|
+ const char *rtx_cond, const char *zip_cond) {
|
425 |
102 |
dgisselq |
+
|
426 |
202 |
dgisselq |
+ fprintf(fp, "(define_insn \"%s_%s\"\n"
|
427 |
|
|
+ "\t[(cond_exec (%s (reg:CC CC_REG) (const_int 0))\n"
|
428 |
|
|
+ "\t\t\t%s)]\n"
|
429 |
|
|
+ "\t\"%s\"\t; Condition\n"
|
430 |
|
|
+ "\t\"%s.%s\\t%%1,%%0\t; genzip, conditional operator\"\t; Template\n"
|
431 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") "
|
432 |
|
|
+ "(set_attr \"ccresult\" \"unchanged\")])\n;\n;\n",
|
433 |
|
|
+ md_opname, rtx_cond, rtx_cond, rtxstr, insn_cond, zip_op, zip_cond);
|
434 |
102 |
dgisselq |
+
|
435 |
202 |
dgisselq |
+}
|
436 |
102 |
dgisselq |
+
|
437 |
202 |
dgisselq |
+void genzipop_long(FILE *fp, const char *md_opname, const char *uncond_rtx, const char *insn_cond, const char *split_rtx, const char *dup_rtx, const char *zip_op) {
|
438 |
|
|
+ char heading[128];
|
439 |
|
|
+ sprintf(heading, "%s (genzipop_long)", zip_op);
|
440 |
|
|
+ fprintf(fp, ";\n;\n;\n; %s (genzipop_long)\n;\n;\n;\n", zip_op);
|
441 |
102 |
dgisselq |
+
|
442 |
202 |
dgisselq |
+ fprintf(fp, "(define_insn \"%s\"\n"
|
443 |
|
|
+"\t[%s\n"
|
444 |
|
|
+"\t(clobber (reg:CC CC_REG))]\n"
|
445 |
|
|
+"\t\"%s\"\n"
|
446 |
|
|
+"\t\"%s\\t%%2,%%0\t; %s\"\n"
|
447 |
|
|
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
|
448 |
|
|
+ md_opname, uncond_rtx, insn_cond, zip_op, md_opname);
|
449 |
102 |
dgisselq |
+
|
450 |
|
|
+
|
451 |
202 |
dgisselq |
+ fprintf(fp, "(define_insn \"%s_raw\"\n"
|
452 |
|
|
+"\t[%s\n"
|
453 |
|
|
+"\t(set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]\n"
|
454 |
|
|
+"\t\"%s\"\n"
|
455 |
|
|
+"\t\"%s\\t%%1,%%0\t; %s_raw\"\n"
|
456 |
|
|
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
|
457 |
|
|
+ md_opname, dup_rtx, insn_cond, zip_op, md_opname);
|
458 |
102 |
dgisselq |
+
|
459 |
202 |
dgisselq |
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "eq", "Z");
|
460 |
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ne", "NZ");
|
461 |
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "lt", "LT");
|
462 |
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ge", "GE");
|
463 |
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ltu", "C");
|
464 |
|
|
+ genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "geu", "NC");
|
465 |
|
|
+}
|
466 |
102 |
dgisselq |
+
|
467 |
202 |
dgisselq |
+void genzipop(FILE *fp, const char *md_opname, const char *rtx_name, const char *insn_cond, const char *zip_op) {
|
468 |
|
|
+ char rtxstr[512], splitstr[512], dupstr[512], altname[64];
|
469 |
102 |
dgisselq |
+
|
470 |
202 |
dgisselq |
+ sprintf(rtxstr,
|
471 |
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
472 |
|
|
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
|
473 |
|
|
+"\t\t\t(match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
|
474 |
|
|
+ sprintf(splitstr,
|
475 |
|
|
+ "(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))", rtx_name);
|
476 |
102 |
dgisselq |
+
|
477 |
202 |
dgisselq |
+ sprintf(dupstr,
|
478 |
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
479 |
|
|
+"\t\t(%s (match_dup 0)\n"
|
480 |
|
|
+"\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
|
481 |
102 |
dgisselq |
+
|
482 |
202 |
dgisselq |
+ genzipop_long(fp, md_opname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
|
483 |
171 |
dgisselq |
+
|
484 |
202 |
dgisselq |
+ sprintf(rtxstr,
|
485 |
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
486 |
|
|
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
|
487 |
|
|
+"\t\t\t(plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n"
|
488 |
|
|
+"\t\t\t\t(match_operand:SI 3 \"const_int_operand\" \"N\"))))", rtx_name);
|
489 |
|
|
+ sprintf(splitstr,
|
490 |
|
|
+ "(set (match_dup 0) (%s (match_dup 0)\n"
|
491 |
|
|
+"\t\t\t(plus:SI (match_dup 2) (match_dup 3))))", rtx_name);
|
492 |
171 |
dgisselq |
+
|
493 |
202 |
dgisselq |
+ sprintf(dupstr,
|
494 |
|
|
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
495 |
|
|
+"\t\t(%s (match_dup 0)\n"
|
496 |
|
|
+"\t\t\t(plus:SI (match_operand:SI 1 \"register_operand\" \"r\")\n"
|
497 |
|
|
+"\t\t\t\t(match_operand:SI 2 \"const_int_operand\" \"N\"))))", rtx_name);
|
498 |
102 |
dgisselq |
+
|
499 |
202 |
dgisselq |
+ sprintf(altname, "%s_off", md_opname);
|
500 |
102 |
dgisselq |
+
|
501 |
202 |
dgisselq |
+ genzipop_long(fp, altname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
|
502 |
|
|
+}
|
503 |
102 |
dgisselq |
+
|
504 |
202 |
dgisselq |
+void gencmov(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
505 |
|
|
+ fprintf(fp, ";\n;\n"
|
506 |
|
|
+"(define_insn \"%s_%s\"\n"
|
507 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,Q\")\n"
|
508 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
509 |
|
|
+ "\t\t\t(match_operand:SI 1 \"general_operand\" \"r,Q,i,r\")\n"
|
510 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
511 |
|
|
+ "\t\"\"\n"
|
512 |
|
|
+ "\t\"@\n"
|
513 |
|
|
+ "\tMOV.%s\t%%1,%%0\t; cmov\n"
|
514 |
|
|
+ "\tLW.%s\t%%1,%%0\t; cmov\n"
|
515 |
|
|
+ "\tLDI.%s\t%%1,%%0\t; cmov\n"
|
516 |
|
|
+ "\tSW.%s\t%%1,%%0\t; cmov\"\n"
|
517 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
518 |
|
|
+ md_opname, md_cond, md_cond, zip_cond, zip_cond, zip_cond, zip_cond);
|
519 |
102 |
dgisselq |
+
|
520 |
202 |
dgisselq |
+}
|
521 |
|
|
+
|
522 |
|
|
+void gencadd(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
523 |
|
|
+ fprintf(fp, ";\n;\n"
|
524 |
|
|
+"(define_insn \"%s_%s\"\n"
|
525 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
526 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
527 |
|
|
+ "\t\t\t(plus:SI (match_dup 0)\n"
|
528 |
|
|
+ "\t\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
529 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
530 |
|
|
+ "\t\"\"\n"
|
531 |
|
|
+ "\t\"ADD.%s\t%%1,%%0\t; cadd\"\n"
|
532 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
533 |
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
534 |
|
|
+}
|
535 |
|
|
+
|
536 |
|
|
+void gencnot(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
537 |
|
|
+ fprintf(fp, ";\n;\n"
|
538 |
|
|
+"(define_insn \"%s_%s\"\n"
|
539 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
540 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
541 |
|
|
+ "\t\t\t(xor:SI (match_dup 0)\n"
|
542 |
|
|
+ "\t\t\t\t(const_int -1))\n"
|
543 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
544 |
|
|
+ "\t\"\"\n"
|
545 |
|
|
+ "\t\"NOT.%s\t%%0\t; cnot\"\n"
|
546 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
547 |
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
548 |
|
|
+}
|
549 |
|
|
+
|
550 |
|
|
+void gencneg(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
551 |
|
|
+ fprintf(fp, ";\n;\n"
|
552 |
|
|
+"(define_insn \"%s_%s\"\n"
|
553 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
554 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
555 |
|
|
+ "\t\t\t(neg:SI (match_dup 0))\n"
|
556 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
557 |
|
|
+ "\t\"\"\n"
|
558 |
|
|
+ "\t\"NEG.%s\t%%0\t; cneg\"\n"
|
559 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
560 |
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
561 |
|
|
+}
|
562 |
|
|
+
|
563 |
|
|
+
|
564 |
|
|
+void gencand(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
565 |
|
|
+ fprintf(fp, ";\n;\n"
|
566 |
|
|
+"(define_insn \"%s_%s\"\n"
|
567 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
568 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
569 |
|
|
+ "\t\t\t(and:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
570 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
571 |
|
|
+ "\t\"\"\n"
|
572 |
|
|
+ "\t\"AND.%s\t%%1,%%0\t; cand\"\n"
|
573 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
574 |
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
575 |
|
|
+}
|
576 |
|
|
+
|
577 |
|
|
+
|
578 |
|
|
+void gencior(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
579 |
|
|
+ fprintf(fp, ";\n;\n"
|
580 |
|
|
+"(define_insn \"%s_%s\"\n"
|
581 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
582 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
583 |
|
|
+ "\t\t\t(ior:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
584 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
585 |
|
|
+ "\t\"\"\n"
|
586 |
|
|
+ "\t\"OR.%s\t%%1,%%0\t; cior\"\n"
|
587 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
588 |
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
589 |
|
|
+}
|
590 |
|
|
+
|
591 |
|
|
+void gencxor(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
|
592 |
|
|
+ fprintf(fp, ";\n;\n"
|
593 |
|
|
+"(define_insn \"%s_%s\"\n"
|
594 |
|
|
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
|
595 |
|
|
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
|
596 |
|
|
+ "\t\t\t(xor:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
|
597 |
|
|
+ "\t\t\t(match_dup 0)))]\n"
|
598 |
|
|
+ "\t\"\"\n"
|
599 |
|
|
+ "\t\"XOR.%s\t%%1,%%0\t; cxor\"\n"
|
600 |
|
|
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
|
601 |
|
|
+ md_opname, md_cond, md_cond, zip_cond);
|
602 |
|
|
+}
|
603 |
|
|
+
|
604 |
|
|
+void usage(void) {
|
605 |
|
|
+ printf("USAGE: genzipops <new-zip-ops.md filename>\n");
|
606 |
|
|
+}
|
607 |
|
|
+
|
608 |
|
|
+const char *TMPPATH = ".zip-ops.md";
|
609 |
|
|
+const char *TAILPATH = "zip-ops.md";
|
610 |
|
|
+
|
611 |
|
|
+int main(int argc, char **argv) {
|
612 |
|
|
+ FILE *fp = fopen(TMPPATH, "w");
|
613 |
|
|
+ const char *newname = TAILPATH;
|
614 |
|
|
+
|
615 |
|
|
+ if ((argc>1)&&(argv[1][0] == '-')) {
|
616 |
|
|
+ usage();
|
617 |
|
|
+ exit(EXIT_FAILURE);
|
618 |
|
|
+ }
|
619 |
|
|
+
|
620 |
|
|
+ if (argc>1) {
|
621 |
|
|
+ if ((strlen(argv[1])>=strlen(TAILPATH))
|
622 |
|
|
+ &&(strcmp(&argv[1][strlen(argv[1])-strlen(TAILPATH)],
|
623 |
|
|
+ TAILPATH)==0)
|
624 |
|
|
+ &&(access(argv[1], F_OK)==0))
|
625 |
|
|
+ unlink(argv[1]);
|
626 |
|
|
+ newname = argv[1];
|
627 |
|
|
+ }
|
628 |
|
|
+
|
629 |
|
|
+ legal(fp);
|
630 |
|
|
+ genzipop(fp, "addsi3", "plus:SI", "", "ADD");
|
631 |
|
|
+ genzipop(fp, "subsi3", "minus:SI", "", "SUB");
|
632 |
|
|
+ genzipop(fp, "mulsi3", "mult:SI", "", "MPY");
|
633 |
|
|
+ genzipop(fp, "divsi3", "div:SI", "(ZIP_DIVIDE)", "DIVS");
|
634 |
|
|
+ genzipop(fp, "udivsi3", "udiv:SI", "(ZIP_DIVIDE)", "DIVU");
|
635 |
|
|
+ genzipop(fp, "andsi3", "and:SI", "", "AND");
|
636 |
|
|
+ genzipop(fp, "iorsi3", "ior:SI", "", "OR");
|
637 |
|
|
+ genzipop(fp, "xorsi3", "xor:SI", "", "XOR");
|
638 |
|
|
+ genzipop(fp, "ashrsi3", "ashiftrt:SI","", "ASR");
|
639 |
|
|
+ genzipop(fp, "ashlsi3", "ashift:SI", "", "LSL");
|
640 |
|
|
+ genzipop(fp, "lshrsi3", "lshiftrt:SI","", "LSR");
|
641 |
|
|
+
|
642 |
|
|
+ genzipop_long(fp, "smulsi_highpart",
|
643 |
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
644 |
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
645 |
|
|
+ "\t\t\t(sign_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
|
646 |
|
|
+ "\t\t\t(sign_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
|
647 |
|
|
+ "\t\t\t(const_int 32))))",
|
648 |
|
|
+ "(ZIP_HAS_DI)",
|
649 |
|
|
+ "(set (match_dup 0)\n"
|
650 |
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
651 |
|
|
+ "\t\t\t(sign_extend:DI (match_dup 1))\n"
|
652 |
|
|
+ "\t\t\t(sign_extend:DI (match_dup 2)))\n"
|
653 |
|
|
+ "\t\t\t(const_int 32))))",
|
654 |
|
|
+ //
|
655 |
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
656 |
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
657 |
|
|
+ "\t\t\t(sign_extend:DI (match_dup 0))\n"
|
658 |
|
|
+ "\t\t\t(sign_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
|
659 |
|
|
+ "\t\t\t(const_int 32))))",
|
660 |
|
|
+ "MPYSHI");
|
661 |
|
|
+ genzipop_long(fp, "umulsi_highpart",
|
662 |
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
663 |
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
664 |
|
|
+ "\t\t\t(zero_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
|
665 |
|
|
+ "\t\t\t(zero_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
|
666 |
|
|
+ "\t\t\t(const_int 32))))",
|
667 |
|
|
+ "(ZIP_HAS_DI)",
|
668 |
|
|
+ "(set (match_dup 0)\n"
|
669 |
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
670 |
|
|
+ "\t\t\t(zero_extend:DI (match_dup 1))\n"
|
671 |
|
|
+ "\t\t\t(zero_extend:DI (match_dup 2)))\n"
|
672 |
|
|
+ "\t\t\t(const_int 32))))",
|
673 |
|
|
+ //
|
674 |
|
|
+ "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
|
675 |
|
|
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
|
676 |
|
|
+ "\t\t\t(zero_extend:DI (match_dup 0))\n"
|
677 |
|
|
+ "\t\t\t(zero_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
|
678 |
|
|
+ "\t\t\t(const_int 32))))",
|
679 |
|
|
+ "MPYUHI");
|
680 |
|
|
+
|
681 |
|
|
+ gen_heading(fp, "Conditional move instructions");
|
682 |
|
|
+
|
683 |
|
|
+ gencmov(fp, "cmov", "eq", "Z");
|
684 |
|
|
+ gencmov(fp, "cmov", "ne", "NZ");
|
685 |
|
|
+ gencmov(fp, "cmov", "lt", "LT");
|
686 |
|
|
+ gencmov(fp, "cmov", "ge", "GE");
|
687 |
|
|
+ gencmov(fp, "cmov", "ltu", "C");
|
688 |
|
|
+ gencmov(fp, "cmov", "geu", "NC");
|
689 |
|
|
+
|
690 |
|
|
+ gen_heading(fp, "Conditional add instructions");
|
691 |
|
|
+
|
692 |
|
|
+ gencadd(fp, "cadd", "eq", "Z");
|
693 |
|
|
+ gencadd(fp, "cadd", "ne", "NZ");
|
694 |
|
|
+ gencadd(fp, "cadd", "lt", "LT");
|
695 |
|
|
+ gencadd(fp, "cadd", "ge", "GE");
|
696 |
|
|
+ gencadd(fp, "cadd", "ltu", "C");
|
697 |
|
|
+ gencadd(fp, "cadd", "geu", "NC");
|
698 |
|
|
+
|
699 |
|
|
+ gen_heading(fp, "Conditional negate instructions");
|
700 |
|
|
+
|
701 |
|
|
+ gencneg(fp, "cneg", "eq", "Z");
|
702 |
|
|
+ gencneg(fp, "cneg", "ne", "NZ");
|
703 |
|
|
+ gencneg(fp, "cneg", "lt", "LT");
|
704 |
|
|
+ gencneg(fp, "cneg", "ge", "GE");
|
705 |
|
|
+ gencneg(fp, "cneg", "ltu", "C");
|
706 |
|
|
+ gencneg(fp, "cneg", "geu", "NC");
|
707 |
|
|
+
|
708 |
|
|
+ gen_heading(fp, "Conditional not instructions");
|
709 |
|
|
+
|
710 |
|
|
+ gencnot(fp, "cnot", "eq", "Z");
|
711 |
|
|
+ gencnot(fp, "cnot", "ne", "NZ");
|
712 |
|
|
+ gencnot(fp, "cnot", "lt", "LT");
|
713 |
|
|
+ gencnot(fp, "cnot", "ge", "GE");
|
714 |
|
|
+ gencnot(fp, "cnot", "ltu", "C");
|
715 |
|
|
+ gencnot(fp, "cnot", "geu", "NC");
|
716 |
|
|
+
|
717 |
|
|
+ gen_heading(fp, "Conditional and instructions");
|
718 |
|
|
+
|
719 |
|
|
+ gencand(fp, "cand", "eq", "Z");
|
720 |
|
|
+ gencand(fp, "cand", "ne", "NZ");
|
721 |
|
|
+ gencand(fp, "cand", "lt", "LT");
|
722 |
|
|
+ gencand(fp, "cand", "ge", "GE");
|
723 |
|
|
+ gencand(fp, "cand", "ltu", "C");
|
724 |
|
|
+ gencand(fp, "cand", "geu", "NC");
|
725 |
|
|
+
|
726 |
|
|
+ gen_heading(fp, "Conditional ior instructions");
|
727 |
|
|
+
|
728 |
|
|
+ gencior(fp, "cior", "eq", "Z");
|
729 |
|
|
+ gencior(fp, "cior", "ne", "NZ");
|
730 |
|
|
+ gencior(fp, "cior", "lt", "LT");
|
731 |
|
|
+ gencior(fp, "cior", "ge", "GE");
|
732 |
|
|
+ gencior(fp, "cior", "ltu", "C");
|
733 |
|
|
+ gencior(fp, "cior", "geu", "NC");
|
734 |
|
|
+
|
735 |
|
|
+ gen_heading(fp, "Conditional xor instructions");
|
736 |
|
|
+
|
737 |
|
|
+ gencxor(fp, "cxor", "eq", "Z");
|
738 |
|
|
+ gencxor(fp, "cxor", "ne", "NZ");
|
739 |
|
|
+ gencxor(fp, "cxor", "lt", "LT");
|
740 |
|
|
+ gencxor(fp, "cxor", "ge", "GE");
|
741 |
|
|
+ gencxor(fp, "cxor", "ltu", "C");
|
742 |
|
|
+ gencxor(fp, "cxor", "geu", "NC");
|
743 |
|
|
+
|
744 |
|
|
+ fclose(fp);
|
745 |
|
|
+
|
746 |
|
|
+ if (rename(TMPPATH, newname) != 0) {
|
747 |
|
|
+ fprintf(stderr, "ERR: Could not create %s, leaving results in %s\n", newname, TMPPATH);
|
748 |
|
|
+ exit(EXIT_FAILURE);
|
749 |
|
|
+ } exit(EXIT_SUCCESS);
|
750 |
|
|
+}
|
751 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c
|
752 |
|
|
--- gcc-6.2.0/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
|
753 |
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip.c 2017-03-07 12:03:18.566583672 -0500
|
754 |
|
|
@@ -0,0 +1,2679 @@
|
755 |
102 |
dgisselq |
+////////////////////////////////////////////////////////////////////////////////
|
756 |
|
|
+//
|
757 |
|
|
+// Filename: zip.c
|
758 |
|
|
+//
|
759 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
760 |
|
|
+//
|
761 |
|
|
+// Purpose:
|
762 |
|
|
+//
|
763 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
764 |
|
|
+// Gisselquist Technology, LLC
|
765 |
|
|
+//
|
766 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
767 |
|
|
+//
|
768 |
202 |
dgisselq |
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
769 |
102 |
dgisselq |
+//
|
770 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
771 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
772 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
773 |
|
|
+// your option) any later version.
|
774 |
|
|
+//
|
775 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
776 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
777 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
778 |
|
|
+// for more details.
|
779 |
|
|
+//
|
780 |
|
|
+// You should have received a copy of the GNU General Public License along
|
781 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
782 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
783 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
784 |
|
|
+//
|
785 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
786 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
787 |
|
|
+//
|
788 |
|
|
+//
|
789 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
790 |
|
|
+#include "config.h"
|
791 |
|
|
+#include "system.h"
|
792 |
|
|
+#include "coretypes.h"
|
793 |
|
|
+#include "tm.h"
|
794 |
|
|
+#include "rtl.h"
|
795 |
|
|
+#include "dominance.h"
|
796 |
|
|
+#include "cfg.h"
|
797 |
|
|
+#include "cfgrtl.h"
|
798 |
|
|
+#include "cfganal.h"
|
799 |
|
|
+#include "lcm.h"
|
800 |
|
|
+#include "cfgbuild.h"
|
801 |
|
|
+#include "cfgcleanup.h"
|
802 |
|
|
+#include "predict.h"
|
803 |
|
|
+#include "basic-block.h"
|
804 |
202 |
dgisselq |
+#include "bitmap.h"
|
805 |
102 |
dgisselq |
+#include "df.h"
|
806 |
|
|
+#include "hashtab.h"
|
807 |
|
|
+#include "hash-set.h"
|
808 |
|
|
+#include "machmode.h"
|
809 |
|
|
+#include "symtab.h"
|
810 |
|
|
+#include "rtlhash.h"
|
811 |
|
|
+#include "tree.h"
|
812 |
|
|
+#include "regs.h"
|
813 |
|
|
+#include "hard-reg-set.h"
|
814 |
|
|
+#include "real.h"
|
815 |
|
|
+#include "insn-config.h"
|
816 |
|
|
+#include "conditions.h"
|
817 |
|
|
+#include "output.h"
|
818 |
|
|
+#include "insn-attr.h"
|
819 |
|
|
+#include "flags.h"
|
820 |
|
|
+#include "expr.h"
|
821 |
|
|
+#include "function.h"
|
822 |
|
|
+#include "recog.h"
|
823 |
|
|
+#include "toplev.h"
|
824 |
|
|
+#include "ggc.h"
|
825 |
|
|
+#include "builtins.h"
|
826 |
|
|
+#include "calls.h"
|
827 |
|
|
+#include "langhooks.h"
|
828 |
|
|
+#include "optabs.h"
|
829 |
|
|
+#include "explow.h"
|
830 |
|
|
+#include "emit-rtl.h"
|
831 |
122 |
dgisselq |
+#include "ifcvt.h"
|
832 |
202 |
dgisselq |
+#include "genrtl.h"
|
833 |
102 |
dgisselq |
+
|
834 |
|
|
+// #include "tmp_p.h"
|
835 |
|
|
+#include "target.h"
|
836 |
|
|
+#include "target-def.h"
|
837 |
|
|
+// #include "tm-constrs.h"
|
838 |
122 |
dgisselq |
+#include "tm-preds.h"
|
839 |
102 |
dgisselq |
+
|
840 |
|
|
+#include "diagnostic.h"
|
841 |
|
|
+// #include "integrate.h"
|
842 |
|
|
+
|
843 |
200 |
dgisselq |
+#include "zip-protos.h"
|
844 |
|
|
+
|
845 |
102 |
dgisselq |
+static bool zip_return_in_memory(const_tree, const_tree);
|
846 |
|
|
+static bool zip_frame_pointer_required(void);
|
847 |
|
|
+
|
848 |
|
|
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
|
849 |
|
|
+ const_tree type, bool named);
|
850 |
|
|
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
|
851 |
|
|
+
|
852 |
|
|
+static void zip_asm_trampoline_template(FILE *);
|
853 |
|
|
+static void zip_trampoline_init(rtx, tree, rtx);
|
854 |
|
|
+static void zip_init_builtins(void);
|
855 |
202 |
dgisselq |
+static tree zip_builtin_decl(unsigned, bool);
|
856 |
102 |
dgisselq |
+// static void zip_asm_output_anchor(rtx x);
|
857 |
|
|
+ void zip_asm_output_def(FILE *s, const char *n, const char *v);
|
858 |
|
|
+static rtx zip_expand_builtin(tree exp, rtx target, rtx subtarget,
|
859 |
|
|
+ enum machine_mode tmode, int ignore);
|
860 |
|
|
+static bool zip_scalar_mode_supported_p(enum machine_mode mode);
|
861 |
|
|
+static bool zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
|
862 |
|
|
+static int zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
|
863 |
|
|
+static bool zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
|
864 |
|
|
+static unsigned HOST_WIDE_INT zip_const_anchor = 0x20000;
|
865 |
122 |
dgisselq |
+static HOST_WIDE_INT zip_min_opb_imm = -0x20000;
|
866 |
|
|
+static HOST_WIDE_INT zip_max_opb_imm = 0x1ffff;
|
867 |
142 |
dgisselq |
+static HOST_WIDE_INT zip_min_anchor_offset = -0x2000;
|
868 |
|
|
+static HOST_WIDE_INT zip_max_anchor_offset = 0x1fff;
|
869 |
102 |
dgisselq |
+static HOST_WIDE_INT zip_min_mov_offset = -0x1000;
|
870 |
|
|
+static HOST_WIDE_INT zip_max_mov_offset = 0x0fff;
|
871 |
|
|
+static int zip_sched_issue_rate(void) { return 1; }
|
872 |
|
|
+static bool zip_legitimate_address_p(machine_mode, rtx, bool);
|
873 |
|
|
+static bool zip_legitimate_move_operand_p(machine_mode, rtx, bool);
|
874 |
|
|
+ void zip_debug_rtx_pfx(const char *, const_rtx x);
|
875 |
|
|
+ void zip_debug_rtx(const_rtx x);
|
876 |
|
|
+static void zip_override_options(void);
|
877 |
|
|
+static bool zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
|
878 |
|
|
+static int zip_memory_move_cost(machine_mode, reg_class_t, bool);
|
879 |
111 |
dgisselq |
+static rtx zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
|
880 |
117 |
dgisselq |
+static bool zip_cannot_modify_jumps_p(void);
|
881 |
122 |
dgisselq |
+static bool zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
|
882 |
102 |
dgisselq |
+
|
883 |
|
|
+
|
884 |
202 |
dgisselq |
+#define ZIP_ALL_DEBUG_OFF false
|
885 |
|
|
+#define ZIP_ALL_DEBUG_ON false
|
886 |
|
|
+#define ZIPDEBUGFLAG(A,B) const bool A = \
|
887 |
|
|
+ ((ZIP_ALL_DEBUG_ON)||(B))&&(!ZIP_ALL_DEBUG_OFF)
|
888 |
102 |
dgisselq |
+
|
889 |
|
|
+enum ZIP_BUILTIN_ID_CODE {
|
890 |
|
|
+ ZIP_BUILTIN_RTU,
|
891 |
|
|
+ ZIP_BUILTIN_HALT,
|
892 |
|
|
+ ZIP_BUILTIN_IDLE,
|
893 |
|
|
+ ZIP_BUILTIN_SYSCALL,
|
894 |
|
|
+ ZIP_BUILTIN_SAVE_CONTEXT,
|
895 |
|
|
+ ZIP_BUILTIN_RESTORE_CONTEXT,
|
896 |
|
|
+ ZIP_BUILTIN_BITREV,
|
897 |
|
|
+ ZIP_BUILTIN_CC,
|
898 |
117 |
dgisselq |
+ ZIP_BUILTIN_UCC,
|
899 |
171 |
dgisselq |
+ ZIP_BUILTIN_BUSY,
|
900 |
102 |
dgisselq |
+ ZIP_BUILTIN_MAX
|
901 |
|
|
+};
|
902 |
|
|
+
|
903 |
|
|
+static GTY (()) tree zip_builtins[(int)ZIP_BUILTIN_MAX];
|
904 |
|
|
+static enum insn_code zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
|
905 |
|
|
+
|
906 |
202 |
dgisselq |
+#undef TARGET_ASM_ALIGNED_HI_OP
|
907 |
|
|
+#undef TARGET_ASM_ALIGNED_SI_OP
|
908 |
|
|
+#undef TARGET_ASM_ALIGNED_DI_OP
|
909 |
|
|
+#define TARGET_ASM_ALIGNED_HI_OP "\t.short\t"
|
910 |
|
|
+#define TARGET_ASM_ALIGNED_SI_OP "\t.int\t"
|
911 |
|
|
+#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
|
912 |
102 |
dgisselq |
+
|
913 |
202 |
dgisselq |
+#undef TARGET_ASM_UNALIGNED_HI_OP
|
914 |
|
|
+#undef TARGET_ASM_UNALIGNED_SI_OP
|
915 |
|
|
+#undef TARGET_ASM_UNALIGNED_DI_OP
|
916 |
|
|
+#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
|
917 |
|
|
+#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
|
918 |
|
|
+#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
|
919 |
|
|
+
|
920 |
102 |
dgisselq |
+#include "gt-zip.h"
|
921 |
|
|
+
|
922 |
|
|
+/* The Global 'targetm' Variable. */
|
923 |
|
|
+struct gcc_target targetm = TARGET_INITIALIZER;
|
924 |
|
|
+
|
925 |
|
|
+
|
926 |
|
|
+enum reg_class zip_reg_class(int);
|
927 |
|
|
+
|
928 |
|
|
+#define LOSE_AND_RETURN(msgid, x) \
|
929 |
|
|
+ do { \
|
930 |
|
|
+ zip_operand_lossage(msgid, x); \
|
931 |
|
|
+ return; \
|
932 |
|
|
+ } while(0)
|
933 |
|
|
+
|
934 |
|
|
+/* Per-function machine data. */
|
935 |
|
|
+struct GTY(()) machine_function
|
936 |
|
|
+{
|
937 |
|
|
+ /* number of pretented arguments for varargs */
|
938 |
|
|
+ int pretend_size;
|
939 |
|
|
+
|
940 |
|
|
+ /* Number of bytes saved on the stack for local variables. */
|
941 |
|
|
+ int local_vars_size;
|
942 |
|
|
+
|
943 |
|
|
+ /* Number of bytes saved on stack for register save area */
|
944 |
|
|
+ int saved_reg_size;
|
945 |
|
|
+ int save_ret;
|
946 |
|
|
+
|
947 |
|
|
+ int sp_fp_offset;
|
948 |
|
|
+ bool fp_needed;
|
949 |
|
|
+ int size_for_adjusting_sp;
|
950 |
|
|
+};
|
951 |
|
|
+
|
952 |
|
|
+/* Allocate a chunk of memory for per-function machine-dependent data. */
|
953 |
|
|
+
|
954 |
|
|
+static struct machine_function *
|
955 |
|
|
+zip_init_machine_status(void) {
|
956 |
|
|
+ return ggc_cleared_alloc<machine_function>();
|
957 |
|
|
+}
|
958 |
|
|
+
|
959 |
|
|
+static void
|
960 |
|
|
+zip_override_options(void)
|
961 |
|
|
+{
|
962 |
|
|
+ init_machine_status = zip_init_machine_status;
|
963 |
|
|
+}
|
964 |
|
|
+
|
965 |
|
|
+enum reg_class
|
966 |
|
|
+zip_reg_class(int regno)
|
967 |
|
|
+{
|
968 |
|
|
+ if (is_ZIP_GENERAL_REG(regno)) {
|
969 |
|
|
+ return GENERAL_REGS;
|
970 |
|
|
+ } else if (is_ZIP_REG(regno)) {
|
971 |
|
|
+ return ALL_REGS;
|
972 |
|
|
+ } return NO_REGS;
|
973 |
|
|
+}
|
974 |
|
|
+
|
975 |
|
|
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
|
976 |
|
|
+static bool
|
977 |
|
|
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
|
978 |
|
|
+ const HOST_WIDE_INT size = int_size_in_bytes(type);
|
979 |
202 |
dgisselq |
+ return (size == -1)||(size > 2*UNITS_PER_WORD);
|
980 |
102 |
dgisselq |
+}
|
981 |
|
|
+
|
982 |
|
|
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
|
983 |
|
|
+ * insn. Formatted output isn't easily implemented, since we use output operand
|
984 |
|
|
+ * lossage to output the actual message and handle the categorization of the
|
985 |
|
|
+ * error. */
|
986 |
|
|
+
|
987 |
|
|
+static void
|
988 |
|
|
+zip_operand_lossage(const char *msgid, rtx op) {
|
989 |
|
|
+ debug_rtx(op);
|
990 |
|
|
+ zip_debug_rtx(op);
|
991 |
|
|
+ output_operand_lossage("%s", msgid);
|
992 |
|
|
+}
|
993 |
|
|
+
|
994 |
|
|
+/* The PRINT_OPERAND_ADDRESS worker. */
|
995 |
|
|
+void
|
996 |
|
|
+zip_print_operand_address(FILE *file, rtx x) {
|
997 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
998 |
102 |
dgisselq |
+
|
999 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
1000 |
|
|
+ switch(GET_CODE(x)) {
|
1001 |
|
|
+ case REG:
|
1002 |
127 |
dgisselq |
+ gcc_assert(is_ZIP_REG(REGNO(x)));
|
1003 |
171 |
dgisselq |
+ gcc_assert(REGNO(x) < 16);
|
1004 |
102 |
dgisselq |
+ fprintf(file, "(%s)", reg_names[REGNO(x)]);
|
1005 |
|
|
+ break;
|
1006 |
|
|
+ case SYMBOL_REF:
|
1007 |
|
|
+ fprintf(file, "%s", XSTR(x,0));
|
1008 |
|
|
+ break;
|
1009 |
|
|
+ case LABEL_REF:
|
1010 |
|
|
+ x = LABEL_REF_LABEL(x);
|
1011 |
|
|
+ case CODE_LABEL:
|
1012 |
|
|
+ { char buf[256];
|
1013 |
|
|
+ ASM_GENERATE_INTERNAL_LABEL(buf, "L", CODE_LABEL_NUMBER(x));
|
1014 |
|
|
+#ifdef ASM_OUTPUT_LABEL_REF
|
1015 |
|
|
+ ASM_OUTPUT_LABEL_REF(file, buf);
|
1016 |
|
|
+#else
|
1017 |
|
|
+ assemble_name(file, buf);
|
1018 |
|
|
+#endif
|
1019 |
|
|
+ }
|
1020 |
|
|
+ break;
|
1021 |
|
|
+ case PLUS:
|
1022 |
111 |
dgisselq |
+ if (!REG_P(XEXP(x, 0))) {
|
1023 |
|
|
+ fprintf(stderr, "Unsupported address construct\n");
|
1024 |
|
|
+ zip_debug_rtx(x);
|
1025 |
102 |
dgisselq |
+ abort();
|
1026 |
127 |
dgisselq |
+ } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0))));
|
1027 |
171 |
dgisselq |
+ gcc_assert(REGNO(XEXP(x,0))<16);
|
1028 |
127 |
dgisselq |
+ if (CONST_INT_P(XEXP(x, 1))) {
|
1029 |
102 |
dgisselq |
+ if (INTVAL(XEXP(x,1))!=0) {
|
1030 |
|
|
+ fprintf(file, "%ld(%s)",
|
1031 |
135 |
dgisselq |
+ (long)INTVAL(XEXP(x, 1)),
|
1032 |
102 |
dgisselq |
+ reg_names[REGNO(XEXP(x, 0))]);
|
1033 |
|
|
+ } else {
|
1034 |
|
|
+ fprintf(file, "(%s)",
|
1035 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
1036 |
|
|
+ }
|
1037 |
|
|
+ } else if (GET_CODE(XEXP(x,1)) == SYMBOL_REF) {
|
1038 |
|
|
+ fprintf(file, "%s(%s)", XSTR(x,0),
|
1039 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
1040 |
|
|
+ } else if ((GET_CODE(XEXP(x, 1)) == MINUS)
|
1041 |
|
|
+ && (GET_CODE(XEXP(XEXP(x, 1), 0))==SYMBOL_REF)
|
1042 |
|
|
+ && (GET_CODE(XEXP(XEXP(x, 1), 1))==SYMBOL_REF)) {
|
1043 |
|
|
+ fprintf(file, "%s-%s(%s)",
|
1044 |
|
|
+ XSTR(XEXP(XEXP(x, 1),0),0),
|
1045 |
|
|
+ XSTR(XEXP(XEXP(x, 1),1),0),
|
1046 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
1047 |
|
|
+ } else
|
1048 |
|
|
+ fprintf(file, "#INVALID(%s)",
|
1049 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
1050 |
|
|
+ /*
|
1051 |
|
|
+ else if (GET_CODE(XEXP(addr, 1)) == LABEL)
|
1052 |
|
|
+ fprintf(file, "%s(%s)",
|
1053 |
|
|
+ GET_CODE(XEXP(addr, 1)),
|
1054 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1055 |
|
|
+ else if ((GET_CODE(XEXP(addr, 1)) == MINUS)
|
1056 |
|
|
+ && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 0))==LABEL)
|
1057 |
|
|
+ && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 1))==LABEL)) {
|
1058 |
|
|
+ fprintf(file, "%s-%s(%s)",
|
1059 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1060 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1061 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1062 |
|
|
+ }
|
1063 |
|
|
+ */
|
1064 |
|
|
+ break;
|
1065 |
|
|
+ // We don't support direct memory addressing within our
|
1066 |
|
|
+ // instruction set, even though the instructions themselves
|
1067 |
|
|
+ // would support direct memory addressing of the lower 18 bits
|
1068 |
|
|
+ // of memory space.
|
1069 |
|
|
+ case MEM:
|
1070 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
1071 |
|
|
+ zip_print_operand_address(file, XEXP(x, 0));
|
1072 |
|
|
+ break;
|
1073 |
111 |
dgisselq |
+ case CONST_INT:
|
1074 |
135 |
dgisselq |
+ fprintf(file, "%ld",(long)INTVAL(x));
|
1075 |
111 |
dgisselq |
+ break;
|
1076 |
102 |
dgisselq |
+ default:
|
1077 |
111 |
dgisselq |
+ fprintf(stderr, "Unknown address format\n");
|
1078 |
|
|
+ zip_debug_rtx(x);
|
1079 |
102 |
dgisselq |
+ abort(); break;
|
1080 |
|
|
+ // output_addr_const(file, x);
|
1081 |
|
|
+ break;
|
1082 |
|
|
+ }
|
1083 |
|
|
+}
|
1084 |
|
|
+
|
1085 |
|
|
+/* The PRINT_OPERAND worker. */
|
1086 |
|
|
+
|
1087 |
|
|
+void
|
1088 |
|
|
+zip_print_operand(FILE *file, rtx x, int code)
|
1089 |
|
|
+{
|
1090 |
|
|
+ rtx operand = x;
|
1091 |
|
|
+ int rgoff = 0;
|
1092 |
|
|
+
|
1093 |
|
|
+ // fprintf(file, "Print Operand!\n");
|
1094 |
|
|
+
|
1095 |
|
|
+ /* New code entries should just be added to the switch below. If
|
1096 |
|
|
+ * handling is finished, just return. If handling was just a
|
1097 |
|
|
+ * modification of the operand, the modified operand should be put in
|
1098 |
|
|
+ * "operand", and then do a break to let default handling
|
1099 |
|
|
+ * (zero-modifier) output the operand.
|
1100 |
|
|
+ */
|
1101 |
|
|
+ switch(code) {
|
1102 |
|
|
+ case 0:
|
1103 |
|
|
+ /* No code, print as usual. */
|
1104 |
|
|
+ break;
|
1105 |
|
|
+ case 'L':
|
1106 |
|
|
+ /* Lower of two registers, print one up */
|
1107 |
|
|
+ rgoff = 1;
|
1108 |
|
|
+ break;
|
1109 |
|
|
+ case 'R':
|
1110 |
|
|
+ case 'H':
|
1111 |
|
|
+ /* Higher of a register pair, print normal */
|
1112 |
|
|
+ break;
|
1113 |
|
|
+
|
1114 |
|
|
+ default:
|
1115 |
|
|
+ LOSE_AND_RETURN("invalid operand modifier letter", x);
|
1116 |
|
|
+ }
|
1117 |
|
|
+
|
1118 |
|
|
+ /* Print an operand as without a modifier letter. */
|
1119 |
|
|
+ switch (GET_CODE(operand)) {
|
1120 |
|
|
+ case REG:
|
1121 |
|
|
+ if (REGNO(operand)+rgoff >= FIRST_PSEUDO_REGISTER)
|
1122 |
|
|
+ internal_error("internal error: bad register: %d", REGNO(operand));
|
1123 |
|
|
+ fprintf(file, "%s", reg_names[REGNO(operand)+rgoff]);
|
1124 |
|
|
+ return;
|
1125 |
|
|
+ case SCRATCH:
|
1126 |
|
|
+ LOSE_AND_RETURN("Need a scratch register", x);
|
1127 |
|
|
+ return;
|
1128 |
|
|
+
|
1129 |
|
|
+ case CODE_LABEL:
|
1130 |
|
|
+ case LABEL_REF:
|
1131 |
|
|
+ case SYMBOL_REF:
|
1132 |
|
|
+ case PLUS:
|
1133 |
|
|
+ PRINT_OPERAND_ADDRESS(file, operand);
|
1134 |
|
|
+ return;
|
1135 |
|
|
+ case MEM:
|
1136 |
|
|
+ PRINT_OPERAND_ADDRESS(file, XEXP(operand, 0));
|
1137 |
|
|
+ return;
|
1138 |
|
|
+
|
1139 |
|
|
+ default:
|
1140 |
|
|
+ /* No need to handle all strange variants, let
|
1141 |
|
|
+ * output_addr_const do it for us.
|
1142 |
|
|
+ */
|
1143 |
|
|
+ if (CONSTANT_P(operand)) {
|
1144 |
|
|
+ output_addr_const(file, operand);
|
1145 |
|
|
+ return;
|
1146 |
|
|
+ }
|
1147 |
|
|
+
|
1148 |
202 |
dgisselq |
+ zip_debug_rtx(x);
|
1149 |
102 |
dgisselq |
+ LOSE_AND_RETURN("unexpected operand", x);
|
1150 |
|
|
+ }
|
1151 |
|
|
+}
|
1152 |
|
|
+
|
1153 |
|
|
+static bool
|
1154 |
|
|
+zip_frame_pointer_required(void)
|
1155 |
|
|
+{
|
1156 |
|
|
+ // This should really depend upon whether we have variable sized
|
1157 |
|
|
+ // arguments in our frame or not. Once this fails, let's look
|
1158 |
|
|
+ // at what the problem was and then whether or not we can detect
|
1159 |
|
|
+ // it.
|
1160 |
|
|
+ //
|
1161 |
|
|
+ // Use a GCC global to determine our answer
|
1162 |
103 |
dgisselq |
+ if (cfun->calls_alloca)
|
1163 |
|
|
+ return true;
|
1164 |
202 |
dgisselq |
+
|
1165 |
|
|
+ // If the stack frame is too large to access saved registers with
|
1166 |
|
|
+ // immediate offsets, then we *must* use a frame pointer
|
1167 |
|
|
+ unsigned stack_size = 36;
|
1168 |
|
|
+ stack_size += (ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
|
1169 |
|
|
+
|
1170 |
|
|
+ //
|
1171 |
|
|
+ // if cfun->machine->size_for_adjusting_sp might ever be larger than
|
1172 |
|
|
+ // zip_max_anchor_offset, then we MUST have a frame pointer.
|
1173 |
|
|
+ //
|
1174 |
|
|
+ // cfun->machine->size_for_adjusting_sp =
|
1175 |
|
|
+ // get_frame_size
|
1176 |
|
|
+ // + saved_reg_size (will always be <= 36)
|
1177 |
|
|
+ // + outgoing_args_size;
|
1178 |
|
|
+ // + pretend_args_size;
|
1179 |
|
|
+
|
1180 |
|
|
+ if(crtl->args.pretend_args_size > 0)
|
1181 |
|
|
+ stack_size += crtl->args.pretend_args_size;
|
1182 |
|
|
+ stack_size += get_frame_size();
|
1183 |
|
|
+ // Align our attempted stack size
|
1184 |
|
|
+ stack_size = ((stack_size+3)&-4);
|
1185 |
|
|
+
|
1186 |
|
|
+ // Now here's our test
|
1187 |
|
|
+ if (stack_size >= zip_max_anchor_offset)
|
1188 |
|
|
+ return true;
|
1189 |
102 |
dgisselq |
+ return (frame_pointer_needed);
|
1190 |
|
|
+/*
|
1191 |
|
|
+*/
|
1192 |
|
|
+}
|
1193 |
|
|
+
|
1194 |
|
|
+/* Determine whether or not a register needs to be saved on the stack or not.
|
1195 |
|
|
+ */
|
1196 |
|
|
+static bool
|
1197 |
|
|
+zip_save_reg(int regno) {
|
1198 |
|
|
+ if (regno == 0)
|
1199 |
|
|
+ return ((!crtl->is_leaf)
|
1200 |
|
|
+ ||((df_regs_ever_live_p(0))&&(!call_used_regs[0])));
|
1201 |
|
|
+ else if ((regno == zip_GOT)&&(!ZIP_PIC))
|
1202 |
|
|
+ return ((df_regs_ever_live_p(regno))
|
1203 |
|
|
+ &&(!call_used_regs[regno]));
|
1204 |
|
|
+ else if (regno == zip_FP)
|
1205 |
|
|
+ return((zip_frame_pointer_required())||((df_regs_ever_live_p(regno))
|
1206 |
|
|
+ &&(!call_used_regs[regno])));
|
1207 |
|
|
+ else if (regno < zip_FP)
|
1208 |
|
|
+ return ((df_regs_ever_live_p(regno))
|
1209 |
|
|
+ &&(!call_used_regs[regno]));
|
1210 |
|
|
+ return false;
|
1211 |
|
|
+}
|
1212 |
|
|
+
|
1213 |
|
|
+/* Compute the size of the local area and the size to be adjusted by the
|
1214 |
|
|
+ * prologue and epilogue.
|
1215 |
|
|
+ *
|
1216 |
|
|
+ * Here's what we are looking at (top is the current, bottom is the last ...)
|
1217 |
|
|
+ *
|
1218 |
|
|
+ * Stack Pointer ->
|
1219 |
124 |
dgisselq |
+ * Outgoing arguments
|
1220 |
102 |
dgisselq |
+ * Local variables (could be variable size)
|
1221 |
|
|
+ * Frame Pointer -> (= Stack Pointer + sp_fp_offset)
|
1222 |
|
|
+ * Saved return address, if saved
|
1223 |
|
|
+ * Other Saved registers
|
1224 |
|
|
+ * Saved frame pointer (if used)
|
1225 |
|
|
+ * Saved R12, if used
|
1226 |
|
|
+ * (Stack pointer is not saved)
|
1227 |
171 |
dgisselq |
+ * (PRETEND-ARGS)
|
1228 |
102 |
dgisselq |
+ * Original stack pointer -> (= Stack_Pointer +size_for_adjusting_sp)
|
1229 |
|
|
+ * Called arguments (not passed in registers)
|
1230 |
|
|
+ * Return arguments (not R1, args.pretend_args_size)
|
1231 |
|
|
+ * (Prior function's stack frame ... )
|
1232 |
|
|
+ *
|
1233 |
|
|
+ */
|
1234 |
|
|
+static void
|
1235 |
|
|
+zip_compute_frame(void) {
|
1236 |
|
|
+ int regno;
|
1237 |
|
|
+ int args_size;
|
1238 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
1239 |
102 |
dgisselq |
+
|
1240 |
171 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
|
1241 |
102 |
dgisselq |
+ // gcc_assert(crtl);
|
1242 |
|
|
+ gcc_assert(cfun);
|
1243 |
|
|
+ gcc_assert(cfun->machine);
|
1244 |
|
|
+
|
1245 |
|
|
+ args_size=(ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
|
1246 |
|
|
+
|
1247 |
|
|
+ if(crtl->args.pretend_args_size > 0) {
|
1248 |
|
|
+ args_size += crtl->args.pretend_args_size;
|
1249 |
171 |
dgisselq |
+ if (dbg) fprintf(stderr, "%s pretend_args_size : %d\n", current_function_name(),
|
1250 |
|
|
+ crtl->args.pretend_args_size);
|
1251 |
102 |
dgisselq |
+ cfun->machine->pretend_size = crtl->args.pretend_args_size;
|
1252 |
|
|
+ }
|
1253 |
|
|
+
|
1254 |
|
|
+ cfun->machine->local_vars_size = get_frame_size();
|
1255 |
|
|
+
|
1256 |
202 |
dgisselq |
+ // Force frame alignment of the local variable section
|
1257 |
|
|
+ cfun->machine->local_vars_size += 3;
|
1258 |
|
|
+ cfun->machine->local_vars_size &= -4;
|
1259 |
|
|
+
|
1260 |
102 |
dgisselq |
+ // Save callee-saved registers.
|
1261 |
|
|
+ cfun->machine->saved_reg_size = 0;
|
1262 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1263 |
|
|
+ if (zip_save_reg(regno))
|
1264 |
202 |
dgisselq |
+ cfun->machine->saved_reg_size += 4;
|
1265 |
102 |
dgisselq |
+ }
|
1266 |
|
|
+
|
1267 |
|
|
+ cfun->machine->fp_needed = (zip_frame_pointer_required());
|
1268 |
|
|
+
|
1269 |
|
|
+ if ((cfun->machine->fp_needed)&&
|
1270 |
|
|
+ (!df_regs_ever_live_p(zip_FP))) {
|
1271 |
202 |
dgisselq |
+ cfun->machine->saved_reg_size += 4;
|
1272 |
102 |
dgisselq |
+ }
|
1273 |
|
|
+
|
1274 |
171 |
dgisselq |
+ cfun->machine->sp_fp_offset = crtl->outgoing_args_size
|
1275 |
|
|
+ + cfun->machine->local_vars_size;
|
1276 |
102 |
dgisselq |
+ cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
|
1277 |
|
|
+ + cfun->machine->saved_reg_size
|
1278 |
|
|
+ + args_size;
|
1279 |
124 |
dgisselq |
+ if(dbg) {
|
1280 |
171 |
dgisselq |
+ fprintf(stderr, "\t---- STACK PTR ----\n");
|
1281 |
|
|
+ fprintf(stderr, "\tOUTGOIN-SIZE: %d\n",
|
1282 |
|
|
+ crtl->outgoing_args_size);
|
1283 |
124 |
dgisselq |
+ fprintf(stderr, "\tLOCALS-SIZE : %d\n",
|
1284 |
|
|
+ cfun->machine->local_vars_size);
|
1285 |
171 |
dgisselq |
+ fprintf(stderr, "\t---- FRAME PTR ----%s\n",
|
1286 |
|
|
+ cfun->machine->fp_needed?"":" (Eliminated)");
|
1287 |
124 |
dgisselq |
+ fprintf(stderr, "\tREGISTERS : %d\n",
|
1288 |
|
|
+ cfun->machine->saved_reg_size);
|
1289 |
171 |
dgisselq |
+ fprintf(stderr, "\tPRETEND SIZE: %d\n",
|
1290 |
|
|
+ crtl->args.pretend_args_size);
|
1291 |
|
|
+ fprintf(stderr, "\t---- ARG PTR (Original SP, should be eliminated) ----\n");
|
1292 |
|
|
+ fprintf(stderr, "\t----\n");
|
1293 |
|
|
+ fprintf(stderr, "\tARGS-SIZE : %d\n", args_size);
|
1294 |
124 |
dgisselq |
+ fprintf(stderr, "\tSP_FP_OFFSET: %d\n",
|
1295 |
|
|
+ cfun->machine->sp_fp_offset);
|
1296 |
|
|
+ fprintf(stderr, "\tSP-ADJUSTMNT: %d\n",
|
1297 |
|
|
+ cfun->machine->size_for_adjusting_sp);
|
1298 |
|
|
+ }
|
1299 |
102 |
dgisselq |
+}
|
1300 |
|
|
+
|
1301 |
|
|
+void
|
1302 |
202 |
dgisselq |
+zip_save_registers(rtx basereg_rtx, int sp_offset_to_first_register) {
|
1303 |
102 |
dgisselq |
+ rtx insn;
|
1304 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
1305 |
102 |
dgisselq |
+
|
1306 |
202 |
dgisselq |
+ // Compute Frame has already been calculated before coming into here
|
1307 |
|
|
+ //
|
1308 |
|
|
+ // zip_compute_frame();
|
1309 |
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE::SAVE-REGISTER\n");
|
1310 |
|
|
+
|
1311 |
|
|
+ int offset = 0, regno;
|
1312 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1313 |
|
|
+ if (zip_save_reg(regno)) {
|
1314 |
|
|
+ if (dbg) fprintf(stderr,
|
1315 |
|
|
+ "PROLOGUE::SAVE-REGISTER Saving R%d in %d+%d(SP)\n",
|
1316 |
|
|
+ regno, sp_offset_to_first_register, offset);
|
1317 |
|
|
+ insn=emit_insn(gen_movsi_sto_off(
|
1318 |
|
|
+ basereg_rtx,
|
1319 |
|
|
+ GEN_INT(sp_offset_to_first_register +offset),
|
1320 |
|
|
+ gen_rtx_REG(SImode, regno)));
|
1321 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1322 |
|
|
+ offset += 4;
|
1323 |
|
|
+ }
|
1324 |
|
|
+ } if (dbg) fprintf(stderr, "%d registers saved%s\n", offset,
|
1325 |
|
|
+ (crtl->saves_all_registers)?", should be all of them":", less than all");
|
1326 |
|
|
+
|
1327 |
|
|
+}
|
1328 |
|
|
+
|
1329 |
|
|
+/*
|
1330 |
|
|
+ * zip_expand_small_prologue()
|
1331 |
|
|
+ *
|
1332 |
|
|
+ * To be used when the sp_fp_offset is less then zip_max_opb_offset.
|
1333 |
|
|
+ *
|
1334 |
|
|
+ *
|
1335 |
|
|
+ * Approach:
|
1336 |
|
|
+ * SUB size_for_adjusting_sp,SP
|
1337 |
|
|
+ * SW REG,0(SP)
|
1338 |
|
|
+ * SW REG,4(SP)
|
1339 |
|
|
+ * SW REG,8(SP)
|
1340 |
|
|
+ * ....
|
1341 |
|
|
+ * SW REG,#(SP)
|
1342 |
|
|
+ *
|
1343 |
|
|
+ * and if we need a frame register, we'll either do ...
|
1344 |
|
|
+ * MOV sp_fp_offset+SP,FP
|
1345 |
|
|
+ * or if the offset is too large, we'll do ...
|
1346 |
|
|
+ * MOV SP,FP
|
1347 |
|
|
+ * ADD sp_fp_offset,FP
|
1348 |
|
|
+ *
|
1349 |
|
|
+ */
|
1350 |
|
|
+void
|
1351 |
|
|
+zip_expand_small_prologue(void) {
|
1352 |
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
1353 |
|
|
+ rtx insn;
|
1354 |
|
|
+
|
1355 |
102 |
dgisselq |
+ zip_compute_frame();
|
1356 |
|
|
+
|
1357 |
202 |
dgisselq |
+ if (dbg) fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(SP-FP offset is %d)\n",
|
1358 |
|
|
+ cfun->machine->sp_fp_offset);
|
1359 |
|
|
+
|
1360 |
|
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
|
1361 |
102 |
dgisselq |
+ gen_int_mode(cfun->machine->size_for_adjusting_sp,
|
1362 |
|
|
+ SImode)));
|
1363 |
202 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1364 |
102 |
dgisselq |
+
|
1365 |
202 |
dgisselq |
+ zip_save_registers(stack_pointer_rtx, cfun->machine->sp_fp_offset);
|
1366 |
102 |
dgisselq |
+
|
1367 |
|
|
+ if (cfun->machine->fp_needed) {
|
1368 |
202 |
dgisselq |
+ if (dbg) fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(FP-NEEDED)\n");
|
1369 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx(stack_pointer_rtx);
|
1370 |
|
|
+ if (dbg) zip_debug_rtx(frame_pointer_rtx);
|
1371 |
202 |
dgisselq |
+ if (cfun->machine->sp_fp_offset < zip_max_mov_offset) {
|
1372 |
|
|
+ if (dbg) fprintf(stderr,
|
1373 |
|
|
+ "PROLOGUE:::EXPAND-SMALL-PROLOGUE() "
|
1374 |
|
|
+ "gen_movsi_reg_off(FP, SP, %d), %d < %ld\n",
|
1375 |
|
|
+ cfun->machine->sp_fp_offset,
|
1376 |
|
|
+ cfun->machine->sp_fp_offset,
|
1377 |
|
|
+ zip_max_mov_offset);
|
1378 |
|
|
+ insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
|
1379 |
124 |
dgisselq |
+ stack_pointer_rtx,
|
1380 |
|
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
1381 |
202 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1382 |
|
|
+ } else {
|
1383 |
|
|
+ rtx fp_rtx;
|
1384 |
|
|
+
|
1385 |
|
|
+ fp_rtx = gen_rtx_REG(SImode, zip_FP);
|
1386 |
|
|
+
|
1387 |
|
|
+ insn = emit_insn(gen_movsi(fp_rtx, stack_pointer_rtx));
|
1388 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1389 |
|
|
+
|
1390 |
|
|
+ insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx,
|
1391 |
|
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
1392 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1393 |
|
|
+ }
|
1394 |
102 |
dgisselq |
+ }
|
1395 |
|
|
+}
|
1396 |
|
|
+
|
1397 |
202 |
dgisselq |
+/*
|
1398 |
|
|
+ * zip_expand_large_prologue()
|
1399 |
|
|
+ *
|
1400 |
|
|
+ * The prologue function will be called when the size_for_adjusting_sp is too
|
1401 |
|
|
+ * large to fit into a single OPB-immediate as part of a subtract.
|
1402 |
|
|
+ *
|
1403 |
|
|
+ * Approach:
|
1404 |
|
|
+ * SUB (size_for_adjusting_sp-sp_fp_offset),SP
|
1405 |
|
|
+ * SW R0,(SP)
|
1406 |
|
|
+ * SW R5,4(SP)
|
1407 |
|
|
+ * SW R6,8SP)
|
1408 |
|
|
+ * SW R7,(SP)
|
1409 |
|
|
+ * ...
|
1410 |
|
|
+ * SW FP,(SP)
|
1411 |
|
|
+ *
|
1412 |
|
|
+ * LDI sp_fp_offset,FP
|
1413 |
|
|
+ * SUB FP,SP
|
1414 |
|
|
+ * ADD SP,FP
|
1415 |
|
|
+ */
|
1416 |
|
|
+void
|
1417 |
|
|
+zip_expand_large_prologue(void) {
|
1418 |
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
1419 |
|
|
+ rtx insn, fp_rtx;
|
1420 |
|
|
+
|
1421 |
|
|
+ gcc_assert(cfun->machine->fp_needed);
|
1422 |
|
|
+
|
1423 |
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE::expand-large(%d-%d)\n",
|
1424 |
|
|
+ cfun->machine->size_for_adjusting_sp,
|
1425 |
|
|
+ cfun->machine->sp_fp_offset);
|
1426 |
|
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
|
1427 |
|
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp
|
1428 |
|
|
+ -cfun->machine->sp_fp_offset, SImode)));
|
1429 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1430 |
|
|
+
|
1431 |
|
|
+ zip_save_registers(stack_pointer_rtx, 0);
|
1432 |
|
|
+
|
1433 |
|
|
+ fp_rtx = gen_rtx_REG(SImode, zip_FP);
|
1434 |
|
|
+
|
1435 |
|
|
+ insn = emit_insn(gen_movsi(fp_rtx,
|
1436 |
|
|
+ gen_int_mode(cfun->machine->sp_fp_offset, SImode)));
|
1437 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1438 |
|
|
+
|
1439 |
|
|
+ insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
|
1440 |
|
|
+ fp_rtx));
|
1441 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1442 |
|
|
+
|
1443 |
|
|
+ insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx, stack_pointer_rtx));
|
1444 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1445 |
|
|
+}
|
1446 |
|
|
+
|
1447 |
|
|
+void
|
1448 |
|
|
+zip_expand_prologue(void) {
|
1449 |
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
1450 |
|
|
+
|
1451 |
|
|
+ zip_compute_frame();
|
1452 |
|
|
+
|
1453 |
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
|
1454 |
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
|
1455 |
|
|
+ cfun->machine->sp_fp_offset);
|
1456 |
|
|
+ if (cfun->machine->size_for_adjusting_sp != 0) {
|
1457 |
|
|
+ if (cfun->machine->size_for_adjusting_sp <= zip_max_anchor_offset) {
|
1458 |
|
|
+ if (dbg) fprintf(stderr, "PROLOGUE: "
|
1459 |
|
|
+ "%d <= %ld, so going small\n",
|
1460 |
|
|
+ cfun->machine->size_for_adjusting_sp,
|
1461 |
|
|
+ zip_max_opb_imm);
|
1462 |
|
|
+ zip_expand_small_prologue();
|
1463 |
|
|
+ } else {
|
1464 |
|
|
+ zip_expand_large_prologue();
|
1465 |
|
|
+ }
|
1466 |
|
|
+ }
|
1467 |
|
|
+}
|
1468 |
|
|
+
|
1469 |
200 |
dgisselq |
+int
|
1470 |
102 |
dgisselq |
+zip_use_return_insn(void)
|
1471 |
|
|
+{
|
1472 |
|
|
+ if ((!reload_completed)||(cfun->machine->fp_needed)
|
1473 |
|
|
+ ||(get_frame_size()!=0)) {
|
1474 |
|
|
+ // If R0 ever gets pushed to the stack, then we cannot
|
1475 |
|
|
+ // use a master return from anywhere. We need to clean up the
|
1476 |
|
|
+ // stack first.
|
1477 |
|
|
+ if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
|
1478 |
|
|
+ &&(!call_used_regs[0]))) {
|
1479 |
200 |
dgisselq |
+ return 0;
|
1480 |
102 |
dgisselq |
+ }
|
1481 |
|
|
+ }
|
1482 |
|
|
+ zip_compute_frame();
|
1483 |
200 |
dgisselq |
+ return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
|
1484 |
102 |
dgisselq |
+}
|
1485 |
|
|
+
|
1486 |
|
|
+/* As per the notes in M68k.c, quote the function epilogue should not depend
|
1487 |
202 |
dgisselq |
+ * upon the current stack pointer. It should use the frame pointer only,
|
1488 |
102 |
dgisselq |
+ * if there is a frame pointer. This is mandatory because of alloca; we also
|
1489 |
|
|
+ * take advantage of it to omit stack adjustments before returning ...
|
1490 |
|
|
+ *
|
1491 |
|
|
+ * Let's see if we can use their approach here.
|
1492 |
|
|
+ *
|
1493 |
|
|
+ * We can't. Consider our choices:
|
1494 |
202 |
dgisselq |
+ * LW (FP),R0
|
1495 |
|
|
+ * LW 4(FP),R4
|
1496 |
|
|
+ * LW 8(FP),R5
|
1497 |
|
|
+ * LW 12(FP),R6
|
1498 |
|
|
+ * LW 16(FP),FP
|
1499 |
102 |
dgisselq |
+ * ... Then what is the stack pointer?
|
1500 |
|
|
+ * or
|
1501 |
202 |
dgisselq |
+ * LW (FP),R0
|
1502 |
|
|
+ * LW 4(FP),R4
|
1503 |
|
|
+ * LW 8(FP),R5
|
1504 |
|
|
+ * LW 12(FP),R6
|
1505 |
102 |
dgisselq |
+ * MOV FP,SP
|
1506 |
202 |
dgisselq |
+ * LW 16(SP),FP
|
1507 |
102 |
dgisselq |
+ * ... Which suffers unnecessary pipeline stalls, and certainly doesn't
|
1508 |
|
|
+ * exploit our pipeline memory function
|
1509 |
|
|
+ * or
|
1510 |
|
|
+ * MOV FP,SP
|
1511 |
202 |
dgisselq |
+ * LW (SP),R0
|
1512 |
|
|
+ * LW 4(SP),R4
|
1513 |
|
|
+ * LW 8(SP),R5
|
1514 |
|
|
+ * LW 12(SP),R6
|
1515 |
|
|
+ * LW 16(SP),FP
|
1516 |
102 |
dgisselq |
+ * Which will be our choice. Note that we do use the stack pointer, eventually.
|
1517 |
|
|
+ *
|
1518 |
|
|
+ */
|
1519 |
|
|
+void
|
1520 |
|
|
+zip_expand_epilogue(void) {
|
1521 |
|
|
+ int regno, offset;
|
1522 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
1523 |
138 |
dgisselq |
+ rtx insn;
|
1524 |
102 |
dgisselq |
+
|
1525 |
|
|
+ zip_compute_frame();
|
1526 |
|
|
+
|
1527 |
|
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
1528 |
|
|
+ if (cfun->machine->fp_needed) {
|
1529 |
124 |
dgisselq |
+ // This is done special--if you can't trust the stack pointer
|
1530 |
|
|
+ // enough so that you must have a frame pointer, then you can't
|
1531 |
|
|
+ // trust its offset enough to restore from it. Hence, we start
|
1532 |
|
|
+ // by moving the frame pointer to the stack pointer to recover
|
1533 |
|
|
+ // the stack pointer back to a usable value.
|
1534 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
|
1535 |
202 |
dgisselq |
+ insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
|
1536 |
138 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1537 |
102 |
dgisselq |
+ }
|
1538 |
|
|
+
|
1539 |
|
|
+ if (cfun->machine->saved_reg_size != 0) {
|
1540 |
124 |
dgisselq |
+ if (cfun->machine->fp_needed)
|
1541 |
|
|
+ offset = 0;
|
1542 |
|
|
+ else
|
1543 |
|
|
+ offset = cfun->machine->sp_fp_offset;
|
1544 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
|
1545 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1546 |
|
|
+ if (zip_save_reg(regno)) {
|
1547 |
202 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d from SP+%d\n", regno, offset);
|
1548 |
138 |
dgisselq |
+ rtx reg = gen_rtx_REG(SImode, regno);
|
1549 |
|
|
+ insn = emit_insn(gen_movsi_lod_off(
|
1550 |
|
|
+ reg,
|
1551 |
124 |
dgisselq |
+ stack_pointer_rtx,
|
1552 |
202 |
dgisselq |
+ GEN_INT(offset)));
|
1553 |
138 |
dgisselq |
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
1554 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1555 |
202 |
dgisselq |
+ offset += 4;
|
1556 |
102 |
dgisselq |
+ }
|
1557 |
|
|
+ }
|
1558 |
|
|
+ }
|
1559 |
|
|
+
|
1560 |
124 |
dgisselq |
+ if (cfun->machine->fp_needed) {
|
1561 |
|
|
+ // Restore the stack pointer back to the original, the
|
1562 |
|
|
+ // difference being the difference from the frame pointer
|
1563 |
|
|
+ // to the original stack
|
1564 |
202 |
dgisselq |
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx,
|
1565 |
138 |
dgisselq |
+ stack_pointer_rtx,
|
1566 |
124 |
dgisselq |
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
1567 |
|
|
+ -cfun->machine->sp_fp_offset)));
|
1568 |
138 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1569 |
124 |
dgisselq |
+ } else {
|
1570 |
|
|
+ // else now the difference is between the stack pointer and
|
1571 |
|
|
+ // the original stack pointer.
|
1572 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
|
1573 |
|
|
+ cfun->machine->size_for_adjusting_sp);
|
1574 |
202 |
dgisselq |
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
|
1575 |
124 |
dgisselq |
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
1576 |
138 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1577 |
102 |
dgisselq |
+ }
|
1578 |
|
|
+ if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
|
1579 |
|
|
+
|
1580 |
138 |
dgisselq |
+ // The return RTX is not allowed to be frame related
|
1581 |
|
|
+ insn = emit_jump_insn(ret_rtx);
|
1582 |
|
|
+ // RTX_FRAME_RELATED_P(insn) = 1;
|
1583 |
102 |
dgisselq |
+}
|
1584 |
|
|
+
|
1585 |
191 |
dgisselq |
+void
|
1586 |
|
|
+zip_sibcall_epilogue(void) {
|
1587 |
|
|
+ int regno, offset;
|
1588 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
1589 |
191 |
dgisselq |
+ rtx insn;
|
1590 |
|
|
+
|
1591 |
|
|
+ zip_compute_frame();
|
1592 |
|
|
+
|
1593 |
|
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
1594 |
|
|
+ if (cfun->machine->fp_needed) {
|
1595 |
|
|
+ // This is done special--if you can't trust the stack pointer
|
1596 |
|
|
+ // enough so that you must have a frame pointer, then you can't
|
1597 |
|
|
+ // trust its offset enough to restore from it. Hence, we start
|
1598 |
|
|
+ // by moving the frame pointer to the stack pointer to recover
|
1599 |
|
|
+ // the stack pointer back to a usable value.
|
1600 |
|
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
|
1601 |
202 |
dgisselq |
+ insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
|
1602 |
191 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1603 |
|
|
+ }
|
1604 |
|
|
+
|
1605 |
|
|
+ if (cfun->machine->saved_reg_size != 0) {
|
1606 |
|
|
+ if (cfun->machine->fp_needed)
|
1607 |
|
|
+ offset = 0;
|
1608 |
|
|
+ else
|
1609 |
|
|
+ offset = cfun->machine->sp_fp_offset;
|
1610 |
|
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
|
1611 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1612 |
|
|
+ if (zip_save_reg(regno)) {
|
1613 |
|
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
|
1614 |
|
|
+ rtx reg = gen_rtx_REG(SImode, regno);
|
1615 |
|
|
+ insn = emit_insn(gen_movsi_lod_off(
|
1616 |
|
|
+ reg,
|
1617 |
|
|
+ stack_pointer_rtx,
|
1618 |
202 |
dgisselq |
+ GEN_INT(offset)));
|
1619 |
191 |
dgisselq |
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
1620 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1621 |
202 |
dgisselq |
+ offset += 4;
|
1622 |
191 |
dgisselq |
+ }
|
1623 |
|
|
+ }
|
1624 |
|
|
+ }
|
1625 |
|
|
+
|
1626 |
|
|
+ if (cfun->machine->fp_needed) {
|
1627 |
|
|
+ // Restore the stack pointer back to the original, the
|
1628 |
|
|
+ // difference being the difference from the frame pointer
|
1629 |
|
|
+ // to the original stack
|
1630 |
202 |
dgisselq |
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
|
1631 |
191 |
dgisselq |
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
1632 |
|
|
+ -cfun->machine->sp_fp_offset)));
|
1633 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1634 |
|
|
+ } else {
|
1635 |
|
|
+ // else now the difference is between the stack pointer and
|
1636 |
|
|
+ // the original stack pointer.
|
1637 |
|
|
+ if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
|
1638 |
|
|
+ cfun->machine->size_for_adjusting_sp);
|
1639 |
202 |
dgisselq |
+ insn = emit_insn(gen_addsi3(stack_pointer_rtx,stack_pointer_rtx,
|
1640 |
191 |
dgisselq |
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
1641 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1642 |
|
|
+ }
|
1643 |
|
|
+}
|
1644 |
|
|
+
|
1645 |
202 |
dgisselq |
+rtx
|
1646 |
|
|
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
|
1647 |
|
|
+{
|
1648 |
|
|
+ //
|
1649 |
|
|
+ // Don't try to compute anything other than frame zero.
|
1650 |
|
|
+ //
|
1651 |
|
|
+ if (count != 0)
|
1652 |
|
|
+ return NULL_RTX;
|
1653 |
|
|
+
|
1654 |
|
|
+ // Make sure we've computed our frame, do we need to save registers?
|
1655 |
|
|
+ zip_compute_frame();
|
1656 |
|
|
+
|
1657 |
|
|
+ if (zip_save_reg(zip_LR)) {
|
1658 |
|
|
+ if (cfun->machine->fp_needed)
|
1659 |
|
|
+ return gen_rtx_MEM(SImode, frame_pointer_rtx);
|
1660 |
|
|
+ else
|
1661 |
|
|
+ return gen_rtx_MEM(SImode, gen_rtx_PLUS(Pmode,
|
1662 |
|
|
+ stack_pointer_rtx,
|
1663 |
|
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
1664 |
|
|
+ } else {
|
1665 |
|
|
+ return gen_rtx_REG(Pmode, zip_LR);
|
1666 |
|
|
+
|
1667 |
|
|
+ }
|
1668 |
|
|
+}
|
1669 |
|
|
+
|
1670 |
102 |
dgisselq |
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
|
1671 |
|
|
+ *
|
1672 |
|
|
+ * We currently only support calculating the return address for the current
|
1673 |
|
|
+ * frame.
|
1674 |
|
|
+ */
|
1675 |
|
|
+
|
1676 |
|
|
+/*
|
1677 |
|
|
+rtx
|
1678 |
|
|
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
|
1679 |
|
|
+{
|
1680 |
|
|
+ if (count)
|
1681 |
|
|
+ return NULL_RTX;
|
1682 |
|
|
+
|
1683 |
|
|
+ zip_compute_frame();
|
1684 |
|
|
+
|
1685 |
|
|
+ // saved return address for current function is at fp - 1
|
1686 |
|
|
+ if (cfun->machine->save_ret)
|
1687 |
|
|
+ return gen_rtx_MEM(Pmode, plus_constant(frame_pointer_rtx,
|
1688 |
|
|
+ -UNITS_PER_WORD));
|
1689 |
|
|
+ return get_hard_reg_initial_val(Pmode, RETURN_ADDRESS_REGNUM);
|
1690 |
|
|
+}
|
1691 |
|
|
+*/
|
1692 |
|
|
+
|
1693 |
|
|
+/* Implements the macro INITIAL_ELIMINATION_OFFSET,
|
1694 |
|
|
+ * return the OFFSET.
|
1695 |
|
|
+ */
|
1696 |
|
|
+int
|
1697 |
|
|
+zip_initial_elimination_offset(int from, int to) {
|
1698 |
|
|
+ int ret = 0;
|
1699 |
|
|
+ zip_compute_frame();
|
1700 |
|
|
+
|
1701 |
171 |
dgisselq |
+/*
|
1702 |
102 |
dgisselq |
+ if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
|
1703 |
|
|
+ ret = cfun->machine->sp_fp_offset;
|
1704 |
117 |
dgisselq |
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
|
1705 |
171 |
dgisselq |
+ // Since the ARG_POINTER_REGNUM is defined to be identical
|
1706 |
|
|
+ // to the FRAME_POINTER_REGNUM, this "if" will never ever
|
1707 |
|
|
+ // get called.
|
1708 |
117 |
dgisselq |
+ ret = cfun->machine->sp_fp_offset;
|
1709 |
102 |
dgisselq |
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
|
1710 |
171 |
dgisselq |
+ // Since we define ARG_POINTER_REGNUM to be FRAME_POINTER_REGNUM
|
1711 |
|
|
+ // we're asked for the offset between the frame pointer and
|
1712 |
|
|
+ // itself. The result had better be zero.
|
1713 |
|
|
+ //
|
1714 |
117 |
dgisselq |
+ ret = 0;
|
1715 |
102 |
dgisselq |
+ } else {
|
1716 |
|
|
+ abort();
|
1717 |
|
|
+ }
|
1718 |
171 |
dgisselq |
+*/
|
1719 |
102 |
dgisselq |
+
|
1720 |
171 |
dgisselq |
+ // Let's try using an ARG_POINTER != FRAME_POINTER
|
1721 |
|
|
+ if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
|
1722 |
|
|
+ ret = cfun->machine->sp_fp_offset;
|
1723 |
|
|
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
|
1724 |
|
|
+ // Since the ARG_POINTER_REGNUM is defined to be identical
|
1725 |
|
|
+ // to the FRAME_POINTER_REGNUM, this "if" will never ever
|
1726 |
|
|
+ // get called.
|
1727 |
|
|
+ ret = cfun->machine->size_for_adjusting_sp;
|
1728 |
|
|
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
|
1729 |
|
|
+ ret = cfun->machine->size_for_adjusting_sp
|
1730 |
|
|
+ - cfun->machine->sp_fp_offset;
|
1731 |
|
|
+ } else {
|
1732 |
|
|
+ abort();
|
1733 |
|
|
+ }
|
1734 |
|
|
+
|
1735 |
102 |
dgisselq |
+ return ret;
|
1736 |
|
|
+}
|
1737 |
|
|
+
|
1738 |
|
|
+/*
|
1739 |
|
|
+ * Code taken from m68k ...
|
1740 |
|
|
+ */
|
1741 |
|
|
+static bool
|
1742 |
|
|
+zip_can_eliminate(int from, int to)
|
1743 |
|
|
+{
|
1744 |
|
|
+ // fprintf(stderr, "CAN_ELIMINATE::QUERYING(%d,%d)\n", from, to);
|
1745 |
|
|
+ if ((from == zip_FP)&&(to == zip_SP))
|
1746 |
|
|
+ return !cfun->machine->fp_needed;
|
1747 |
|
|
+ return true;
|
1748 |
|
|
+}
|
1749 |
|
|
+
|
1750 |
171 |
dgisselq |
+/* Compute the number of word sized registers needed to hold a function
|
1751 |
102 |
dgisselq |
+ * argument of mode INT_MODE and tree type TYPE.
|
1752 |
|
|
+ */
|
1753 |
|
|
+int
|
1754 |
|
|
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
|
1755 |
|
|
+ int size;
|
1756 |
|
|
+
|
1757 |
|
|
+ if (targetm.calls.must_pass_in_stack(mode, type))
|
1758 |
|
|
+ return 0;
|
1759 |
|
|
+
|
1760 |
|
|
+ if ((type)&&(mode == BLKmode))
|
1761 |
|
|
+ size = int_size_in_bytes(type);
|
1762 |
|
|
+ else
|
1763 |
|
|
+ size = GET_MODE_SIZE(mode);
|
1764 |
|
|
+
|
1765 |
|
|
+ return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
|
1766 |
|
|
+}
|
1767 |
|
|
+
|
1768 |
|
|
+static void
|
1769 |
|
|
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
|
1770 |
|
|
+ const_tree type, bool named ATTRIBUTE_UNUSED) {
|
1771 |
|
|
+ CUMULATIVE_ARGS *cum;
|
1772 |
|
|
+ int nreg;
|
1773 |
|
|
+
|
1774 |
|
|
+ cum = get_cumulative_args(ca);
|
1775 |
|
|
+ nreg = zip_num_arg_regs(mode, type);
|
1776 |
|
|
+ if (((*cum)+nreg) > NUM_ARG_REGS)
|
1777 |
|
|
+ (*cum) = NUM_ARG_REGS;
|
1778 |
|
|
+ else
|
1779 |
|
|
+ (*cum) += nreg;
|
1780 |
|
|
+}
|
1781 |
|
|
+
|
1782 |
|
|
+static rtx
|
1783 |
|
|
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
|
1784 |
|
|
+ const_tree type ATTRIBUTE_UNUSED, bool named) {
|
1785 |
|
|
+ CUMULATIVE_ARGS *cum;
|
1786 |
|
|
+
|
1787 |
|
|
+ if (!named)
|
1788 |
|
|
+ return NULL_RTX;
|
1789 |
|
|
+ cum = get_cumulative_args(ca);
|
1790 |
|
|
+
|
1791 |
|
|
+ if ((*cum) >= NUM_ARG_REGS)
|
1792 |
|
|
+ return NULL_RTX;
|
1793 |
|
|
+ return
|
1794 |
|
|
+ gen_rtx_REG(mode, (*cum)+1);
|
1795 |
|
|
+}
|
1796 |
|
|
+
|
1797 |
191 |
dgisselq |
+/* DECL is the declaration of the function being targeted by the call, and EXP
|
1798 |
|
|
+ * is the CALL_EXPR representing the call.
|
1799 |
|
|
+ */
|
1800 |
|
|
+bool zip_function_ok_for_sibcall(ATTRIBUTE_UNUSED tree decl, tree exp) {
|
1801 |
|
|
+ // calls.c already checks whether or not the parameter stack space
|
1802 |
|
|
+ // is identical, so ... let's hope this all works and find out.
|
1803 |
|
|
+
|
1804 |
|
|
+ //
|
1805 |
|
|
+ // Actually, this will fail: If the sibling uses R5 to pass registers
|
1806 |
|
|
+ // in and we don't, then there will be no way to restore R5. This is
|
1807 |
|
|
+ // true for the current configuration. It will be true for future
|
1808 |
|
|
+ // configurations if the sibling ever uses a register that must be
|
1809 |
|
|
+ // saved as a parameter register.
|
1810 |
|
|
+ //
|
1811 |
|
|
+ // We can check this ... if we can count how many registers the
|
1812 |
|
|
+ // sibling call will use.
|
1813 |
|
|
+ //
|
1814 |
|
|
+ CUMULATIVE_ARGS cum_v;
|
1815 |
|
|
+ cumulative_args_t cum;
|
1816 |
|
|
+ tree parameter;
|
1817 |
|
|
+ machine_mode mode;
|
1818 |
|
|
+ tree ttype;
|
1819 |
|
|
+ rtx parm_rtx;
|
1820 |
|
|
+ int i;
|
1821 |
|
|
+ static const char zip_call_used_register[] = CALL_USED_REGISTERS;
|
1822 |
|
|
+
|
1823 |
|
|
+ INIT_CUMULATIVE_ARGS(cum_v, NULL, NULL, 0,0);
|
1824 |
|
|
+ cum = pack_cumulative_args(&cum_v);
|
1825 |
|
|
+ for (i=0; i<call_expr_nargs(exp); i++) {
|
1826 |
|
|
+
|
1827 |
|
|
+ parameter = CALL_EXPR_ARG(exp, i);
|
1828 |
|
|
+
|
1829 |
|
|
+ if ((!parameter) || (TREE_CODE(parameter)==ERROR_MARK))
|
1830 |
|
|
+ return true;
|
1831 |
|
|
+ ttype = TREE_TYPE(parameter);
|
1832 |
|
|
+ gcc_assert(ttype);
|
1833 |
|
|
+ mode = ttype->type_common.mode;
|
1834 |
|
|
+
|
1835 |
|
|
+ if (pass_by_reference(&cum_v, mode, ttype, true)) {
|
1836 |
|
|
+ mode = Pmode;
|
1837 |
|
|
+ ttype = build_pointer_type(ttype);
|
1838 |
|
|
+ }
|
1839 |
|
|
+
|
1840 |
|
|
+ parm_rtx = zip_function_arg(cum, mode, ttype, 0);
|
1841 |
|
|
+ zip_function_arg_advance(cum, mode, ttype, 0);
|
1842 |
|
|
+ if (!parm_rtx)
|
1843 |
|
|
+ continue;
|
1844 |
|
|
+
|
1845 |
|
|
+ // If it is a register
|
1846 |
|
|
+ // and it is *NOT* a CALL_USED_REGISTER
|
1847 |
|
|
+ // then we can't do this.
|
1848 |
|
|
+ //
|
1849 |
|
|
+ // Example: func(R1,..R4,R5)
|
1850 |
|
|
+ // can be followed by func2(R1,.., up to R5)
|
1851 |
|
|
+ // (not supported, though... just to simplify our test
|
1852 |
|
|
+ // below)
|
1853 |
|
|
+ // Example: func(R1,..R4)
|
1854 |
|
|
+ // cannot be followed by func2(R1,..,R5)
|
1855 |
|
|
+ // We would blow R5 away by our prologue, even if it was
|
1856 |
|
|
+ // properly set.
|
1857 |
|
|
+ // Example: func(R1,..R5)
|
1858 |
|
|
+ // can be followed by func2(R1,.., up to R4)
|
1859 |
|
|
+ // func2 may save R5 (which doesn't need saving) but that's
|
1860 |
|
|
+ // irrelevant
|
1861 |
|
|
+ // Example: func(R1,..up to R4)
|
1862 |
|
|
+ // can be followed by func2(R1,.., up to R4)
|
1863 |
|
|
+ //
|
1864 |
|
|
+ if (REG_P(parm_rtx)&&(REGNO(parm_rtx))
|
1865 |
|
|
+ &&(REGNO(parm_rtx)<sizeof(zip_call_used_register))
|
1866 |
|
|
+ &&(!zip_call_used_register[REGNO(parm_rtx)]))
|
1867 |
|
|
+ return false;
|
1868 |
|
|
+ }
|
1869 |
|
|
+
|
1870 |
|
|
+ return true;
|
1871 |
|
|
+
|
1872 |
|
|
+ // We also need to check if the return types are the same ... or
|
1873 |
|
|
+ // will GCC handle that for us?
|
1874 |
|
|
+}
|
1875 |
|
|
+
|
1876 |
122 |
dgisselq |
+void zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
|
1877 |
|
|
+ bool preserve_op0)
|
1878 |
|
|
+{
|
1879 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
1880 |
|
|
+ bool reverse = false;
|
1881 |
102 |
dgisselq |
+
|
1882 |
122 |
dgisselq |
+ if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
|
1883 |
|
|
+ if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
|
1884 |
|
|
+ if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
|
1885 |
|
|
+ if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
|
1886 |
|
|
+
|
1887 |
202 |
dgisselq |
+ // Z -> Z
|
1888 |
|
|
+ // NZ -> !Z
|
1889 |
|
|
+ // LT -> N
|
1890 |
|
|
+ // GE -> !N
|
1891 |
|
|
+ // LTU -> C
|
1892 |
|
|
+ // GEU -> !C
|
1893 |
|
|
+ //
|
1894 |
|
|
+ // LTE -> GTE w/ swapped operands
|
1895 |
|
|
+ // GT -> LT w/ swapped operands
|
1896 |
|
|
+ // GTU -> LTU w/ swapped operands
|
1897 |
|
|
+ // LEU -> GEU w/ swapped operands
|
1898 |
|
|
+ //
|
1899 |
|
|
+
|
1900 |
|
|
+ if ((CONST_INT_P(*op0))||(GET_CODE(*op0) == PLUS)) {
|
1901 |
|
|
+ rtx tmp = *op0;
|
1902 |
122 |
dgisselq |
+ *op0 = *op1;
|
1903 |
202 |
dgisselq |
+ *op1 = tmp;
|
1904 |
122 |
dgisselq |
+ *code = (int)swap_condition((enum rtx_code)*code);
|
1905 |
|
|
+ }
|
1906 |
|
|
+
|
1907 |
202 |
dgisselq |
+ if (*code == GTU) {
|
1908 |
|
|
+ if (REG_P(*op1)) {
|
1909 |
|
|
+ //; Reverse the comparison
|
1910 |
|
|
+ reverse = true;
|
1911 |
|
|
+ } else if (CONST_INT_P(*op1)) {
|
1912 |
|
|
+ //; A > B
|
1913 |
|
|
+ //; A >= B+1
|
1914 |
|
|
+ //; Add one to the integer constant,
|
1915 |
|
|
+ //; And use a GEU comparison
|
1916 |
|
|
+ *code = GEU;
|
1917 |
|
|
+ *op1 = GEN_INT(INTVAL(*op1)+1);
|
1918 |
|
|
+ } else {
|
1919 |
|
|
+ //; Reverse the comparison
|
1920 |
|
|
+ reverse = true;
|
1921 |
122 |
dgisselq |
+ }
|
1922 |
202 |
dgisselq |
+ } else if (*code == LEU) {
|
1923 |
|
|
+ if (REG_P(*op1)) {
|
1924 |
|
|
+ reverse = true;
|
1925 |
|
|
+ } else if (CONST_INT_P(*op1)) {
|
1926 |
|
|
+ //; A <= B
|
1927 |
|
|
+ //; A < B+1
|
1928 |
|
|
+ //; Add one to the integer constant,
|
1929 |
|
|
+ //; And use a GTU comparison
|
1930 |
|
|
+ *op1 = GEN_INT(INTVAL(*op1)+1);
|
1931 |
|
|
+ *code = LTU;
|
1932 |
|
|
+ } else {
|
1933 |
|
|
+ reverse = true;
|
1934 |
|
|
+ }
|
1935 |
|
|
+ } else if (*code == LE) {
|
1936 |
|
|
+ if (REG_P(*op1)) {
|
1937 |
|
|
+ reverse = true;
|
1938 |
|
|
+ } else if (CONST_INT_P(*op1)) {
|
1939 |
|
|
+ //; A < B
|
1940 |
|
|
+ //; A <= B-1
|
1941 |
|
|
+ //; Add one to the integer constant,
|
1942 |
|
|
+ //; And use a GTU comparison
|
1943 |
|
|
+ *op1 = GEN_INT(INTVAL(*op1)-1);
|
1944 |
|
|
+ *code = LT;
|
1945 |
|
|
+ } else {
|
1946 |
|
|
+ reverse = true;
|
1947 |
|
|
+ }
|
1948 |
|
|
+ } else if (*code == GT) {
|
1949 |
|
|
+ if (REG_P(*op1)) {
|
1950 |
|
|
+ //; Reverse the comparison
|
1951 |
|
|
+ reverse = true;
|
1952 |
|
|
+ } else if (CONST_INT_P(*op1)) {
|
1953 |
|
|
+ //; A > B
|
1954 |
|
|
+ //; A >= B+1
|
1955 |
|
|
+ //; Add one to the integer constant,
|
1956 |
|
|
+ //; And use a GTU comparison
|
1957 |
|
|
+ *op1 = GEN_INT(INTVAL(*op1)+1);
|
1958 |
|
|
+ *code = GE;
|
1959 |
|
|
+ } else {
|
1960 |
|
|
+ reverse = true;
|
1961 |
|
|
+ }
|
1962 |
122 |
dgisselq |
+ }
|
1963 |
202 |
dgisselq |
+
|
1964 |
|
|
+ if (reverse) {
|
1965 |
|
|
+ rtx tem = *op0;
|
1966 |
|
|
+ *op0 = *op1;
|
1967 |
|
|
+ *op1 = tem;
|
1968 |
|
|
+ *code = (int)swap_condition((enum rtx_code)*code);
|
1969 |
|
|
+ }
|
1970 |
122 |
dgisselq |
+}
|
1971 |
|
|
+
|
1972 |
|
|
+static bool
|
1973 |
|
|
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
|
1974 |
|
|
+ *a = zip_CC;
|
1975 |
|
|
+ *b = INVALID_REGNUM;
|
1976 |
|
|
+ return true;
|
1977 |
|
|
+}
|
1978 |
|
|
+
|
1979 |
|
|
+
|
1980 |
102 |
dgisselq |
+/* totally buggy - we can't return pointers to nested functions */
|
1981 |
|
|
+static void
|
1982 |
202 |
dgisselq |
+zip_asm_trampoline_template(FILE *f)
|
1983 |
|
|
+{
|
1984 |
138 |
dgisselq |
+ fprintf(f, "\tbrev\t0,r1\n");
|
1985 |
|
|
+ fprintf(f, "\tldilo\t0,r1\n");
|
1986 |
102 |
dgisselq |
+ fprintf(f, "\tjmp r1\n");
|
1987 |
|
|
+}
|
1988 |
|
|
+
|
1989 |
|
|
+/* Worker function for TARGET_TRAMPOLINE_INIT. */
|
1990 |
|
|
+static void
|
1991 |
|
|
+zip_trampoline_init(rtx m_tramp ATTRIBUTE_UNUSED,
|
1992 |
|
|
+ tree fndecl ATTRIBUTE_UNUSED,
|
1993 |
|
|
+ rtx chain_value ATTRIBUTE_UNUSED) {
|
1994 |
|
|
+// #warning "This needs to be filled out"
|
1995 |
|
|
+ abort();
|
1996 |
|
|
+}
|
1997 |
|
|
+
|
1998 |
|
|
+static tree
|
1999 |
|
|
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
|
2000 |
|
|
+ tree type)
|
2001 |
|
|
+{
|
2002 |
202 |
dgisselq |
+ tree t = add_builtin_function(name,type,code, BUILT_IN_MD, NULL, NULL_TREE);
|
2003 |
102 |
dgisselq |
+
|
2004 |
|
|
+ if(t) {
|
2005 |
|
|
+ zip_builtins[code] = t;
|
2006 |
|
|
+ zip_builtins_icode[code] = icode;
|
2007 |
|
|
+ }
|
2008 |
|
|
+
|
2009 |
|
|
+ return t;
|
2010 |
|
|
+
|
2011 |
|
|
+}
|
2012 |
|
|
+
|
2013 |
|
|
+void zip_init_builtins(void) {
|
2014 |
|
|
+
|
2015 |
|
|
+ tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
|
2016 |
|
|
+#ifdef HAVE_zip_rtu
|
2017 |
|
|
+ def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
|
2018 |
|
|
+#endif
|
2019 |
|
|
+#ifdef HAVE_zip_halt
|
2020 |
|
|
+ def_builtin("zip_halt", CODE_FOR_zip_halt, ZIP_BUILTIN_HALT, void_ftype_void);
|
2021 |
|
|
+#endif
|
2022 |
171 |
dgisselq |
+#ifdef HAVE_zip_busy
|
2023 |
|
|
+ def_builtin("zip_busy", CODE_FOR_zip_busy, ZIP_BUILTIN_BUSY, void_ftype_void);
|
2024 |
|
|
+#endif
|
2025 |
102 |
dgisselq |
+#ifdef HAVE_zip_idle
|
2026 |
|
|
+ def_builtin("zip_idle", CODE_FOR_zip_idle, ZIP_BUILTIN_IDLE, void_ftype_void);
|
2027 |
|
|
+#endif
|
2028 |
|
|
+
|
2029 |
|
|
+#ifdef HAVE_zip_syscall
|
2030 |
|
|
+// Support int SYSCALL(callID, int a, int b, int c);
|
2031 |
|
|
+ def_builtin("zip_syscall", CODE_FOR_zip_syscall, ZIP_BUILTIN_SYSCALL,
|
2032 |
|
|
+ build_function_type_list(void_type_node, NULL_TREE));
|
2033 |
|
|
+#endif
|
2034 |
|
|
+
|
2035 |
|
|
+#ifdef HAVE_zip_save_context
|
2036 |
|
|
+ def_builtin("zip_save_context", CODE_FOR_zip_save_context, ZIP_BUILTIN_SAVE_CONTEXT,
|
2037 |
|
|
+ build_function_type_list(void_type_node, ptr_type_node, 0));
|
2038 |
|
|
+#endif
|
2039 |
|
|
+
|
2040 |
|
|
+#ifdef HAVE_zip_restore_context
|
2041 |
|
|
+ def_builtin("zip_restore_context", CODE_FOR_zip_restore_context, ZIP_BUILTIN_RESTORE_CONTEXT,
|
2042 |
|
|
+ build_function_type_list(void_type_node, ptr_type_node, 0));
|
2043 |
|
|
+#endif
|
2044 |
|
|
+
|
2045 |
|
|
+#ifdef HAVE_zip_bitrev
|
2046 |
|
|
+ def_builtin("zip_bitrev", CODE_FOR_zip_bitrev, ZIP_BUILTIN_BITREV,
|
2047 |
|
|
+ build_function_type_list(unsigned_type_node, unsigned_type_node,
|
2048 |
|
|
+ NULL_TREE));
|
2049 |
|
|
+#endif
|
2050 |
|
|
+
|
2051 |
|
|
+#ifdef HAVE_zip_cc
|
2052 |
|
|
+ def_builtin("zip_cc", CODE_FOR_zip_cc, ZIP_BUILTIN_CC,
|
2053 |
|
|
+ build_function_type_list(unsigned_type_node, NULL_TREE));
|
2054 |
|
|
+#endif
|
2055 |
|
|
+
|
2056 |
117 |
dgisselq |
+#ifdef HAVE_zip_ucc
|
2057 |
|
|
+ def_builtin("zip_ucc", CODE_FOR_zip_ucc, ZIP_BUILTIN_UCC,
|
2058 |
|
|
+ build_function_type_list(unsigned_type_node, NULL_TREE));
|
2059 |
|
|
+#endif
|
2060 |
|
|
+
|
2061 |
102 |
dgisselq |
+}
|
2062 |
|
|
+
|
2063 |
|
|
+static tree
|
2064 |
|
|
+zip_builtin_decl(unsigned zip_builtin_code, bool initialize_p ATTRIBUTE_UNUSED)
|
2065 |
|
|
+{
|
2066 |
|
|
+ if (zip_builtin_code >= ZIP_BUILTIN_MAX)
|
2067 |
|
|
+ return error_mark_node;
|
2068 |
|
|
+
|
2069 |
|
|
+ return zip_builtins[zip_builtin_code];
|
2070 |
|
|
+}
|
2071 |
|
|
+
|
2072 |
|
|
+static rtx
|
2073 |
|
|
+zip_expand_builtin(tree exp, rtx target,
|
2074 |
|
|
+ rtx subtarget ATTRIBUTE_UNUSED,
|
2075 |
|
|
+ machine_mode tmode ATTRIBUTE_UNUSED,
|
2076 |
202 |
dgisselq |
+ int ignore ATTRIBUTE_UNUSED)
|
2077 |
|
|
+{
|
2078 |
102 |
dgisselq |
+ tree fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
|
2079 |
|
|
+ bool nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
|
2080 |
|
|
+ enum ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
|
2081 |
|
|
+ enum insn_code icode = zip_builtins_icode[code];
|
2082 |
|
|
+ rtx pat, op[5];
|
2083 |
|
|
+ call_expr_arg_iterator iter;
|
2084 |
|
|
+ tree arg;
|
2085 |
|
|
+
|
2086 |
|
|
+ if ((code == ZIP_BUILTIN_SAVE_CONTEXT)
|
2087 |
|
|
+ ||(code == ZIP_BUILTIN_RESTORE_CONTEXT)) {
|
2088 |
|
|
+ arg = first_call_expr_arg(exp, &iter);
|
2089 |
|
|
+ if (arg == error_mark_node)
|
2090 |
|
|
+ return NULL_RTX;
|
2091 |
|
|
+ op[0] = expand_normal(arg);
|
2092 |
|
|
+ if (GET_CODE(op[0]) != REG)
|
2093 |
|
|
+ op[0] = force_reg(Pmode, op[0]);
|
2094 |
|
|
+ pat = GEN_FCN(icode)(op[0]);
|
2095 |
|
|
+ } else if (code == ZIP_BUILTIN_BITREV) {
|
2096 |
|
|
+ arg = first_call_expr_arg(exp, &iter);
|
2097 |
|
|
+ if (arg == error_mark_node) {
|
2098 |
|
|
+ return NULL_RTX;
|
2099 |
|
|
+ }
|
2100 |
|
|
+ op[0] = expand_normal(arg);
|
2101 |
|
|
+ if (!target)
|
2102 |
|
|
+ target = gen_reg_rtx(SImode);
|
2103 |
|
|
+ pat = GEN_FCN(icode)(target, op[0]);
|
2104 |
117 |
dgisselq |
+ } else if ((code == ZIP_BUILTIN_CC)||(code == ZIP_BUILTIN_UCC)) {
|
2105 |
102 |
dgisselq |
+ if (!target)
|
2106 |
|
|
+ target = gen_reg_rtx(SImode);
|
2107 |
|
|
+ pat = GEN_FCN(icode)(target);
|
2108 |
|
|
+ } else // RTU, HALT, IDLE
|
2109 |
|
|
+ pat = GEN_FCN(icode)();
|
2110 |
|
|
+ if (!pat)
|
2111 |
|
|
+ return NULL_RTX;
|
2112 |
|
|
+ emit_insn(pat);
|
2113 |
|
|
+ return (nonvoid ? target : const0_rtx);
|
2114 |
|
|
+}
|
2115 |
|
|
+
|
2116 |
|
|
+static bool
|
2117 |
202 |
dgisselq |
+zip_scalar_mode_supported_p(enum machine_mode mode)
|
2118 |
|
|
+{
|
2119 |
|
|
+ if ((ZIP_HAS_DI)&&(mode == DImode))
|
2120 |
|
|
+ return true;
|
2121 |
|
|
+ if ((mode==SImode)||(mode==HImode)||(mode==QImode))
|
2122 |
|
|
+ return true;
|
2123 |
|
|
+ if (mode==SFmode) // &&(ZIP_FPU)
|
2124 |
|
|
+ return true; // If (!ZIP_CPU), will need to be emulated
|
2125 |
|
|
+ if (mode==DFmode) // Must always be emulated
|
2126 |
|
|
+ return true;
|
2127 |
|
|
+ return false;
|
2128 |
102 |
dgisselq |
+}
|
2129 |
|
|
+
|
2130 |
|
|
+static bool
|
2131 |
202 |
dgisselq |
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode)
|
2132 |
|
|
+{
|
2133 |
102 |
dgisselq |
+ return ((mode)==SFmode)||((mode)==DFmode);
|
2134 |
|
|
+}
|
2135 |
|
|
+
|
2136 |
|
|
+static int
|
2137 |
|
|
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
|
2138 |
|
|
+ enum machine_mode mode ATTRIBUTE_UNUSED,
|
2139 |
|
|
+ addr_space_t as ATTRIBUTE_UNUSED, bool spd ATTRIBUTE_UNUSED) {
|
2140 |
|
|
+ return 1;
|
2141 |
|
|
+}
|
2142 |
|
|
+
|
2143 |
|
|
+static bool
|
2144 |
|
|
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
|
2145 |
|
|
+ addr_space_t as ATTRIBUTE_UNUSED) {
|
2146 |
|
|
+ return false;
|
2147 |
|
|
+}
|
2148 |
|
|
+
|
2149 |
|
|
+static void
|
2150 |
|
|
+zip_debug_print(const char *pfx, int lvl, const char *str) {
|
2151 |
|
|
+ int i;
|
2152 |
|
|
+ i = lvl;
|
2153 |
|
|
+ if ((true)||(lvl == 0))
|
2154 |
|
|
+ fprintf(stderr, "%s", pfx);
|
2155 |
|
|
+ else
|
2156 |
|
|
+ i += strlen(pfx);
|
2157 |
|
|
+ while(i-->0)
|
2158 |
|
|
+ fprintf(stderr, " ");
|
2159 |
|
|
+ fprintf(stderr, "%s\n", str);
|
2160 |
|
|
+}
|
2161 |
|
|
+
|
2162 |
|
|
+static void
|
2163 |
|
|
+zip_debug_print_m(const char *pfx, int lvl, const char *str, enum machine_mode m) {
|
2164 |
|
|
+ int i;
|
2165 |
|
|
+
|
2166 |
|
|
+ i = lvl;
|
2167 |
|
|
+ if ((true)||(lvl == 0))
|
2168 |
|
|
+ fprintf(stderr, "%s", pfx);
|
2169 |
|
|
+ else
|
2170 |
|
|
+ i = lvl+strlen(pfx);
|
2171 |
|
|
+ while(i-->0)
|
2172 |
|
|
+ fprintf(stderr, " ");
|
2173 |
|
|
+ switch(m) {
|
2174 |
|
|
+ case VOIDmode:
|
2175 |
|
|
+ fprintf(stderr, "%s:V\n", str);
|
2176 |
|
|
+ break;
|
2177 |
|
|
+ case BLKmode:
|
2178 |
|
|
+ fprintf(stderr, "%s:BLK\n", str);
|
2179 |
|
|
+ break;
|
2180 |
|
|
+ case BImode:
|
2181 |
|
|
+ fprintf(stderr, "%s:BI\n", str);
|
2182 |
|
|
+ break;
|
2183 |
|
|
+ case QImode:
|
2184 |
|
|
+ fprintf(stderr, "%s:QI\n", str);
|
2185 |
|
|
+ break;
|
2186 |
|
|
+ case HImode:
|
2187 |
|
|
+ fprintf(stderr, "%s:HI\n", str);
|
2188 |
|
|
+ break;
|
2189 |
202 |
dgisselq |
+#ifdef HAVE_SImode
|
2190 |
102 |
dgisselq |
+ case SImode:
|
2191 |
|
|
+ fprintf(stderr, "%s:SI\n", str);
|
2192 |
|
|
+ break;
|
2193 |
202 |
dgisselq |
+#endif
|
2194 |
|
|
+#ifdef HAVE_DImode
|
2195 |
|
|
+ case DImode:
|
2196 |
|
|
+ fprintf(stderr, "%s:DI\n", str);
|
2197 |
|
|
+ break;
|
2198 |
|
|
+#endif
|
2199 |
122 |
dgisselq |
+ case CCmode:
|
2200 |
|
|
+ fprintf(stderr, "%s:CC\n", str);
|
2201 |
|
|
+ break;
|
2202 |
102 |
dgisselq |
+ default:
|
2203 |
|
|
+ fprintf(stderr, "%s:?\n", str);
|
2204 |
|
|
+ }
|
2205 |
|
|
+}
|
2206 |
|
|
+
|
2207 |
|
|
+static void
|
2208 |
|
|
+zip_debug_rtx_1(const char *pfx, const_rtx x, int lvl) {
|
2209 |
|
|
+ if (x == NULL_RTX) {
|
2210 |
|
|
+ zip_debug_print(pfx, lvl, "(NULL-RTX)");
|
2211 |
|
|
+ return;
|
2212 |
|
|
+ } else if (GET_CODE(x) > NUM_RTX_CODE) {
|
2213 |
|
|
+ char buf[64];
|
2214 |
|
|
+ sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
|
2215 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2216 |
117 |
dgisselq |
+ gcc_assert(0 && "Bad RTX Code");
|
2217 |
102 |
dgisselq |
+ return;
|
2218 |
|
|
+ } switch(GET_CODE(x)) { // rtl.def
|
2219 |
122 |
dgisselq |
+ case PARALLEL:
|
2220 |
|
|
+ zip_debug_print(pfx, lvl, "(PARALLEL");
|
2221 |
202 |
dgisselq |
+ if (XVEC(x,0) != NULL)
|
2222 |
|
|
+ for(int j=0; j<XVECLEN(x,0);j++)
|
2223 |
|
|
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
|
2224 |
122 |
dgisselq |
+ zip_debug_print(pfx, lvl, ")");
|
2225 |
|
|
+ debug_rtx(x);
|
2226 |
|
|
+ break;
|
2227 |
102 |
dgisselq |
+ case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
|
2228 |
122 |
dgisselq |
+ case SEQUENCE:
|
2229 |
|
|
+ zip_debug_print(pfx, lvl, "(SEQUENCE");
|
2230 |
|
|
+ for(int j=0; j<XVECLEN(x,0);j++)
|
2231 |
|
|
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
|
2232 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2233 |
|
|
+ debug_rtx(x);
|
2234 |
|
|
+ break;
|
2235 |
102 |
dgisselq |
+ case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
|
2236 |
|
|
+ case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
|
2237 |
|
|
+ case INSN:
|
2238 |
|
|
+ zip_debug_print(pfx, lvl, "(INSN");
|
2239 |
|
|
+ /*
|
2240 |
|
|
+ { const rtx_insn *tmp_rtx;
|
2241 |
|
|
+ for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
|
2242 |
|
|
+ zip_debug_rtx_1(tmp_rtx, lvl+1);
|
2243 |
|
|
+ }}
|
2244 |
|
|
+ */
|
2245 |
|
|
+ zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
|
2246 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2247 |
117 |
dgisselq |
+ debug_rtx(x);
|
2248 |
102 |
dgisselq |
+ break;
|
2249 |
|
|
+ case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
|
2250 |
111 |
dgisselq |
+ zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
|
2251 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2252 |
|
|
+ /*
|
2253 |
102 |
dgisselq |
+ if (JUMP_LABEL(x)) {
|
2254 |
111 |
dgisselq |
+ if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
|
2255 |
|
|
+ char buf[64];
|
2256 |
|
|
+ sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
|
2257 |
|
|
+ zip_debug_print(pfx, lvl+1, buf);
|
2258 |
|
|
+ } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
|
2259 |
|
|
+ char buf[64];
|
2260 |
|
|
+ sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
|
2261 |
|
|
+ zip_debug_print(pfx, lvl+1, buf);
|
2262 |
|
|
+ } else
|
2263 |
|
|
+ zip_debug_print(pfx, lvl+1, "(w/Label))");
|
2264 |
102 |
dgisselq |
+ } else
|
2265 |
111 |
dgisselq |
+ zip_debug_print(pfx, lvl+1, "(NO label))");
|
2266 |
|
|
+ debug_rtx(x);
|
2267 |
|
|
+ */
|
2268 |
102 |
dgisselq |
+ break;
|
2269 |
|
|
+ case CALL:
|
2270 |
|
|
+ zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
|
2271 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
|
2272 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
|
2273 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2274 |
|
|
+ break;
|
2275 |
|
|
+ case CALL_INSN: zip_debug_print(pfx, lvl, "(CALL-INSN");
|
2276 |
|
|
+ debug_rtx(x);
|
2277 |
|
|
+ break;
|
2278 |
|
|
+ case BARRIER: zip_debug_print(pfx, lvl, "(BARRIER)"); break;
|
2279 |
|
|
+ case RETURN: zip_debug_print(pfx, lvl, "(RETURN)"); break;
|
2280 |
|
|
+ case NOTE:
|
2281 |
|
|
+ { char buf[128];
|
2282 |
|
|
+ sprintf(buf, "(NOTE %s)", GET_REG_NOTE_NAME(GET_MODE(x)));
|
2283 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2284 |
|
|
+ }break;
|
2285 |
|
|
+ case COND_EXEC: zip_debug_print(pfx, lvl, "(COND_EXEC)");
|
2286 |
|
|
+ debug_rtx(x);
|
2287 |
|
|
+ break;
|
2288 |
|
|
+ case ASM_INPUT: zip_debug_print(pfx, lvl, "(ASM INPUT)"); break;
|
2289 |
|
|
+ case ASM_OPERANDS: zip_debug_print(pfx, lvl, "(ASM OPERANDS)"); break;
|
2290 |
|
|
+ case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
|
2291 |
|
|
+ case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
|
2292 |
|
|
+ case CODE_LABEL:
|
2293 |
|
|
+ {
|
2294 |
192 |
dgisselq |
+ char buf[128];
|
2295 |
111 |
dgisselq |
+ sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
|
2296 |
102 |
dgisselq |
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
|
2297 |
|
|
+ } break;
|
2298 |
|
|
+ case SET:
|
2299 |
|
|
+ zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
|
2300 |
117 |
dgisselq |
+ zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
|
2301 |
|
|
+ zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
|
2302 |
102 |
dgisselq |
+ zip_debug_print(pfx, lvl, ")");
|
2303 |
117 |
dgisselq |
+ debug_rtx(x);
|
2304 |
102 |
dgisselq |
+ break;
|
2305 |
122 |
dgisselq |
+ case REG: {
|
2306 |
127 |
dgisselq |
+ char buf[25], mstr[4];
|
2307 |
|
|
+ mstr[0] = '\0';
|
2308 |
202 |
dgisselq |
+ if (GET_MODE(x) == QImode)
|
2309 |
|
|
+ strcpy(mstr, ":QI");
|
2310 |
|
|
+ else if (GET_MODE(x) == HImode)
|
2311 |
|
|
+ strcpy(mstr, ":HI");
|
2312 |
127 |
dgisselq |
+ else if (GET_MODE(x) == VOIDmode)
|
2313 |
|
|
+ strcpy(mstr, ":V");
|
2314 |
102 |
dgisselq |
+ if (REGNO(x) == zip_PC)
|
2315 |
127 |
dgisselq |
+ sprintf(buf, "(PC%s)", mstr);
|
2316 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_CC)
|
2317 |
127 |
dgisselq |
+ sprintf(buf, "(CC%s)", mstr);
|
2318 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_SP)
|
2319 |
127 |
dgisselq |
+ sprintf(buf, "(SP%s)", mstr);
|
2320 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_FP)
|
2321 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s FP)", mstr);
|
2322 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_GOT)
|
2323 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s GBL)", mstr);
|
2324 |
102 |
dgisselq |
+ else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
|
2325 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s RTN-VL)", mstr);
|
2326 |
102 |
dgisselq |
+ else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
|
2327 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s RTN-AD)", mstr);
|
2328 |
122 |
dgisselq |
+ else
|
2329 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s %d)", mstr, REGNO(x));
|
2330 |
|
|
+ if (mstr[0])
|
2331 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2332 |
|
|
+ else
|
2333 |
|
|
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
|
2334 |
102 |
dgisselq |
+ } break;
|
2335 |
|
|
+ case IF_THEN_ELSE: // 51
|
2336 |
|
|
+ zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
|
2337 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2338 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2339 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,2),lvl+1);
|
2340 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2341 |
|
|
+ break;
|
2342 |
|
|
+ case PC:
|
2343 |
|
|
+ zip_debug_print(pfx, lvl, "(PC)");
|
2344 |
|
|
+ break;
|
2345 |
|
|
+ case CC0:
|
2346 |
|
|
+ zip_debug_print(pfx, lvl, "(CC0)");
|
2347 |
|
|
+ break;
|
2348 |
|
|
+ case COMPARE:
|
2349 |
127 |
dgisselq |
+ zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x));
|
2350 |
102 |
dgisselq |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2351 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2352 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2353 |
|
|
+ break;
|
2354 |
111 |
dgisselq |
+ case CONST:
|
2355 |
|
|
+ zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
|
2356 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2357 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2358 |
|
|
+ break;
|
2359 |
102 |
dgisselq |
+ case CONST_INT:
|
2360 |
192 |
dgisselq |
+ { char buf[128];
|
2361 |
202 |
dgisselq |
+ if (GET_MODE(x)==QImode)
|
2362 |
|
|
+ sprintf(buf, "(CONST_INT:QI %ld)", (long)INTVAL(x));
|
2363 |
102 |
dgisselq |
+ else if (GET_MODE(x)==VOIDmode)
|
2364 |
202 |
dgisselq |
+ sprintf(buf, "(CONST_INT:V %ld, %016lx)", (long)INTVAL(x),
|
2365 |
|
|
+ (unsigned long)INTVAL(x));
|
2366 |
102 |
dgisselq |
+ else
|
2367 |
135 |
dgisselq |
+ sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
|
2368 |
102 |
dgisselq |
+ zip_debug_print(pfx, lvl, buf);
|
2369 |
|
|
+ } break;
|
2370 |
|
|
+ case LABEL_REF:
|
2371 |
122 |
dgisselq |
+ { char buf[256];
|
2372 |
111 |
dgisselq |
+ sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
|
2373 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2374 |
|
|
+ }
|
2375 |
102 |
dgisselq |
+ break;
|
2376 |
|
|
+ case SYMBOL_REF:
|
2377 |
|
|
+ {
|
2378 |
202 |
dgisselq |
+ char buf[1024];
|
2379 |
102 |
dgisselq |
+ sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
|
2380 |
|
|
+ // fprintf(file, "%s", XSTR(x,0));
|
2381 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2382 |
|
|
+ }
|
2383 |
|
|
+ break;
|
2384 |
|
|
+ case MEM:
|
2385 |
|
|
+ zip_debug_print_m(pfx, lvl, "(MEM", GET_MODE(x));
|
2386 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2387 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2388 |
|
|
+ break;
|
2389 |
|
|
+ /*
|
2390 |
|
|
+ case VALUE:
|
2391 |
|
|
+ {
|
2392 |
|
|
+ char buf[64];
|
2393 |
|
|
+ sprintf(buf, "(VALUE: %d)", INTVAL(XEXP,0));
|
2394 |
|
|
+ zip_debug_print_m(pfx, lvl, "buf", GET_MODE(x));
|
2395 |
|
|
+ }
|
2396 |
|
|
+ break;
|
2397 |
|
|
+ */
|
2398 |
|
|
+ case PLUS:
|
2399 |
|
|
+ zip_debug_print_m(pfx, lvl, "(PLUS", GET_MODE(x));
|
2400 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2401 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2402 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2403 |
|
|
+ break;
|
2404 |
|
|
+ case MINUS:
|
2405 |
|
|
+ zip_debug_print_m(pfx, lvl, "(MINUS", GET_MODE(x));
|
2406 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2407 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2408 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2409 |
|
|
+ break;
|
2410 |
|
|
+ case AND:
|
2411 |
|
|
+ zip_debug_print_m(pfx, lvl, "(AND", GET_MODE(x));
|
2412 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2413 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2414 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2415 |
|
|
+ break;
|
2416 |
|
|
+ case IOR:
|
2417 |
|
|
+ zip_debug_print_m(pfx, lvl, "(OR", GET_MODE(x));
|
2418 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2419 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2420 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2421 |
|
|
+ break;
|
2422 |
|
|
+ case XOR:
|
2423 |
|
|
+ zip_debug_print_m(pfx, lvl, "(XOR", GET_MODE(x));
|
2424 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2425 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2426 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2427 |
|
|
+ break;
|
2428 |
|
|
+ case MULT:
|
2429 |
|
|
+ zip_debug_print_m(pfx, lvl, "(MULT", GET_MODE(x));
|
2430 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2431 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2432 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2433 |
|
|
+ break;
|
2434 |
|
|
+ case EQ: //
|
2435 |
|
|
+ zip_debug_print_m(pfx, lvl, "(EQ", GET_MODE(x));
|
2436 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2437 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2438 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2439 |
|
|
+ break;
|
2440 |
|
|
+ case NE: //
|
2441 |
|
|
+ zip_debug_print_m(pfx, lvl, "(NE", GET_MODE(x));
|
2442 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2443 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2444 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2445 |
|
|
+ break;
|
2446 |
|
|
+ case GE: //
|
2447 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GE", GET_MODE(x));
|
2448 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2449 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2450 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2451 |
|
|
+ break;
|
2452 |
|
|
+ case GT: //
|
2453 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GT", GET_MODE(x));
|
2454 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2455 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2456 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2457 |
|
|
+ break;
|
2458 |
|
|
+ case LE: //
|
2459 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LE", GET_MODE(x));
|
2460 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2461 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2462 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2463 |
|
|
+ break;
|
2464 |
|
|
+ case LT: //
|
2465 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LT", GET_MODE(x));
|
2466 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2467 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2468 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2469 |
|
|
+ break;
|
2470 |
|
|
+ case GEU: //
|
2471 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GEU", GET_MODE(x));
|
2472 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2473 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2474 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2475 |
|
|
+ break;
|
2476 |
|
|
+ case GTU: //
|
2477 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GTU", GET_MODE(x));
|
2478 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2479 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2480 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2481 |
|
|
+ break;
|
2482 |
|
|
+ case LEU: //
|
2483 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LEU", GET_MODE(x));
|
2484 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2485 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2486 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2487 |
|
|
+ break;
|
2488 |
|
|
+ case LTU: //
|
2489 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LTU", GET_MODE(x));
|
2490 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2491 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2492 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2493 |
|
|
+ break;
|
2494 |
|
|
+ case SCRATCH: //
|
2495 |
|
|
+ zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
|
2496 |
|
|
+ break;
|
2497 |
|
|
+ case SUBREG:
|
2498 |
202 |
dgisselq |
+ { char buf[64], mstr[8];
|
2499 |
|
|
+ if (GET_MODE(x) == QImode)
|
2500 |
|
|
+ strcpy(mstr, ":QI");
|
2501 |
|
|
+ else if (GET_MODE(x) == HImode)
|
2502 |
|
|
+ strcpy(mstr, ":HI");
|
2503 |
|
|
+ else if (GET_MODE(x) == SImode)
|
2504 |
|
|
+ strcpy(mstr, ":SI");
|
2505 |
|
|
+ else if (GET_MODE(x) == VOIDmode)
|
2506 |
|
|
+ strcpy(mstr, ":V");
|
2507 |
|
|
+ else
|
2508 |
|
|
+ strcpy(mstr, ":?");
|
2509 |
111 |
dgisselq |
+ if (REG_P(XEXP(x,0))) {
|
2510 |
202 |
dgisselq |
+ int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),
|
2511 |
|
|
+ sb = SUBREG_BYTE(x);
|
2512 |
|
|
+ if (mod==QImode)
|
2513 |
|
|
+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
|
2514 |
|
|
+ else if (mod==HImode)
|
2515 |
|
|
+ sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);
|
2516 |
|
|
+ else if (mod==QImode)
|
2517 |
|
|
+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
|
2518 |
|
|
+ else if (mod==VOIDmode)
|
2519 |
|
|
+ sprintf(buf,"(SUBREG%s (REG:V %d)/%d)",mstr,hreg, sb);
|
2520 |
|
|
+ else
|
2521 |
|
|
+ sprintf(buf,"(SUBREG%s %d:?/%d)",mstr,hreg, sb);
|
2522 |
111 |
dgisselq |
+ zip_debug_print(pfx, lvl, buf);
|
2523 |
|
|
+ } else if (MEM_P(XEXP(x,0))) {
|
2524 |
202 |
dgisselq |
+ sprintf(buf, "(SUBREG%s /%d", mstr,SUBREG_BYTE(x));
|
2525 |
111 |
dgisselq |
+ zip_debug_print(pfx, lvl, buf);
|
2526 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2527 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2528 |
|
|
+ } else {
|
2529 |
202 |
dgisselq |
+ sprintf(buf, "(SUBREG%s UNK /%d", mstr,SUBREG_BYTE(x));
|
2530 |
111 |
dgisselq |
+ zip_debug_print(pfx, lvl, buf);
|
2531 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2532 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2533 |
|
|
+ }}
|
2534 |
|
|
+ break;
|
2535 |
127 |
dgisselq |
+ case ASHIFT:
|
2536 |
|
|
+ zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x));
|
2537 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2538 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2539 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2540 |
|
|
+ break;
|
2541 |
|
|
+ case ASHIFTRT:
|
2542 |
|
|
+ zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x));
|
2543 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2544 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2545 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2546 |
|
|
+ break;
|
2547 |
|
|
+ case LSHIFTRT:
|
2548 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
|
2549 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2550 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2551 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2552 |
|
|
+ break;
|
2553 |
202 |
dgisselq |
+ case ZERO_EXTRACT:
|
2554 |
|
|
+ zip_debug_print_m(pfx, lvl, "(ZERO_EXTRACT", GET_MODE(x));
|
2555 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2556 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2557 |
|
|
+ break;
|
2558 |
|
|
+ case ZERO_EXTEND:
|
2559 |
|
|
+ zip_debug_print_m(pfx, lvl, "(ZERO_EXTEND", GET_MODE(x));
|
2560 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2561 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2562 |
|
|
+ break;
|
2563 |
102 |
dgisselq |
+ default:
|
2564 |
111 |
dgisselq |
+ { char buf[128];
|
2565 |
102 |
dgisselq |
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
|
2566 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2567 |
|
|
+ debug_rtx(x);
|
2568 |
|
|
+ } break;
|
2569 |
|
|
+ }
|
2570 |
|
|
+}
|
2571 |
|
|
+
|
2572 |
|
|
+void
|
2573 |
|
|
+zip_debug_rtx_pfx(const char *pfx, const_rtx x) {
|
2574 |
|
|
+ zip_debug_rtx_1(pfx, x, 0);
|
2575 |
|
|
+}
|
2576 |
|
|
+
|
2577 |
|
|
+void
|
2578 |
|
|
+zip_debug_rtx(const_rtx x) {
|
2579 |
|
|
+ zip_debug_rtx_pfx("", x);
|
2580 |
|
|
+}
|
2581 |
|
|
+
|
2582 |
|
|
+void
|
2583 |
142 |
dgisselq |
+zip_debug_ccode(int ccode) {
|
2584 |
|
|
+ switch(ccode) {
|
2585 |
|
|
+ case EQ: fprintf(stderr, "EQ"); break;
|
2586 |
|
|
+ case NE: fprintf(stderr, "NE"); break;
|
2587 |
|
|
+ case GE: fprintf(stderr, "GE"); break;
|
2588 |
|
|
+ case LT: fprintf(stderr, "LT"); break;
|
2589 |
202 |
dgisselq |
+ case LTU: fprintf(stderr, "LTU"); break;
|
2590 |
142 |
dgisselq |
+ case GEU: fprintf(stderr, "GEU"); break;
|
2591 |
202 |
dgisselq |
+ case GT: fprintf(stderr, "GT[!]"); break;
|
2592 |
|
|
+ case LE: fprintf(stderr, "LE[!]"); break;
|
2593 |
|
|
+ case GTU: fprintf(stderr, "GTU[!]"); break;
|
2594 |
|
|
+ case LEU: fprintf(stderr, "LEU[!]"); break;
|
2595 |
142 |
dgisselq |
+ default:
|
2596 |
|
|
+ fprintf(stderr, "%d", ccode); break;
|
2597 |
|
|
+ }
|
2598 |
|
|
+}
|
2599 |
|
|
+
|
2600 |
|
|
+void
|
2601 |
102 |
dgisselq |
+zip_debug_insn(rtx_insn *insn ATTRIBUTE_UNUSED) {
|
2602 |
|
|
+}
|
2603 |
|
|
+
|
2604 |
|
|
+void
|
2605 |
|
|
+zip_debug_bb(basic_block bb) {
|
2606 |
|
|
+ rtx_insn *insn;
|
2607 |
|
|
+
|
2608 |
|
|
+ fprintf(stderr, "************ BASIC-BLOCK ***************\n");
|
2609 |
|
|
+ FOR_BB_INSNS(bb, insn)
|
2610 |
|
|
+ {
|
2611 |
|
|
+ zip_debug_rtx(insn);
|
2612 |
|
|
+ }
|
2613 |
|
|
+}
|
2614 |
|
|
+
|
2615 |
|
|
+
|
2616 |
|
|
+static bool
|
2617 |
122 |
dgisselq |
+zip_legitimate_opb(rtx x, bool strict)
|
2618 |
102 |
dgisselq |
+{
|
2619 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2620 |
102 |
dgisselq |
+
|
2621 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
|
2622 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("Test: ", x);
|
2623 |
|
|
+
|
2624 |
|
|
+ if (NULL_RTX == x)
|
2625 |
|
|
+ return false;
|
2626 |
202 |
dgisselq |
+ else if ((GET_MODE(x) != QImode)
|
2627 |
|
|
+ &&(GET_MODE(x) != HImode)
|
2628 |
|
|
+ &&(GET_MODE(x) != SImode)
|
2629 |
|
|
+ &&(GET_MODE(x) != VOIDmode)) {
|
2630 |
122 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
|
2631 |
102 |
dgisselq |
+ return false;
|
2632 |
122 |
dgisselq |
+ } else if ((strict)&&(REG_P(x))) {
|
2633 |
|
|
+ if (REGNO(x)<zip_CC) {
|
2634 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
|
2635 |
|
|
+ return true;
|
2636 |
|
|
+ } else return false;
|
2637 |
|
|
+ } else if (register_operand(x, GET_MODE(x))) {
|
2638 |
|
|
+ // This also handles subregs
|
2639 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
|
2640 |
|
|
+ return true;
|
2641 |
111 |
dgisselq |
+ } else if ((CONST_INT_P(x))
|
2642 |
|
|
+ &&(INTVAL(x) >= zip_min_opb_imm)
|
2643 |
|
|
+ &&(INTVAL(x) <= zip_max_opb_imm)) {
|
2644 |
136 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", (long)zip_min_opb_imm, (long)INTVAL(x), (long)zip_max_opb_imm);
|
2645 |
111 |
dgisselq |
+ return true;
|
2646 |
122 |
dgisselq |
+ // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
|
2647 |
|
|
+ // return true;
|
2648 |
102 |
dgisselq |
+ } else if (GET_CODE(x) == PLUS) {
|
2649 |
|
|
+ // Is it a valid register?
|
2650 |
202 |
dgisselq |
+ rtx regrtx = XEXP(x, 0);
|
2651 |
|
|
+ if ((!strict)&&(!REG_P(regrtx))) {
|
2652 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
|
2653 |
102 |
dgisselq |
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
|
2654 |
|
|
+ return false;
|
2655 |
122 |
dgisselq |
+ } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
|
2656 |
102 |
dgisselq |
+ return false;
|
2657 |
|
|
+ } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
|
2658 |
|
|
+ &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
|
2659 |
|
|
+ &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
|
2660 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
|
2661 |
103 |
dgisselq |
+ // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
|
2662 |
|
|
+ // gcc_unreachable();
|
2663 |
102 |
dgisselq |
+ return true;
|
2664 |
|
|
+ } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
|
2665 |
122 |
dgisselq |
+ ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL)
|
2666 |
102 |
dgisselq |
+ ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
|
2667 |
|
|
+ // While we can technically support this, the problem
|
2668 |
|
|
+ // is that the symbol address could be anywhere, and we
|
2669 |
|
|
+ // have no way of recovering if it's outside of our
|
2670 |
|
|
+ // 14 allowable bits.
|
2671 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
|
2672 |
102 |
dgisselq |
+ return false;
|
2673 |
|
|
+ }
|
2674 |
|
|
+ }
|
2675 |
|
|
+
|
2676 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
|
2677 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx(x);
|
2678 |
|
|
+ return false;
|
2679 |
|
|
+}
|
2680 |
|
|
+
|
2681 |
|
|
+static bool
|
2682 |
|
|
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
|
2683 |
202 |
dgisselq |
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
2684 |
102 |
dgisselq |
+
|
2685 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
|
2686 |
|
|
+ if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
|
2687 |
|
|
+
|
2688 |
122 |
dgisselq |
+ if (!zip_legitimate_opb(x, strict))
|
2689 |
102 |
dgisselq |
+ return false;
|
2690 |
122 |
dgisselq |
+ else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) {
|
2691 |
|
|
+ if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset)
|
2692 |
|
|
+ ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) {
|
2693 |
135 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %ld\n", (long)INTVAL(XEXP(x,1)));
|
2694 |
102 |
dgisselq |
+ return false;
|
2695 |
|
|
+ }
|
2696 |
|
|
+ }
|
2697 |
|
|
+
|
2698 |
122 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n");
|
2699 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx(x);
|
2700 |
122 |
dgisselq |
+ return true;
|
2701 |
102 |
dgisselq |
+}
|
2702 |
|
|
+
|
2703 |
|
|
+int
|
2704 |
|
|
+zip_pd_mov_operand(rtx op)
|
2705 |
|
|
+{
|
2706 |
202 |
dgisselq |
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
2707 |
102 |
dgisselq |
+
|
2708 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
|
2709 |
|
|
+ return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
|
2710 |
|
|
+}
|
2711 |
|
|
+
|
2712 |
|
|
+int
|
2713 |
111 |
dgisselq |
+zip_pd_mvimm_operand(rtx op)
|
2714 |
|
|
+{
|
2715 |
202 |
dgisselq |
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
2716 |
111 |
dgisselq |
+
|
2717 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
|
2718 |
|
|
+ if (!CONST_INT_P(op))
|
2719 |
|
|
+ return false;
|
2720 |
|
|
+ if (INTVAL(op) > zip_max_mov_offset)
|
2721 |
|
|
+ return false;
|
2722 |
|
|
+ if (INTVAL(op) < zip_min_mov_offset)
|
2723 |
|
|
+ return false;
|
2724 |
|
|
+ return true;
|
2725 |
|
|
+}
|
2726 |
|
|
+
|
2727 |
|
|
+int
|
2728 |
|
|
+zip_pd_imm_operand(rtx op)
|
2729 |
|
|
+{
|
2730 |
202 |
dgisselq |
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
2731 |
111 |
dgisselq |
+
|
2732 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
|
2733 |
|
|
+ if (!CONST_INT_P(op))
|
2734 |
|
|
+ return false;
|
2735 |
|
|
+ if (INTVAL(op) > zip_max_anchor_offset)
|
2736 |
|
|
+ return false;
|
2737 |
|
|
+ if (INTVAL(op) < zip_min_anchor_offset)
|
2738 |
|
|
+ return false;
|
2739 |
|
|
+ return true;
|
2740 |
|
|
+}
|
2741 |
|
|
+
|
2742 |
|
|
+int
|
2743 |
102 |
dgisselq |
+zip_address_operand(rtx op)
|
2744 |
|
|
+{
|
2745 |
202 |
dgisselq |
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
2746 |
102 |
dgisselq |
+
|
2747 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
|
2748 |
111 |
dgisselq |
+ if ((REG_P(op))&&(REGNO(op)==zip_CC))
|
2749 |
|
|
+ return false;
|
2750 |
|
|
+ else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
|
2751 |
|
|
+ &&(REGNO(XEXP(op,0))==zip_CC))
|
2752 |
|
|
+ return false;
|
2753 |
|
|
+ else
|
2754 |
|
|
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
|
2755 |
102 |
dgisselq |
+}
|
2756 |
|
|
+
|
2757 |
|
|
+int
|
2758 |
111 |
dgisselq |
+zip_pd_opb_operand(rtx op)
|
2759 |
102 |
dgisselq |
+{
|
2760 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2761 |
102 |
dgisselq |
+
|
2762 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
|
2763 |
122 |
dgisselq |
+ return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
|
2764 |
102 |
dgisselq |
+}
|
2765 |
|
|
+
|
2766 |
|
|
+int
|
2767 |
|
|
+zip_ct_address_operand(rtx op)
|
2768 |
|
|
+{
|
2769 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2770 |
102 |
dgisselq |
+
|
2771 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
|
2772 |
111 |
dgisselq |
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
|
2773 |
102 |
dgisselq |
+}
|
2774 |
|
|
+
|
2775 |
|
|
+int
|
2776 |
|
|
+zip_const_address_operand(rtx x) {
|
2777 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2778 |
102 |
dgisselq |
+
|
2779 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
|
2780 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
2781 |
127 |
dgisselq |
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
2782 |
|
|
+ fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
|
2783 |
102 |
dgisselq |
+ return false;
|
2784 |
127 |
dgisselq |
+ }
|
2785 |
102 |
dgisselq |
+ if ((GET_CODE(x) == LABEL_REF)
|
2786 |
|
|
+ ||(GET_CODE(x) == CODE_LABEL)
|
2787 |
|
|
+ ||(GET_CODE(x) == SYMBOL_REF)) {
|
2788 |
127 |
dgisselq |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n");
|
2789 |
102 |
dgisselq |
+ return true;
|
2790 |
|
|
+ } else if (CONST_INT_P(x)) {
|
2791 |
127 |
dgisselq |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n");
|
2792 |
102 |
dgisselq |
+ return true;
|
2793 |
|
|
+ } else if (GET_CODE(x) == PLUS) {
|
2794 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
|
2795 |
|
|
+ return ((zip_const_address_operand(XEXP(x,0)))
|
2796 |
|
|
+ &&(CONST_INT_P(XEXP(x,1))));
|
2797 |
|
|
+ } else if (GET_CODE(x) == MINUS) {
|
2798 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(MINUS)\n");
|
2799 |
|
|
+ return ((zip_const_address_operand(XEXP(x,0)))
|
2800 |
|
|
+ &&(zip_const_address_operand(XEXP(x,1))));
|
2801 |
|
|
+ }
|
2802 |
|
|
+
|
2803 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> No\n");
|
2804 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
2805 |
|
|
+ return false;
|
2806 |
|
|
+}
|
2807 |
|
|
+
|
2808 |
|
|
+int
|
2809 |
|
|
+zip_ct_const_address_operand(rtx x) {
|
2810 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2811 |
102 |
dgisselq |
+
|
2812 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
|
2813 |
|
|
+ return zip_const_address_operand(x);
|
2814 |
|
|
+}
|
2815 |
|
|
+
|
2816 |
|
|
+int
|
2817 |
|
|
+zip_pd_const_address_operand(rtx x) {
|
2818 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2819 |
102 |
dgisselq |
+
|
2820 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
|
2821 |
|
|
+ return zip_const_address_operand(x);
|
2822 |
|
|
+}
|
2823 |
|
|
+
|
2824 |
|
|
+
|
2825 |
|
|
+static bool
|
2826 |
|
|
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
|
2827 |
|
|
+{
|
2828 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2829 |
102 |
dgisselq |
+
|
2830 |
|
|
+ if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
|
2831 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
2832 |
|
|
+
|
2833 |
|
|
+ // Only insist the register be a valid register if strict is true
|
2834 |
111 |
dgisselq |
+ if (zip_legitimate_opb(x, strict))
|
2835 |
102 |
dgisselq |
+ return true;
|
2836 |
111 |
dgisselq |
+ // else if (zip_const_address_operand(x))
|
2837 |
|
|
+ // return true;
|
2838 |
102 |
dgisselq |
+
|
2839 |
|
|
+ return false;
|
2840 |
|
|
+}
|
2841 |
|
|
+
|
2842 |
111 |
dgisselq |
+static rtx
|
2843 |
|
|
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
|
2844 |
202 |
dgisselq |
+ ZIPDEBUGFLAG(dbg, false);
|
2845 |
111 |
dgisselq |
+
|
2846 |
202 |
dgisselq |
+
|
2847 |
111 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
|
2848 |
|
|
+ if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
2849 |
|
|
+ return x;
|
2850 |
|
|
+
|
2851 |
202 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("ILLEGITIMATE: ", x);
|
2852 |
111 |
dgisselq |
+ if (GET_CODE(x)==PLUS) {
|
2853 |
202 |
dgisselq |
+ // if ((zip_legitimate_address_p(mode, XEXP(x,0),
|
2854 |
|
|
+ // !can_create_pseudo_p()))
|
2855 |
|
|
+ // &&(GETMODE(XEXP(x,1))==CONST_INT)) {
|
2856 |
|
|
+ //}
|
2857 |
111 |
dgisselq |
+ if (!REG_P(XEXP(x,0)))
|
2858 |
202 |
dgisselq |
+ XEXP(x,0) = force_reg(Pmode,XEXP(x,0));
|
2859 |
111 |
dgisselq |
+ if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
2860 |
|
|
+ &&(!CONST_INT_P(XEXP(x,1))))
|
2861 |
|
|
+ x = force_reg(GET_MODE(x),x);
|
2862 |
|
|
+ } else if (MEM_P(x))
|
2863 |
|
|
+ x = force_reg(GET_MODE(x),x);
|
2864 |
|
|
+
|
2865 |
|
|
+ if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
|
2866 |
|
|
+ return x;
|
2867 |
|
|
+}
|
2868 |
|
|
+
|
2869 |
102 |
dgisselq |
+void
|
2870 |
|
|
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
|
2871 |
|
|
+{
|
2872 |
202 |
dgisselq |
+ fprintf(stream, "\t.equ %s, %s\n", name, value);
|
2873 |
102 |
dgisselq |
+}
|
2874 |
|
|
+
|
2875 |
202 |
dgisselq |
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
|
2876 |
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
2877 |
102 |
dgisselq |
+
|
2878 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
|
2879 |
|
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
2880 |
|
|
+ if (dbg) zip_debug_rtx_pfx("REG", dst);
|
2881 |
|
|
+ switch(GET_CODE(condition)) {
|
2882 |
202 |
dgisselq |
+ case EQ: return "LDI\t0,%0\n\tLDILO.Z\t1,%0\t; set01_eq";
|
2883 |
|
|
+ case NE: return "LDI\t0,%0\n\tLDILO.NZ\t1,%0\t; set01_ne";
|
2884 |
|
|
+ case LT: return "LDI\t0,%0\n\tLDILO.LT\t1,%0\t; set01_lt";
|
2885 |
|
|
+ case GT: return "LDI\t1,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_gt";
|
2886 |
|
|
+ case LE: return "LDI\t0,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_le";
|
2887 |
|
|
+ case GE: return "LDI\t0,%0\n\tLDILO.GE\t1,%0\t; set01_ge";
|
2888 |
|
|
+ case LTU: return "LDI\t0,%0\n\tLDILO.C\t1,%0\t; set01_ltu";
|
2889 |
|
|
+ case GEU: return "LDI\t0,%0\n\tLDILO.NC\t1,%0\t; set01_geu";
|
2890 |
|
|
+ case GTU: return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0\t; set01_gtu";
|
2891 |
|
|
+ case LEU: return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\t; set01_leu";
|
2892 |
102 |
dgisselq |
+ default:
|
2893 |
|
|
+ zip_debug_rtx(condition);
|
2894 |
|
|
+ internal_error("CSTORE Unsupported condition");
|
2895 |
|
|
+ return NULL;
|
2896 |
|
|
+ }
|
2897 |
|
|
+}
|
2898 |
|
|
+
|
2899 |
200 |
dgisselq |
+int
|
2900 |
127 |
dgisselq |
+zip_supported_condition(int c) {
|
2901 |
|
|
+ switch(c) {
|
2902 |
202 |
dgisselq |
+ case EQ: case NE: case LT: case GE: case LTU: case GEU:
|
2903 |
200 |
dgisselq |
+ return 1;
|
2904 |
127 |
dgisselq |
+ break;
|
2905 |
|
|
+ default:
|
2906 |
|
|
+ break;
|
2907 |
200 |
dgisselq |
+ } return 0;
|
2908 |
102 |
dgisselq |
+}
|
2909 |
|
|
+
|
2910 |
127 |
dgisselq |
+bool
|
2911 |
|
|
+zip_signed_comparison(int c) {
|
2912 |
|
|
+ switch(c) {
|
2913 |
202 |
dgisselq |
+ case NE: case LT: case EQ: case GE:
|
2914 |
127 |
dgisselq |
+ return true;
|
2915 |
|
|
+ default:
|
2916 |
|
|
+ break;
|
2917 |
|
|
+ } return false;
|
2918 |
|
|
+}
|
2919 |
|
|
+
|
2920 |
200 |
dgisselq |
+int
|
2921 |
202 |
dgisselq |
+zip_expand_movdi(rtx dst, rtx src) {
|
2922 |
|
|
+ ZIPDEBUGFLAG(dbg, false);
|
2923 |
|
|
+
|
2924 |
|
|
+ if (dbg) fprintf(stderr, "\nZIP::MOVDI\n");
|
2925 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("DST", dst);
|
2926 |
202 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("SRC", src);
|
2927 |
127 |
dgisselq |
+
|
2928 |
202 |
dgisselq |
+ // MOV !REG->!REG
|
2929 |
|
|
+ if ((!REG_P(dst))&&(!REG_P(src))&&(can_create_pseudo_p())) {
|
2930 |
|
|
+ // This includes:
|
2931 |
|
|
+ // MOV MEM->MEM
|
2932 |
|
|
+ // MOV IMM->MEM
|
2933 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- !REG->!REG\n");
|
2934 |
127 |
dgisselq |
+
|
2935 |
202 |
dgisselq |
+ rtx tmp = gen_reg_rtx(DImode);
|
2936 |
|
|
+ emit_insn(gen_movdi(tmp, src));
|
2937 |
|
|
+ emit_insn(gen_movdi(dst, tmp));
|
2938 |
|
|
+ return 1;
|
2939 |
142 |
dgisselq |
+ }
|
2940 |
|
|
+
|
2941 |
202 |
dgisselq |
+ // MOV REG->REG
|
2942 |
|
|
+ if ((REG_P(dst))&&(REG_P(src))) {
|
2943 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->REG\n");
|
2944 |
127 |
dgisselq |
+
|
2945 |
202 |
dgisselq |
+ emit_insn(gen_movdi_raw(dst, src));
|
2946 |
|
|
+ return 1;
|
2947 |
|
|
+ }
|
2948 |
127 |
dgisselq |
+
|
2949 |
202 |
dgisselq |
+ // MOV REG->MEM (a store instruction)
|
2950 |
|
|
+ if ((MEM_P(dst))&&(REG_P(src))) {
|
2951 |
|
|
+ rtx addr = XEXP(dst,0);
|
2952 |
|
|
+ long offset = 0;
|
2953 |
|
|
+ if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
|
2954 |
|
|
+ offset = INTVAL(XEXP(addr,1));
|
2955 |
127 |
dgisselq |
+
|
2956 |
202 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->MEM\n");
|
2957 |
|
|
+ if (REG_P(addr)) {
|
2958 |
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
2959 |
|
|
+ return 1;
|
2960 |
|
|
+ } else if ((GET_CODE(addr)==PLUS)
|
2961 |
|
|
+ &&(REG_P(XEXP(addr,0)))
|
2962 |
|
|
+ &&(CONST_INT_P(XEXP(addr,1)))
|
2963 |
|
|
+ &&(offset>=(long)zip_min_anchor_offset)
|
2964 |
|
|
+ &&(offset+4<(long)zip_max_anchor_offset)) {
|
2965 |
|
|
+ // Demonstrated and works
|
2966 |
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
2967 |
|
|
+ return 1;
|
2968 |
|
|
+ } else if (can_create_pseudo_p()) {
|
2969 |
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
2970 |
|
|
+ emit_insn(gen_movsi(tmp, addr));
|
2971 |
|
|
+ emit_insn(gen_movdi_raw(gen_rtx_MEM(DImode, tmp), src));
|
2972 |
|
|
+ return 1;
|
2973 |
102 |
dgisselq |
+ }
|
2974 |
|
|
+ }
|
2975 |
|
|
+
|
2976 |
202 |
dgisselq |
+ // MOV MEM->REG (a load instruction)
|
2977 |
|
|
+ if ((REG_P(dst))&&(MEM_P(src))) {
|
2978 |
|
|
+ rtx addr = XEXP(src,0);
|
2979 |
|
|
+ long offset = 0;
|
2980 |
|
|
+ if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
|
2981 |
|
|
+ offset = INTVAL(XEXP(addr,1));
|
2982 |
142 |
dgisselq |
+
|
2983 |
202 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM->REG\n");
|
2984 |
|
|
+ if (REG_P(addr)) {
|
2985 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[R]->REG\n");
|
2986 |
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
2987 |
|
|
+ return 1;
|
2988 |
|
|
+ } else if ((GET_CODE(addr)==PLUS)
|
2989 |
|
|
+ &&(REG_P(XEXP(addr,0)))
|
2990 |
|
|
+ &&(CONST_INT_P(XEXP(addr,1)))
|
2991 |
|
|
+ &&(offset>=(long)zip_min_anchor_offset)
|
2992 |
|
|
+ &&(offset+4<(long)zip_max_anchor_offset)) {
|
2993 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[#+R]->REG -- DONE\n");
|
2994 |
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
2995 |
|
|
+ return 1;
|
2996 |
|
|
+ } else if (can_create_pseudo_p()) {
|
2997 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- LDI #,R, MEM[R]->REG\n");
|
2998 |
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
2999 |
|
|
+ emit_insn(gen_movsi(tmp, addr));
|
3000 |
|
|
+ emit_insn(gen_movdi_raw(dst,
|
3001 |
|
|
+ gen_rtx_MEM(DImode, tmp)));
|
3002 |
|
|
+ return 1;
|
3003 |
|
|
+ } else if (dbg)
|
3004 |
|
|
+ fprintf(stderr, "ZIP::MOVDI -- MEM[?]->REG (no match)\n");
|
3005 |
142 |
dgisselq |
+ }
|
3006 |
127 |
dgisselq |
+
|
3007 |
202 |
dgisselq |
+ // MOV #->REG (An LDI instruction, but for DIwords)
|
3008 |
|
|
+ if ((CONST_INT_P(src))&&(REG_P(dst))) {
|
3009 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVDI -- IMM->REG\n");
|
3010 |
|
|
+ emit_insn(gen_movdi_raw(dst, src));
|
3011 |
|
|
+ return 1;
|
3012 |
142 |
dgisselq |
+ }
|
3013 |
127 |
dgisselq |
+
|
3014 |
202 |
dgisselq |
+ return 0;
|
3015 |
|
|
+}
|
3016 |
142 |
dgisselq |
+
|
3017 |
202 |
dgisselq |
+const char *
|
3018 |
|
|
+zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv) {
|
3019 |
|
|
+ // We know upon entry that REG_P(dst) must be true
|
3020 |
|
|
+ if (!REG_P(dst))
|
3021 |
|
|
+ internal_error("%s","ADDSICC into something other than register");
|
3022 |
127 |
dgisselq |
+
|
3023 |
202 |
dgisselq |
+ if ((REG_P(dst))&&(REG_P(ifsrc))&&(REG_P(addv))
|
3024 |
|
|
+ &&(REGNO(dst)!=REGNO(ifsrc))) {
|
3025 |
|
|
+ switch (GET_CODE(condition)) {
|
3026 |
|
|
+ case EQ: return "MOV.Z\t%2,%0\n\tADD.Z\t%3,%0";
|
3027 |
|
|
+ case NE: return "MOV.NZ\t%2,%0\n\tADD.NZ\t%3,%0";
|
3028 |
|
|
+ case LT: return "MOV.LT\t%2,%0\n\tADD.LT\t%3,%0";
|
3029 |
127 |
dgisselq |
+
|
3030 |
202 |
dgisselq |
+ case LE: return "MOV.LT\t%3,%0\n\tMOV.Z\t%3,%0\n\tADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
|
3031 |
|
|
+ case GE: return "MOV.GE\t%2,%0\n\tADD.GE\t%3,%0";
|
3032 |
142 |
dgisselq |
+
|
3033 |
202 |
dgisselq |
+ case GT: return "BLT\t%.Laddsi%=\n\tBZ\t%%.Laddsi%=\n\tMOV\t%2,%0\n\tADD\t%3,%0\n.Laddsi%=:";
|
3034 |
|
|
+ case LTU: return "MOV.C\t%2,%0\n\tADD.C\t%3,%0";
|
3035 |
|
|
+
|
3036 |
|
|
+ case LEU: return "MOV.C\t%2,%0\n\tMOV.Z\t%2,%0\n\tADD.C\t%3,%0\n\tADD.Z\t%3,%0";
|
3037 |
|
|
+ case GEU: return "MOV.NC\t%2,%0\n\tADD.NC\t%3,%0";
|
3038 |
|
|
+ case GTU: return "BZ\t%.Laddsi%=\n\tMOV.NC\t%3,%0\n\tADD.NC\t%3,%0\n.Laddsi%=:";
|
3039 |
|
|
+ default:
|
3040 |
|
|
+ internal_error("%s", "Zip/No usable addsi expansion");
|
3041 |
|
|
+ break;
|
3042 |
|
|
+ }
|
3043 |
142 |
dgisselq |
+ }
|
3044 |
|
|
+
|
3045 |
102 |
dgisselq |
+ if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
|
3046 |
|
|
+ switch (GET_CODE(condition)) {
|
3047 |
|
|
+ case EQ: return "ADD.Z\t%3,%0";
|
3048 |
|
|
+ case NE: return "ADD.NZ\t%3,%0";
|
3049 |
|
|
+ case LT: return "ADD.LT\t%3,%0";
|
3050 |
|
|
+ case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
|
3051 |
|
|
+ case GE: return "ADD.GE\t%3,%0";
|
3052 |
202 |
dgisselq |
+ case GT: return "ADD.GE\t%3,%0\n\tSUB.Z\t%3,%0";
|
3053 |
102 |
dgisselq |
+ case LTU: return "ADD.C\t%3,%0";
|
3054 |
|
|
+ case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
|
3055 |
202 |
dgisselq |
+ case GEU: return "ADD.NC\t%3,%0";
|
3056 |
|
|
+ case GTU: return "SUB.Z\t%3,%0\n\tADD.NC\t%3,%0";
|
3057 |
102 |
dgisselq |
+ default:
|
3058 |
|
|
+ internal_error("%s", "Zip/No usable addsi expansion");
|
3059 |
|
|
+ break;
|
3060 |
|
|
+ }
|
3061 |
|
|
+ } else {
|
3062 |
|
|
+ // MOV A+REG,REG
|
3063 |
|
|
+ switch (GET_CODE(condition)) {
|
3064 |
|
|
+ case EQ: return "MOV.Z\t%3+%2,%0";
|
3065 |
|
|
+ case NE: return "MOV.NZ\t%3+%2,%0";
|
3066 |
|
|
+ case LT: return "MOV.LT\t%3+%2,%0";
|
3067 |
202 |
dgisselq |
+ case GT: return "BLT\t.Laddcc%=\n\tBZ\t.Laddcc%=\n\tMOV\t%3+%2,%0\n.Laddcc%=";
|
3068 |
102 |
dgisselq |
+ case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
3069 |
|
|
+ case GE: return "MOV.GE\t%3+%2,%0";
|
3070 |
|
|
+ case LTU: return "MOV.C\t%3+%2,%0";
|
3071 |
|
|
+ case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
3072 |
202 |
dgisselq |
+ case GEU: return "MOV.NC\t%3+%2,%0";
|
3073 |
|
|
+ case GTU: return "BZ\t.Laddcc%=\n\tMOV.NC\t%3+%2,%0\n\t.Laddcc%=:";
|
3074 |
102 |
dgisselq |
+ default:
|
3075 |
|
|
+ internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
|
3076 |
|
|
+ break;
|
3077 |
|
|
+ }
|
3078 |
|
|
+ }
|
3079 |
|
|
+
|
3080 |
|
|
+ return "BREAK";
|
3081 |
|
|
+}
|
3082 |
|
|
+
|
3083 |
103 |
dgisselq |
+static int zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
|
3084 |
102 |
dgisselq |
+ int rv = 14;
|
3085 |
|
|
+ if ((mode == DImode)||(mode == DFmode))
|
3086 |
|
|
+ rv += 2;
|
3087 |
|
|
+ return rv;
|
3088 |
|
|
+}
|
3089 |
|
|
+
|
3090 |
103 |
dgisselq |
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
|
3091 |
117 |
dgisselq |
+static bool zip_cannot_modify_jumps_p(void) {
|
3092 |
|
|
+ // Let's try their suggested approach, keeping us from modifying jumps
|
3093 |
|
|
+ // after reload. This should also allow our peephole2 optimizations
|
3094 |
|
|
+ // to adjust things back to what they need to be if necessary.
|
3095 |
|
|
+ return (reload_completed || reload_in_progress);
|
3096 |
|
|
+}
|
3097 |
122 |
dgisselq |
+
|
3098 |
|
|
+rtx_insn *zip_ifcvt_info;
|
3099 |
|
|
+
|
3100 |
|
|
+void
|
3101 |
|
|
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
|
3102 |
202 |
dgisselq |
+ const bool dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
|
3103 |
122 |
dgisselq |
+ if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
|
3104 |
|
|
+ if (*true_expr) switch(GET_CODE(*true_expr)) {
|
3105 |
202 |
dgisselq |
+ // These are our unsupported conditions
|
3106 |
122 |
dgisselq |
+ case LE:
|
3107 |
202 |
dgisselq |
+ case GT:
|
3108 |
|
|
+ case LEU:
|
3109 |
122 |
dgisselq |
+ case GTU:
|
3110 |
|
|
+ if (dbg) fprintf(stderr, "TRUE, missing expr\n");
|
3111 |
|
|
+ if (dbg) zip_debug_rtx(*true_expr);
|
3112 |
|
|
+ *true_expr = NULL_RTX;
|
3113 |
|
|
+ break;
|
3114 |
|
|
+ default: // LT, GT, GTE, LTU, NE, EQ
|
3115 |
|
|
+ break;
|
3116 |
|
|
+ }
|
3117 |
|
|
+
|
3118 |
|
|
+ if (*false_expr) switch(GET_CODE(*false_expr)) {
|
3119 |
|
|
+ case LE:
|
3120 |
202 |
dgisselq |
+ case GT:
|
3121 |
|
|
+ case LEU:
|
3122 |
122 |
dgisselq |
+ case GTU:
|
3123 |
|
|
+ if (dbg) fprintf(stderr, "FALSE, missing expr\n");
|
3124 |
|
|
+ if (dbg) zip_debug_rtx(*false_expr);
|
3125 |
|
|
+ *false_expr = NULL_RTX;
|
3126 |
|
|
+ default:
|
3127 |
|
|
+ break;
|
3128 |
|
|
+ }
|
3129 |
|
|
+ if ((dbg)&&((!*true_expr)||(!*false_expr)))
|
3130 |
|
|
+ fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n");
|
3131 |
|
|
+}
|
3132 |
|
|
+
|
3133 |
|
|
+void
|
3134 |
142 |
dgisselq |
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
|
3135 |
122 |
dgisselq |
+/*
|
3136 |
142 |
dgisselq |
+if (!ceinfo->then_bb)
|
3137 |
|
|
+ return;
|
3138 |
|
|
+rtx_insn *insn;
|
3139 |
|
|
+FOR_BB_INSNS(ceinfo->then_bb, insn) {
|
3140 |
|
|
+ fprintf(stderr, "IFCVT -- INIT\n");
|
3141 |
|
|
+ zip_debug_rtx_pfx("INIT-BB", insn);
|
3142 |
122 |
dgisselq |
+}
|
3143 |
|
|
+*/
|
3144 |
|
|
+/*
|
3145 |
|
|
+ zip_ifcvt_info = NULL;
|
3146 |
|
|
+ rtx_insn *insn, *ifinsn = NULL;
|
3147 |
|
|
+ FOR_BB_INSNS(ceinfo->test_bb, insn) {
|
3148 |
|
|
+ rtx p;
|
3149 |
|
|
+ p = single_set(insn);
|
3150 |
|
|
+ if (!p) continue;
|
3151 |
|
|
+ if (SET_DEST(p)==pc_rtx) {
|
3152 |
|
|
+ ifinsn = insn;
|
3153 |
|
|
+ }
|
3154 |
|
|
+ if (!REG_P(SET_DEST(p)))
|
3155 |
|
|
+ continue;
|
3156 |
|
|
+ if (GET_MODE(SET_DEST(p))!=CCmode)
|
3157 |
|
|
+ continue;
|
3158 |
|
|
+ if (REGNO(SET_DEST(p))!=zip_CC)
|
3159 |
|
|
+ continue;
|
3160 |
|
|
+ zip_ifcvt_info = insn;
|
3161 |
|
|
+ }
|
3162 |
|
|
+
|
3163 |
|
|
+ if (zip_ifcvt_info)
|
3164 |
|
|
+ zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info);
|
3165 |
|
|
+ if (ifinsn)
|
3166 |
|
|
+ zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
|
3167 |
|
|
+*/
|
3168 |
|
|
+}
|
3169 |
|
|
+
|
3170 |
142 |
dgisselq |
+void
|
3171 |
|
|
+zip_ifcvt_modify_insn(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED,
|
3172 |
|
|
+ rtx pattern ATTRIBUTE_UNUSED,
|
3173 |
|
|
+ rtx_insn *insn ATTRIBUTE_UNUSED) {
|
3174 |
|
|
+ // zip_debug_rtx_pfx("MODIFY-INSN: ", insn);
|
3175 |
|
|
+}
|
3176 |
|
|
+
|
3177 |
|
|
+void
|
3178 |
|
|
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
|
3179 |
|
|
+/*
|
3180 |
|
|
+ fprintf(stderr, "IFCVT -- CANCEL\n");
|
3181 |
|
|
+ zip_ifcvt_info = NULL;
|
3182 |
|
|
+*/
|
3183 |
|
|
+}
|
3184 |
|
|
+
|
3185 |
|
|
+void
|
3186 |
|
|
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
|
3187 |
|
|
+/*
|
3188 |
|
|
+rtx_insn *insn;
|
3189 |
|
|
+FOR_BB_INSNS(ceinfo->test_bb, insn) {
|
3190 |
|
|
+ fprintf(stderr, "IFCVT -- FINAL\n");
|
3191 |
|
|
+ zip_debug_rtx_pfx("FINAL-TEST-BB", insn);
|
3192 |
|
|
+}
|
3193 |
|
|
+ zip_ifcvt_info = NULL;
|
3194 |
|
|
+*/
|
3195 |
|
|
+}
|
3196 |
|
|
+
|
3197 |
|
|
+
|
3198 |
127 |
dgisselq |
+int zip_insn_sets_cc(rtx_insn *insn) {
|
3199 |
|
|
+ return (get_attr_ccresult(insn)==CCRESULT_SET);
|
3200 |
|
|
+}
|
3201 |
|
|
+
|
3202 |
202 |
dgisselq |
+const char *
|
3203 |
|
|
+zip_cbranchdi_const(rtx comparison,
|
3204 |
|
|
+ rtx a ATTRIBUTE_UNUSED,
|
3205 |
|
|
+ rtx b,
|
3206 |
|
|
+ rtx label ATTRIBUTE_UNUSED) {
|
3207 |
|
|
+ gcc_assert(CONST_INT_P(b));
|
3208 |
|
|
+ long value = INTVAL(b);
|
3209 |
|
|
+
|
3210 |
|
|
+ // Look into the combine routines to find out why this routine never
|
3211 |
|
|
+ // gets called.
|
3212 |
|
|
+
|
3213 |
|
|
+ switch(GET_CODE(comparison)) {
|
3214 |
|
|
+ case EQ:
|
3215 |
|
|
+ if (value < 0)
|
3216 |
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# EQ (neg)\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
|
3217 |
|
|
+ else
|
3218 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# EQ\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
|
3219 |
|
|
+ case NE:
|
3220 |
|
|
+ if (value < 0)
|
3221 |
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# NE (neg)\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
|
3222 |
|
|
+ else
|
3223 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# NE\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
|
3224 |
|
|
+ case LE:
|
3225 |
|
|
+ if (value == 0)
|
3226 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LE 0\n\tBLT\t%3\n\tCMP.Z\t0,%L1\n\tBZ\t%3";
|
3227 |
|
|
+ else if (value == -1)
|
3228 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LE -1\n\tBLT\t%3";
|
3229 |
|
|
+ else if (value < 0) {
|
3230 |
|
|
+ char tmp[128];
|
3231 |
|
|
+ sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# LE (neg)\n"
|
3232 |
|
|
+ "\tBLT\t.Lcmpdile%%=\n"
|
3233 |
|
|
+ "\tBNZ\t%%3\n"
|
3234 |
|
|
+ "\tCMP\t%ld,%%L1\n"
|
3235 |
|
|
+ "\tBC\t%%3", (value+1l)&0x0ffffffff);
|
3236 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3237 |
|
|
+ } else { //; value > 0
|
3238 |
|
|
+ char tmp[128];
|
3239 |
|
|
+ sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LE\n"
|
3240 |
|
|
+ "\tBLT\t%%3\n"
|
3241 |
|
|
+ "\tBNZ\t.Lcmple%%=\n"
|
3242 |
|
|
+ "\tCMP\t%ld,%%L1\n"
|
3243 |
|
|
+ "\tBC\t%%3\n"
|
3244 |
|
|
+ ".Lcmple%%=:", value-1);
|
3245 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3246 |
|
|
+ }
|
3247 |
|
|
+ case LT:
|
3248 |
|
|
+ if (value == 0)
|
3249 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LT 0\n\tBLT\t%3";
|
3250 |
|
|
+ else if (value < 0)
|
3251 |
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# LT neg\n\tCMP.Z\t%2,%L1\n\tBC\t%3";
|
3252 |
|
|
+ else
|
3253 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# LT\n"
|
3254 |
|
|
+ "\tBLT\t%3\n"
|
3255 |
|
|
+ "\tBNZ\t.Lcmplt%=\n"
|
3256 |
|
|
+ "\tCMP\t%2,%L1\n"
|
3257 |
|
|
+ "\tBC\t%3\n"
|
3258 |
|
|
+ ".Lcmplt%=:";
|
3259 |
|
|
+ case GT:
|
3260 |
|
|
+ if (value == 0)
|
3261 |
|
|
+ return "CMP\t1,%H1\t; cbranchdi/# GT 0\n"
|
3262 |
|
|
+ "\tBGE\t%3\n"
|
3263 |
|
|
+ "\tBNZ\t.Lcmpgt%=\n"
|
3264 |
|
|
+ "\tCMP\t0,%L1\n"
|
3265 |
|
|
+ "\tBNZ\t%3\n"
|
3266 |
|
|
+ ".Lcmpgt%=:";
|
3267 |
|
|
+ else if (value == -1)
|
3268 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GT -1\n"
|
3269 |
|
|
+ "\tBGE\t%3\n";
|
3270 |
|
|
+ else if (value < 0) {
|
3271 |
|
|
+ char tmp[128];
|
3272 |
|
|
+ sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# GT neg\n"
|
3273 |
|
|
+ "\tBLT\t.Lcmpgt%%=\n"
|
3274 |
|
|
+ "\tBNZ\t%%3\n"
|
3275 |
|
|
+ "\tCMP\t%ld,%%H3\n"
|
3276 |
|
|
+ "\tBNC\t%%3\n"
|
3277 |
|
|
+ ".Lcmpgt%%=:", value+1l);
|
3278 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3279 |
|
|
+ } else {
|
3280 |
|
|
+ char tmp[128];
|
3281 |
|
|
+ sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# GT\n"
|
3282 |
|
|
+ "\tBLT\t.Lcmpgt%%=\n"
|
3283 |
|
|
+ "\tBNZ\t%%3\n"
|
3284 |
|
|
+ "\tCMP\t%ld,%%L1\n"
|
3285 |
|
|
+ "\tBNC\t%%3\n"
|
3286 |
|
|
+ ".Lcmpgt%%=:", value+1l);
|
3287 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3288 |
|
|
+ }
|
3289 |
|
|
+ case GE:
|
3290 |
|
|
+ if (value == 0)
|
3291 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GE 0\n"
|
3292 |
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
3293 |
|
|
+ "\tBNZ\t%3\n"
|
3294 |
|
|
+ "\tCMP\t0,%L1\n"
|
3295 |
|
|
+ "\tBNC\t%3\n"
|
3296 |
|
|
+ ".Lcmpge%=:";
|
3297 |
|
|
+ else if (value == -1)
|
3298 |
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# GE -1\n"
|
3299 |
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
3300 |
|
|
+ "\tBNZ\t%3\n"
|
3301 |
|
|
+ "\tCMP\t-1,%L1\n"
|
3302 |
|
|
+ "\tBZ\t%3\n"
|
3303 |
|
|
+ ".Lcmpge%=:";
|
3304 |
|
|
+ else if (value < 0)
|
3305 |
|
|
+ return "CMP\t-1,%H1\t; cbranchdi/# GE <\n"
|
3306 |
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
3307 |
|
|
+ "\tBNZ\t%3\n"
|
3308 |
|
|
+ "\tCMP\t%2,%L1\n"
|
3309 |
|
|
+ "\tBNC\t%3\n"
|
3310 |
|
|
+ ".Lcmpge%=:";
|
3311 |
|
|
+ else
|
3312 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GE\n"
|
3313 |
|
|
+ "\tBLT\t.Lcmpge%=\n"
|
3314 |
|
|
+ "\tBNZ\t%3\n"
|
3315 |
|
|
+ "\tCMP\t%2,%L1\n"
|
3316 |
|
|
+ "\tBNC\t%3\n"
|
3317 |
|
|
+ ".Lcmpge%=:";
|
3318 |
|
|
+ case LTU:
|
3319 |
|
|
+ if (value == 0) { //; Impossible, cannot be < 0 unsignd
|
3320 |
|
|
+ return "; cbranchdi/# LTU 0 (Impossible!)";
|
3321 |
|
|
+ } else
|
3322 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/#\n\tCMP.Z\t%2,%L1\n\tBC\t%3\n";
|
3323 |
|
|
+ case LEU:
|
3324 |
|
|
+ if (value == 0) { //; Only possible if == 0
|
3325 |
|
|
+ return "CMP\t0,%%H0\t; cbranchdi/# LEU 0\n"
|
3326 |
|
|
+ "\tCMP.Z\t0,%%L0\n"
|
3327 |
|
|
+ "\tBZ\t%3";
|
3328 |
|
|
+ } else {
|
3329 |
|
|
+ //; Subtract one, and LTU works
|
3330 |
|
|
+ char tmp[128];
|
3331 |
|
|
+ sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LEU\n"
|
3332 |
|
|
+ "\tCMP.Z\t%ld,%%L1\n"
|
3333 |
|
|
+ "\tBC\t%%3\n", value-1);
|
3334 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3335 |
|
|
+ }
|
3336 |
|
|
+ case GTU:
|
3337 |
|
|
+ if (value == 0) {
|
3338 |
|
|
+ //; Equivalent to not equal to zero
|
3339 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GTU 0\n\tCMP.Z\t0,%L1\n\tBNZ\t%3";
|
3340 |
|
|
+ } else {
|
3341 |
|
|
+ char tmp[128];
|
3342 |
|
|
+ sprintf(tmp,
|
3343 |
|
|
+ "CMP\t0,%%H1\t; cbranchdi/# GTU\n"
|
3344 |
|
|
+ "\tBNZ\t%%3\n"
|
3345 |
|
|
+ "\tCMP\t%ld,%%L1\n"
|
3346 |
|
|
+ "\tBNC\t%%3\n", value+1);
|
3347 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3348 |
|
|
+ }
|
3349 |
|
|
+ case GEU:
|
3350 |
|
|
+ if (value == 0) //; Unsigned, always true
|
3351 |
|
|
+ return "BRA\t%3\t; cbranchdi/# GEU 0";
|
3352 |
|
|
+ else
|
3353 |
|
|
+ return "CMP\t0,%H1\t; cbranchdi/# GEU\n"
|
3354 |
|
|
+ "\tBNZ\t%3\n"
|
3355 |
|
|
+ "\tCMP\t%2,%L1\n"
|
3356 |
|
|
+ "\tBNC\t%3";
|
3357 |
|
|
+ default:
|
3358 |
|
|
+ gcc_unreachable();
|
3359 |
|
|
+ }
|
3360 |
127 |
dgisselq |
+}
|
3361 |
202 |
dgisselq |
+
|
3362 |
|
|
+const char *
|
3363 |
|
|
+zip_cbranchdi_reg(rtx comparison,
|
3364 |
|
|
+ rtx a ATTRIBUTE_UNUSED,
|
3365 |
|
|
+ rtx b ATTRIBUTE_UNUSED,
|
3366 |
|
|
+ rtx label ATTRIBUTE_UNUSED) {
|
3367 |
|
|
+
|
3368 |
|
|
+ switch(GET_CODE(comparison)) {
|
3369 |
|
|
+ case EQ:
|
3370 |
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r EQ\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
|
3371 |
|
|
+ case NE:
|
3372 |
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r NE\n\tCMP.Z\t%L2,%L1\n\tBNZ\t%3";
|
3373 |
|
|
+ case LE:
|
3374 |
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r LE\n"
|
3375 |
|
|
+ "\tBLT\t%3\n"
|
3376 |
|
|
+ "\tBNZ\t.Ldi%=\n"
|
3377 |
|
|
+ "\tCMP\t%L1,%L2\n"
|
3378 |
|
|
+ "\tBNC\t%3\n"
|
3379 |
|
|
+ ".Ldi%=:";
|
3380 |
|
|
+ case GT:
|
3381 |
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r GT\n"
|
3382 |
|
|
+ "\tBLT\t%3\n"
|
3383 |
|
|
+ "\tBNZ\t.Ldi%=\n"
|
3384 |
|
|
+ "\tCMP\t%L1,%L2\n"
|
3385 |
|
|
+ "\tBC\t%3\n"
|
3386 |
|
|
+ ".Ldi%=:";
|
3387 |
|
|
+ case LT:
|
3388 |
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r LT\n"
|
3389 |
|
|
+ "\tBLT\t%3\n"
|
3390 |
|
|
+ "\tBNZ\t.Ldi%=\n"
|
3391 |
|
|
+ "\tCMP\t%L2,%L1\n"
|
3392 |
|
|
+ "\tBC\t%3\n"
|
3393 |
|
|
+ ".Ldi%=:";
|
3394 |
|
|
+ case GE:
|
3395 |
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r GE\n"
|
3396 |
|
|
+ "\tBLT\t%3\n"
|
3397 |
|
|
+ "\tBNZ\t.Ldi%=\n"
|
3398 |
|
|
+ "\tCMP\t%L2,%L1\n"
|
3399 |
|
|
+ "\tBNC\t%3\n"
|
3400 |
|
|
+ ".Ldi%=:";
|
3401 |
|
|
+ case LTU:
|
3402 |
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r LTU\n"
|
3403 |
|
|
+ "\tCMP.Z\t%L2,%L1\n"
|
3404 |
|
|
+ "\tBC\t%3\n";
|
3405 |
|
|
+ case LEU:
|
3406 |
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r LEU\n"
|
3407 |
|
|
+ "\tBC\t.Ldi%=\n" //; H1 > H2, skip
|
3408 |
|
|
+ "\tCMP.Z\t%L1,%L2\n" //; (H1==H2) test L1-L2
|
3409 |
|
|
+ "\tBNC\t%3\n" //; If (L1>=L2)||(H1>H2)
|
3410 |
|
|
+ ".Ldi%=:";
|
3411 |
|
|
+ case GTU:
|
3412 |
|
|
+ return "CMP\t%H1,%H2\t; cbranchdi/r GTU\n"
|
3413 |
|
|
+ "\tCMP.Z\t%L1,%L2\n"
|
3414 |
|
|
+ "\tBC\t%3";
|
3415 |
|
|
+ case GEU:
|
3416 |
|
|
+ return "CMP\t%H2,%H1\t; cbranchdi/r GEU\n"
|
3417 |
|
|
+ "\tBC\t.Ldi%=\n"
|
3418 |
|
|
+ "\tCMP.Z\t%L2,%L1\n"
|
3419 |
|
|
+ "\tBNC\t%3\n"
|
3420 |
|
|
+ ".Ldi%=:";
|
3421 |
|
|
+ default:
|
3422 |
|
|
+ gcc_unreachable();
|
3423 |
|
|
+ }
|
3424 |
|
|
+}
|
3425 |
|
|
+
|
3426 |
|
|
+const char *
|
3427 |
|
|
+zip_cbranchdi(rtx comparison, rtx a, rtx b, rtx label) {
|
3428 |
|
|
+ if (REG_P(b))
|
3429 |
|
|
+ return zip_cbranchdi_reg(comparison, a, b, label);
|
3430 |
|
|
+ else
|
3431 |
|
|
+ return zip_cbranchdi_const(comparison, a, b, label);
|
3432 |
|
|
+}
|
3433 |
|
|
+
|
3434 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zipdbg.h gcc-6.2.0-zip/gcc/config/zip/zipdbg.h
|
3435 |
|
|
--- gcc-6.2.0/gcc/config/zip/zipdbg.h 1969-12-31 19:00:00.000000000 -0500
|
3436 |
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zipdbg.h 2017-02-17 16:47:25.727651898 -0500
|
3437 |
|
|
@@ -0,0 +1,8 @@
|
3438 |
|
|
+#define DO_ZIP_DEBUGS
|
3439 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
3440 |
|
|
+#include <stdio.h>
|
3441 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
3442 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
3443 |
|
|
+#else
|
3444 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
3445 |
|
|
+#endif
|
3446 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md
|
3447 |
|
|
--- gcc-6.2.0/gcc/config/zip/zip-di.md 1969-12-31 19:00:00.000000000 -0500
|
3448 |
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md 2017-02-22 15:56:17.195319460 -0500
|
3449 |
|
|
@@ -0,0 +1,528 @@
|
3450 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3451 |
|
|
+;;
|
3452 |
|
|
+;; Filename: zip-di.md
|
3453 |
|
|
+;;
|
3454 |
|
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
3455 |
|
|
+;;
|
3456 |
|
|
+;; Purpose: This is the machine description of the Zip CPU as needed by the
|
3457 |
|
|
+;; GNU compiler collection (GCC). Specifically, this is the
|
3458 |
|
|
+;; section of the description associated with 64-bit values and
|
3459 |
|
|
+;; arithmetic.
|
3460 |
|
|
+;;
|
3461 |
|
|
+;;
|
3462 |
|
|
+;; Creator: Dan Gisselquist, Ph.D.
|
3463 |
|
|
+;; Gisselquist Technology, LLC
|
3464 |
|
|
+;;
|
3465 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3466 |
|
|
+;;
|
3467 |
|
|
+;; Copyright (C) 2015, Gisselquist Technology, LLC
|
3468 |
|
|
+;;
|
3469 |
|
|
+;; This program is free software (firmware): you can redistribute it and/or
|
3470 |
|
|
+;; modify it under the terms of the GNU General Public License as published
|
3471 |
|
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
3472 |
|
|
+;; your option) any later version.
|
3473 |
|
|
+;;
|
3474 |
|
|
+;; This program is distributed in the hope that it will be useful, but WITHOUT
|
3475 |
|
|
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
3476 |
|
|
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
3477 |
|
|
+;; for more details.
|
3478 |
|
|
+;;
|
3479 |
|
|
+;; License: GPL, v3, as defined and found on www.gnu.org,
|
3480 |
|
|
+;; http://www.gnu.org/licenses/gpl.html
|
3481 |
|
|
+;;
|
3482 |
|
|
+;;
|
3483 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3484 |
|
|
+;;
|
3485 |
|
|
+;;
|
3486 |
|
|
+;
|
3487 |
|
|
+;
|
3488 |
|
|
+;
|
3489 |
|
|
+(define_expand "movdi"
|
3490 |
|
|
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
3491 |
|
|
+ (match_operand:DI 1 "general_operand" ""))]
|
3492 |
|
|
+ "(ZIP_HAS_DI)"
|
3493 |
|
|
+ {
|
3494 |
|
|
+ if (zip_expand_movdi(operands[0], operands[1]))
|
3495 |
|
|
+ DONE;
|
3496 |
|
|
+ FAIL;
|
3497 |
|
|
+ }
|
3498 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
3499 |
|
|
+;
|
3500 |
|
|
+;
|
3501 |
|
|
+;
|
3502 |
|
|
+(define_insn "movdi_raw"
|
3503 |
|
|
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,Q,r,r")
|
3504 |
|
|
+ (match_operand:DI 1 "general_operand" "r,r,Q,i"))]
|
3505 |
|
|
+ "(ZIP_HAS_DI)"
|
3506 |
|
|
+ {
|
3507 |
|
|
+ if ((REG_P(operands[0]))&&(REG_P(operands[1])))
|
3508 |
|
|
+ return "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";
|
3509 |
|
|
+ else if (MEM_P(operands[0])) //; StoreDI
|
3510 |
|
|
+ return "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";
|
3511 |
|
|
+ else if (MEM_P(operands[1])) //; LoadDI
|
3512 |
|
|
+ return "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";
|
3513 |
|
|
+ else if (CONST_INT_P(operands[1])) {
|
3514 |
|
|
+ char tmp[128];
|
3515 |
|
|
+ HOST_WIDE_INT v = INTVAL(operands[1]);
|
3516 |
|
|
+ sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",
|
3517 |
|
|
+ (unsigned)(v>>32),
|
3518 |
|
|
+ (unsigned)(v));
|
3519 |
|
|
+ return ggc_alloc_string(tmp, -1);
|
3520 |
|
|
+ } else
|
3521 |
|
|
+ gcc_unreachable();
|
3522 |
|
|
+ }
|
3523 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
3524 |
|
|
+;
|
3525 |
|
|
+;
|
3526 |
|
|
+;
|
3527 |
|
|
+; ADD
|
3528 |
|
|
+;
|
3529 |
|
|
+;
|
3530 |
|
|
+(define_insn "adddi3" ; Fastest/best instruction always goes first
|
3531 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3532 |
|
|
+ (plus:DI (match_operand:DI 1 "register_operand" "0")
|
3533 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3534 |
|
|
+ (clobber (reg:CC CC_REG))
|
3535 |
|
|
+ ]
|
3536 |
|
|
+ "(ZIP_HAS_DI)"
|
3537 |
|
|
+ "ADD %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
|
3538 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3539 |
|
|
+;
|
3540 |
|
|
+;
|
3541 |
|
|
+;
|
3542 |
|
|
+; SUB
|
3543 |
|
|
+;
|
3544 |
|
|
+;
|
3545 |
|
|
+(define_insn "subdi3"
|
3546 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3547 |
|
|
+ (minus:DI (match_operand:DI 1 "register_operand" "0")
|
3548 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3549 |
|
|
+ (clobber (reg:CC CC_REG))
|
3550 |
|
|
+ ]
|
3551 |
|
|
+ "(ZIP_HAS_DI)"
|
3552 |
|
|
+ "SUB %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
|
3553 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3554 |
|
|
+;
|
3555 |
|
|
+;
|
3556 |
|
|
+;
|
3557 |
|
|
+; AND
|
3558 |
|
|
+;
|
3559 |
|
|
+;
|
3560 |
|
|
+(define_insn "anddi3"
|
3561 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3562 |
|
|
+ (and:DI (match_operand:DI 1 "register_operand" "%0")
|
3563 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3564 |
|
|
+ (clobber (reg:CC CC_REG))
|
3565 |
|
|
+ ]
|
3566 |
|
|
+ "(ZIP_HAS_DI)"
|
3567 |
|
|
+ "AND %L2,%L0\t; AND:DI\n\tAND\t%H2,%H0"
|
3568 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3569 |
|
|
+;
|
3570 |
|
|
+;
|
3571 |
|
|
+;
|
3572 |
|
|
+; iOR
|
3573 |
|
|
+;
|
3574 |
|
|
+;
|
3575 |
|
|
+(define_insn "iordi3"
|
3576 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3577 |
|
|
+ (ior:DI (match_operand:DI 1 "register_operand" "%0")
|
3578 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3579 |
|
|
+ (clobber (reg:CC CC_REG))
|
3580 |
|
|
+ ]
|
3581 |
|
|
+ "(ZIP_HAS_DI)"
|
3582 |
|
|
+ "OR %L2,%L0\t; OR:DI\n\tOR\t%H2,%H0"
|
3583 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3584 |
|
|
+;
|
3585 |
|
|
+;
|
3586 |
|
|
+;
|
3587 |
|
|
+; XOR
|
3588 |
|
|
+;
|
3589 |
|
|
+;
|
3590 |
|
|
+(define_insn "xordi3"
|
3591 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3592 |
|
|
+ (xor:DI (match_operand:DI 1 "register_operand" "%0")
|
3593 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3594 |
|
|
+ (clobber (reg:CC CC_REG))
|
3595 |
|
|
+ ]
|
3596 |
|
|
+ "(ZIP_HAS_DI)"
|
3597 |
|
|
+ "XOR %L2,%L0\t; XOR:DI\n\tXOR\t%H2,%H0"
|
3598 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3599 |
|
|
+;
|
3600 |
|
|
+;
|
3601 |
|
|
+; NEG
|
3602 |
|
|
+;
|
3603 |
|
|
+;
|
3604 |
|
|
+(define_insn "negdi2"
|
3605 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3606 |
|
|
+ (neg:DI (match_operand:DI 1 "register_operand" "0")))
|
3607 |
|
|
+ (clobber (reg:CC CC_REG))
|
3608 |
|
|
+ ]
|
3609 |
|
|
+ "(ZIP_HAS_DI)"
|
3610 |
|
|
+ "XOR -1,%L0\t; NEG:DI\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
|
3611 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3612 |
|
|
+;
|
3613 |
|
|
+;
|
3614 |
|
|
+;
|
3615 |
|
|
+; ABS
|
3616 |
|
|
+;
|
3617 |
|
|
+;
|
3618 |
|
|
+(define_insn "absdi2"
|
3619 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3620 |
|
|
+ (abs:DI (match_operand:DI 1 "register_operand" "0")))
|
3621 |
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
3622 |
|
|
+ (clobber (reg:CC CC_REG))
|
3623 |
|
|
+ ]
|
3624 |
|
|
+ "(ZIP_HAS_DI)"
|
3625 |
|
|
+ "CLR %2 ; ABSDI
|
3626 |
|
|
+ TEST %H0
|
3627 |
|
|
+ LDILO.LT 1,%2
|
3628 |
|
|
+ XOR.LT -1,%L0
|
3629 |
|
|
+ XOR.LT -1,%H0
|
3630 |
|
|
+ ADD %2,%L0
|
3631 |
|
|
+ ADD.C 1,%H0"
|
3632 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3633 |
|
|
+;
|
3634 |
|
|
+;
|
3635 |
|
|
+; NOT
|
3636 |
|
|
+;
|
3637 |
|
|
+;
|
3638 |
|
|
+(define_insn "one_cmpldi2"
|
3639 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3640 |
|
|
+ (not:DI (match_operand:DI 1 "register_operand" "0")))
|
3641 |
|
|
+ (clobber (reg:CC CC_REG))
|
3642 |
|
|
+ ]
|
3643 |
|
|
+ "(ZIP_HAS_DI)"
|
3644 |
|
|
+ "XOR -1,%L0\t; NOT:DI\n\tXOR\t-1,%H0"
|
3645 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3646 |
|
|
+;
|
3647 |
|
|
+;
|
3648 |
|
|
+; Unsigned min/max
|
3649 |
|
|
+;
|
3650 |
|
|
+;
|
3651 |
|
|
+(define_insn "umindi3"
|
3652 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3653 |
|
|
+ (umin:DI (match_operand:DI 1 "register_operand" "%0")
|
3654 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3655 |
|
|
+ (clobber (reg:CC CC_REG))
|
3656 |
|
|
+ ]
|
3657 |
|
|
+ "(ZIP_HAS_DI)"
|
3658 |
|
|
+ "CMP %H0,%H2 ; umin:DI
|
3659 |
|
|
+ CMP.Z %L0,%L2
|
3660 |
|
|
+ MOV.C %H2,%H0
|
3661 |
|
|
+ MOV.C %L2,%L0"
|
3662 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3663 |
|
|
+(define_insn "umaxdi3"
|
3664 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3665 |
|
|
+ (umax:DI (match_operand:DI 1 "register_operand" "%0")
|
3666 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3667 |
|
|
+ (clobber (reg:CC CC_REG))
|
3668 |
|
|
+ ]
|
3669 |
|
|
+ "(ZIP_HAS_DI)"
|
3670 |
|
|
+ "CMP %H2,%H0 ; umax:DI
|
3671 |
|
|
+ CMP.Z %L2,%L0
|
3672 |
|
|
+ MOV.C %H2,%H0
|
3673 |
|
|
+ MOV.C %L2,%L0"
|
3674 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3675 |
|
|
+;
|
3676 |
|
|
+;
|
3677 |
|
|
+; Multiply
|
3678 |
|
|
+;
|
3679 |
|
|
+;
|
3680 |
|
|
+(define_expand "muldi3"
|
3681 |
|
|
+ [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
|
3682 |
|
|
+ (mult:DI (match_operand:DI 1 "register_operand" "r")
|
3683 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3684 |
|
|
+ (clobber (match_dup 1))
|
3685 |
|
|
+ (clobber (match_dup 2))
|
3686 |
|
|
+ (clobber (match_scratch:SI 3 "=r"))
|
3687 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
3688 |
|
|
+ "(ZIP_HAS_DI)")
|
3689 |
|
|
+;
|
3690 |
|
|
+(define_insn "muldi3_raw"
|
3691 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
3692 |
|
|
+ (mult:DI (match_operand:DI 1 "register_operand" "r")
|
3693 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
3694 |
|
|
+ (clobber (match_dup 1))
|
3695 |
|
|
+ (clobber (match_dup 2))
|
3696 |
|
|
+ (clobber (match_scratch:SI 3 "=r"))
|
3697 |
|
|
+ (clobber (reg:CC CC_REG))]
|
3698 |
|
|
+ "(ZIP_HAS_DI)"
|
3699 |
|
|
+ {
|
3700 |
|
|
+ int regno[3];
|
3701 |
|
|
+ regno[0] = REGNO(operands[0]);
|
3702 |
|
|
+ regno[1] = REGNO(operands[1]);
|
3703 |
|
|
+ regno[2] = REGNO(operands[2]);
|
3704 |
|
|
+ //; We need to adjust what we are doing based upon which
|
3705 |
|
|
+ //; registers are in common. We have a couple of cases:
|
3706 |
|
|
+ //;
|
3707 |
|
|
+ if ((regno[0] == regno[1])&&(regno[0] == regno[2])) {
|
3708 |
|
|
+ //; RA = RA * RA
|
3709 |
|
|
+ //;
|
3710 |
|
|
+ //; (H0:L0) = (H0:L0) * (H0:L0)
|
3711 |
|
|
+ //; (H0:L0) = (H0*2^32 + L0) * (H0 * 2^32 + L0)
|
3712 |
|
|
+ //; (H0:L0) = (H0*H0*2^64 + (H0*L0+L0*H0)*2^32 + L0 *L0)
|
3713 |
|
|
+ //; = (H0*L0+L0*H1):(L0*L0)
|
3714 |
|
|
+ //; :L0 = LOPART(L0 * L0)
|
3715 |
|
|
+ //; H0 = HIPART(L0 * L0)
|
3716 |
|
|
+ //; H0 += LOPART(H0 * L0)
|
3717 |
|
|
+ //; H0 += LOPART(L0 * H0)
|
3718 |
|
|
+ //;
|
3719 |
|
|
+ //; Rx = L0
|
3720 |
|
|
+ //; H0 *= L0 ( = LOPART( HI * LO )
|
3721 |
|
|
+ //; H0 <<= 1 ( = 2*LOPART( HI * LO ) )
|
3722 |
|
|
+ //; Rx *= L0 ( = HIPART( LO * LO )
|
3723 |
|
|
+ //; L0 *= L0 ( = LOPART( LO * LO )
|
3724 |
|
|
+ //; H0 += Rx ( = 2*LOPART( HI * LO ) + HIPART( LO *LO)
|
3725 |
|
|
+ //;
|
3726 |
|
|
+ return "; muldi3_raw/A (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
3727 |
|
|
+ "\tMOV\t%L0,%3\n"
|
3728 |
|
|
+ "\tMPY\t%L0,%H0\n"
|
3729 |
|
|
+ "\tLSL\t1,%H0\n"
|
3730 |
|
|
+ "\tMPYUHI\t%L0,%3\n"
|
3731 |
|
|
+ "\tMPY\t%L0,%L0\n"
|
3732 |
|
|
+ "\tADD\t%3,%H0";
|
3733 |
|
|
+ } else if ((regno[0] != regno[1])&&(regno[1] == regno[2])) {
|
3734 |
|
|
+ //; RA = RB * RB
|
3735 |
|
|
+ //;
|
3736 |
|
|
+ //; (H0:L0) = (H1:L1) * (H1:L1)
|
3737 |
|
|
+ //; (H0:L0) = (H1*2^32 + L1) * (H1 * 2^32 + L1)
|
3738 |
|
|
+ //; (H0:L0) = (H1*H1*2^64 + (H1*L1+L1*H1)*2^32 + L1 * L1)
|
3739 |
|
|
+ //; = (H1*L1+L1*H1):(L1*L1)
|
3740 |
|
|
+ //; :L0 = LOPART(L1 * L1)
|
3741 |
|
|
+ //; H0 = HIPART(L1 * L1)
|
3742 |
|
|
+ //; H0 += LOPART(H1 * L1)
|
3743 |
|
|
+ //; H0 += LOPART(L1 * H1)
|
3744 |
|
|
+ //;
|
3745 |
|
|
+ //; -------------------
|
3746 |
|
|
+ //; L0 = L1
|
3747 |
|
|
+ //; L0 = LOPART(L0 * L1)
|
3748 |
|
|
+ //; H0 = H1
|
3749 |
|
|
+ //; H0 = LOPART(H0 * L1)
|
3750 |
|
|
+ //; H0 <<= 1; i.e. *= 2
|
3751 |
|
|
+ //; L1 = HIPART(L1 * L1)
|
3752 |
|
|
+ //; H0 += L1
|
3753 |
|
|
+ //;
|
3754 |
|
|
+ return "; muldi3_raw/B (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
3755 |
|
|
+ "\tMOV\t%L1,%L0\n"
|
3756 |
|
|
+ "\tMPY\t%L1,%L0\n"
|
3757 |
|
|
+ "\tMOV\t%H1,%H0\n"
|
3758 |
|
|
+ "\tMPY\t%H1,%H0\n"
|
3759 |
|
|
+ "\tLSL\t1,%H0\n"
|
3760 |
|
|
+ "\tMPY\t%L1,%L1\n"
|
3761 |
|
|
+ "\tADD\t%L2,%H0";
|
3762 |
|
|
+ } else if ((regno[0] == regno[1])&&(regno[1] != regno[2])) {
|
3763 |
|
|
+ //; RA = RA * RB, with scratch Rx
|
3764 |
|
|
+ //;
|
3765 |
|
|
+ //; (H0:L0) = (H0:L0) * (H1:L1)
|
3766 |
|
|
+ //; (H0:L0) = (H0*2^32 + L0) * (H1 * 2^32 + L1)
|
3767 |
|
|
+ //; (H0:L0) = (H0*H1*2^64 + (H0*L1+L0*H1)*2^32 + L0 *L1)
|
3768 |
|
|
+ //; = (H0*L1+L0*H1):(L0*L1)
|
3769 |
|
|
+ //; Rx = L0
|
3770 |
|
|
+ //; :L0 = LOPART(L1 * R0)
|
3771 |
|
|
+ //; H0 = LOPART(H0 * L1)
|
3772 |
|
|
+ //; H0 += H1 = LOPART(Rx * H1)
|
3773 |
|
|
+ //; H0 += HIPART(L1 * Rx)
|
3774 |
|
|
+ //;
|
3775 |
|
|
+ return "; muldi3_raw/C (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
3776 |
|
|
+ "\tMOV\t%L0,%3\n"
|
3777 |
|
|
+ "\tMPY\t%L1,%L0\n"
|
3778 |
|
|
+ "\tMOV\t%L1,%H0\n"
|
3779 |
|
|
+ "\tMPY\t%H1,%H0\n"
|
3780 |
|
|
+ "\tMPY\t%3,%H1\n"
|
3781 |
|
|
+ "\tADD\t%H1,%H0\n"
|
3782 |
|
|
+ "\tMPY\t%3,%L1\n"
|
3783 |
|
|
+ "\tADD\t%L1,%H0";
|
3784 |
|
|
+ } else {
|
3785 |
|
|
+ //; RA = RB * RC
|
3786 |
|
|
+ //;
|
3787 |
|
|
+ //; (H0:L0) = (H1:L1) * (H2:L2)
|
3788 |
|
|
+ //; (H0:L0) = (H1*2^32 + L1) * (H2 * 2^32 + L2)
|
3789 |
|
|
+ //; (H0:L0) = (H1*H2*2^64 + (H1*L2+L1*H2)*2^32 + L1 *L2)
|
3790 |
|
|
+ //; = (H1*L2+L1*H2):(L1*L2)
|
3791 |
|
|
+ //; :L0 = LOPART(L1 * L2)
|
3792 |
|
|
+ //; H0 = HIPART(L1 * L2)
|
3793 |
|
|
+ //; H0 += LOPART(H1 * L2)
|
3794 |
|
|
+ //; H0 += LOPART(L1 * H2)
|
3795 |
|
|
+ //;
|
3796 |
|
|
+ //; We can re-order this to try to save some registers
|
3797 |
|
|
+ //;
|
3798 |
|
|
+ //; H1 *= L0 // Was H1 * L2
|
3799 |
|
|
+ //; :L0 = LOPART(L1 * L2)
|
3800 |
|
|
+ //; H0 = LOPART(L1 * R1)
|
3801 |
|
|
+ //; H0 += HIPART(L1 * H2)
|
3802 |
|
|
+ //; H0 += H1
|
3803 |
|
|
+ //;
|
3804 |
|
|
+ return "; muldi3_raw/D (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
|
3805 |
|
|
+ "\tMPY %L2,%H1 ; H1 = H1 * L2\n"
|
3806 |
|
|
+ "\tMPY %L1,%H2 ; H2 = L1 * L2\n"
|
3807 |
|
|
+ "\tMOV %L2,%L0 ; H0:L0 = L1 * L2\n"
|
3808 |
|
|
+ "\tMOV %L2,%H0\n"
|
3809 |
|
|
+ "\tMPY %L1,%L0\n"
|
3810 |
|
|
+ "\tMPYUHI %L1,%H0\n"
|
3811 |
|
|
+ "\tADD %H2,%H0 ; H0 += (H2 = L1 * H2)\n"
|
3812 |
|
|
+ "\tADD %H1,%H0 ; H0 += (H1 = H1 * L2)";
|
3813 |
|
|
+ }
|
3814 |
|
|
+ }
|
3815 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3816 |
|
|
+;
|
3817 |
|
|
+;
|
3818 |
|
|
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
|
3819 |
|
|
+; div:di, divu:di (library routine)
|
3820 |
|
|
+;
|
3821 |
|
|
+;
|
3822 |
|
|
+;
|
3823 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3824 |
|
|
+;;
|
3825 |
|
|
+;; Conditional arithmetic instructions
|
3826 |
|
|
+;;
|
3827 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3828 |
|
|
+;
|
3829 |
|
|
+;
|
3830 |
|
|
+;
|
3831 |
|
|
+;
|
3832 |
|
|
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
|
3833 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
3834 |
|
|
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
|
3835 |
|
|
+ [(match_operand:DI 2 "register_operand" "r")
|
3836 |
|
|
+ (match_operand:DI 3 "register_operand" "r")])
|
3837 |
|
|
+ (const_int 1) (const_int 0)))
|
3838 |
|
|
+ (clobber (reg:CC CC_REG))]
|
3839 |
|
|
+ "(ZIP_HAS_DI)&&(0)"
|
3840 |
|
|
+ {
|
3841 |
|
|
+ switch(GET_CODE(operands[1])) {
|
3842 |
|
|
+ case EQ: return "CLR\t%0\t; CSTORE-EQ\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
|
3843 |
|
|
+ case NE: return "CLR\t%0\t; CSTORE-NE\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
|
3844 |
|
|
+ //; Missing LT
|
3845 |
|
|
+ //; Missing LE
|
3846 |
|
|
+ //; Missing GT
|
3847 |
|
|
+ //; Missing GE
|
3848 |
|
|
+ case LTU: return "CLR\t%0\t; CSTORE-LTU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
|
3849 |
|
|
+ case LEU:
|
3850 |
|
|
+ return "CLR\t%0\t; CSTORE-LEU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
|
3851 |
|
|
+ case GTU: return "CLR\t%0\t; CSTORE-GTU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
|
3852 |
|
|
+ case GEU:
|
3853 |
|
|
+ return "CLR\t%0\t; CSTORE-GEU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
|
3854 |
|
|
+ default:
|
3855 |
|
|
+ gcc_unreachable();
|
3856 |
|
|
+ }
|
3857 |
|
|
+ }
|
3858 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3859 |
|
|
+;
|
3860 |
|
|
+;
|
3861 |
|
|
+;
|
3862 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3863 |
|
|
+;;
|
3864 |
|
|
+;; Comparison instructions, both compare and test
|
3865 |
|
|
+;;
|
3866 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3867 |
|
|
+;
|
3868 |
|
|
+;
|
3869 |
|
|
+;
|
3870 |
|
|
+(define_expand "cmpdi"
|
3871 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC
|
3872 |
|
|
+ (match_operand:DI 0 "register_operand" "r")
|
3873 |
|
|
+ (match_operand:DI 1 "nonmemory_operand" "")))]
|
3874 |
|
|
+ ""
|
3875 |
|
|
+ {
|
3876 |
|
|
+ if (!REG_P(operands[1])) {
|
3877 |
|
|
+ if (can_create_pseudo_p()) {
|
3878 |
|
|
+ //; fprintf(stderr, "Generating pseudo register for compare\n");
|
3879 |
|
|
+ rtx tmp = gen_reg_rtx(DImode);
|
3880 |
|
|
+ emit_insn(gen_movdi(tmp,operands[1]));
|
3881 |
|
|
+ operands[1] = tmp;
|
3882 |
|
|
+ emit_insn(gen_cmpdi_reg(operands[0],tmp));
|
3883 |
|
|
+ DONE;
|
3884 |
|
|
+ } else FAIL;
|
3885 |
|
|
+ }
|
3886 |
|
|
+ })
|
3887 |
|
|
+(define_insn "cmpdi_reg"
|
3888 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC
|
3889 |
|
|
+ (match_operand:SI 0 "register_operand" "r")
|
3890 |
|
|
+ (match_operand:SI 1 "register_operand" "r")))]
|
3891 |
|
|
+ ""
|
3892 |
|
|
+ "CMP\t%H1,%H0
|
3893 |
|
|
+ CMP.Z\t%L1,%L0"
|
3894 |
|
|
+ [(set_attr "ccresult" "set")])
|
3895 |
|
|
+;
|
3896 |
|
|
+;
|
3897 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3898 |
|
|
+;;
|
3899 |
|
|
+;; Conditional move instructions, since these won't accept conditional
|
3900 |
|
|
+;; execution RTL
|
3901 |
|
|
+;;
|
3902 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3903 |
|
|
+;
|
3904 |
|
|
+(define_expand "cbranchdi4"
|
3905 |
|
|
+ [(set (pc) (if_then_else
|
3906 |
|
|
+ (match_operator 0 "ordered_comparison_operator"
|
3907 |
|
|
+ [(match_operand:DI 1 "register_operand" "r")
|
3908 |
|
|
+ (match_operand:DI 2 "nonimmediate_operand" "")])
|
3909 |
|
|
+ (label_ref (match_operand 3 "" ""))
|
3910 |
|
|
+ (pc)))
|
3911 |
|
|
+ (clobber (reg:CC CC_REG))]
|
3912 |
|
|
+ "(ZIP_HAS_DI)"
|
3913 |
|
|
+ {
|
3914 |
|
|
+ if (!REG_P(operands[2])) {
|
3915 |
|
|
+ if ((CONST_INT_P(operands[2]))
|
3916 |
|
|
+ &&(INTVAL(operands[2])> -(1l<<17))
|
3917 |
|
|
+ &&(INTVAL(operands[2])<(1l<<17)-1)) {
|
3918 |
|
|
+ emit_jump_insn(gen_cbranchdi4_internal(operands[0],
|
3919 |
|
|
+ operands[1], operands[2], operands[3]));
|
3920 |
|
|
+ DONE;
|
3921 |
|
|
+ } if (can_create_pseudo_p()) {
|
3922 |
|
|
+ rtx tmp = gen_reg_rtx(DImode);
|
3923 |
|
|
+ emit_insn(gen_movsi(tmp, operands[2]));
|
3924 |
|
|
+ operands[2] = tmp;
|
3925 |
|
|
+ }
|
3926 |
|
|
+ }
|
3927 |
|
|
+
|
3928 |
|
|
+ if (REG_P(operands[2])) {
|
3929 |
|
|
+ emit_jump_insn(gen_cbranchdi4_internal(operands[0],
|
3930 |
|
|
+ operands[1], operands[2], operands[3]));
|
3931 |
|
|
+ DONE;
|
3932 |
|
|
+ }
|
3933 |
|
|
+ })
|
3934 |
|
|
+(define_insn "cbranchdi4_internal"
|
3935 |
|
|
+ [(set (pc) (if_then_else
|
3936 |
|
|
+ (match_operator 0 "ordered_comparison_operator"
|
3937 |
|
|
+ [(match_operand:DI 1 "register_operand" "r,r,r")
|
3938 |
|
|
+ (match_operand:DI 2 "nonmemory_operand" "K,x,r")])
|
3939 |
|
|
+ (label_ref (match_operand 3 "" ""))
|
3940 |
|
|
+ (pc)))
|
3941 |
|
|
+ (clobber (reg:CC CC_REG))]
|
3942 |
|
|
+ "(ZIP_HAS_DI)"
|
3943 |
|
|
+ {
|
3944 |
|
|
+ return zip_cbranchdi(operands[0], operands[1], operands[2], operands[3]);
|
3945 |
|
|
+ }
|
3946 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
3947 |
|
|
+;
|
3948 |
|
|
+;
|
3949 |
|
|
+;
|
3950 |
|
|
+;
|
3951 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3952 |
|
|
+;;
|
3953 |
|
|
+;; Unimplemented (or not yet implemented) RTL Codes
|
3954 |
|
|
+;;
|
3955 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3956 |
|
|
+;
|
3957 |
|
|
+;
|
3958 |
|
|
+;
|
3959 |
|
|
+;
|
3960 |
|
|
+;(define_insn "addvdi4"
|
3961 |
|
|
+; )
|
3962 |
|
|
+;(define_insn "subvdi4"
|
3963 |
|
|
+; )
|
3964 |
|
|
+;(define_insn "mulvdi4"
|
3965 |
|
|
+; )
|
3966 |
|
|
+;(define_insn "umulvdi4"
|
3967 |
|
|
+; )
|
3968 |
|
|
+;(define_insn "umulvdi4"
|
3969 |
|
|
+; )
|
3970 |
|
|
+;(define_insn "negvdi3"
|
3971 |
|
|
+; )
|
3972 |
|
|
+;
|
3973 |
|
|
+;(define_insn "maddsidi4"
|
3974 |
|
|
+;(define_insn "umaddsidi4"
|
3975 |
|
|
+;(define_insn "msubsidi4"
|
3976 |
|
|
+;(define_insn "umsubsidi4"
|
3977 |
|
|
+;
|
3978 |
|
|
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-float.md gcc-6.2.0-zip/gcc/config/zip/zip-float.md
|
3979 |
|
|
--- gcc-6.2.0/gcc/config/zip/zip-float.md 1969-12-31 19:00:00.000000000 -0500
|
3980 |
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip-float.md 2017-01-10 14:01:42.029341062 -0500
|
3981 |
200 |
dgisselq |
@@ -0,0 +1,138 @@
|
3982 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3983 |
|
|
+;;
|
3984 |
|
|
+;; Filename: zip-float.md
|
3985 |
|
|
+;;
|
3986 |
|
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
3987 |
|
|
+;;
|
3988 |
|
|
+;; Purpose: This is the machine description of the ZipCPU floating point
|
3989 |
|
|
+;; unit (if installed).
|
3990 |
|
|
+;;
|
3991 |
|
|
+;;
|
3992 |
|
|
+;; Creator: Dan Gisselquist, Ph.D.
|
3993 |
|
|
+;; Gisselquist Technology, LLC
|
3994 |
|
|
+;;
|
3995 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
3996 |
|
|
+;;
|
3997 |
202 |
dgisselq |
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
|
3998 |
200 |
dgisselq |
+;;
|
3999 |
|
|
+;; This program is free software (firmware): you can redistribute it and/or
|
4000 |
|
|
+;; modify it under the terms of the GNU General Public License as published
|
4001 |
|
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
4002 |
|
|
+;; your option) any later version.
|
4003 |
|
|
+;;
|
4004 |
|
|
+;; This program is distributed in the hope that it will be useful, but WITHOUT
|
4005 |
|
|
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
4006 |
|
|
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
4007 |
|
|
+;; for more details.
|
4008 |
|
|
+;;
|
4009 |
|
|
+;; License: GPL, v3, as defined and found on www.gnu.org,
|
4010 |
|
|
+;; http://www.gnu.org/licenses/gpl.html
|
4011 |
|
|
+;;
|
4012 |
|
|
+;;
|
4013 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
4014 |
|
|
+;;
|
4015 |
|
|
+;;
|
4016 |
|
|
+;
|
4017 |
|
|
+;
|
4018 |
|
|
+;
|
4019 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
4020 |
|
|
+;;
|
4021 |
|
|
+;; Floating point Op-codes
|
4022 |
|
|
+;;
|
4023 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
4024 |
|
|
+;
|
4025 |
|
|
+;
|
4026 |
|
|
+;
|
4027 |
|
|
+(define_insn "addsf3"
|
4028 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
4029 |
|
|
+ (plus:SF (match_operand:SF 1 "register_operand" "0")
|
4030 |
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
4031 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
4032 |
|
|
+ "(ZIP_FPU)"
|
4033 |
|
|
+ "FPADD %2,%0"
|
4034 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
4035 |
|
|
+(define_insn "subsf3"
|
4036 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
4037 |
|
|
+ (minus:SF (match_operand:SF 1 "register_operand" "0")
|
4038 |
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
4039 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
4040 |
|
|
+ "(ZIP_FPU)"
|
4041 |
|
|
+ "FPSUB %2,%0"
|
4042 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
4043 |
|
|
+(define_insn "mulsf3"
|
4044 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
4045 |
|
|
+ (mult:SF (match_operand:SF 1 "register_operand" "0")
|
4046 |
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
4047 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
4048 |
|
|
+ "(ZIP_FPU)"
|
4049 |
|
|
+ "FPMUL %2,%0"
|
4050 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
4051 |
|
|
+(define_insn "divsf3"
|
4052 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
4053 |
|
|
+ (div:SF (match_operand:SF 1 "register_operand" "0")
|
4054 |
|
|
+ (match_operand:SF 2 "register_operand" "r")))
|
4055 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
4056 |
|
|
+ "(ZIP_FPU)"
|
4057 |
|
|
+ "FPDIV %2,%0"
|
4058 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
4059 |
|
|
+; (define_insn "floatsisf2"
|
4060 |
|
|
+; [(set (match_operand:SF 0 "register_operand" "=r"
|
4061 |
202 |
dgisselq |
+; (float:QI (match_operand:SF 1 "register_operand" "r"))))
|
4062 |
200 |
dgisselq |
+; (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
|
4063 |
|
|
+; "(ZIP_FPU)"
|
4064 |
|
|
+; "FPI2F %1,%0")
|
4065 |
|
|
+; (define_insn "floatunssisf2" ... ?)
|
4066 |
|
|
+; (define_insn "fix_truncsfsi2"
|
4067 |
202 |
dgisselq |
+; [(set (match_operand:QI 0 "register_operand" "=r"
|
4068 |
200 |
dgisselq |
+; (float:SF (match_operand:SF 1 "register_operand" "r"))))
|
4069 |
|
|
+; (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
|
4070 |
|
|
+; "(ZIP_FPU)"
|
4071 |
|
|
+; "FPI2F %1,%0")
|
4072 |
|
|
+; (define_insn "nearbyintsf2" ... ?)
|
4073 |
|
|
+; (define_insn "truncsfsi2" ... ?)
|
4074 |
|
|
+(define_expand "negsf2"
|
4075 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
4076 |
|
|
+ (neg:SF (match_operand:SF 1 "register_operand" "0")))
|
4077 |
|
|
+ ]
|
4078 |
|
|
+ ""
|
4079 |
|
|
+ {
|
4080 |
|
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
4081 |
|
|
+ if (can_create_pseudo_p()) {
|
4082 |
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
4083 |
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
|
4084 |
|
|
+ emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
|
4085 |
|
|
+ DONE;
|
4086 |
|
|
+ } else {
|
4087 |
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
4088 |
|
|
+ emit_insn(gen_iorsi3(operands[0], operands[0],
|
4089 |
|
|
+ gen_int_mode(1,SImode)));
|
4090 |
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
4091 |
|
|
+ DONE;
|
4092 |
|
|
+ }
|
4093 |
|
|
+ })
|
4094 |
|
|
+(define_expand "abssf2"
|
4095 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
4096 |
|
|
+ (abs:SF (match_operand:SF 1 "register_operand" "0")))
|
4097 |
|
|
+ ]
|
4098 |
|
|
+ ""
|
4099 |
|
|
+ {
|
4100 |
|
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
4101 |
|
|
+ if (can_create_pseudo_p()) {
|
4102 |
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
4103 |
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
|
4104 |
|
|
+ emit_insn(gen_andsi3(operands[0], operands[0], tmp));
|
4105 |
|
|
+ DONE;
|
4106 |
|
|
+ } else {
|
4107 |
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
4108 |
|
|
+ emit_insn(gen_andsi3(operands[0], operands[0],
|
4109 |
|
|
+ gen_int_mode(-2,SImode)));
|
4110 |
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
4111 |
|
|
+ DONE;
|
4112 |
|
|
+ }
|
4113 |
|
|
+ })
|
4114 |
|
|
+;
|
4115 |
|
|
+;
|
4116 |
|
|
+; STILL MISSING:
|
4117 |
|
|
+;
|
4118 |
|
|
+;
|
4119 |
|
|
+;
|
4120 |
202 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h
|
4121 |
|
|
--- gcc-6.2.0/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
|
4122 |
|
|
+++ gcc-6.2.0-zip/gcc/config/zip/zip.h 2017-03-03 09:30:57.671304970 -0500
|
4123 |
|
|
@@ -0,0 +1,4114 @@
|
4124 |
102 |
dgisselq |
+////////////////////////////////////////////////////////////////////////////////
|
4125 |
|
|
+//
|
4126 |
|
|
+// Filename: gcc/config/zip/zip.h
|
4127 |
|
|
+//
|
4128 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
4129 |
|
|
+//
|
4130 |
|
|
+// Purpose:
|
4131 |
|
|
+//
|
4132 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
4133 |
|
|
+// Gisselquist Technology, LLC
|
4134 |
|
|
+//
|
4135 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
4136 |
|
|
+//
|
4137 |
202 |
dgisselq |
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
|
4138 |
102 |
dgisselq |
+//
|
4139 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
4140 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
4141 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
4142 |
|
|
+// your option) any later version.
|
4143 |
|
|
+//
|
4144 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
4145 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
4146 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
4147 |
|
|
+// for more details.
|
4148 |
|
|
+//
|
4149 |
|
|
+// You should have received a copy of the GNU General Public License along
|
4150 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
4151 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
4152 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
4153 |
|
|
+//
|
4154 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
4155 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
4156 |
|
|
+//
|
4157 |
|
|
+//
|
4158 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
4159 |
|
|
+#ifndef GCC_ZIP_H
|
4160 |
|
|
+#define GCC_ZIP_H
|
4161 |
|
|
+
|
4162 |
|
|
+
|
4163 |
|
|
+//
|
4164 |
|
|
+//
|
4165 |
127 |
dgisselq |
+// Zip CPU configuration defines
|
4166 |
102 |
dgisselq |
+//
|
4167 |
|
|
+//
|
4168 |
|
|
+#define ZIP_USER 0 // Assume we are in supervisor mode
|
4169 |
|
|
+#define ZIP_MULTIPLY 1 // Assume we have multiply instructions
|
4170 |
|
|
+#define ZIP_DIVIDE 1 // Assume we have divide instructions
|
4171 |
|
|
+#define ZIP_FPU 0 // Assume we have no floating point instructions
|
4172 |
|
|
+#define ZIP_PIPELINED 1 // Assume our instructions are pipelined
|
4173 |
202 |
dgisselq |
+#define ZIP_THUMB 1 // Assume we have the THUMB feature
|
4174 |
200 |
dgisselq |
+#define ZIP_ATOMIC (ZIP_PIPELINED)
|
4175 |
102 |
dgisselq |
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT
|
4176 |
|
|
+#define ZIP_HAS_DI 1
|
4177 |
127 |
dgisselq |
+// Should we use the peephole optimizations?
|
4178 |
|
|
+#define ZIP_PEEPHOLE 1 // 0 means no peephole optimizations.
|
4179 |
202 |
dgisselq |
+#define ZIP_NOT_AN_INSTRUCTION "NAI\t;// This is not an instruction. Getting here implies a compiler error. Please contact help support\n"
|
4180 |
102 |
dgisselq |
+
|
4181 |
|
|
+// Zip has 16 registers in each user mode.
|
4182 |
|
|
+// Register 15 is the program counter (PC)
|
4183 |
|
|
+// Register 14 is the condition codes (CC)
|
4184 |
|
|
+// Register 13 is the stack pointer (SP)
|
4185 |
|
|
+// Register 12 (may be) the Global Offset Table pointer (GOT)
|
4186 |
|
|
+// Register 0 (may be) the return address pointer
|
4187 |
|
|
+// Registers 16-31 may only be used in supervisor mode.
|
4188 |
|
|
+#define is_ZIP_GENERAL_REG(REGNO) ((REGNO)<13)
|
4189 |
171 |
dgisselq |
+#define is_ZIP_REG(REGNO) ((REGNO)<33)
|
4190 |
102 |
dgisselq |
+
|
4191 |
171 |
dgisselq |
+#define zip_AP_PSEUDO 32
|
4192 |
103 |
dgisselq |
+#define zip_PC 15
|
4193 |
|
|
+#define zip_CC 14
|
4194 |
|
|
+#define zip_SP 13
|
4195 |
|
|
+#define zip_FP 12
|
4196 |
|
|
+#define zip_GOT 11
|
4197 |
171 |
dgisselq |
+// #define zip_AP 10 // We're using a PSEUDO REG instead
|
4198 |
202 |
dgisselq |
+#define zip_R5 5 // Used for the static chain, if it exists
|
4199 |
103 |
dgisselq |
+#define zip_R1 1
|
4200 |
|
|
+#define zip_R0 0
|
4201 |
202 |
dgisselq |
+#define zip_LR zip_R0 // Link Register is also R0
|
4202 |
102 |
dgisselq |
+
|
4203 |
|
|
+#define ZIP_FIRST_ARG_REGNO 1
|
4204 |
|
|
+#define ZIP_LAST_ARG_REGNO 5
|
4205 |
111 |
dgisselq |
+#define NUM_ARG_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
4206 |
|
|
+#define MAX_PARM_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
4207 |
102 |
dgisselq |
+
|
4208 |
|
|
+/* The overall framework of an assembler file */
|
4209 |
|
|
+
|
4210 |
|
|
+#define ASM_COMMENT_START ";"
|
4211 |
|
|
+#define ASM_APP_ON ""
|
4212 |
|
|
+#define ASM_APP_OFF ""
|
4213 |
|
|
+
|
4214 |
|
|
+#define FILE_ASM_OP "\t.file\n"
|
4215 |
|
|
+
|
4216 |
|
|
+/* Output and Generation of Labels */
|
4217 |
|
|
+#define GLOBAL_ASM_OP "\t.global\t"
|
4218 |
|
|
+
|
4219 |
202 |
dgisselq |
+#define BITS_PER_WORD 32
|
4220 |
102 |
dgisselq |
+
|
4221 |
|
|
+
|
4222 |
|
|
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
|
4223 |
|
|
+ * for an instruction operand X. */
|
4224 |
|
|
+#define PRINT_OPERAND(STREAM, X, CODE) zip_print_operand(STREAM, X, CODE)
|
4225 |
|
|
+#define PRINT_OPERAND_ADDRESS(STREAM, X) zip_print_operand_address(STREAM, X)
|
4226 |
|
|
+
|
4227 |
|
|
+/* Passing arguments in registers */
|
4228 |
|
|
+#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO)==zip_R1)
|
4229 |
|
|
+
|
4230 |
|
|
+/* Define how to find the value returned by a function. VALTYPE is the data
|
4231 |
|
|
+ * type of the value (as a tree). If the precise function being called is known
|
4232 |
|
|
+ * FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */
|
4233 |
|
|
+#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG(TYPE_MODE(VALTYPE), zip_R1)
|
4234 |
|
|
+
|
4235 |
|
|
+/* Define how to find the value returned by a library function assuming the
|
4236 |
|
|
+ * value has mode MODE.
|
4237 |
|
|
+ */
|
4238 |
|
|
+#define LIBCALL_VALUE(MODE) gen_rtx_REG(MODE, zip_R1)
|
4239 |
|
|
+
|
4240 |
|
|
+
|
4241 |
|
|
+/* STACK AND CALLING */
|
4242 |
|
|
+
|
4243 |
|
|
+
|
4244 |
|
|
+/* Define this macro as a C expression that is nonzero for registers that are
|
4245 |
|
|
+ * used by the epilogue or the return pattern. The stack and frame pointer
|
4246 |
|
|
+ * registers are already assumed to be used as needed.
|
4247 |
|
|
+ */
|
4248 |
|
|
+#define EPILOGUE_USES(R) (R == RETURN_ADDRESS_REGNUM)
|
4249 |
|
|
+
|
4250 |
|
|
+
|
4251 |
|
|
+/* The best alignment to use in cases where we have a choice. */
|
4252 |
127 |
dgisselq |
+#define FASTEST_ALIGNMENT BITS_PER_WORD
|
4253 |
102 |
dgisselq |
+
|
4254 |
|
|
+/* Generate Code for Profiling
|
4255 |
|
|
+ */
|
4256 |
|
|
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0)
|
4257 |
|
|
+
|
4258 |
|
|
+
|
4259 |
|
|
+/* A C expression which is nonzero if register number NUM is suitable for use
|
4260 |
|
|
+ * as an index register in operand addresses.
|
4261 |
|
|
+ */
|
4262 |
|
|
+#define REGNO_OK_FOR_INDEX_P(NUM) 0
|
4263 |
|
|
+
|
4264 |
|
|
+
|
4265 |
|
|
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
|
4266 |
|
|
+ * (an RTX) is a legitimate memory address on the target machine for a memory
|
4267 |
|
|
+ * operand of mode MODE.
|
4268 |
|
|
+ */
|
4269 |
111 |
dgisselq |
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
|
4270 |
|
|
+// DRIVER_SELF_SPECS
|
4271 |
|
|
+// OPTION_DEFAULT_SPECS
|
4272 |
|
|
+// CPP_SPEC
|
4273 |
|
|
+// CPLUSPLUS_CPP_SPEC
|
4274 |
|
|
+// CC1_SPEC
|
4275 |
|
|
+// CC1PLUS_SPEC
|
4276 |
|
|
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
|
4277 |
|
|
+ * to pass to the assembler. It can also specify how to translate options you
|
4278 |
|
|
+ * give to GCC into options for GCC to pass to the assembler. See the file
|
4279 |
|
|
+ * 'sun3.h' for an example of this.
|
4280 |
|
|
+ *
|
4281 |
|
|
+ * Do not define thismacro if it does not need to do anything.
|
4282 |
|
|
+ */
|
4283 |
|
|
+// #undef ASM_SPEC
|
4284 |
|
|
+// ASM_FINAL_SPEC
|
4285 |
|
|
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
|
4286 |
|
|
+
|
4287 |
|
|
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
|
4288 |
|
|
+ * to pass to the linker. It can also specify how to translate options you give
|
4289 |
|
|
+ * to GCC into options for GCC to pass to the linker.
|
4290 |
|
|
+ *
|
4291 |
|
|
+ * Do not define this macro if it does not need to do anything.
|
4292 |
|
|
+ */
|
4293 |
|
|
+
|
4294 |
|
|
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC. The
|
4295 |
|
|
+ * difference between the two is that LIB_SPEC is used at the end of the
|
4296 |
|
|
+ * command given to the linker.
|
4297 |
|
|
+ *
|
4298 |
|
|
+ * If this macro is not defined, a default is provided that loads the standard
|
4299 |
|
|
+ * C library from the usual place. See 'gcc.c'.
|
4300 |
202 |
dgisselq |
+ *
|
4301 |
|
|
+ * ZipCPU ... We need this at its default value. It is necessary to build
|
4302 |
|
|
+ * the various GCC libraries that depend upon one another and newlib. Hence,
|
4303 |
|
|
+ * as an example we *must* include the library containing strnlen or libgfortran
|
4304 |
|
|
+ * will not. Alternatively, we might figure out how to pass arguments to the
|
4305 |
|
|
+ * compiler via the configure process ... but we'll just allow this to have its
|
4306 |
|
|
+ * default value for now.
|
4307 |
111 |
dgisselq |
+ */
|
4308 |
202 |
dgisselq |
+// #undef LIB_SPEC
|
4309 |
111 |
dgisselq |
+// #define LIB_SPEC "%{!g:-lc} %{g:-lg} -lzip"
|
4310 |
202 |
dgisselq |
+// #define LIB_SPEC ""
|
4311 |
111 |
dgisselq |
+
|
4312 |
|
|
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
|
4313 |
|
|
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
|
4314 |
|
|
+ * line. This constant is placed both before and after the value of LIB_SPEC.
|
4315 |
|
|
+ *
|
4316 |
|
|
+ * If this macro is not defined, the GCC driver provides a default that passes
|
4317 |
|
|
+ * the string '-lgcc' to the linker.
|
4318 |
|
|
+ */
|
4319 |
|
|
+#undef LIBGCC_SPEC
|
4320 |
|
|
+#define LIBGCC_SPEC ""
|
4321 |
|
|
+
|
4322 |
|
|
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
|
4323 |
|
|
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
|
4324 |
|
|
+ * modified to refer to different versions of 'libgcc.a' depending on the
|
4325 |
|
|
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
|
4326 |
|
|
+ * and '-shared-libgcc'. On targets where these modifications are
|
4327 |
|
|
+ * inappropriate, define REAL_LIBGCC_SPEC instead. REAL_LIBGCC_SPEC tells the
|
4328 |
|
|
+ * driver how to place a reference to 'libgcc' on the link command line, but
|
4329 |
|
|
+ * unlike LIBGCC_SPEC, it is used unmodified.
|
4330 |
|
|
+ */
|
4331 |
|
|
+#define REAL_LIBGCC_SPEC ""
|
4332 |
|
|
+
|
4333 |
|
|
+// USE_LD_AS_NEEDED
|
4334 |
|
|
+// LINK_EH_SPEC
|
4335 |
|
|
+
|
4336 |
|
|
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC. The
|
4337 |
|
|
+ * difference between the two is that STARTFILE_SPEC is used at the very
|
4338 |
|
|
+ * beginning of the command given to the linker.
|
4339 |
|
|
+ *
|
4340 |
|
|
+ * If this macro is not defined, a default is provided that loads the standard
|
4341 |
|
|
+ * C startup file from the usual place. See 'gcc.c'
|
4342 |
|
|
+ */
|
4343 |
|
|
+#undef STARTFILE_SPEC
|
4344 |
|
|
+#define STARTFILE_SPEC ""
|
4345 |
|
|
+
|
4346 |
|
|
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC. The
|
4347 |
|
|
+ * difference between the two is that ENDFILE_SPEC is used at the very end
|
4348 |
|
|
+ * of the command given to the linker.
|
4349 |
|
|
+ *
|
4350 |
|
|
+ * Do not define this macro if it does not do anything.
|
4351 |
|
|
+ */
|
4352 |
|
|
+// #undef ENDFILE_SPEC
|
4353 |
|
|
+// #define ENDFILE_SPEC ""
|
4354 |
|
|
+
|
4355 |
|
|
+// THREAD_MODEL_SPEC
|
4356 |
|
|
+// SYSROOT_SUFFIX_SPEC
|
4357 |
|
|
+// SYSROOT_HEADERS_SUFFIX_SPEC
|
4358 |
|
|
+// EXTRA_SPECS
|
4359 |
|
|
+// LINK_LIBGCC_SPECIAL_1
|
4360 |
|
|
+// LINK_GCC_C_SEQUENCE_SPEC
|
4361 |
|
|
+// LINK_COMMAND_SPEC
|
4362 |
|
|
+// TARGET_ALWAYS_STRIP_DOTDOT
|
4363 |
|
|
+// MULTILIB_DEFAULTS
|
4364 |
|
|
+// RELATIVE_PREFIX_NOT_LINKDIR
|
4365 |
|
|
+// MD_EXEC_PREFIX
|
4366 |
|
|
+// STANDARD_STARTFILE_PREFIX
|
4367 |
|
|
+// STANDARD_STARTFILE_PREFIX_1
|
4368 |
|
|
+// STANDARD_STARTFILE_PREFIX_2
|
4369 |
|
|
+// MD_STARTFILE_PREFIX
|
4370 |
|
|
+// MD_STARTFILE_PREFIX_1
|
4371 |
|
|
+// INIT_ENVIRONMENT
|
4372 |
|
|
+// LOCAL_INCLUDE_DIR
|
4373 |
|
|
+#undef LOCAL_INCLUDE_DIR
|
4374 |
|
|
+
|
4375 |
|