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[/] [zipcpu/] [trunk/] [sw/] [lib/] [mpy32s.S] - Blame information for rev 69

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1 59 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename:     mpy32s.S
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;
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; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose:      Zip assembly file for running a 32-bit by 32-bit signed
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;               multiply.  It works by adjusting the sign of the 32x32-bit
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;               unsigned multiply.
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;
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; Creator:      Dan Gisselquist, Ph.D.
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;               Gisselquist Technology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of  the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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; for more details.
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;
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; License:      GPL, v3, as defined and found on www.gnu.org,
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;               http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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;
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; We could build mul32s (32-bit signed multiply) as
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;
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;       R0 - incoming value to be multiplied
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;       R1 - Second multiplicand
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;       R2 - Comes in as scratch
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;       R3 - used as scratch internally
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mpy32s:
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        ADD     2,SP
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        STO     R2,(SP)
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        STO     R3,2(SP)
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        ;
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        CLR     R3              ; Keep track of resulting sign in R2
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        TST     -1,R0           ; Is R0 negative?
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        XOR.LT  1,R3            ; If so, resulting sign will be negative, and
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        NEG.NZ  R0              ; then we negate R0 (R0 = ABS(R0))
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        TST     -1,R1           ; Is R1 negative?
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        XOR.LT  1,R3            ; If so, result will be opposite sign of before
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        NEG.LT  R1              ; Now we get R1=ABS(R1)
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        ; JSR mpy32u
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        MOV     __HERE__+2(PC),R2       ; Do our unsigned multiply
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        BRA     mpy32u
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        ;
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        TST     -1,R3           ; Check resulting sign
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        BZ      ret_mul32s      ; If positive, do nothing more
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        NOT     R0              ; If negative, negate the result
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        NOT     R1
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        ADD     $1,R1
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        ADD.C   $1,R0
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ret_mul32s:
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        LOD     (SP),R2
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        LOD     2(SP),R3
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        ADD     2,SP
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        JMP     R2
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