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[/] [zipcpu/] [trunk/] [sw/] [lib/] [mpy32u.S] - Blame information for rev 69

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename:     mpyu.S
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;
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; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose:      Zip assembly file for running doing an unsigned 32x32 bit
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;               multiply..
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;
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; Creator:      Dan Gisselquist, Ph.D.
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;               Gisselquist Technology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of  the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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; for more details.
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;
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; License:      GPL, v3, as defined and found on www.gnu.org,
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;               http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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;
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mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1, R2 = rtn addr (on stack)
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        SUB     3,SP
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        STO     R2,(SP)
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        STO     R3,1(SP)
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        STO     R4,2(SP)
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        ;
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        MOV     R0,R2
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        MPYU    R1,R2   ; R2 = Low order bits, low(R0) * low(R1)
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        MOV     R0,R3
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        LSR     16,R3   ; Put high order bits in lower half of R3
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        MPYU    R1,R3   ; R3 = Mid order bits, high(R0) * low(R1)
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        LSR     16,R1   ; R1 = High order bits of R1, being done w/ low order
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        MOV     R1,R4   ;
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        MPYU    R0,R4   ; R4 = Mid order bits, low(R0) * high(R1)
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        LSR     16,R0
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        MPYU    R1,R0   ; R0 = High order bits, high(R0) * high(R1)
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        ADD     R3,R4   ; R4 = sum of mid order bits
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        ADD.C   0x010000,R0     ; Add in the carry (if it happened)
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        MOV     R4,R3
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        LSR     16,R3
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        ADD     R3,R0   ; R0 = high order bits plus high order mid-bits
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        LSL     16,R4
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        ADD     R4,R2   ; R2 = low order bits plus low order mid-bits
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        ADD.C   1,R0    ; Add in the carry to R0 (if it happened)
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        MOV     R2,R1   ; Place low order bits into R1
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        ;
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        LOD     (SP),R2
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        LOD     1(SP),R3
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        LOD     2(SP),R4
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        ADD     3,SP
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        JMP     R2
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