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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [zopcodes.h] - Blame information for rev 209

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zopcodes.h
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU core
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//
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// Purpose:     A structure defined to keep track of our various opcodes and
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//              some of their shortcut synonyms.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#ifndef ZOPCODES_H
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#define ZOPCODES_H
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#include <stdint.h>
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// MACROS used in the instruction definition list.
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#define ZIP_OPUNUSED    -1
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#define ISUSEROP(A)     ((a&(~0x0f))==0x000)
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#define ISSUPROP(A)     ((a&(~0x0f))==0x010)
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#define ISLCLROP(A)     ((a&(~0x0f))==0x020)
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#define ZIP_BITFIELD(LN,MN)     (((LN&0x0ff)<<8)+(MN&0x0ff)) // A generic bitfield
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#define ZIP_REGFIELD(MN)        (0x00000400 +(MN&0x0ff)) // Normal register field
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#define ZIP_URGFIELD(MN)        (0x0100400 +(MN&0x0ff)) // User register field
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#define ZIP_IMMFIELD(LN,MN)     (0x40000000 + (((LN&0x0ff)<<8)+(MN&0x0ff))) // Sgn extnd
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#define ZIP_SRGFIELD(MN)        (0x0200400 +(MN&0x0ff))
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#define ZIP_SP  0xd0000
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typedef uint32_t        ZIPI;   // A Zip CPU instruction
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typedef struct {
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        char    s_opstr[8];     // OPCode name
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        ZIPI    s_mask,         // Bits that must match 4 this pattern to match
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                s_val;          // What those masked bits must be
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        //
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        // The following describe not the value, but the bits where there
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        // respective vaules will be found within the instruction.  For example,
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        // an instruction with no immediate will have an s_i value of -1
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        // (ZIP_OPUNUSED), whereas an instruction with an immediate value of -1
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        // might have an s_i value of ZIP_BITFIELD(14,0), or 0x0400.  The
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        // opcode itself will tell you what the value is--not this structure
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        // describing the opcode.
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        //
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        int     s_result,       // Register where the result will be placed
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                s_ra,           // A register, often the result
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                s_rb,           // B register, source operand (if used)
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                s_i,            // Immediate value, added to B if B is used
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                s_cf;           // Condition flags.
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} ZOPCODE;
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extern  const   char    *zip_regstr[49], *zip_ccstr[8];
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extern  const ZOPCODE   *zip_oplist, *zip_opbottomlist;
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extern  const int       nzip_oplist, nzip_opbottom;
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// Disassemble an opcode
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extern  void zipi_to_double_string(const uint32_t, const ZIPI, char *, char *);
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extern  const   char    *zop_regstr[];
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extern  const   char    *zop_ccstr[];
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extern  unsigned int    zop_early_branch(const unsigned int pc, const ZIPI ins);
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#endif

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