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mcleod_ide |
//-------------------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : April 30, 2001
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// Update: 4/30/01 copied this file from lcd_2.v (pared down).
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// Update: 5/24/01 changed the first module from "ps2_keyboard_receiver"
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// to "ps2_keyboard_interface"
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// Update: 5/29/01 Added input synchronizing flip-flops. Changed state
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// encoding (m1) for good operation after part config.
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// Update: 5/31/01 Added low drive strength and slow transitions to ps2_clk
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// and ps2_data in the constraints file. Added the signal
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// "tx_shifting_done" as distinguished from "rx_shifting_done."
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// Debugged the transmitter portion in the lab.
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// Update: 6/01/01 Added horizontal tab to the ascii output.
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// Update: 6/01/01 Added parameter TRAP_SHIFT_KEYS.
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// Update: 6/05/01 Debugged the "debounce" timer functionality.
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// Used 60usec timer as a "watchdog" timeout during
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// receive from the keyboard. This means that a keyboard
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// can now be "hot plugged" into the interface, without
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// messing up the bit_count, since the bit_count is reset
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// to zero during periods of inactivity anyway. This was
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// difficult to debug. I ended up using the logic analyzer,
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// and had to scratch my head quite a bit.
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// Update: 6/06/01 Removed extra comments before the input synchronizing
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// flip-flops. Used the correct parameter to size the
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// 5usec_timer_count. Changed the name of this file from
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// ps2.v to ps2_keyboard.v
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// Update: 6/06/01 Removed "&& q[7:0]" in output_strobe logic. Removed extra
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// commented out "else" condition in the shift register and
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// bit counter.
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// Update: 6/07/01 Changed default values for 60usec timer parameters so that
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// they correspond to 60usec for a 49.152MHz clock.
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//
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//
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//
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//
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//
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// Description
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//-------------------------------------------------------------------------------------
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// This is a state-machine driven serial-to-parallel and parallel-to-serial
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// interface to the ps2 style keyboard interface. The details of the operation
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// of the keyboard interface were obtained from the following website:
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//
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// http://www.beyondlogic.org/keyboard/keybrd.htm
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//
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// Some aspects of the keyboard interface are not implemented (e.g, parity
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// checking for the receive side, and recognition of the various commands
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// which the keyboard sends out, such as "power on selt test passed," "Error"
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// and "Resend.") However, if the user wishes to recognize these reply
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// messages, the scan code output can always be used to extend functionality
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// as desired.
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//
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// Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized.
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// The rx interface provides separate indicator flags for these two conditions
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// with every valid character scan code which it provides. The shift keys are
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// also trapped by the interface, in order to provide correct uppercase ASCII
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// characters at the ascii output, although the scan codes for the shift keys
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// are still provided at the scan code output. So, the left/right ALT keys
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// can be differentiated by the presence of the rx_entended signal, while the
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// left/right shift keys are differentiable by the different scan codes
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// received.
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//
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// The interface to the ps2 keyboard uses ps2_clk clock rates of
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// 30-40 kHz, dependent upon the keyboard itself. The rate at which the state
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// machine runs should be at least twice the rate of the ps2_clk, so that the
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// states can accurately follow the clock signal itself. Four times
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// oversampling is better. Say 200kHz at least. The upper limit for clocking
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// the state machine will undoubtedly be determined by delays in the logic
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// which decodes the scan codes into ASCII equivalents. The maximum speed
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// will be most likely many megahertz, depending upon target technology.
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// In order to run the state machine extremely fast, synchronizing flip-flops
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// have been added to the ps2_clk and ps2_data inputs of the state machine.
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// This avoids poor performance related to slow transitions of the inputs.
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//
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// Because this is a bi-directional interface, while reading from the keyboard
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// the ps2_clk and ps2_data lines are used as inputs. While writing to the
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// keyboard, however (which may be done at any time. If writing interrupts a
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// read from the keyboard, the keyboard will buffer up its data, and send
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// it later) both the ps2_clk and ps2_data lines are occasionally pulled low,
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// and pullup resistors are used to bring the lines high again, by setting
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// the drivers to high impedance state.
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//
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// The tx interface, for writing to the keyboard, does not provide any special
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// pre-processing. It simply transmits the 8-bit command value to the
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// keyboard.
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//
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// Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
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// whether they be internal to an FPGA I/O pad, or externally placed.
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// If internal pullups are used, they may be fairly weak, causing bounces
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// due to crosstalk, etc. There is a "debounce timer" implemented in order
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// to eliminate erroneous state transitions which would occur based on bounce.
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//
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// Parameters are provided in order to configure and appropriately size the
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// counter of a 60 microsecond timer used in the transmitter, depending on
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// the clock frequency used. The 60 microsecond period is guaranteed to be
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// more than one period of the ps2_clk_s signal.
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//
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// Also, a smaller 5 microsecond timer has been included for "debounce".
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// This is used because, with internal pullups on the ps2_clk and ps2_data
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// lines, there is some bouncing around which occurs
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//
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// A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses
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// from producing scan codes (along with their "undefined" ASCII equivalents)
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// at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift
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// key status will only be reported by rx_shift_key_on. No ascii or scan
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// codes will be reported for the shift keys. This is useful for those who
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// wish to use the ASCII data stream, and who don't want to have to "filter
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// out" the shift key codes.
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//
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//-------------------------------------------------------------------------------------
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`resetall
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`timescale 1ns/100ps
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`define TOTAL_BITS 11 //total data bits of the data package
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`define EXTEND_CODE 8'hE0 //extend code
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`define RELEASE_CODE 8'hF0 //release code
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module ps2_keyboard(
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clk,
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reset,
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ps2_clk,
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ps2_data,
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interrupt,
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rx_scan_code
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);
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// Parameters
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// The timer value can be up to (2^bits) inclusive.
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parameter TIMER_60USEC_VALUE_PP = 840; // Number of sys_clks for 60usec. (for a 14Mhz clock)
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parameter TIMER_60USEC_BITS_PP = 10; // Number of bits needed for timer
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// State encodings, provided as parameters
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// for flexibility to the one instantiating the module.
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// In general, the default values need not be changed.
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// State "m1_rx_clk_l" has been chosen on purpose. Since the input
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// synchronizing flip-flops initially contain zero, it takes one clk
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// for them to update to reflect the actual (idle = high) status of
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// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
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// allows the state machine to transition to m1_rx_clk_h when the true
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// values of the input signals become present at the outputs of the
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// synchronizing flip-flops. This initial transition is harmless, and it
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// eliminates the need for a "reset" pulse before the interface can operate.
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parameter m1_rx_clk_h = 1;
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parameter m1_rx_clk_l = 0;
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parameter m1_rx_falling_edge_marker = 3;
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parameter m1_rx_rising_edge_marker = 4;
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// I/O declarations
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input clk;
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input reset;
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input ps2_clk;
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input ps2_data;
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output interrupt;
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output [7:0] rx_scan_code;
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//output [7:0] rx_ascii;
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reg rx_extended;
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reg rx_released;
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reg [7:0] rx_scan_code;
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reg interrupt;
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// Internal signal declarations
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wire timer_60usec_done;
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wire extended;
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wire released;
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// NOTE: These two signals used to be one. They
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// were split into two signals because of
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// shift key trapping. With shift key
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// trapping, no event is generated externally,
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// but the "hold" data must still be cleared
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// anyway regardless, in preparation for the
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// next scan codes.
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wire rx_output_strobe; // Used to produce the actual output.
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wire rx_shifting_done;
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reg [`TOTAL_BITS-1:0] q;
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reg [3:0] m1_state;
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reg [3:0] m1_next_state;
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reg [3:0] bit_count;
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reg enable_timer_60usec;
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reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
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reg ps2_clk_s; // Synchronous version of this input
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reg ps2_data_s; // Synchronous version of this input
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//--------------------------------------------------------------------------
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// Module code
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// Input "synchronizing" logic -- synchronizes the inputs to the state
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// machine clock, thus avoiding errors related to
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// spurious state machine transitions.
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always @(posedge clk)
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begin
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ps2_clk_s <= ps2_clk;
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ps2_data_s <= ps2_data;
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end
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// State register
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always @(posedge clk)
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begin : m1_state_register
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if (reset) m1_state <= m1_rx_clk_h;
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else m1_state <= m1_next_state;
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end
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// State transition logic
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always @(m1_state
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or q
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or ps2_clk_s
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or ps2_data_s
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or timer_60usec_done
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)
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begin : m1_state_logic
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// Output signals default to this value, unless changed in a state condition.
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enable_timer_60usec <= 0;
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case (m1_state)
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m1_rx_clk_h :
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begin
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enable_timer_60usec <= 1;
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if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker;
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else m1_next_state <= m1_rx_clk_h;
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end
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m1_rx_falling_edge_marker :
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begin
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enable_timer_60usec <= 0;
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m1_next_state <= m1_rx_clk_l;
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end
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m1_rx_rising_edge_marker :
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begin
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enable_timer_60usec <= 0;
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m1_next_state <= m1_rx_clk_h;
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end
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m1_rx_clk_l :
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begin
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enable_timer_60usec <= 1;
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if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker;
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else m1_next_state <= m1_rx_clk_l;
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end
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default : m1_next_state <= m1_rx_clk_h;
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endcase
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end
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// This is the bit counter
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always @(posedge clk)
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begin
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if ( reset
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|| rx_shifting_done
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)
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bit_count <= 0; // normal reset
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else if (timer_60usec_done
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&& (m1_state == m1_rx_clk_h)
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&& (ps2_clk_s)
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)
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bit_count <= 0; // rx watchdog timer reset
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else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
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)
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bit_count <= bit_count + 1;
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end
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// This signal is high for one clock at the end of the timer count.
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assign rx_shifting_done = (bit_count == `TOTAL_BITS);
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// This is the signal which enables loading of the shift register.
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// It also indicates "ack" to the device writing to the transmitter.
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// This is the ODD parity bit for the transmitted word.
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// This is the shift register
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always @(posedge clk)
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begin
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if (reset) q <= 0;
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else if ( (m1_state == m1_rx_falling_edge_marker) )
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q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
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end
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// This is the 60usec timer counter
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always @(posedge clk)
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begin
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if (~enable_timer_60usec) timer_60usec_count <= 0;
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else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
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end
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assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
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// Create the signals which indicate special scan codes received.
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// These are the "unlatched versions."
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assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
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assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
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// Store the special scan code status bits
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// Not the final output, but an intermediate storage place,
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// until the entire set of output data can be assembled.
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// Output the special scan code flags, the scan code and the ascii
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always @(posedge clk)
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begin
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if (reset)
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begin
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rx_scan_code <= 0;
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interrupt<=0;
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end
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else if (rx_output_strobe) //if not extended, not relaeased,get the scan_code
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begin
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rx_scan_code <= q[8:1];
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interrupt<=1;
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end
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else
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begin
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//rx_scan_code<=rx_scan_code;
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interrupt<=0;
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end
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end
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// Store the final rx output data only when all extend and release codes
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// are received and the next (actual key) scan code is also ready.
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// (the presence of rx_extended or rx_released refers to the
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// the current latest scan code received, not the previously latched flags.)
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
assign rx_output_strobe = rx_shifting_done;
|
348 |
|
|
// && ~extended
|
349 |
|
|
// && ~released
|
350 |
|
|
// );
|
351 |
|
|
|
352 |
|
|
// This part translates the scan code into an ASCII value...
|
353 |
|
|
// Only the ASCII codes which I considered important have been included.
|
354 |
|
|
// if you want more, just add the appropriate case statement lines...
|
355 |
|
|
// (You will need to know the keyboard scan codes you wish to assign.)
|
356 |
|
|
// The entries are listed in ascending order of ASCII value.
|
357 |
|
|
|
358 |
|
|
endmodule
|
359 |
|
|
|
360 |
|
|
//`undefine TOTAL_BITS
|
361 |
|
|
//`undefine EXTEND_CODE
|
362 |
|
|
//`undefine RELEASE_CODE
|
363 |
|
|
//`undefine LEFT_SHIFT
|
364 |
|
|
//`undefine RIGHT_SHIFT
|
365 |
|
|
|